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-rw-r--r--board/esd/common/cmd_loadpci.c2
-rw-r--r--board/esd/du440/du440.c28
-rw-r--r--board/esd/pmc440/cmd_pmc440.c10
-rw-r--r--board/esd/pmc440/pmc440.c32
4 files changed, 36 insertions, 36 deletions
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index 47e946f116..eecae0a7fd 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -48,7 +48,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
u32 la, ptm1la;
#if defined(CONFIG_440)
- ptm1la = in32r(PCIX0_PTM1LA);
+ ptm1la = in32r(PCIL0_PTM1LA);
#else
ptm1la = in32r(PTM1LA);
#endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 056f455d68..d0e52cbab3 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -435,26 +435,26 @@ void pci_target_init(struct pci_controller *hose)
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 1af431bd7d..476e940962 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* map PCI address at 0xc0000000 in PLB space */
/* PMM1 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1MA, 0x00000000);
+ out32r(PCIL0_PMM1MA, 0x00000000);
/* PMM1 Local Address */
- out32r(PCIX0_PMM1LA, 0xc0000000);
+ out32r(PCIL0_PMM1LA, 0xc0000000);
/* PMM1 PCI Low Address */
- out32r(PCIX0_PMM1PCILA, pciaddr);
+ out32r(PCIL0_PMM1PCILA, pciaddr);
/* PMM1 PCI High Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000);
+ out32r(PCIL0_PMM1PCIHA, 0x00000000);
/* 256MB + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0xf0000001);
+ out32r(PCIL0_PMM1MA, 0xf0000001);
} else {
printf("Usage:\npmm %s\n", cmdtp->help);
}
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index f0f9bff3eb..ec9255243c 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -208,7 +208,7 @@ int misc_init_f(void)
if (getenv("pciearly") && (!is_monarch())) {
printf("PCI: early target init\n");
- pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+ pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
pci_target_init(&hose);
}
return 0;
@@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose)
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
/* and enable region */
if (!is_monarch()) {
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIX0_PTM1MS,
+ out32r(PCIL0_PTM1MS,
simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIX0_PTM1LA,
+ out32r(PCIL0_PTM1LA,
simple_strtoul(ptmla_str, NULL, 16));
} else {
/* BAR1: default top 64MB of RAM */
- out32r(PCIX0_PTM1MS, 0xfc000001);
- out32r(PCIX0_PTM1LA, 0x0c000000);
+ out32r(PCIL0_PTM1MS, 0xfc000001);
+ out32r(PCIL0_PTM1LA, 0x0c000000);
}
} else {
/* BAR1: default: complete 256MB RAM */
- out32r(PCIX0_PTM1MS, 0xf0000001);
- out32r(PCIX0_PTM1LA, 0x00000000);
+ out32r(PCIL0_PTM1MS, 0xf0000001);
+ out32r(PCIL0_PTM1LA, 0x00000000);
}
ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+ out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
} else {
/* BAR2: default: 4MB FPGA */
- out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
}
if (is_monarch()) {
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