diff options
Diffstat (limited to 'board/amcc/bamboo')
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 22 | ||||
| -rw-r--r-- | board/amcc/bamboo/config.mk | 2 | ||||
| -rw-r--r-- | board/amcc/bamboo/flash.c | 12 | ||||
| -rw-r--r-- | board/amcc/bamboo/init.S | 28 |
4 files changed, 32 insertions, 32 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index f4157017f1..febc61a086 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -462,7 +462,7 @@ phys_size_t initdram (int board_type) return dram_size; #else - return CFG_MBYTES_SDRAM << 20; + return CONFIG_SYS_MBYTES_SDRAM << 20; #endif } @@ -529,7 +529,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -543,14 +543,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -565,8 +565,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -580,13 +580,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -601,7 +601,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index b46527dcc5..a37636a0a1 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index d004ed7859..001348ac5c 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -45,12 +45,12 @@ #define DEBUGF(x...) #endif /* DEBUG */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ @@ -79,7 +79,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; unsigned long val; @@ -128,7 +128,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -150,8 +150,8 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); #if defined(CONFIG_ENV_IS_IN_FLASH) (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index f4d2ae3f41..a5c9d6d764 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -48,29 +48,29 @@ tlbtab: * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) /* PCI base & peripherals */ - tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) - tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) + tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) + tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) /* PCI */ - tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I) /* USB 2.0 Device */ - tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I) tlbtab_end @@ -79,8 +79,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 |
