diff options
Diffstat (limited to 'arch')
51 files changed, 1442 insertions, 43 deletions
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h new file mode 100644 index 0000000000..2d1a603062 --- /dev/null +++ b/arch/arc/include/asm/linkage.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_LINKAGE_H +#define __ASM_ARC_LINKAGE_H + +#define ASM_NL ` /* use '`' to mark new line in macro */ + +#endif /* __ASM_ARC_LINKAGE_H */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 452a843311..72e7981bbe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -381,6 +381,19 @@ config TARGET_AM43XX_EVM select CPU_V7 select SUPPORT_SPL +config TARGET_BAV335X + bool "Support bav335x" + select CPU_V7 + select SUPPORT_SPL + help + The BAV335x OEM Network Processor integrates all the functions of an + embedded network computer in a small, easy to use SODIMM module which + incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8 + processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit + ethernet with simple connection to external connectors. + + For more information, visit: http://birdland.com/oem + config TARGET_TI814X_EVM bool "Support ti814x_evm" select CPU_V7 @@ -465,6 +478,10 @@ config TARGET_WANDBOARD bool "Support wandboard" select CPU_V7 +config TARGET_WARP + bool "Support WaRP" + select CPU_V7 + config TARGET_TITANIUM bool "Support titanium" select CPU_V7 @@ -837,6 +854,7 @@ source "board/syteco/zmx25/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" +source "board/birdland/bav335x/Kconfig" source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" @@ -847,6 +865,7 @@ source "board/ttcontrol/vision2/Kconfig" source "board/udoo/Kconfig" source "board/vpac270/Kconfig" source "board/wandboard/Kconfig" +source "board/warp/Kconfig" source "board/woodburn/Kconfig" source "board/xaeniax/Kconfig" source "board/xilinx/zynqmp/Kconfig" diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile index 9670ed9382..dcbd57065b 100644 --- a/arch/arm/cpu/arm1136/mx31/Makefile +++ b/arch/arm/cpu/arm1136/mx31/Makefile @@ -8,3 +8,7 @@ obj-y += generic.o obj-y += timer.o obj-y += devices.o + +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm1136/mx31/relocate.S b/arch/arm/cpu/arm1136/mx31/relocate.S new file mode 100644 index 0000000000..1c556df71b --- /dev/null +++ b/arch/arm/cpu/arm1136/mx31/relocate.S @@ -0,0 +1,23 @@ +/* + * relocate - i.MX31-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +/* + * The i.MX31 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM, so let's avoid relocating the vectors. + */ + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile index c533215c3a..796db9c7cc 100644 --- a/arch/arm/cpu/arm1136/mx35/Makefile +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -10,3 +10,7 @@ obj-y += generic.o obj-y += timer.o obj-y += mx35_sdram.o + +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S new file mode 100644 index 0000000000..43003f8044 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/relocate.S @@ -0,0 +1,23 @@ +/* + * relocate - i.MX35-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +/* + * The i.MX35 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM, so let's avoid relocating the vectors. + */ + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 81477aa7b0..67bef23ea9 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -275,6 +275,14 @@ static void watchdog_disable(void) ; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + board_early_init_f(); + sdram_init(); +} +#endif + void s_init(void) { /* @@ -290,6 +298,7 @@ void s_init(void) setup_clocks_for_console(); uart_soft_reset(); #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) + /* TODO: This does not work, gd is not available yet */ gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; @@ -298,9 +307,5 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); #endif -#ifdef CONFIG_SPL_BUILD - board_early_init_f(); - sdram_init(); -#endif } #endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index f1aea05c90..427b0b1321 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -17,10 +17,17 @@ ENTRY(lowlevel_init) /* - * Setup a temporary stack + * Setup a temporary stack. Global data is not available yet. */ ldr sp, =CONFIG_SYS_INIT_SP_ADDR bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#ifdef CONFIG_DM + mov r9, #0 +#else + /* + * Set up global data for boards that still need it. This will be + * removed soon. + */ #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else @@ -28,13 +35,24 @@ ENTRY(lowlevel_init) bic sp, sp, #7 mov r9, sp #endif +#endif /* * Save the old lr(passed in ip) and the current lr to stack */ push {ip, lr} /* - * go setup pll, mux, memory + * Call the very early init function. This should do only the + * absolute bare minimum to get started. It should not: + * + * - set up DRAM + * - use global_data + * - clear BSS + * - try to start a console + * + * For boards with SPL this should be empty since SPL can do all of + * this init in the SPL board_init_f() function which is called + * immediately after this. */ bl s_init pop {ip, pc} diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index e599a12b3a..ef029722b4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -230,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable) struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; +#ifdef CONFIG_MX6SX + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + writew(enable, &wdog3->wmcr); +#endif + /* Write to the PDE (Power Down Enable) bit */ writew(enable, &wdog1->wmcr); writew(enable, &wdog2->wmcr); @@ -255,6 +260,23 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +static void init_bandgap(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + /* + * Ensure the bandgap has stabilized. + */ + while (!(readl(&anatop->ana_misc0) & 0x80)) + ; + /* + * For best noise performance of the analog blocks using the + * outputs of the bandgap, the reftop_selfbiasoff bit should + * be set. + */ + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); +} + + #ifdef CONFIG_MX6SL static void set_preclk_from_osc(void) { @@ -275,6 +297,13 @@ int arch_cpu_init(void) clear_mmdc_ch_mask(); /* + * Disable self-bias circuit in the analog bandap. + * The self-bias circuit is used by the bandgap during startup. + * This bit should be set after the bandgap has initialized. + */ + init_bandgap(); + + /* * When low freq boot is enabled, ROM will not set AHB * freq, so we need to ensure AHB freq is 132MHz in such * scenario. diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index cb35c198f1..6c8f3bcea4 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -128,14 +128,18 @@ void s_init(void) do_io_settings(); #endif prcm_init(); +} + #ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(); #endif /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); -#endif } +#endif /* * Routine: wait_for_command_complete diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 4a0ac2c987..65da6e2c17 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -91,6 +91,10 @@ config TARGET_TWISTER bool "Twister" select SUPPORT_SPL +config TARGET_OMAP3_CAIRO + bool "QUIPOS CAIRO" + select SUPPORT_SPL + endchoice config DM @@ -133,5 +137,6 @@ source "board/matrix_vision/mvblx/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" source "board/technexion/twister/Kconfig" +source "board/quipos/cairo/Kconfig" endif diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7bb5..dd53b207f8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -240,8 +240,6 @@ void try_unlock_memory(void) *****************************************************************************/ void s_init(void) { - int in_sdram = is_running_in_sdram(); - watchdog_init(); try_unlock_memory(); @@ -264,10 +262,14 @@ void s_init(void) #ifdef CONFIG_USB_EHCI_OMAP ehci_clocks_enable(); #endif +} - if (!in_sdram) - mem_init(); +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + mem_init(); } +#endif /* * Routine: misc_init_r @@ -345,7 +347,16 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg goto usage; } } else if (strncmp(argv[1], "sw", 2) == 0) { - omap_nand_switch_ecc(0, 0); + if (argc == 2) { + omap_nand_switch_ecc(0, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(0, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(0, 8); + else + goto usage; + } } else { goto usage; } diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 17d8be5b5b..25de9e5fff 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -46,6 +46,13 @@ int cpu_is_pxa27x(void) return id == CPU_VALUE_PXA27X; } +int cpu_is_pxa27xm(void) +{ + uint32_t id = pxa_get_cpuid(); + return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) && + ((id & CPU_MASK_PXA_REVID) == 8); +} + uint32_t pxa_get_cpu_revision(void) { return pxa_get_cpuid() & CPU_MASK_PRODREV; @@ -91,13 +98,17 @@ static const char *pxa27x_get_revision(void) id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; - if ((id == 5) || (id == 6) || (id > 7)) + if ((id == 5) || (id == 6) || (id > 8)) return unknown; /* Cap the special PXA270 C5 case. */ if (id == 7) id = 5; + /* Cap the special PXA270M A1 case. */ + if (id == 8) + id = 1; + return rev[id]; } @@ -107,7 +118,9 @@ static int print_cpuinfo_pxa2xx(void) puts("Marvell PXA25x rev. "); puts(pxa25x_get_revision()); } else if (cpu_is_pxa27x()) { - puts("Marvell PXA27x rev. "); + puts("Marvell PXA27x"); + if (cpu_is_pxa27xm()) puts("M"); + puts(" rev. "); puts(pxa27x_get_revision()); } else return -EINVAL; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 25a9d4ce12..606482f7a3 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o +obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o quiet_cmd_cpp_cfg = CFGS $@ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c new file mode 100644 index 0000000000..d93d5fb240 --- /dev/null +++ b/arch/arm/imx-common/cmd_dek.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Command for encapsulating DEK blob + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <linux/compiler.h> +#include <fsl_sec.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** +* blob_dek() - Encapsulate the DEK as a blob using CAM's Key +* @src: - Address of data to be encapsulated +* @dst: - Desination address of encapsulated data +* @len: - Size of data to be encapsulated +* +* Returns zero on success,and negative on error. +*/ +static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) +{ + int ret = 0; + u32 jr_size = 4; + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + if (out_jr_size != jr_size) { + hab_caam_clock_enable(1); + sec_init(); + } + + if (!((len == 128) | (len == 192) | (len == 256))) { + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + len /= 8; + ret = blob_dek(src, dst, len); + + return ret; +} + +/** + * do_dek_blob() - Handle the "dek_blob" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uint32_t src_addr, dst_addr, len; + uint8_t *src_ptr, *dst_ptr; + int ret = 0; + + if (argc != 4) + return CMD_RET_USAGE; + + src_addr = simple_strtoul(argv[1], NULL, 16); + dst_addr = simple_strtoul(argv[2], NULL, 16); + len = simple_strtoul(argv[3], NULL, 10); + + src_ptr = map_sysmem(src_addr, len/8); + dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8)); + + ret = blob_encap_dek(src_ptr, dst_ptr, len); + + return ret; +} + +/***************************************************/ +static char dek_blob_help_text[] = + "src dst len - Encapsulate and create blob of data\n" + " $len bits long at address $src and\n" + " store the result at address $dst.\n"; + +U_BOOT_CMD( + dek_blob, 4, 1, do_dek_blob, + "Data Encryption Key blob encapsulation", + dek_blob_help_text +); diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 28ccd29594..067d08f131 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -24,13 +24,16 @@ #include <fsl_esdhc.h> #endif -char *get_reset_cause(void) +static u32 reset_cause = -1; + +static char *get_reset_cause(void) { u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR; cause = readl(&src_regs->srsr); writel(cause, &src_regs->srsr); + reset_cause = cause; switch (cause) { case 0x00001: @@ -53,6 +56,11 @@ char *get_reset_cause(void) } } +u32 get_imx_reset_cause(void) +{ + return reset_cause; +} + #if defined(CONFIG_MX53) || defined(CONFIG_MX6) #if defined(CONFIG_MX53) #define MEMCTL_BASE ESDCTL_BASE_ADDR diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 65ef60bf2e..e522990453 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -176,3 +176,20 @@ ulong get_tbclk(void) { return gpt_get_clk(); } + +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 254136e228..4715f4e894 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -17,3 +17,5 @@ #define CS0_64M_CS1_64M 1 #define CS0_64M_CS1_32M_CS2_32M 2 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 + +u32 get_imx_reset_cause(void); diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 3b6a1696d8..6561ce644e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -27,6 +27,8 @@ #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) @@ -95,7 +97,25 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_MON_LE #define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION +#define CONFIG_FSL_ISBC_KEY_EXT + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif +#endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index ac7705b3b0..b06c77f65c 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -24,6 +24,5 @@ void set_chipselect_size(int const); int fecmxc_initialize(bd_t *bis); u32 get_ahb_clk(void); u32 get_periph_clk(void); -char *get_reset_cause(void); #endif diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c0707b..0592ce0171 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1063,4 +1063,6 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index ae88b6ecab..9a4ad8b559 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -215,6 +215,10 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) + +#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR +#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) + #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 9ded3d851c..6ba1034b2e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -31,7 +31,12 @@ enum { MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0), MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), @@ -58,5 +63,10 @@ enum { MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), + + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), + MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), + MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 17b6f544da..6db405d7d9 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -37,6 +37,8 @@ void spl_board_load_image(void); /* Linker symbols. */ extern char __bss_start[], __bss_end[]; +#ifndef CONFIG_DM extern gd_t gdata; +#endif #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 22df3e5b83..7939cedede 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -113,7 +113,14 @@ here: /* Set up final (full) environment */ bl c_runtime_cpu_setup /* we still call old routine here */ - +#endif +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK) +# ifdef CONFIG_SPL_BUILD + /* Use a DRAM stack for the rest of SPL, if requested */ + bl spl_relocate_stack_gd + cmp r0, #0 + movne sp, r0 +# endif ldr r0, =__bss_start /* this is auto-relocated! */ ldr r1, =__bss_end /* this is auto-relocated! */ @@ -124,9 +131,10 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ addlo r0, r0, #4 /* move to next */ blo clbss_l +#if ! defined(CONFIG_SPL_BUILD) bl coloured_LED_init bl red_led_on - +#endif /* call board_init_r(gd_t *id, ulong dest_addr) */ mov r0, r9 /* gd_t */ ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ @@ -134,7 +142,6 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ ldr pc, =board_init_r /* this is auto-relocated! */ /* we should not return here. */ - #endif ENDPROC(_main) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index c41850aaee..bd8c7d2ede 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -13,6 +13,7 @@ #include <image.h> #include <linux/compiler.h> +#ifndef CONFIG_DM /* Pointer to as well as the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; @@ -21,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; * pafches that rely on it. The global_data area is set up in crt0.S. */ gd_t gdata __attribute__ ((section(".data"))); +#endif /* * In the context of SPL, board_init_f must ensure that any clocks/etc for @@ -33,8 +35,10 @@ void __weak board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); +#ifndef CONFIG_DM /* TODO: Remove settings of the global data pointer here */ gd = &gdata; +#endif board_init_r(NULL, 0); } diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8615248377..fccfd79648 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -29,6 +29,9 @@ config USE_PRIVATE_LIBGCC config DM default y +config SPL_DM + default y + config DM_SERIAL default y diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 78c98ed2d0..53c4aabe1e 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -67,6 +67,9 @@ config TARGET_M5475EVB config TARGET_M5485EVB bool "Support M5485EVB" +config TARGET_AMCORE + bool "Support AMCORE" + endchoice source "board/BuS/eb_cpu5282/Kconfig" @@ -89,5 +92,6 @@ source "board/freescale/m54451evb/Kconfig" source "board/freescale/m54455evb/Kconfig" source "board/freescale/m547xevb/Kconfig" source "board/freescale/m548xevb/Kconfig" +source "board/sysam/amcore/Kconfig" endmenu diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 3b3a7e88ab..a629b68d61 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -11,6 +11,9 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 +# Support generic board on m68k +__HAVE_ARCH_GENERIC_BOARD := y + PLATFORM_CPPFLAGS += -D__M68K__ PLATFORM_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile new file mode 100644 index 0000000000..9492bde816 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o +obj-y = interrupts.o cpu.o speed.o cpu_init.o + diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk new file mode 100644 index 0000000000..aef72d70c5 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/config.mk @@ -0,0 +1,12 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5307:=$(shell grep CONFIG_M5307 $(cfg)) + +ifneq (,$(findstring CONFIG_M5307,$(is5307))) +PLATFORM_CPPFLAGS += -mcpu=5307 +endif diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c new file mode 100644 index 0000000000..78f438548b --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_M5307 +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + sim_t *sim = (sim_t *)(MMAP_SIM); + + /* enable watchdog/reset, set timeout to 0 and wait */ + out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI); + + /* wait for watchdog reset */ + for (;;) + ; + + /* we don't return! */ + return 0; +} + +int checkcpu(void) +{ + char buf[32]; + + printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", + strmhz(buf, CONFIG_SYS_CPU_CLK)); + return 0; +} +#endif diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c new file mode 100644 index 0000000000..80dc23910e --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/immap.h> +#include <asm/io.h> + +#if defined(CONFIG_M5307) +/* + * Simple mcf5307 chip select module init. + * + * Note: this chip has an issue reported in the device "errata": + * MCF5307ER Rev 4.2 reports @ section 35: + * Corrupted Return PC in Exception Stack Frame + * When processing an autovectored interrupt an error can occur that + * causes 0xFFFFFFFF to be written as the return PC value in the + * exception stack frame. The problem is caused by a conflict between + * an internal autovector access and a chip select mapped to the IACK + * address space (0xFFFFXXXX). + * Workaround: + * Set the C/I bit in the chip select mask register (CSMR) for the + * chip select that is mapped to 0xFFFFXXXX. + * This will prevent the chip select from asserting for IACK accesses. + */ + +#define MCF5307_SP_ERR_FIX(cs_base, mask) \ + do { \ + if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \ + 0xffff0000) \ + setbits_be32(&mask, CSMR_CI); \ + } while (0) + +void init_csm(void) +{ + csm_t *csm = (csm_t *)(MMAP_CSM); + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ + defined(CONFIG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#else +#warning "Chip Select 0 are not initialized/used" +#endif +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ + defined(CONFIG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#endif +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ + defined(CONFIG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#endif +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ + defined(CONFIG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#endif +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ + defined(CONFIG_SYS_CS4_CTRL)) + out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK); + out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4); +#endif +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \ + defined(CONFIG_SYS_CS5_CTRL)) + out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK); + out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5); +#endif +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \ + defined(CONFIG_SYS_CS6_CTRL)) + out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK); + out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6); +#endif +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \ + defined(CONFIG_SYS_CS7_CTRL)) + out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK); + out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7); +#endif +} + +/* + * Set up the memory map and initialize registers + */ +void cpu_init_f(void) +{ + sim_t *sim = (sim_t *)(MMAP_SIM); + + out_8(&sim->sypcr, 0x00); + out_8(&sim->swivr, 0x0f); + out_8(&sim->swsr, 0x00); + out_8(&sim->mpark, 0x00); + + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + /* timer 2 not masked */ + out_be32(&icr->imr, 0xfffffbff); + + out_8(&icr->icr0, 0x00); /* sw watchdog */ + out_8(&icr->icr1, 0x00); /* timer 1 */ + out_8(&icr->icr2, 0x88); /* timer 2 */ + out_8(&icr->icr3, 0x00); /* i2c */ + out_8(&icr->icr4, 0x00); /* uart 0 */ + out_8(&icr->icr5, 0x00); /* uart 1 */ + out_8(&icr->icr6, 0x00); /* dma 0 */ + out_8(&icr->icr7, 0x00); /* dma 1 */ + out_8(&icr->icr8, 0x00); /* dma 2 */ + out_8(&icr->icr9, 0x00); /* dma 3 */ + + /* Chipselect Init */ + init_csm(); + + /* enable data/instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return 0; +} + +void uart_port_conf(void) +{ +} + +void arch_preboot_os(void) +{ + /* + * OS can change interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. + */ + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + out_8(&icr->icr1, 0x00); /* timer 1 */ + out_8(&icr->icr2, 0x00); /* timer 2 */ +} +#endif diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c new file mode 100644 index 0000000000..bf4038dff8 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_M5307 +int interrupt_init(void) +{ + enable_interrupts(); + + return 0; +} + +void dtimer_intr_setup(void) +{ + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + /* clearing TIMER2 mask, so enabling the related interrupt */ + out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400); + /* set TIMER2 interrupt priority */ + out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI); +} +#endif diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c new file mode 100644 index 0000000000..3cf1986fc9 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks(void) +{ +#if defined(CONFIG_M5307) + gd->bus_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CONFIG_SYS_CPU_CLK; +#endif + + return 0; +} diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S new file mode 100644 index 0000000000..097958afda --- /dev/null +++ b/arch/m68k/cpu/mcf530x/start.S @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> + * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include "version.h" +#include <asm/cache.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + + +.macro SAVE_ALL + move.w #0x2700,%sr; /* disable intrs */ + subl #60,%sp; /* space for 15 regs */ + moveml %d0-%d7/%a0-%a6,%sp@ +.endm + +.macro RESTORE_ALL + moveml %sp@,%d0-%d7/%a0-%a6; + addl #60,%sp; /* space for 15 regs */ + rte +.endm + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +/* Flash offset is 0 until we setup CS0 */ +.long 0x00000000 +#if defined(CONFIG_M5307) && \ + (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +.long _start - CONFIG_SYS_TEXT_BASE +#else +.long _START +#endif + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + + /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.c %d0, %MBAR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.c %d0, %RAMBAR + + /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ + move.l #CF_CACR_CINVA, %d0 + movec %d0, %CACR + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* + * if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* + * set stackpointer to internal sram end - 80 + * (global data struct size + some bytes) + * get some stackspace for the first c-code, + */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* put relocation table address to a5 */ + move.l #__got_start, %a5 + + /* run low-level CPU init code (from flash) */ + bsr cpu_init_f + + /* run low-level board init code (from flash) */ + bsr board_init_f + + /* board_init_f() does not return */ + +/*--------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1 + /* * fix got pointer register a5 */ + move.l %a1,%a5 + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2 + +7: + move.l (%a1),%d1 + sub.l #_start, %d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) + halt +#endif + jsr (%a1) + +/*--------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + bra _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*--------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 59fa33bb69..812f25c46a 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -15,7 +15,8 @@ #define CONFIG_CF_V2 #endif -#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ + defined(CONFIG_MCF5301x) #define CONFIG_CF_V3 #endif diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 9c4d3fb8fd..7590842881 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -7,6 +7,9 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_GENERIC_GLOBAL_DATA + #define CONFIG_NEEDS_MANUAL_RELOC #define CONFIG_LMB diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f0a76f4377..aca5f3ab2c 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -240,6 +240,30 @@ #endif #endif /* CONFIG_M5282 */ +#ifdef CONFIG_M5307 +#include <asm/immap_5307.h> +#include <asm/m5307.h> + +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ + (CONFIG_SYS_INTR_BASE))->ipr) +#define CONFIG_SYS_TMRINTR_NO (31) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ + MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5307 */ + #if defined(CONFIG_MCF5301x) #include <asm/immap_5301x.h> #include <asm/m5301x.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h new file mode 100644 index 0000000000..c839f4616f --- /dev/null +++ b/arch/m68k/include/asm/immap_5307.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __IMMAP_5307__ +#define __IMMAP_5307__ + +#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) + +typedef struct sim { + u8 rsr; + u8 sypcr; + u8 swivr; + u8 swsr; + u16 par; + u8 irqpar; + u8 res1; + u8 pllcr; + u8 res2; + u16 res3; + u8 mpark; + u8 res4; + u16 res5; + u32 res6; +} sim_t; + +typedef struct intctrl { + u32 ipr; + u32 imr; + u16 res7; + u8 res8; + u8 avr; + u8 icr0; + u8 icr1; + u8 icr2; + u8 icr3; + u8 icr4; + u8 icr5; + u8 icr6; + u8 icr7; + u8 icr8; + u8 icr9; + u16 res9; +} intctrl_t; + +typedef struct csm { + u16 csar0; /* Chip-select Address */ + u16 res1; + u32 csmr0; /* Chip-select Mask */ + u16 res2; + u16 cscr0; /* Chip-select Control */ + u16 csar1; + u16 res3; + u32 csmr1; + u16 res4; + u16 cscr1; + u16 csar2; + u16 res5; + u32 csmr2; + u16 res6; + u16 cscr2; + u16 csar3; + u16 res7; + u32 csmr3; + u16 res8; + u16 cscr3; + u16 csar4; + u16 res9; + u32 csmr4; + u16 res10; + u16 cscr4; + u16 csar5; + u16 res11; + u32 csmr5; + u16 res12; + u16 cscr5; + u16 csar6; + u16 res13; + u32 csmr6; + u16 res14; + u16 cscr6; + u16 csar7; + u16 res15; + u32 csmr7; + u16 res16; + u16 cscr7; +} csm_t; + +typedef struct sdramctrl { + u16 dcr; + u16 res1; + u32 res2; + u32 dacr0; + u32 dmr0; + u32 dacr1; + u32 dmr1; +} sdramctrl_t; + +typedef struct gpio { + u16 paddr; + u16 res1; + u16 padat; + u16 res2; +} gpio_t; + +#endif /* __IMMAP_5307__ */ + diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h new file mode 100644 index 0000000000..8192c46f36 --- /dev/null +++ b/arch/m68k/include/asm/m5307.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef mcf5307_h +#define mcf5307_h + +/* + * Size of internal RAM (RAMBAR) + */ +#define INT_RAM_SIZE 4096 + +/* Bit definitions and macros for SYPCR */ +#define SYPCR_SWTAVAL 0x02 +#define SYPCR_SWTA 0x04 +#define SYPCR_SWT(x) ((x&0x3)<<3) +#define SYPCR_SWP 0x20 +#define SYPCR_SWRI 0x40 +#define SYPCR_SWE 0x80 + +/* Bit definitions and macros for CSMR */ +#define CSMR_V 0x01 +#define CSMR_UD 0x02 +#define CSMR_UC 0x04 +#define CSMR_SD 0x08 +#define CSMR_SC 0x10 +#define CSMR_CI 0x20 +#define CSMR_AM 0x40 +#define CSMR_WP 0x100 + +/* Bit definitions and macros for DACR (SDRAM) */ +#define DACR_PM_CONTINUOUS 0x04 +#define DACR_IP_PRECHG_ALL 0x08 +#define DACR_PORT_SZ_32 0 +#define DACR_PORT_SZ_8 (1<<4) +#define DACR_PORT_SZ_16 (2<<4) +#define DACR_IMRS_INIT_CMD (1<<6) +#define DACR_CMD_PIN(x) ((x&7)<<8) +#define DACR_CASL(x) ((x&3)<<12) +#define DACR_RE (1<<15) + +/* Bit definitions and macros for CSCR */ +#define CSCR_BSTW 0x08 +#define CSCR_BSTR 0x10 +#define CSCR_BEM 0x20 +#define CSCR_PS(x) ((x&0x3)<<6) +#define CSCR_AA 0x100 +#define CSCR_WS ((x&0xf)<<10) + +/* Bit definitions for the ICR family of registers */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + +#endif /* mcf5307_h */ + diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h index 2bdaddc244..8fb3216518 100644 --- a/arch/m68k/include/asm/timer.h +++ b/arch/m68k/include/asm/timer.h @@ -17,7 +17,8 @@ /****************************************************************************/ /* DMA Timer module registers */ typedef struct dtimer_ctrl { -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272) +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ + defined(CONFIG_M5272) || defined(CONFIG_M5307) u16 tmr; /* 0x00 Mode register */ u16 res1; /* 0x02 */ u16 trr; /* 0x04 Reference register */ diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 983cb2d967..911c0d398c 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -20,6 +20,11 @@ * include/asm-ppc/u-boot.h */ +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + #ifndef __ASSEMBLY__ typedef struct bd_info { @@ -48,6 +53,9 @@ typedef struct bd_info { #endif /* __ASSEMBLY__ */ +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_M68K diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 65867d6e47..d0e1a845dd 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o +ifndef CONFIG_SYS_GENERIC_BOARD +obj-y += board.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3d6ec843df..ef08489aa6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -73,6 +73,11 @@ int checkcpu (void) unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); + u32 dsp_mask = cpu_dsp_mask(); +#endif + svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); @@ -166,6 +171,16 @@ int checkcpu (void) printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); } + +#ifdef CONFIG_HETROGENOUS_CLUSTERS + for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { + if (!(j & 3)) + printf("\n "); + printf("DSP CPU%d:%-4s MHz, ", j, + strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); + } +#endif + printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n"); @@ -224,6 +239,19 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif +#if defined(CONFIG_SYS_CPRI) + printf(" "); + printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); +#endif + +#if defined(CONFIG_SYS_MAPLE) + printf("\n "); + printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); + printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); + printf("MAPLE-eTVPE:%-4s MHz\n", + strmhz(buf1, sysinfo.freq_maple_etvpe)); +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 7e698730f3..e24b857672 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -34,6 +34,10 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned int dsp_cpu; + uint rcw_tmp1, rcw_tmp2; +#endif #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; #endif @@ -157,6 +161,7 @@ void get_sys_info(sys_info_t *sys_info) else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } + #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * As per CHASSIS2 architeture total 12 clusters are posible and @@ -181,6 +186,20 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } + +#ifdef CONFIG_HETROGENOUS_CLUSTERS + for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) { + int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu); + u32 c_pll_sel = (in_be32 + (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + cplx_pll += cc_group[dsp_cluster] - 1; + sys_info->freq_processor_dsp[dsp_cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } +#endif + #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 @@ -243,6 +262,127 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; #endif +#if defined(CONFIG_SYS_MAPLE) +#define CPRI_CLK_SEL 0x1C000000 +#define CPRI_CLK_SHIFT 26 +#define CPRI_ALT_CLK_SEL 0x00007000 +#define CPRI_ALT_CLK_SHIFT 12 + + rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ + rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ + /* For MAPLE and CPRI frequency */ + switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) { + case 1: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK]; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK]; + break; + case 2: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; + break; + case 3: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; + break; + case 4: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; + break; + case 5: + if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) + >> CPRI_ALT_CLK_SHIFT) == 6) { + sys_info->freq_maple = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; + sys_info->freq_cpri = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; + } + if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) + >> CPRI_ALT_CLK_SHIFT) == 7) { + sys_info->freq_maple = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; + sys_info->freq_cpri = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; + } + break; + case 6: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; + break; + case 7: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; + break; + default: + printf("Error: Unknown MAPLE/CPRI clock select!\n"); + } + + /* For MAPLE ULB and eTVPE frequencies */ +#define ULB_CLK_SEL 0x00000038 +#define ULB_CLK_SHIFT 3 +#define ETVPE_CLK_SEL 0x00000007 +#define ETVPE_CLK_SHIFT 0 + + switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) { + case 1: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK]; + break; + case 2: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2; + break; + case 3: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3; + break; + case 4: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4; + break; + case 5: + sys_info->freq_maple_ulb = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_maple_ulb = + freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2; + break; + case 7: + sys_info->freq_maple_ulb = + freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3; + break; + default: + printf("Error: Unknown MAPLE ULB clock select!\n"); + } + + switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) { + case 1: + sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK]; + break; + case 2: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2; + break; + case 3: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3; + break; + case 4: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4; + break; + case 5: + sys_info->freq_maple_etvpe = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2; + break; + case 7: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3; + break; + default: + printf("Error: Unknown MAPLE eTVPE clock select!\n"); + } + +#endif + #ifdef CONFIG_SYS_DPAA_FMAN #ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index c92589fb9d..584f3b8d61 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -133,6 +133,53 @@ u32 compute_ppc_cpumask(void) return mask; } +#ifdef CONFIG_HETROGENOUS_CLUSTERS +u32 compute_dsp_cpumask(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int i = CONFIG_DSP_CLUSTER_START, count = 0; + u32 cluster, type, dsp_mask = 0; + + do { + int j; + cluster = in_be32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = init_type(cluster, j); + if (type) { + if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC) + dsp_mask |= 1 << count; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return dsp_mask; +} + +int fsl_qoriq_dsp_core_to_cluster(unsigned int core) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int count = 0, i = CONFIG_DSP_CLUSTER_START; + u32 cluster; + + do { + int j; + cluster = in_be32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + if (init_type(cluster, j)) { + if (count == core) + return i; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} +#endif + int fsl_qoriq_core_to_cluster(unsigned int core) { ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -198,8 +245,43 @@ __weak u32 cpu_mask(void) return cpu->mask; } +#ifdef CONFIG_HETROGENOUS_CLUSTERS +__weak u32 cpu_dsp_mask(void) +{ + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + struct cpu_type *cpu = gd->arch.cpu; + + /* better to query feature reporting register than just assume 1 */ + if (cpu == &cpu_type_unknown) + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; + + if (cpu->dsp_num_cores == 0) + return compute_dsp_cpumask(); + + return cpu->dsp_mask; +} + /* - * Return the number of cores on this SOC. + * Return the number of SC/DSP cores on this SOC. + */ +__weak int cpu_num_dspcores(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + /* + * Report # of cores in terms of the cpu_mask if we haven't + * figured out how many there are yet + */ + if (cpu->dsp_num_cores == 0) + return hweight32(cpu_dsp_mask()); + + return cpu->dsp_num_cores; +} +#endif + +/* + * Return the number of PPC cores on this SOC. */ __weak int cpu_numcores(void) { @@ -215,6 +297,7 @@ __weak int cpu_numcores(void) return cpu->num_cores; } + /* * Check if the given core ID is valid * @@ -248,6 +331,12 @@ int fixup_cpu(void) cpu->num_cores = cpu_numcores(); } +#ifdef CONFIG_HETROGENOUS_CLUSTERS + if (cpu->dsp_num_cores == 0) { + cpu->dsp_mask = cpu_dsp_mask(); + cpu->dsp_num_cores = cpu_num_dspcores(); + } +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 01b09058cc..69e05923f6 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -25,6 +25,8 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SEC_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SEC_MON_BE /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -201,7 +203,7 @@ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -285,7 +287,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -689,13 +691,22 @@ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ +#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ +#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_MAPLE +#define CONFIG_SYS_CPRI +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_CPRI_CLK 3 +#define CONFIG_SYS_ULB_CLK 4 +#define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 @@ -718,8 +729,9 @@ #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 +#define CONFIG_MAX_DSP_CPUS 12 +#define CONFIG_NUM_DSP_CPUS 6 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -731,9 +743,9 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_DSP_CPUS 2 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index b4c0c99b39..49f6814383 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -6,6 +6,19 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H +#include <asm/config_mpc85xx.h> + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif +#endif #ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) @@ -28,9 +41,31 @@ defined(CONFIG_PPC_T1023) || \ defined(CONFIG_PPC_T1024) #define CONFIG_SYS_CPC_REINIT_F +#define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif +#if defined(CONFIG_C29XPCIE) +#define CONFIG_KEY_REVOCATION +#endif + +#if defined(CONFIG_PPC_P3041) || \ + defined(CONFIG_PPC_P4080) || \ + defined(CONFIG_PPC_P5020) || \ + defined(CONFIG_PPC_P5040) || \ + defined(CONFIG_PPC_P2041) + #define CONFIG_FSL_TRUST_ARCH_v1 +#endif + +#if defined(CONFIG_FSL_CORENET) +/* The key used for verification of next level images + * is picked up from an Extension Table which has + * been verified by the ISBC (Internal Secure boot Code) + * in boot ROM of the SoC + */ +#define CONFIG_FSL_ISBC_KEY_EXT +#endif + #endif #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index ace1d120c6..0c9d85ec96 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -17,6 +17,7 @@ #include <asm/fsl_i2c.h> #include <fsl_ifc.h> #include <fsl_sec.h> +#include <fsl_sfp.h> #include <asm/fsl_lbc.h> #include <asm/fsl_fman.h> #include <fsl_immap.h> @@ -2823,21 +2824,6 @@ struct ccsr_pman { u8 res_f4[0xf0c]; }; #endif -#ifdef CONFIG_SYS_FSL_SFP_VER_3_0 -struct ccsr_sfp_regs { - u32 ospr; /* 0x200 */ - u32 reserved0[14]; - u32 srk_hash[8]; /* 0x23c Super Root Key Hash */ - u32 oem_uid; /* 0x9c OEM Unique ID */ - u8 reserved2[0x04]; - u32 ovpr; /* 0xA4 Intent To Secure */ - u8 reserved4[0x08]; - u32 fsl_uid; /* 0xB0 FSL Unique ID */ - u8 reserved5[0x04]; - u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */ - u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */ -}; -#endif #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 @@ -2897,6 +2883,7 @@ struct ccsr_sfp_regs { #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 +#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2964,7 +2951,7 @@ struct ccsr_sfp_regs { #endif #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SNVS_OFFSET 0xE6000 +#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 #define CONFIG_SYS_SFP_OFFSET 0xE7000 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 @@ -3094,6 +3081,9 @@ struct ccsr_sfp_regs { #define CONFIG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CONFIG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) + #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index db8cc8c4e6..fdfca9086f 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1202,12 +1202,17 @@ struct cpu_type { u32 soc_ver; u32 num_cores; u32 mask; /* which cpu(s) actually exist */ +#ifdef CONFIG_HETROGENOUS_CLUSTERS + u32 dsp_num_cores; + u32 dsp_mask; /* which DSP cpu(s) actually exist */ +#endif }; struct cpu_type *identify_cpu(u32 ver); int fixup_cpu(void); int fsl_qoriq_core_to_cluster(unsigned int core); +int fsl_qoriq_dsp_core_to_cluster(unsigned int core); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ |