diff options
Diffstat (limited to 'arch')
30 files changed, 347 insertions, 499 deletions
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 204d0cd9d4..3e1b0c9514 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -106,6 +106,13 @@ _reloc: stw r0, 4(sp) mov fp, sp +#ifdef CONFIG_DEBUG_UART + /* Set up the debug UART */ + movhi r2, %hi(debug_uart_init@h) + ori r2, r2, %lo(debug_uart_init@h) + callr r2 +#endif + /* Allocate and initialize reserved area, update SP */ mov r4, sp movhi r2, %hi(board_init_f_alloc_reserve@h) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a995e32bb9..49e173c820 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -93,9 +93,6 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 -config DM_PCI_COMPAT - default y # Until we finish moving over to the new API - config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024 diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 0b36ace091..2950783055 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -16,19 +16,18 @@ DECLARE_GLOBAL_DATA_PTR; -static struct irq_router irq_router; static struct irq_routing_table *pirq_routing_table; -bool pirq_check_irq_routed(int link, u8 irq) +bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { + struct irq_router *priv = dev_get_priv(dev); u8 pirq; - int base = irq_router.link_base; + int base = priv->link_base; - if (irq_router.config == PIRQ_VIA_PCI) - pirq = x86_pci_read_config8(irq_router.bdf, - LINK_N2V(link, base)); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); else - pirq = readb(irq_router.ibase + LINK_N2V(link, base)); + pirq = readb(priv->ibase + LINK_N2V(link, base)); pirq &= 0xf; @@ -39,24 +38,26 @@ bool pirq_check_irq_routed(int link, u8 irq) return pirq == irq ? true : false; } -int pirq_translate_link(int link) +int pirq_translate_link(struct udevice *dev, int link) { - return LINK_V2N(link, irq_router.link_base); + struct irq_router *priv = dev_get_priv(dev); + + return LINK_V2N(link, priv->link_base); } -void pirq_assign_irq(int link, u8 irq) +void pirq_assign_irq(struct udevice *dev, int link, u8 irq) { - int base = irq_router.link_base; + struct irq_router *priv = dev_get_priv(dev); + int base = priv->link_base; /* IRQ# 0/1/2/8/13 are reserved */ if (irq < 3 || irq == 8 || irq == 13) return; - if (irq_router.config == PIRQ_VIA_PCI) - x86_pci_write_config8(irq_router.bdf, - LINK_N2V(link, base), irq); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); else - writeb(irq, irq_router.ibase + LINK_N2V(link, base)); + writeb(irq, priv->ibase + LINK_N2V(link, base)); } static struct irq_info *check_dup_entry(struct irq_info *slot_base, @@ -74,46 +75,40 @@ static struct irq_info *check_dup_entry(struct irq_info *slot_base, return (i == entry_num) ? NULL : slot; } -static inline void fill_irq_info(struct irq_info *slot, int bus, int device, - int pin, int pirq) +static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, + int bus, int device, int pin, int pirq) { slot->bus = bus; slot->devfn = (device << 3) | 0; - slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base); - slot->irq[pin - 1].bitmap = irq_router.irq_mask; + slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); + slot->irq[pin - 1].bitmap = priv->irq_mask; } static int create_pirq_routing_table(struct udevice *dev) { + struct irq_router *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; - struct fdt_pci_addr addr; int node; int len, count; const u32 *cell; struct irq_routing_table *rt; struct irq_info *slot, *slot_base; int irq_entries = 0; - int parent; int i; int ret; node = dev->of_offset; - parent = dev->parent->of_offset; - ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG, - "reg", &addr); - if (ret) - return ret; /* extract the bdf from fdt_pci_addr */ - irq_router.bdf = addr.phys_hi & 0xffff00; + priv->bdf = dm_pci_get_bdf(dev->parent); ret = fdt_find_string(blob, node, "intel,pirq-config", "pci"); if (!ret) { - irq_router.config = PIRQ_VIA_PCI; + priv->config = PIRQ_VIA_PCI; } else { ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase"); if (!ret) - irq_router.config = PIRQ_VIA_IBASE; + priv->config = PIRQ_VIA_IBASE; else return -EINVAL; } @@ -121,12 +116,12 @@ static int create_pirq_routing_table(struct udevice *dev) ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); if (ret == -1) return ret; - irq_router.link_base = ret; + priv->link_base = ret; - irq_router.irq_mask = fdtdec_get_int(blob, node, - "intel,pirq-mask", PIRQ_BITMAP); + priv->irq_mask = fdtdec_get_int(blob, node, + "intel,pirq-mask", PIRQ_BITMAP); - if (irq_router.config == PIRQ_VIA_IBASE) { + if (priv->config == PIRQ_VIA_IBASE) { int ibase_off; ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0); @@ -143,9 +138,8 @@ static int create_pirq_routing_table(struct udevice *dev) * 2) memory range decoding is enabled. * Hence we don't do any santify test here. */ - irq_router.ibase = x86_pci_read_config32(irq_router.bdf, - ibase_off); - irq_router.ibase &= ~0xf; + dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); + priv->ibase &= ~0xf; } cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); @@ -160,9 +154,8 @@ static int create_pirq_routing_table(struct udevice *dev) /* Populate the PIRQ table fields */ rt->signature = PIRQ_SIGNATURE; rt->version = PIRQ_VERSION; - rt->rtr_bus = PCI_BUS(irq_router.bdf); - rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) | - PCI_FUNC(irq_router.bdf); + rt->rtr_bus = PCI_BUS(priv->bdf); + rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf); rt->rtr_vendor = PCI_VENDOR_ID_INTEL; rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; @@ -199,7 +192,7 @@ static int create_pirq_routing_table(struct udevice *dev) * routing information in the device tree. */ if (slot->irq[pr.pin - 1].link != - LINK_N2V(pr.pirq, irq_router.link_base)) + LINK_N2V(pr.pirq, priv->link_base)) debug("WARNING: Inconsistent PIRQ routing information\n"); continue; } @@ -207,8 +200,8 @@ static int create_pirq_routing_table(struct udevice *dev) slot = slot_base + irq_entries++; } debug("writing INT%c\n", 'A' + pr.pin - 1); - fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin, - pr.pirq); + fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), + pr.pin, pr.pirq); } rt->size = irq_entries * sizeof(struct irq_info) + 32; @@ -228,7 +221,7 @@ int irq_router_common_init(struct udevice *dev) return ret; } /* Route PIRQ */ - pirq_route_irqs(pirq_routing_table->slots, + pirq_route_irqs(dev, pirq_routing_table->slots, get_irq_slot_count(pirq_routing_table)); return 0; @@ -257,6 +250,7 @@ U_BOOT_DRIVER(irq_router_drv) = { .id = UCLASS_IRQ, .of_match = irq_router_ids, .probe = irq_router_probe, + .priv_auto_alloc_size = sizeof(struct irq_router), }; UCLASS_DRIVER(irq) = { diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 2b172d49ba..996707b7fe 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,6 +19,7 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> +#define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc static int pch_revision_id = -1; @@ -170,7 +171,7 @@ static int bd82x6x_probe(struct udevice *dev) return 0; } -static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) +static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) { u32 rcba; @@ -182,11 +183,6 @@ static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) return 0; } -static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) -{ - return PCHV_9; -} - static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) { uint8_t bios_cntl; @@ -205,10 +201,41 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops bd82x6x_pch_ops = { - .get_sbase = bd82x6x_pch_get_sbase, - .get_version = bd82x6x_pch_get_version, + .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, + .get_gpio_base = bd82x6x_get_gpio_base, }; static const struct udevice_id bd82x6x_ids[] = { diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 7a312602a0..c9c7637fa7 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -19,59 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pci_controller *get_hose(void) -{ - if (gd->hose) - return gd->hose; - - return pci_bus_to_hose(0); -} - -unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where) -{ - uint8_t value; - - if (pci_hose_read_config_byte(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where) -{ - uint16_t value; - - if (pci_hose_read_config_word(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where) -{ - uint32_t value; - - if (pci_hose_read_config_dword(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_byte(get_hose(), dev, where, value); -} - -void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_word(get_hose(), dev, where, value); -} - -void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_dword(get_hose(), dev, where, value); -} - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { @@ -119,11 +66,11 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) for (func = 0; func < 8; func++) { bdf = PCI_BDF(bus, device, func); - vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID); + pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); if (vendor == 0xffff || vendor == 0x0000) continue; - pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); /* PCI spec says all values except 1..4 are reserved */ if ((pin < 1) || (pin > 4)) @@ -136,6 +83,6 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", line, bus, device, func, 'A' + pin - 1); - x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); } } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index f8af566dea..7ad0ee49a1 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -5,8 +5,8 @@ */ #include <common.h> +#include <pci.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> @@ -21,23 +21,23 @@ static void enable_pm_piix(void) u16 cmd; /* Set the PM I/O base */ - x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); /* Enable access to the PM I/O space */ - cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND); + pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_IO; - x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); + pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); /* PM I/O Space Enable (PMIOSE) */ - en = x86_pci_read_config8(PIIX_PM, PMREGMISC); + pci_read_config8(PIIX_PM, PMREGMISC, &en); en |= PMIOSE; - x86_pci_write_config8(PIIX_PM, PMREGMISC, en); + pci_write_config8(PIIX_PM, PMREGMISC, en); } static void enable_pm_ich9(void) { /* Set the PM I/O base */ - x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); } static void qemu_chipset_init(void) @@ -50,7 +50,7 @@ static void qemu_chipset_init(void) * the same bitfield layout. Here we determine the offset based on its * PCI device ID. */ - device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); i440fx = (device == PCI_DEVICE_ID_INTEL_82441); pam = i440fx ? I440FX_PAM : Q35_PAM; @@ -60,7 +60,7 @@ static void qemu_chipset_init(void) * Configure legacy segments C/D/E/F to system RAM */ for (i = 0; i < PAM_NUM; i++) - x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); if (i440fx) { /* @@ -71,19 +71,19 @@ static void qemu_chipset_init(void) * registers to see whether legacy ports decode is turned on. * This is to make Linux ata_piix driver happy. */ - x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); - x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); /* Enable I/O APIC */ - xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + pci_read_config16(PIIX_ISA, XBCS, &xbcs); xbcs |= APIC_EN; - x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + pci_write_config16(PIIX_ISA, XBCS, xbcs); enable_pm_piix(); } else { /* Configure PCIe ECAM base address */ - x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, - CONFIG_PCIE_ECAM_BASE | BAR_EN); + pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); enable_pm_ich9(); } @@ -136,8 +136,8 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) * connected to I/O APIC INTPIN#16-19. Instead they are routed * to an irq number controled by the PIRQ routing register. */ - irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), - PCI_INTERRUPT_LINE); + pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE, &irq); } else { /* * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 49d803d794..fac2d72e0d 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -12,6 +12,7 @@ #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/arch/quark.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" @@ -106,8 +107,8 @@ void select_hte(void) */ void dram_init_command(uint32_t data) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0); DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data); diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 6e20930a4d..afb3463797 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -20,21 +20,6 @@ static struct pci_device_id mmc_supported[] = { {}, }; -/* - * TODO: - * - * This whole routine should be removed until we fully convert the ICH SPI - * driver to DM and make use of DT to pass the bios control register offset - */ -static void unprotect_spi_flash(void) -{ - u32 bc; - - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); - bc |= 0x1; /* unprotect the flash */ - qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); -} - static void quark_setup_mtrr(void) { u32 base, mask; @@ -259,8 +244,6 @@ int arch_cpu_init(void) /* Turn on legacy segments (A/B/E/F) decode to system RAM */ quark_enable_legacy_seg(); - unprotect_spi_flash(); - return 0; } diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c index 44369f7ec7..63d0f35a29 100644 --- a/arch/x86/cpu/queensbay/irq.c +++ b/arch/x86/cpu/queensbay/irq.c @@ -18,7 +18,7 @@ int queensbay_irq_router_probe(struct udevice *dev) struct tnc_rcba *rcba; u32 base; - base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); + dm_pci_read_config32(dev->parent, LPC_RCBA, &base); base &= ~MEM_BAR_EN; rcba = (struct tnc_rcba *)base; diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 75f7adb74c..b226e4c5fd 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -5,26 +5,34 @@ */ #include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <pci.h> #include <asm/io.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/arch/device.h> #include <asm/arch/tnc.h> #include <asm/fsp/fsp_support.h> #include <asm/processor.h> -static void unprotect_spi_flash(void) +static int __maybe_unused disable_igd(void) { - u32 bc; + struct udevice *igd, *sdvo; + int ret; - bc = x86_pci_read_config32(TNC_LPC, 0xd8); - bc |= 0x1; /* unprotect the flash */ - x86_pci_write_config32(TNC_LPC, 0xd8, bc); -} + ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); + if (ret) + return ret; + if (!igd) + return 0; + + ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); + if (ret) + return ret; + if (!sdvo) + return 0; -static void __maybe_unused disable_igd(void) -{ /* * According to Atom E6xx datasheet, setting VGA Disable (bit17) * of Graphics Controller register (offset 0x50) prevents IGD @@ -43,8 +51,45 @@ static void __maybe_unused disable_igd(void) * two devices will be completely disabled (invisible in the PCI * configuration space) unless a system reset is performed. */ - x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); - x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); + + /* + * After setting the function disable bit, IGD and SDVO devices will + * disappear in the PCI configuration space. This however creates an + * inconsistent state from a driver model PCI controller point of view, + * as these two PCI devices are still attached to its parent's child + * device list as maintained by the driver model. Some driver model PCI + * APIs like dm_pci_find_class(), are referring to the list to speed up + * the finding process instead of re-enumerating the whole PCI bus, so + * it gets the stale cached data which is wrong. + * + * Note x86 PCI enueration normally happens twice, in pre-relocation + * phase and post-relocation. One option might be to call disable_igd() + * in one of the pre-relocation initialization hooks so that it gets + * disabled in the first round, and when it comes to the second round + * driver model PCI will construct a correct list. Unfortunately this + * does not work as Intel FSP is used on this platform to perform low + * level initialization, and fsp_init_phase_pci() is called only once + * in the post-relocation phase. If we disable IGD and SDVO devices, + * fsp_init_phase_pci() simply hangs and never returns. + * + * So the only option we have is to manually remove these two devices. + */ + ret = device_remove(igd); + if (ret) + return ret; + ret = device_unbind(igd); + if (ret) + return ret; + ret = device_remove(sdvo); + if (ret) + return ret; + ret = device_unbind(sdvo); + if (ret) + return ret; + + return 0; } int arch_cpu_init(void) @@ -62,16 +107,11 @@ int arch_cpu_init(void) int arch_early_init_r(void) { + int ret = 0; + #ifdef CONFIG_DISABLE_IGD - disable_igd(); + ret = disable_igd(); #endif - return 0; -} - -int arch_misc_init(void) -{ - unprotect_spi_flash(); - - return 0; + return ret; } diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index fbca46762c..4ea9262251 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,48 +65,6 @@ }; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x20>; - bank-name = "C"; - }; - - gpiod { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x60 0x20>; - bank-name = "D"; - }; - - gpioe { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x80 0x20>; - bank-name = "E"; - }; - - gpiof { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0xA0 0x20>; - bank-name = "F"; - }; - pci { compatible = "pci-x86"; #address-cells = <3>; @@ -119,6 +77,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,irq-router"; @@ -187,7 +147,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -201,6 +161,48 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; }; }; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 7b2c51504b..4bb0a34b5f 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -37,7 +37,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { reg = <0>; compatible = "winbond,w25q128", "spi-flash"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 58072031df..f85e55cd6d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -54,27 +54,6 @@ }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x10>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x30 0x10>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x10>; - bank-name = "C"; - }; - chosen { stdout-path = "/serial"; }; @@ -255,7 +234,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -270,6 +249,27 @@ }; }; + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + lpc { compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 48f0c77d45..480b36658e 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -18,27 +18,6 @@ no-keyboard; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x10>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x30 0x10>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x10>; - bank-name = "C"; - }; - chosen { stdout-path = "/serial"; }; @@ -55,11 +34,13 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -73,6 +54,27 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; }; }; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 47fab0fda6..337513be57 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -46,20 +46,6 @@ }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - chosen { /* * By default the legacy superio serial port is used as the @@ -162,6 +148,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch7"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,queensbay-irq-router"; @@ -230,7 +218,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich7-spi"; spi-flash@0 { reg = <0>; compatible = "sst,25vf016b", @@ -238,6 +226,20 @@ memory-map = <0xffe00000 0x00200000>; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; }; }; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index dd75fc4dc9..21c36412e2 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -82,6 +82,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch7"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,quark-irq-router"; @@ -118,7 +120,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich7-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -132,21 +134,21 @@ }; }; }; - }; - }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 7afdf6c30b..60bd05afb6 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -29,7 +29,6 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; - io-base = <0x4c>; /* GPIO E0 */ soc_gpio_s5_0@0 { @@ -75,48 +74,6 @@ }; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x20>; - bank-name = "C"; - }; - - gpiod { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x60 0x20>; - bank-name = "D"; - }; - - gpioe { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x80 0x20>; - bank-name = "E"; - }; - - gpiof { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0xA0 0x20>; - bank-name = "F"; - }; - chosen { stdout-path = "/serial"; }; @@ -153,6 +110,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,irq-router"; @@ -221,7 +180,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -235,6 +194,48 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; }; }; diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h deleted file mode 100644 index 4e8987ce5c..0000000000 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h deleted file mode 100644 index 31edef9623..0000000000 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2014, Google Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-efi/gpio.h b/arch/x86/include/asm/arch-efi/gpio.h deleted file mode 100644 index f044f07537..0000000000 --- a/arch/x86/include/asm/arch-efi/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h deleted file mode 100644 index 31edef9623..0000000000 --- a/arch/x86/include/asm/arch-ivybridge/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2014, Google Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-qemu/gpio.h b/arch/x86/include/asm/arch-qemu/gpio.h deleted file mode 100644 index ca8cba4f97..0000000000 --- a/arch/x86/include/asm/arch-qemu/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-quark/gpio.h b/arch/x86/include/asm/arch-quark/gpio.h deleted file mode 100644 index ca8cba4f97..0000000000 --- a/arch/x86/include/asm/arch-quark/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h deleted file mode 100644 index ab4e059131..0000000000 --- a/arch/x86/include/asm/arch-queensbay/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index ed85b08ce7..403851b792 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -7,7 +7,6 @@ #define _X86_GPIO_H_ #include <linux/compiler.h> -#include <asm/arch/gpio.h> #include <asm-generic/gpio.h> struct ich6_bank_platdata { diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index a2945f1aff..f93c840244 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -18,25 +18,6 @@ #ifndef __ASSEMBLY__ -#define DEFINE_PCI_DEVICE_TABLE(_table) \ - const struct pci_device_id _table[] - -struct pci_controller; - -void pci_setup_type1(struct pci_controller *hose); - -/* - * Simple PCI access routines - these work from either the early PCI hose - * or the 'real' one, created after U-Boot has memory available - */ -unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where); -unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where); -unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where); - -void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); -void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); -void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size); diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h index ddc08e11d5..0afcb4615e 100644 --- a/arch/x86/include/asm/pirq_routing.h +++ b/arch/x86/include/asm/pirq_routing.h @@ -72,12 +72,13 @@ static inline int get_irq_slot_count(struct irq_routing_table *rt) * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: link number which represents a PIRQ * @irq: the 8259 IRQ number * @return: true if the irq is already routed to 8259 for a given link, * false elsewise */ -bool pirq_check_irq_routed(int link, u8 irq); +bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq); /** * pirq_translate_link() - Translate a link value @@ -89,10 +90,11 @@ bool pirq_check_irq_routed(int link, u8 irq); * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: platform-specific link value * @return: link number which represents a PIRQ */ -int pirq_translate_link(int link); +int pirq_translate_link(struct udevice *dev, int link); /** * pirq_assign_irq() - Assign an IRQ to a PIRQ link @@ -103,10 +105,11 @@ int pirq_translate_link(int link); * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: link number which represents a PIRQ * @irq: IRQ to which the PIRQ is routed */ -void pirq_assign_irq(int link, u8 irq); +void pirq_assign_irq(struct udevice *dev, int link, u8 irq); /** * pirq_route_irqs() - Route PIRQs to 8259 PIC @@ -117,10 +120,11 @@ void pirq_assign_irq(int link, u8 irq); * The configuration source is taken from a struct irq_info table, the format * of which is defined in PIRQ routing table spec and PCI BIOS spec. * + * @dev: irq router's udevice * @irq: pointer to the base address of the struct irq_info * @num: number of entries in the struct irq_info */ -void pirq_route_irqs(struct irq_info *irq, int num); +void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num); /** * copy_pirq_routing_table() - Copy a PIRQ routing table diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 50bc69a659..4fc19365eb 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,9 +22,6 @@ obj-y += cmd_mtrr.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o -ifndef CONFIG_DM_PCI -obj-$(CONFIG_PCI) += pci_type1.o -endif obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c deleted file mode 100644 index a251adcacd..0000000000 --- a/arch/x86/lib/pci_type1.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Support for type PCI configuration cycles. - * based on pci_indirect.c - */ -#include <common.h> -#include <asm/io.h> -#include <pci.h> -#include <asm/pci.h> - -#define cfg_read(val, addr, op) (*val = op((int)(addr))) -#define cfg_write(val, addr, op) op((val), (int)(addr)) - -#define TYPE1_PCI_OP(rw, size, type, op, mask) \ -static int \ -type1_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), op); \ - return 0; \ -} - -TYPE1_PCI_OP(read, byte, u8 *, inb, 3) -TYPE1_PCI_OP(read, word, u16 *, inw, 2) -TYPE1_PCI_OP(read, dword, u32 *, inl, 0) - -TYPE1_PCI_OP(write, byte, u8, outb, 3) -TYPE1_PCI_OP(write, word, u16, outw, 2) -TYPE1_PCI_OP(write, dword, u32, outl, 0) - -void pci_setup_type1(struct pci_controller *hose) -{ - pci_set_ops(hose, - type1_read_config_byte, - type1_read_config_word, - type1_read_config_dword, - type1_write_config_byte, - type1_write_config_word, - type1_write_config_dword); - - hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; - hose->cfg_data = (unsigned char *)PCI_REG_DATA; -} diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index ba4116908c..3cc6adbbbb 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -14,7 +14,7 @@ static bool irq_already_routed[16]; -static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) +static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap) { int i, link; u8 irq = 0; @@ -33,7 +33,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) continue; for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { - if (pirq_check_irq_routed(link, irq)) { + if (pirq_check_irq_routed(dev, link, irq)) { irq_already_routed[irq] = true; break; } @@ -52,7 +52,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) return irq; } -void pirq_route_irqs(struct irq_info *irq, int num) +void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num) { unsigned char irq_slot[MAX_INTX_ENTRIES]; unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; @@ -80,11 +80,11 @@ void pirq_route_irqs(struct irq_info *irq, int num) } /* translate link value to link number */ - link = pirq_translate_link(link); + link = pirq_translate_link(dev, link); /* yet not routed */ if (!pirq[link]) { - irq = pirq_get_next_free_irq(pirq, bitmap); + irq = pirq_get_next_free_irq(dev, pirq, bitmap); pirq[link] = irq; } else { irq = pirq[link]; @@ -94,7 +94,7 @@ void pirq_route_irqs(struct irq_info *irq, int num) irq_slot[intx] = irq; /* Assign IRQ in the interrupt router */ - pirq_assign_irq(link, irq); + pirq_assign_irq(dev, link, irq); } /* Bus, device, slots IRQs for {A,B,C,D} */ |
