diff options
Diffstat (limited to 'arch')
102 files changed, 1426 insertions, 249 deletions
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3fffe1eec3..c95d1d3b35 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &qspi; }; cpus { @@ -908,7 +909,9 @@ qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 3f9d808091..89feaf3eb7 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -567,7 +567,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "mx66l51235l"; + compatible = "mx66l51235l","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index e4daa991e9..797d411d6f 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -487,7 +487,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index feb3708dc6..e7fecf7656 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -41,6 +41,7 @@ ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; + spi0 = &qspi; }; timer { @@ -1113,8 +1114,11 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index efb544c6bb..a62550f0e0 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -604,7 +604,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index b703c3c1f2..1cc4a96bf4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,7 +11,6 @@ else obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif obj-y += rk_timer.o -obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 3a1491cab3..801548109b 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <debug_uart.h> #include <asm/io.h> #include <asm/arch/grf_rk3036.h> #include <asm/arch/hardware.h> @@ -34,7 +35,7 @@ void board_init_f(ulong dummy) GPIO1C2_MASK << GPIO1C2_SHIFT, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); - rk_uart_init((void *)DEBUG_UART_BASE); + debug_uart_init(); #endif rockchip_timer_init(); sdram_init(); @@ -53,3 +54,9 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } + +void hang(void) +{ + while (1) + ; +} diff --git a/arch/arm/mach-rockchip/rk_early_print.c b/arch/arm/mach-rockchip/rk_early_print.c deleted file mode 100644 index a1c14b0210..0000000000 --- a/arch/arm/mach-rockchip/rk_early_print.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <asm/arch/uart.h> -#include <common.h> - -static struct rk_uart *uart_ptr; - -static void uart_wrtie_byte(char byte) -{ - writel(byte, &uart_ptr->rbr); - while (!(readl(&uart_ptr->lsr) & 0x40)) - ; -} - -void print(char *s) -{ - while (*s) { - if (*s == '\n') - uart_wrtie_byte('\r'); - uart_wrtie_byte(*s); - s++; - } -} - -void print_hex(unsigned int n) -{ - int i; - int temp; - - uart_wrtie_byte('0'); - uart_wrtie_byte('x'); - - for (i = 8; i > 0; i--) { - temp = (n >> (i - 1) * 4) & 0x0f; - if (temp < 10) - uart_wrtie_byte((char)(temp + '0')); - else - uart_wrtie_byte((char)(temp - 10 + 'a')); - } - uart_wrtie_byte('\n'); - uart_wrtie_byte('\r'); -} - -/* - * TODO: since rk3036 only 4K sram to use in SPL, for saving space, - * we implement uart driver this way, we should convert this to use - * ns16550 driver in future, which support DEBUG_UART in the standard way - */ -void rk_uart_init(void *base) -{ - uart_ptr = (struct rk_uart *)base; - writel(0x83, &uart_ptr->lcr); - writel(0x0d, &uart_ptr->rbr); - writel(0x03, &uart_ptr->lcr); - - /* fifo enable, sfe is shadow register of FCR[0] */ - writel(0x01, &uart_ptr->sfe); -} diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fbfb204e6e..48a387c957 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -3,6 +3,7 @@ if TEGRA config TEGRA_COMMON bool "Tegra common options" select DM + select DM_ETH select DM_GPIO select DM_I2C select DM_KEYBOARD diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 9e6ac3a0ff..03256be403 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -70,8 +70,17 @@ config CMD_PINMON config CMD_DDRPHY_DUMP bool "Enable dump command of DDR PHY parameters" + depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \ + ARCH_UNIPHIER_PH1_SLD8 help The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. +config CMD_DDRMPHY_DUMP + bool "Enable dump command of DDR Multi PHY parameters" + depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B + help + The command "ddrmphy" shows the resulting parameters of DDR Multi PHY + training; it is useful for the evaluation of DDR Multi PHY training. + endif diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5b19f93ea9..ea3ae5425e 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -24,8 +24,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o -obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o obj-y += pinctrl/ clk/ diff --git a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h b/arch/arm/mach-uniphier/arm-mpcore.h index cf7cd46c10..cf7cd46c10 100644 --- a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h +++ b/arch/arm/mach-uniphier/arm-mpcore.h diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c index e9d3761fde..f82c7d1f8e 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/bcu-regs.h> -#include <mach/init.h> + +#include "../init.h" +#include "bcu-regs.h" #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c index cb6f862721..75ccd155b0 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/bcu-regs.h> -#include <mach/init.h> + +#include "../init.h" +#include "bcu-regs.h" #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) diff --git a/arch/arm/mach-uniphier/include/mach/bcu-regs.h b/arch/arm/mach-uniphier/bcu/bcu-regs.h index 0dfd94e5d7..0dfd94e5d7 100644 --- a/arch/arm/mach-uniphier/include/mach/bcu-regs.h +++ b/arch/arm/mach-uniphier/bcu/bcu-regs.h diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 198004b59b..020ffcae1d 100644 --- a/arch/arm/mach-uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -5,7 +5,8 @@ */ #include <common.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" int board_init(void) { diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 5e0d246ce4..824da25ac7 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/micro-support-card.h> -#include <mach/soc_info.h> +#include "init.h" +#include "micro-support-card.h" +#include "soc-info.h" int board_early_init_f(void) { diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c index 28c7f82228..b26da3633f 100644 --- a/arch/arm/mach-uniphier/board_early_init_r.c +++ b/arch/arm/mach-uniphier/board_early_init_r.c @@ -5,7 +5,8 @@ */ #include <common.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" int board_early_init_r(void) { diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index d075a11ca2..f12415022b 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -7,7 +7,8 @@ #include <common.h> #include <libfdt.h> #include <linux/kernel.h> -#include <mach/init.h> + +#include "init.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 0797d6e615..be0de8f9a9 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o + +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h index 2ab5a535fa..2ab5a535fa 100644 --- a/arch/arm/mach-uniphier/include/mach/boot-device.h +++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c index f974d9f08d..8334373f08 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sg-regs.h> -#include <mach/sbc-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c index c68cb59fc0..0ec6a08879 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c index c943e12db1..b0f3f9a805 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sg-regs.h> -#include <mach/sbc-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NONE, "Reserved"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c index 10a47c6fcc..de12953585 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c @@ -7,10 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index c6cafa7919..0c5749badb 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -6,10 +6,10 @@ #include <common.h> #include <spl.h> -#include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/soc_info.h> + +#include "../sbc/sbc-regs.h" +#include "../soc-info.h" +#include "boot-device.h" u32 spl_boot_device(void) { diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index b15ee9dd60..3ff756b7dd 100644 --- a/arch/arm/mach-uniphier/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -5,9 +5,10 @@ */ #include <common.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/soc_info.h> + +#include "../sbc/sbc-regs.h" +#include "../soc-info.h" +#include "boot-device.h" static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index bf85ad6fd9..b4ca8b6934 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/io.h> #include <asm/armv7.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" #ifdef CONFIG_UNIPHIER_L2CACHE_ON static void uniphier_cache_maint_all(u32 operation) diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c index 8b95fbb008..4de9bfb102 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_ld4_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c index 2e1b20a423..3df017edd2 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_pro4_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c index f78edbbe3f..039da737d0 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_pro5_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-proxstream2.c b/arch/arm/mach-uniphier/clk/clk-proxstream2.c index b494021ecf..a528f048f7 100644 --- a/arch/arm/mach-uniphier/clk/clk-proxstream2.c +++ b/arch/arm/mach-uniphier/clk/clk-proxstream2.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void proxstream2_clk_init(void) { diff --git a/arch/arm/mach-uniphier/cmd_ddrmphy.c b/arch/arm/mach-uniphier/cmd_ddrmphy.c new file mode 100644 index 0000000000..c18f099f2c --- /dev/null +++ b/arch/arm/mach-uniphier/cmd_ddrmphy.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "ddrmphy-regs.h" + +/* Select either decimal or hexadecimal */ +#if 1 +#define PRINTF_FORMAT "%2d" +#else +#define PRINTF_FORMAT "%02x" +#endif +/* field separator */ +#define FS " " + +static void __iomem *get_phy_base(int ch) +{ + return (void __iomem *)(0x5b830000 + ch * 0x00200000); +} + +static int get_nr_ch(void) +{ + const struct uniphier_board_data *bd = uniphier_get_board_param(); + + return bd->dram_ch2_width ? 3 : 2; +} + +static int get_nr_datx8(int ch) +{ + unsigned int width; + + const struct uniphier_board_data *bd = uniphier_get_board_param(); + + switch (ch) { + case 0: + width = bd->dram_ch0_width; + break; + case 1: + width = bd->dram_ch1_width; + break; + default: + width = bd->dram_ch2_width; + break; + } + + return width / 8; +} + +static void print_bdl(void __iomem *reg, int n) +{ + u32 val = readl(reg); + int i; + + for (i = 0; i < n; i++) + printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f); +} + +static void dump_loop(void (*callback)(void __iomem *)) +{ + int ch, dx, nr_ch, nr_dx; + void __iomem *dx_base; + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + dx_base = get_phy_base(ch) + DMPHY_DX_BASE; + nr_dx = get_nr_datx8(ch); + + for (dx = 0; dx < nr_dx; dx++) { + printf("CH%dDX%d:", ch, dx); + (*callback)(dx_base); + dx_base += DMPHY_DX_STRIDE; + printf("\n"); + } + } +} + +static void zq_dump(void) +{ + int ch, zq, nr_ch, nr_zq, i; + void __iomem *zq_base; + u32 dr, pr; + + printf("\n--- Impedance Data ---\n"); + printf(" ZPD ZPU OPD OPU ZDV ODV\n"); + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE; + nr_zq = 3; + + for (zq = 0; zq < nr_zq; zq++) { + printf("CH%dZQ%d:", ch, zq); + + dr = readl(zq_base + DMPHY_ZQ_DR); + for (i = 0; i < 4; i++) { + printf(FS PRINTF_FORMAT, dr & 0x7f); + dr >>= 7; + } + + pr = readl(zq_base + DMPHY_ZQ_PR); + for (i = 0; i < 2; i++) { + printf(FS PRINTF_FORMAT, pr & 0xf); + pr >>= 4; + } + + zq_base += DMPHY_ZQ_STRIDE; + printf("\n"); + } + } +} + +static void __wbdl_dump(void __iomem *dx_base) +{ + print_bdl(dx_base + DMPHY_DX_BDLR0, 4); + print_bdl(dx_base + DMPHY_DX_BDLR1, 4); + print_bdl(dx_base + DMPHY_DX_BDLR2, 2); + + printf(FS "(+" PRINTF_FORMAT ")", + readl(dx_base + DMPHY_DX_LCDLR1) & 0xff); +} + +static void wbdl_dump(void) +{ + printf("\n--- Write Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); + + dump_loop(&__wbdl_dump); +} + +static void __rbdl_dump(void __iomem *dx_base) +{ + print_bdl(dx_base + DMPHY_DX_BDLR3, 4); + print_bdl(dx_base + DMPHY_DX_BDLR4, 4); + print_bdl(dx_base + DMPHY_DX_BDLR5, 1); + + printf(FS "(+" PRINTF_FORMAT ")", + (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff); + + printf(FS "(+" PRINTF_FORMAT ")", + (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff); +} + +static void rbdl_dump(void) +{ + printf("\n--- Read Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n"); + + dump_loop(&__rbdl_dump); +} + +static void __wld_dump(void __iomem *dx_base) +{ + int rank; + u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0); + u32 gtr = readl(dx_base + DMPHY_DX_GTR); + + for (rank = 0; rank < 4; rank++) { + u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ + u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ + + printf(FS PRINTF_FORMAT "%sT", wld, + wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1"); + } +} + +static void wld_dump(void) +{ + printf("\n--- Write Leveling Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__wld_dump); +} + +static void __dqsgd_dump(void __iomem *dx_base) +{ + int rank; + u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2); + u32 gtr = readl(dx_base + DMPHY_DX_GTR); + + for (rank = 0; rank < 4; rank++) { + u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ + u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ + + printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl); + } +} + +static void dqsgd_dump(void) +{ + printf("\n--- DQS Gating Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__dqsgd_dump); +} + +static void __mdl_dump(void __iomem *dx_base) +{ + int i; + u32 mdl = readl(dx_base + DMPHY_DX_MDLR); + + for (i = 0; i < 3; i++) + printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); +} + +static void mdl_dump(void) +{ + printf("\n--- Master Delay Line ---\n"); + printf(" IPRD TPRD MDLD\n"); + + dump_loop(&__mdl_dump); +} + +#define REG_DUMP(x) \ + { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \ + printf("%3d: %-10s: %p : %08x\n", \ + ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); } + +#define DX_REG_DUMP(dx, x) \ + { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \ + DMPHY_DX_## x; \ + void __iomem *reg = phy_base + ofst; \ + printf("%3d: DX%d%-7s: %p : %08x\n", \ + ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); } + +static void reg_dump(void) +{ + int ch, dx, nr_ch, nr_dx; + void __iomem *phy_base; + + printf("\n--- DDR PHY registers ---\n"); + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + phy_base = get_phy_base(ch); + nr_dx = get_nr_datx8(ch); + + printf("== Ch%d ==\n", ch); + printf(" No: Name : Address : Data\n"); + + REG_DUMP(RIDR); + REG_DUMP(PIR); + REG_DUMP(PGCR0); + REG_DUMP(PGCR1); + REG_DUMP(PGCR2); + REG_DUMP(PGCR3); + REG_DUMP(PGSR0); + REG_DUMP(PGSR1); + REG_DUMP(PLLCR); + REG_DUMP(PTR0); + REG_DUMP(PTR1); + REG_DUMP(PTR2); + REG_DUMP(PTR3); + REG_DUMP(PTR4); + REG_DUMP(ACMDLR); + REG_DUMP(ACBDLR0); + REG_DUMP(DXCCR); + REG_DUMP(DSGCR); + REG_DUMP(DCR); + REG_DUMP(DTPR0); + REG_DUMP(DTPR1); + REG_DUMP(DTPR2); + REG_DUMP(DTPR3); + REG_DUMP(MR0); + REG_DUMP(MR1); + REG_DUMP(MR2); + REG_DUMP(MR3); + + for (dx = 0; dx < nr_dx; dx++) { + DX_REG_DUMP(dx, GCR0); + DX_REG_DUMP(dx, GCR1); + DX_REG_DUMP(dx, GCR2); + DX_REG_DUMP(dx, GCR3); + DX_REG_DUMP(dx, GTR); + } + } +} + +static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + + if (argc == 1) + cmd = "all"; + + if (!strcmp(cmd, "zq") || !strcmp(cmd, "all")) + zq_dump(); + + if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) + wbdl_dump(); + + if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) + rbdl_dump(); + + if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) + wld_dump(); + + if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) + dqsgd_dump(); + + if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) + mdl_dump(); + + if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) + reg_dump(); + + return 0; +} + +U_BOOT_CMD( + ddrm, 2, 1, do_ddrm, + "UniPhier DDR PHY parameters dumper", + "- dump all of the followings\n" + "ddrm zq - dump Impedance Data\n" + "ddrm wbdl - dump Write Bit Delay\n" + "ddrm rbdl - dump Read Bit Delay\n" + "ddrm wld - dump Write Leveling\n" + "ddrm dqsgd - dump DQS Gating Delay\n" + "ddrm mdl - dump Master Delay Line\n" + "ddrm reg - dump registers\n" +); diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 935b209fa1..4e9d01bafd 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/sg-regs.h> + +#include "sg-regs.h" int print_cpuinfo(void) { diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S index d8c9fe43e3..6aa5f897a1 100644 --- a/arch/arm/mach-uniphier/debug_ll.S +++ b/arch/arm/mach-uniphier/debug_ll.S @@ -8,9 +8,10 @@ #include <linux/serial_reg.h> #include <linux/linkage.h> -#include <mach/bcu-regs.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "bcu/bcu-regs.h" +#include "sc-regs.h" +#include "sg-regs.h" #if !defined(CONFIG_DEBUG_SEMIHOSTING) #include CONFIG_DEBUG_LL_INCLUDE diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index d3a767b525..cab7df1653 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -8,3 +8,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ ddrphy-training.o ddrphy-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ ddrphy-training.o ddrphy-ph1-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o + +obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o +obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index f9b79ab3d9..078eb6f71b 100644 --- a/arch/arm/mach-uniphier/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" /* Select either decimal or hexadecimal */ #if 1 diff --git a/arch/arm/mach-uniphier/dram/ddrmphy-regs.h b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h new file mode 100644 index 0000000000..569504d657 --- /dev/null +++ b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h @@ -0,0 +1,146 @@ +/* + * UniPhier DDR MultiPHY registers + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRMPHY_REGS_H +#define ARCH_DDRMPHY_REGS_H + +#include <linux/bitops.h> + +#define DMPHY_SHIFT 2 + +#define DMPHY_RIDR (0x000 << DMPHY_SHIFT) +#define DMPHY_PIR (0x001 << DMPHY_SHIFT) +#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */ +#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ +#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ +#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */ +#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */ +#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ +#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ +#define DMPHY_PIR_WL BIT(9) /* Write Leveling */ +#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ +#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ +#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ +#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ +#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ +#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ +#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ +#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ +#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT) +#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ +#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT) +#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ +#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT) +#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ +#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ +#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT) +#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT) +#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ +#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ +#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ +#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ +#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ +#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ +#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ +#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ +#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ +#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ +#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ +#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ +#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ +#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ +#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ +#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ +#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ +#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ +#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ +#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ +#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT) +#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ +#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT) +#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT) +#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT) +#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT) +#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT) +#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT) +#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT) +#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT) +#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT) +#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT) +#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT) +#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT) +#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT) +#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT) +#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT) +#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT) +#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT) +#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT) +#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT) +#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT) +#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT) +#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT) +#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT) +#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT) +#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT) +#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT) +#define DMPHY_DCR (0x022 << DMPHY_SHIFT) +#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT) +#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT) +#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT) +#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT) +#define DMPHY_MR0 (0x027 << DMPHY_SHIFT) +#define DMPHY_MR1 (0x028 << DMPHY_SHIFT) +#define DMPHY_MR2 (0x029 << DMPHY_SHIFT) +#define DMPHY_MR3 (0x02A << DMPHY_SHIFT) +#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT) +#define DMPHY_DTCR (0x02C << DMPHY_SHIFT) +#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT)) +#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT) +#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT) +#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT) +#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT) +#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT) +#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT) +#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT) +#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT) +#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT) +#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ +#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ +/* ZQ */ +#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT) +#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT) +#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT) +#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT) +#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT) +/* DATX8 */ +#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT) +#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT) +#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT) +#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ +#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT)) +#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT) +#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT) +#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT) +#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT) +#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT) +#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT) +#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT) +#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT) +#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT) +#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT) +#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT) + +#endif /* ARCH_DDRMPHY_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 991d9294fd..d2bc5a15d4 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -6,7 +6,8 @@ #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index bc47ba3280..2c8cbc2579 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -6,7 +6,8 @@ #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 39024a09d5..651069073c 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c @@ -7,7 +7,8 @@ #include <config.h> #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 03aedc2e63..03aedc2e63 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h diff --git a/arch/arm/mach-uniphier/dram/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c index 4852f2dec8..a3481363fe 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-training.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 81246850b3..ffd7aa97b2 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 8c9f0579fc..4d976e3a97 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index bc60a3472e..09f9ccfb43 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c new file mode 100644 index 0000000000..63a84e68c0 --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -0,0 +1,669 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by: + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/processor.h> + +#include "../init.h" +#include "../soc-info.h" +#include "ddrmphy-regs.h" + +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00083004 + +/* UD registers */ +#define UMC_BITPERPIXELMODE_D0 0x010 +#define UMC_PAIR1DOFF_D0 0x054 + +/* DC registers */ +#define UMC_INITSET 0x014 +#define UMC_INITSTAT 0x018 +#define UMC_CMDCTLA 0x000 +#define UMC_CMDCTLB 0x004 +#define UMC_SPCCTLA 0x030 +#define UMC_SPCCTLB 0x034 +#define UMC_SPCSETB 0x03c +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ +#define UMC_ACSSETA 0x060 +#define UMC_FLOWCTLA 0x400 +#define UMC_FLOWCTLB 0x404 +#define UMC_FLOWCTLC 0x408 +#define UMC_FLOWCTLG 0x508 +#define UMC_FLOWCTLOB0 0x520 +#define UMC_FLOWCTLOB1 0x524 +#define UMC_RDATACTL_D0 0x600 +#define UMC_RDATACTL_RADLTY_SHIFT 4 +#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) +#define UMC_RDATACTL_RAD2LTY_SHIFT 8 +#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) +#define UMC_WDATACTL_D0 0x604 +#define UMC_RDATACTL_D1 0x608 +#define UMC_WDATACTL_D1 0x60c +#define UMC_DATASET 0x610 +#define UMC_RESPCTL 0x624 +#define UMC_DCCGCTL 0x720 +#define UMC_ERRMASKA 0x958 +#define UMC_ERRMASKB 0x95c +#define UMC_BSICMAPSET 0x988 +#define UMC_DIOCTLA 0xc00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ +#define UMC_DFICUPDCTLA 0xc20 + +enum dram_freq { + FREQ_1866M, + FREQ_2133M, + FREQ_NR, +}; + +enum dram_size { + SIZE_0, + SIZE_512M, + SIZE_1G, + SIZE_NR, +}; + +static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; +static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; +static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; +static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357}; +static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; +static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88}; +static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0}; +static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00}; +static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; +static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; +static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; + +static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; +/* + * The ch2 is a different generation UMC core. + * The register spec is different, unfortunately. + */ +static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44}; +static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; +static u32 umc_spcctla[FREQ_NR][SIZE_NR] = { + {0x00000000, 0x004A071D, 0x0078071D}, + {0x00000000, 0x0055081E, 0x0089081E}, +}; + +static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B}; +/* The ch2 is different for some reason only hardware guys know... */ +static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022}; +static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E}; + +/* DDR multiPHY */ +static inline int ddrphy_get_rank(int dx) +{ + return dx / 2; +} + +static void ddrphy_fifo_reset(void __iomem *phy_base) +{ + u32 tmp; + + tmp = readl(phy_base + DMPHY_PGCR0); + tmp &= ~DMPHY_PGCR0_PHYFRST; + writel(tmp, phy_base + DMPHY_PGCR0); + + udelay(1); + + tmp |= DMPHY_PGCR0_PHYFRST; + writel(tmp, phy_base + DMPHY_PGCR0); + + udelay(1); +} + +static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) +{ + u32 tmp; + + tmp = readl(phy_base + DMPHY_PGCR1); + + if (enable) + tmp &= ~DMPHY_PGCR1_INHVT; + else + tmp |= DMPHY_PGCR1_INHVT; + + writel(tmp, phy_base + DMPHY_PGCR1); + + if (!enable) { + while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP)) + cpu_relax(); + } +} + +static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) +{ + int dx; + u32 lcdlr1, rdqsd; + void __iomem *dx_base = phy_base + DMPHY_DX_BASE; + + ddrphy_vt_ctrl(phy_base, 0); + + for (dx = 0; dx < nr_dx; dx++) { + lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1); + rdqsd = (lcdlr1 >> 8) & 0xff; + rdqsd = clamp(rdqsd + step, 0U, 0xffU); + lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8); + writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1); + readl(dx_base + DMPHY_DX_LCDLR1); /* relax */ + dx_base += DMPHY_DX_STRIDE; + } + + ddrphy_vt_ctrl(phy_base, 1); +} + +static int ddrphy_get_system_latency(void __iomem *phy_base, int width) +{ + void __iomem *dx_base = phy_base + DMPHY_DX_BASE; + const int nr_dx = width / 8; + int dx, rank; + u32 gtr; + int dgsl, dgsl_min = INT_MAX, dgsl_max = 0; + + for (dx = 0; dx < nr_dx; dx++) { + gtr = readl(dx_base + DMPHY_DX_GTR); + for (rank = 0; rank < 4; rank++) { + dgsl = gtr & 0x7; + /* if dgsl is zero, this rank was not trained. skip. */ + if (dgsl) { + dgsl_min = min(dgsl_min, dgsl); + dgsl_max = max(dgsl_max, dgsl); + } + gtr >>= 3; + } + dx_base += DMPHY_DX_STRIDE; + } + + if (dgsl_min != dgsl_max) + printf("DQS Gateing System Latencies are not all leveled.\n"); + + return dgsl_max; +} + +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) +{ + u32 tmp; + void __iomem *zq_base, *dx_base; + int zq, dx; + int nr_dx; + + nr_dx = width / 8; + + writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR); + /* + * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation) + * to avoid read error issue. + */ + writel(0x07d81e37, phy_base + DMPHY_PGCR0); + writel(0x0200c4e0, phy_base + DMPHY_PGCR1); + + tmp = ddrphy_pgcr2[freq]; + if (width >= 32) + tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC; + writel(tmp, phy_base + DMPHY_PGCR2); + + writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0); + writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1); + writel(0x00083def, phy_base + DMPHY_PTR2); + writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3); + writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4); + + writel(0x55555555, phy_base + DMPHY_ACIOCR1); + writel(0x00000000, phy_base + DMPHY_ACIOCR2); + writel(0x55555555, phy_base + DMPHY_ACIOCR3); + writel(0x00000000, phy_base + DMPHY_ACIOCR4); + writel(0x00000055, phy_base + DMPHY_ACIOCR5); + writel(0x00181aa4, phy_base + DMPHY_DXCCR); + + writel(0x0024641e, phy_base + DMPHY_DSGCR); + writel(0x0000040b, phy_base + DMPHY_DCR); + writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0); + writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1); + writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2); + writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3); + writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0); + writel(0x00000006, phy_base + DMPHY_MR1); + writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2); + writel(0x00000000, phy_base + DMPHY_MR3); + + tmp = 0; + for (dx = 0; dx < nr_dx; dx++) + tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx)); + writel(0x90003087 | tmp, phy_base + DMPHY_DTCR); + + writel(0x00000000, phy_base + DMPHY_DTAR0); + writel(0x00000008, phy_base + DMPHY_DTAR1); + writel(0x00000010, phy_base + DMPHY_DTAR2); + writel(0x00000018, phy_base + DMPHY_DTAR3); + writel(0xdd22ee11, phy_base + DMPHY_DTDR0); + writel(0x7788bb44, phy_base + DMPHY_DTDR1); + + /* impedance control settings */ + writel(0x04048900, phy_base + DMPHY_ZQCR); + + zq_base = phy_base + DMPHY_ZQ_BASE; + for (zq = 0; zq < 4; zq++) { + /* + * board-dependent + * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D + */ + writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR); + zq_base += DMPHY_ZQ_STRIDE; + } + + /* DATX8 settings */ + dx_base = phy_base + DMPHY_DX_BASE; + for (dx = 0; dx < 4; dx++) { + tmp = readl(dx_base + DMPHY_DX_GCR0); + tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK; + tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) & + DMPHY_DX_GCR0_WLRKEN_MASK; + writel(tmp, dx_base + DMPHY_DX_GCR0); + + writel(0x00000000, dx_base + DMPHY_DX_GCR1); + writel(0x00000000, dx_base + DMPHY_DX_GCR2); + writel(0x00000000, dx_base + DMPHY_DX_GCR3); + dx_base += DMPHY_DX_STRIDE; + } + + while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE)) + cpu_relax(); + + ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static const struct ddrphy_init_sequence impedance_calibration_sequence[] = { + { + "Impedance Calibration", + DMPHY_PIR_ZCAL, + DMPHY_PGSR0_ZCDONE, + DMPHY_PGSR0_ZCERR, + }, + { /* sentinel */ } +}; + +static const struct ddrphy_init_sequence dram_init_sequence[] = { + { + "DRAM Initialization", + DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT, + DMPHY_PGSR0_DIDONE, + 0, + }, + { /* sentinel */ } +}; + +static const struct ddrphy_init_sequence training_sequence[] = { + { + "Write Leveling", + DMPHY_PIR_WL, + DMPHY_PGSR0_WLDONE, + DMPHY_PGSR0_WLERR, + }, + { + "Read DQS Gate Training", + DMPHY_PIR_QSGATE, + DMPHY_PGSR0_QSGDONE, + DMPHY_PGSR0_QSGERR, + }, + { + "Write Leveling Adjustment", + DMPHY_PIR_WLADJ, + DMPHY_PGSR0_WLADONE, + DMPHY_PGSR0_WLAERR, + }, + { + "Read Bit Deskew", + DMPHY_PIR_RDDSKW, + DMPHY_PGSR0_RDDONE, + DMPHY_PGSR0_RDERR, + }, + { + "Write Bit Deskew", + DMPHY_PIR_WRDSKW, + DMPHY_PGSR0_WDDONE, + DMPHY_PGSR0_WDERR, + }, + { + "Read Eye Training", + DMPHY_PIR_RDEYE, + DMPHY_PGSR0_REDONE, + DMPHY_PGSR0_REERR, + }, + { + "Write Eye Training", + DMPHY_PIR_WREYE, + DMPHY_PGSR0_WEDONE, + DMPHY_PGSR0_WEERR, + }, + { /* sentinel */ } +}; + +static int __ddrphy_training(void __iomem *phy_base, + const struct ddrphy_init_sequence *seq) +{ + const struct ddrphy_init_sequence *s; + u32 pgsr0; + u32 init_flag = DMPHY_PIR_INIT; + u32 done_flag = DMPHY_PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (s = seq; s->description; s++) { + init_flag |= s->init_flag; + done_flag |= s->done_flag; + } + + writel(init_flag, phy_base + DMPHY_PIR); + + do { + if (--timeout < 0) { + printf("%s: error: timeout during DDR training\n", + __func__); + return -ETIMEDOUT; + } + udelay(1); + pgsr0 = readl(phy_base + DMPHY_PGSR0); + } while ((pgsr0 & done_flag) != done_flag); + + for (s = seq; s->description; s++) { + if (pgsr0 & s->err_flag) { + printf("%s: error: %s failed\n", __func__, + s->description); + return -EIO; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} + +static int ddrphy_impedance_calibration(void __iomem *phy_base) +{ + int ret; + u32 tmp; + + ret = __ddrphy_training(phy_base, impedance_calibration_sequence); + if (ret) + return ret; + + /* + * Because of a hardware bug, IDONE flag is set when the first ZQ block + * is calibrated. The flag does not guarantee the completion for all + * the ZQ blocks. Wait a little more just in case. + */ + udelay(1); + + /* reflect ZQ settings and enable average algorithm*/ + tmp = readl(phy_base + DMPHY_ZQCR); + tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE; + writel(tmp, phy_base + DMPHY_ZQCR); + tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE; + tmp |= DMPHY_ZQCR_AVGEN; + writel(tmp, phy_base + DMPHY_ZQCR); + + return 0; +} + +static int ddrphy_dram_init(void __iomem *phy_base) +{ + return __ddrphy_training(phy_base, dram_init_sequence); +} + +static int ddrphy_training(void __iomem *phy_base) +{ + return __ddrphy_training(phy_base, training_sequence); +} + +/* UMC */ +static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) +{ + u32 val; + int latency; + + val = readl(umc_dc_base + UMC_RDATACTL_D0); + latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT; + latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> + UMC_RDATACTL_RAD2LTY_SHIFT; + /* + * UMC works at the half clock rate of the PHY. + * The LSB of latency is ignored + */ + latency += phy_latency & ~1; + + val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK); + if (latency > 0xf) { + val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT; + val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; + } else { + val |= latency << UMC_RDATACTL_RADLTY_SHIFT; + } + + writel(val, umc_dc_base + UMC_RDATACTL_D0); + writel(val, umc_dc_base + UMC_RDATACTL_D1); + + readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */ +} + +/* enable/disable auto refresh */ +void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) +{ + u32 tmp; + + tmp = readl(umc_dc_base + UMC_SPCSETB); + tmp &= ~UMC_SPCSETB_AREFMD_MASK; + + if (enable) + tmp |= UMC_SPCSETB_AREFMD_ARB; + else + tmp |= UMC_SPCSETB_AREFMD_REG; + + writel(tmp, umc_dc_base + UMC_SPCSETB); + udelay(1); +} + +static void umc_ud_init(void __iomem *umc_base, int ch) +{ + writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0); + + if (ch == 2) + writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0); +} + +static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, + enum dram_size size, int ch, int width) +{ + int latency; + u32 val; + + writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA); + + writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], + umc_dc_base + UMC_CMDCTLB); + + writel(umc_spcctla[freq][size / (width / 16)], + umc_dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB); + + val = 0x000e000e; + latency = 12; + /* ES2 inserted one more FF to the logic. */ + if (uniphier_get_soc_model() >= 2) + latency += 2; + + if (latency > 0xf) { + val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT; + val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; + } else { + val |= latency << UMC_RDATACTL_RADLTY_SHIFT; + } + + writel(val, umc_dc_base + UMC_RDATACTL_D0); + if (width >= 32) + writel(val, umc_dc_base + UMC_RDATACTL_D1); + + writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0); + if (width >= 32) + writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1); + writel(0x04000000, umc_dc_base + UMC_DATASET); + writel(0x00400020, umc_dc_base + UMC_DCCGCTL); + writel(0x00000084, umc_dc_base + UMC_FLOWCTLG); + writel(0x00000000, umc_dc_base + UMC_ACSSETA); + + writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq], + umc_dc_base + UMC_FLOWCTLA); + + writel(0x00004400, umc_dc_base + UMC_FLOWCTLC); + writel(0x200A0A00, umc_dc_base + UMC_SPCSETB); + writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA); + writel(0x0000000D, umc_dc_base + UMC_RESPCTL); + + if (ch != 2) { + writel(0x00202000, umc_dc_base + UMC_FLOWCTLB); + writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0); + writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1); + writel(0x00080700, umc_dc_base + UMC_BSICMAPSET); + } else { + writel(0x00200000, umc_dc_base + UMC_FLOWCTLB); + writel(0x00000000, umc_dc_base + UMC_BSICMAPSET); + } + + writel(0x00000000, umc_dc_base + UMC_ERRMASKA); + writel(0x00000000, umc_dc_base + UMC_ERRMASKB); +} + +static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, + enum dram_size size, int width) +{ + void __iomem *umc_dc_base = umc_base + 0x00011000; + void __iomem *phy_base = umc_base + 0x00030000; + int ret; + + writel(0x00000002, umc_dc_base + UMC_INITSET); + while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2)) + cpu_relax(); + + /* deassert PHY reset signals */ + writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, + umc_dc_base + UMC_DIOCTLA); + + ddrphy_init(phy_base, freq, width); + + ret = ddrphy_impedance_calibration(phy_base); + if (ret) + return ret; + + ddrphy_dram_init(phy_base); + if (ret) + return ret; + + umc_dc_init(umc_dc_base, freq, size, ch, width); + + umc_ud_init(umc_base, ch); + + if (size) { + ret = ddrphy_training(phy_base); + if (ret) + return ret; + } + + udelay(1); + + /* match the system latency between UMC and PHY */ + umc_set_system_latency(umc_dc_base, + ddrphy_get_system_latency(phy_base, width)); + + udelay(1); + + /* stop auto refresh before clearing FIFO in PHY */ + umc_refresh_ctrl(umc_dc_base, 0); + ddrphy_fifo_reset(phy_base); + umc_refresh_ctrl(umc_dc_base, 1); + + udelay(10); + + return 0; +} + +static void um_init(void __iomem *um_base) +{ + writel(0x000000ff, um_base + UMC_MBUS0); + writel(0x000000ff, um_base + UMC_MBUS1); + writel(0x000000ff, um_base + UMC_MBUS2); + writel(0x000000ff, um_base + UMC_MBUS3); +} + +int proxstream2_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *um_base = (void __iomem *)0x5b600000; + void __iomem *umc_ch0_base = (void __iomem *)0x5b800000; + void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000; + void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000; + enum dram_freq freq; + int ret; + + switch (bd->dram_freq) { + case 1866: + freq = FREQ_1866M; + break; + case 2133: + freq = FREQ_2133M; + break; + default: + printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + return -EINVAL; + } + + ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M, + bd->dram_ch0_width); + if (ret) { + printf("failed to initialize UMC ch0\n"); + return ret; + } + + ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M, + bd->dram_ch1_width); + if (ret) { + printf("failed to initialize UMC ch1\n"); + return ret; + } + + ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M, + bd->dram_ch2_width); + if (ret) { + printf("failed to initialize UMC ch2\n"); + return ret; + } + + um_init(um_base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/include/mach/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 6159281fd3..6159281fd3 100644 --- a/arch/arm/mach-uniphier/include/mach/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c index f646c9b7df..6574767f30 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c @@ -7,8 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c index 007d3b8570..d98635878b 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c index c303f16a57..a573a96ee5 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c @@ -7,8 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int proxstream2_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c index 1bb9375016..7923644cd5 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/sg-regs.h> +#include "../init.h" +#include "../sg-regs.h" int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/init.h index 27ae27dc9f..0a47e70dcf 100644 --- a/arch/arm/mach-uniphier/include/mach/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -80,6 +80,7 @@ int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd); int ph1_ld4_umc_init(const struct uniphier_board_data *bd); int ph1_pro4_umc_init(const struct uniphier_board_data *bd); int ph1_sld8_umc_init(const struct uniphier_board_data *bd); +int proxstream2_umc_init(const struct uniphier_board_data *bd); void ph1_sld3_pin_init(void); void ph1_ld4_pin_init(void); diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c index 8d0ef0389e..a9c6d72e0b 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-ld4.c +++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_ld4_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c index b9ce08d88f..6fcd8b6c85 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-pro4.c +++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_pro4_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro5.c b/arch/arm/mach-uniphier/init/init-ph1-pro5.c index 92b3f21d93..45c65cf49a 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-pro5.c +++ b/arch/arm/mach-uniphier/init/init-ph1-pro5.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_pro5_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c index 1146fdab97..7827ec0bdc 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-sld3.c +++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_sld3_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c index 741e88c212..6c96aede2a 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-sld8.c +++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_sld8_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-proxstream2.c b/arch/arm/mach-uniphier/init/init-proxstream2.c index 8d03b8f86a..029c544997 100644 --- a/arch/arm/mach-uniphier/init/init-proxstream2.c +++ b/arch/arm/mach-uniphier/init/init-proxstream2.c @@ -6,12 +6,14 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int proxstream2_init(const struct uniphier_board_data *bd) { + int ret; + proxstream2_sbc_init(bd); support_card_reset(); @@ -37,5 +39,11 @@ int proxstream2_init(const struct uniphier_board_data *bd) led_puts("L4"); + ret = proxstream2_umc_init(bd); + if (ret) + return ret; + + led_puts("L5"); + return 0; } diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index eda169e374..b30f3bd9d6 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -6,8 +6,9 @@ #include <common.h> #include <spl.h> -#include <mach/init.h> -#include <mach/soc_info.h> + +#include "../init.h" +#include "../soc-info.h" void spl_board_init(void) { diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S index 1363364c80..cce91dfac7 100644 --- a/arch/arm/mach-uniphier/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -6,7 +6,8 @@ */ #include <linux/linkage.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" ENTRY(lowlevel_init) ldr r1, = SSCC diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 5936045e86..291337070e 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -8,9 +8,8 @@ #include <linux/linkage.h> #include <linux/sizes.h> #include <asm/system.h> -#include <mach/arm-mpcore.h> -#include <mach/sbc-regs.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" ENTRY(lowlevel_init) mov r8, lr @ persevere link reg across call diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c index e13f56d1dc..9718cc560f 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int ph1_sld3_memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c index d7bf0d4e5f..9a91fb33ef 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int proxstream2_memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c index d490736fa4..f2a0eaf3f5 100644 --- a/arch/arm/mach-uniphier/memconf/memconf.c +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 4c34748c25..f777ac1ffe 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/ctype.h> #include <linux/io.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" #define MICRO_SUPPORT_CARD_BASE 0x43f00000 #define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000) @@ -70,7 +71,6 @@ int board_eth_init(bd_t *bis) #if !defined(CONFIG_SYS_NO_FLASH) #include <mtd/cfi_flash.h> -#include <mach/sbc-regs.h> struct memory_bank { phys_addr_t base; diff --git a/arch/arm/mach-uniphier/include/mach/micro-support-card.h b/arch/arm/mach-uniphier/micro-support-card.h index 5da0ada726..5da0ada726 100644 --- a/arch/arm/mach-uniphier/include/mach/micro-support-card.h +++ b/arch/arm/mach-uniphier/micro-support-card.h diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c index 160d3ef299..8168a63d31 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_ld4_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c index 4f950d3fc6..4faeaf535c 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_ld6b_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c index f50644c52b..23b5f9349a 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_pro4_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c index a6cc0824e2..79160d6c95 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_pro5_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c index f1b2bbbb4a..6fc0dee70e 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/sg-regs.h> +#include "../init.h" +#include "../sg-regs.h" void ph1_sld3_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c index f936a53d1f..a4e3e7a614 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_sld8_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c index 96abd0235c..a662db8ac9 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void proxstream2_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c index a272a900e1..b2de9e8d5e 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c @@ -7,9 +7,10 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" #undef DPLL_SSC_RATE_1PER diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c index 906c22f6c5..69d518d265 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c @@ -7,9 +7,10 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" #undef DPLL_SSC_RATE_1PER diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c index 6294a452c2..b93806cdc0 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> +#include "../init.h" int ph1_sld3_pll_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c index f249abeeda..3c7550446a 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" static void dpll_init(void) { diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c index cad0ed8cdd..a1c8089de7 100644 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c index 43dc973654..94654eeba0 100644 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c @@ -6,8 +6,9 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c index 5140b0c438..695b7aeeb3 100644 --- a/arch/arm/mach-uniphier/print_misc_info.c +++ b/arch/arm/mach-uniphier/print_misc_info.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/micro-support-card.h> +#include "micro-support-card.h" int misc_init_f(void) { diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 4c825116f7..b5825bc0c7 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/sc-regs.h> + +#include "sc-regs.h" void reset_cpu(unsigned long ignored) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c index 929f50a883..fcce43cb99 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c index 1032c54e64..8313c5a3e5 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c index fb707be83a..c03c2843a6 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c index 9c3aeb7cd0..0d9ffe153f 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c +++ b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c @@ -5,9 +5,10 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int proxstream2_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/include/mach/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index 493363bb64..493363bb64 100644 --- a/arch/arm/mach-uniphier/include/mach/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index 474b82d243..474b82d243 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 678d437fc9..678d437fc9 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/soc-info.h index 3cfd1e9d6e..3cfd1e9d6e 100644 --- a/arch/arm/mach-uniphier/include/mach/soc_info.h +++ b/arch/arm/mach-uniphier/soc-info.h diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c index 6cdeae6578..fd799ca39a 100644 --- a/arch/arm/mach-uniphier/soc_info.c +++ b/arch/arm/mach-uniphier/soc_info.c @@ -6,8 +6,9 @@ #include <linux/io.h> #include <linux/types.h> -#include <mach/sg-regs.h> -#include <mach/soc_info.h> + +#include "sg-regs.h" +#include "soc-info.h" #if UNIPHIER_MULTI_SOC enum uniphier_soc_id uniphier_get_soc_type(void) diff --git a/arch/arm/mach-uniphier/include/mach/ssc-regs.h b/arch/arm/mach-uniphier/ssc-regs.h index 02fca3b6f6..02fca3b6f6 100644 --- a/arch/arm/mach-uniphier/include/mach/ssc-regs.h +++ b/arch/arm/mach-uniphier/ssc-regs.h diff --git a/arch/arm/mach-uniphier/timer.c b/arch/arm/mach-uniphier/timer.c index 27ada2924c..a34e30b72b 100644 --- a/arch/arm/mach-uniphier/timer.c +++ b/arch/arm/mach-uniphier/timer.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/arm-mpcore.h> + +#include "arm-mpcore.h" #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ #define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index b76a7319ae..528865f5d3 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -76,6 +76,10 @@ static int _raw_packet_start(const char *ifname, unsigned char *ethmac, printf("Failed to set promiscuous mode: %d %s\n" "Falling back to the old \"flags\" way...\n", errno, strerror(errno)); + if (strlen(ifname) >= IFNAMSIZ) { + printf("Interface name %s is too long.\n", ifname); + return -EINVAL; + } strncpy(ifr.ifr_name, ifname, IFNAMSIZ); if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) { printf("Failed to read flags: %d %s\n", errno, diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 9b30451b28..7299f2cddc 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -14,12 +14,12 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD }, + {}, }; int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("ValleyView SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("ValleyView SDHCI", mmc_supported); } #ifndef CONFIG_EFI_APP diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 3e7a907e00..434dfd649f 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -86,8 +86,10 @@ static int bd82x6x_probe(struct udevice *dev) debug("%s: Cannot find GMA node\n", __func__); return -EINVAL; } - ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, - gma_node); + ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); + if (ret) + return ret; + ret = gma_func0_init(dev, blob, gma_node); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 89d4a5e9cc..85a09c64b6 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -728,8 +728,7 @@ static int int15_handler(void) return res; } -int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, - const void *blob, int node) +int gma_func0_init(struct udevice *dev, const void *blob, int node) { #ifdef CONFIG_VIDEO ulong start; @@ -740,16 +739,16 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, int ret; /* IGD needs to be Bus Master */ - reg32 = x86_pci_read_config32(dev, PCI_COMMAND); + dm_pci_read_config32(dev, PCI_COMMAND, ®32); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - x86_pci_write_config32(dev, PCI_COMMAND, reg32); + dm_pci_write_config32(dev, PCI_COMMAND, reg32); /* Use write-combining for the graphics memory, 256MB */ - base = pci_read_bar32(hose, dev, 2); + base = dm_pci_read_bar32(dev, 2); mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); mtrr_commit(true); - gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); + gtt_bar = (void *)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); ret = gma_pm_init_pre_vbios(gtt_bar); if (ret) @@ -757,8 +756,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, #ifdef CONFIG_VIDEO start = get_timer(0); - ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); + ret = dm_pci_run_vga_bios(dev, int15_handler, + PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK); debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index c2bf497d68..37ce3940b0 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -19,6 +19,7 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, + {}, }; /* @@ -337,8 +338,7 @@ int arch_early_init_r(void) int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("Quark SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("Quark SDHCI", mmc_supported); } void cpu_irq_init(void) diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c index 9faf1b92bb..b76dd7de69 100644 --- a/arch/x86/cpu/queensbay/topcliff.c +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -11,10 +11,10 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + {}, }; int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("Topcliff SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("Topcliff SDHCI", mmc_supported); } diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 7786493be7..fcdf6e26cb 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -12,8 +12,7 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); -int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, - const void *blob, int node); +int gma_func0_init(struct udevice *dev, const void *blob, int node); int bd82x6x_init(void); /** diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 1d75cfc263..9324bdb83e 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -242,9 +242,10 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) vbe_set_mode(mode_info); } -void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, +void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, struct vbe_mode_info *mode_info) { + pci_dev_t pcidev = dm_pci_get_bdf(dev); u32 num_dev; num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 | diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index 47d9f599a3..e8ca6e60f2 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -105,13 +105,15 @@ int int1a_handler(void) unsigned short func = (unsigned short)M.x86.R_EAX; int retval = 1; unsigned short devid, vendorid, devfn; + struct udevice *dev; /* Use short to get rid of gabage in upper half of 32-bit register */ short devindex; unsigned char bus; - pci_dev_t dev; + pci_dev_t bdf; u32 dword; u16 word; u8 byte, reg; + int ret; switch (func) { case 0xb101: /* PCIBIOS Check */ @@ -131,17 +133,20 @@ int int1a_handler(void) devid = M.x86.R_ECX; vendorid = M.x86.R_EDX; devindex = M.x86.R_ESI; - dev = pci_find_device(vendorid, devid, devindex); - if (dev != -1) { + bdf = -1; + ret = dm_pci_find_device(vendorid, devid, devindex, &dev); + if (!ret) { unsigned short busdevfn; + + bdf = dm_pci_get_bdf(dev); M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; /* * busnum is an unsigned char; * devfn is an int, so we mask it off. */ - busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 | - PCI_FUNC(dev); + busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 | + PCI_FUNC(bdf); debug("0x%x: return 0x%x\n", func, busdevfn); M.x86.R_EBX = busdevfn; retval = 1; @@ -160,35 +165,40 @@ int int1a_handler(void) devfn = M.x86.R_EBX & 0xff; bus = M.x86.R_EBX >> 8; reg = M.x86.R_EDI; - dev = PCI_BDF(bus, devfn >> 3, devfn & 7); + bdf = PCI_BDF(bus, devfn >> 3, devfn & 7); + + ret = dm_pci_bus_find_bdf(bdf, &dev); + if (ret) { + debug("%s: Device %x not found\n", __func__, bdf); + break; + } switch (func) { case 0xb108: /* Read Config Byte */ - byte = x86_pci_read_config8(dev, reg); + dm_pci_read_config8(dev, reg, &byte); M.x86.R_ECX = byte; break; case 0xb109: /* Read Config Word */ - word = x86_pci_read_config16(dev, reg); + dm_pci_read_config16(dev, reg, &word); M.x86.R_ECX = word; break; case 0xb10a: /* Read Config Dword */ - dword = x86_pci_read_config32(dev, reg); + dm_pci_read_config32(dev, reg, &dword); M.x86.R_ECX = dword; break; case 0xb10b: /* Write Config Byte */ byte = M.x86.R_ECX; - x86_pci_write_config8(dev, reg, byte); + dm_pci_write_config8(dev, reg, byte); break; case 0xb10c: /* Write Config Word */ word = M.x86.R_ECX; - x86_pci_write_config16(dev, reg, word); + dm_pci_write_config16(dev, reg, word); break; case 0xb10d: /* Write Config Dword */ dword = M.x86.R_ECX; - x86_pci_write_config32(dev, reg, dword); + dm_pci_write_config32(dev, reg, dword); break; } - #ifdef CONFIG_REALMODE_DEBUG debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, M.x86.R_ECX); |
