diff options
Diffstat (limited to 'arch')
68 files changed, 3637 insertions, 350 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e9d2fc9845..3237a74f72 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -304,13 +304,13 @@ config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" select CPU_V7 -config TARGET_KWB - bool "Support kwb" +config TARGET_BRXRE1 + bool "Support BRXRE1" select CPU_V7 select SUPPORT_SPL -config TARGET_TSERIES - bool "Support tseries" +config TARGET_BRPPT1 + bool "Support BRPPT1" select CPU_V7 select SUPPORT_SPL @@ -908,8 +908,8 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" source "board/bosch/shc/Kconfig" -source "board/BuR/kwb/Kconfig" -source "board/BuR/tseries/Kconfig" +source "board/BuR/brxre1/Kconfig" +source "board/BuR/brppt1/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index bc98edda7a..068d93eeec 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -526,7 +526,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_BUILD -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0a5ac97df0..ddd8d12d51 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -18,15 +18,8 @@ obj-y += lowlevel_init.o endif endif -ifneq ($(CONFIG_ARMV7_NONSEC),) -obj-y += nonsec_virt.o -obj-y += virt-v7.o -obj-y += virt-dt.o -endif - -ifneq ($(CONFIG_ARMV7_PSCI),) -obj-y += psci.o -endif +obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_IPROC) += iproc-common/ obj-$(CONFIG_KONA) += kona-common/ diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c index ce3d019125..80187e3eca 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c @@ -292,7 +292,7 @@ static struct ccu_clock kps_ccu_clk = { .ops = &ccu_clk_ops, .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, }, - .num_policy_masks = 2, + .num_policy_masks = 1, .policy_freq_offset = 0x00000008, .freq_bit_shift = 8, .policy_ctl_offset = 0x0000000c, @@ -300,10 +300,6 @@ static struct ccu_clock kps_ccu_clk = { .policy1_mask_offset = 0x00000014, .policy2_mask_offset = 0x00000018, .policy3_mask_offset = 0x0000001c, - .policy0_mask2_offset = 0x00000048, - .policy1_mask2_offset = 0x0000004c, - .policy2_mask2_offset = 0x00000050, - .policy3_mask2_offset = 0x00000054, .lvm_en_offset = 0x00000034, .freq_id = 2, .freq_tbl = slave_axi_freq_tbl, diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index 2b5da6bb6b..a326dfea6c 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -449,10 +449,9 @@ int clk_enable(struct clk *c) if (ret) return ret; - if (!c->use_cnt) { - c->use_cnt++; + if (!c->use_cnt) ret = c->ops->enable(c, 1); - } + c->use_cnt++; return ret; } @@ -464,9 +463,10 @@ void clk_disable(struct clk *c) if (!c->ops || !c->ops->enable) return; - if (c->use_cnt) { + if (c->use_cnt > 0) { c->use_cnt--; - c->ops->enable(c, 0); + if (c->use_cnt == 0) + c->ops->enable(c, 0); } /* disable parent */ diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 02890584a5..1246eed2ca 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -15,7 +15,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NAND; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 8333b20001..60c367a202 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -166,7 +166,7 @@ u32 spl_boot_device(void) return gd->arch.omap_boot_device; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return gd->arch.omap_boot_mode; } diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 032bd2c24f..49e3a971d9 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -77,7 +77,7 @@ ulong get_timer_masked(void) /* move stamp fordward with absoulte diff ticks */ gd->arch.tbl += (now - gd->arch.lastinc); } else { /* we have rollover of incrementer */ - gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / + gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; } gd->arch.lastinc = now; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 3a77b21d0a..d0dc58d181 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include <fsl_ifc.h> +#include "cpu.h" DECLARE_GLOBAL_DATA_PTR; @@ -47,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info) [5] = 2, /* CC2 PPL / 2 */ }; - uint i; + uint i, cluster; uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -80,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } - for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { - u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_pll[c_pll_sel]; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d8ec426ce2..f62b78d102 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has DP_DDR */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; @@ -40,7 +40,7 @@ bool soc_has_aiop(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has AIOP */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 5883c002be..19e34fade2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -24,7 +24,7 @@ u32 spl_boot_device(void) return 0; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index c1a2f456d5..670e323b61 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -258,12 +258,10 @@ ENDPROC(lowlevel_init) WEAK(smp_kick_all_cpus) /* Kick secondary cpus up by SGI 0 interrupt */ - mov x29, lr /* Save LR */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) ldr x0, =GICD_BASE - bl gic_kick_secondary_cpus + b gic_kick_secondary_cpus #endif - mov lr, x29 /* Restore LR */ ret ENDPROC(smp_kick_all_cpus) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index e3e2a4fb5a..867d2b25a8 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -68,7 +68,7 @@ u32 spl_boot_device(void) return 0; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { switch (spl_boot_device()) { case BOOT_DEVICE_RAM: diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index de75e24d1b..5d463cea4a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -2,7 +2,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb +dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ + at91sam9g20-taurus.dtb \ + at91sam9g45-corvus.dtb \ + at91sam9g45-gurnard.dtb + dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts new file mode 100644 index 0000000000..faed763e43 --- /dev/null +++ b/arch/arm/dts/at91sam9260-smartweb.dts @@ -0,0 +1,110 @@ +/* + * at91sam9260-smartweb.dts + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Siemens smartweb"; + compatible = "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ + }; + + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi new file mode 100644 index 0000000000..d4884dd1c2 --- /dev/null +++ b/arch/arm/dts/at91sam9260.dtsi @@ -0,0 +1,1034 @@ +/* + * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, + * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel AT91SAM9260 family SoC"; + compatible = "atmel,at91sam9260"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &uart0; + serial6 = &uart1; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + ssc0 = &ssc0; + }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x04000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + }; + + sram0: sram@002ff000 { + compatible = "mmio-sram"; + reg = <0x002ff000 0x2000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <29 30 31>; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9260-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9260-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_xtal>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, + <150000000 240000000 2 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 5000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 105000000>; + atmel,clk-divisors = <1 2 4 0>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <9>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk { + reg = <11>; + #clock-cells = <0>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <19>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <20>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <22>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <23>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <24>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <25>; + }; + + tc3_clk: tc3_clk { + #clock-cells = <0>; + reg = <26>; + }; + + tc4_clk: tc4_clk { + #clock-cells = <0>; + reg = <27>; + }; + + tc5_clk: tc5_clk { + #clock-cells = <0>; + reg = <28>; + }; + }; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffdc000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 + 27 IRQ_TYPE_LEVEL_HIGH 0 + 28 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = < + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + 0xffffffff 0x007fffff /* pioC */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ + }; + + pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { + atmel,pins = + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ + }; + + pinctrl_usart0_dcd: usart0_dcd-0 { + atmel,pins = + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ + }; + + pinctrl_usart0_ri: usart0_ri-0 { + atmel,pins = + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ + AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ + AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ + }; + + pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { + atmel,pins = + <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ + AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ + }; + + pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { + atmel,pins = + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE + AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffd0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd0000 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart0: serial@fffd4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd4000 0x200>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@fffd8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd8000 0x200>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + mmc0: mmc@fffa8000 { + compatible = "atmel,hsmci"; + reg = <0xfffa8000 0x600>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffbc000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + adc0: adc@fffe0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9260-adc"; + reg = <0xfffe0000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0xf>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <15>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger@0 { + reg = <0>; + trigger-name = "timer-counter-0"; + trigger-value = <0x1>; + }; + trigger@1 { + reg = <1>; + trigger-name = "timer-counter-1"; + trigger-value = <0x3>; + }; + + trigger@2 { + reg = <2>; + trigger-name = "timer-counter-2"; + trigger-value = <0x5>; + }; + + trigger@3 { + reg = <3>; + trigger-name = "external"; + trigger-value = <0xd>; + trigger-external; + }; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe800 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ + &pioA 24 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi new file mode 100644 index 0000000000..5e09de4eb9 --- /dev/null +++ b/arch/arm/dts/at91sam9261.dtsi @@ -0,0 +1,876 @@ +/* + * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC + * + * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * + * Licensed under GPLv2 only. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel AT91SAM9261 family SoC"; + compatible = "atmel,at91sam9261"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + ssc2 = &ssc2; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x28000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&ohci_clk>, <&hclk0>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + fb0: fb@0x00600000 { + compatible = "atmel,at91sam9261-lcdc"; + reg = <0x00600000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&hclk1>; + clock-names = "lcdc_clk", "hclk"; + status = "disabled"; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000>; + atmel,nand-addr-offset = <22>; + atmel,nand-cmd-offset = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>, + <&pioC 14 GPIO_ACTIVE_HIGH>, + <0>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91sam9261-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + atmel,matrix = <&matrix>; + status = "disabled"; + }; + + mmc0: mmc@fffa8000 { + compatible = "atmel,hsmci"; + reg = <0xfffa8000 0x600>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9261-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_twi>; + reg = <0xfffac000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000{ + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffbc000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fffc0000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc2: ssc@fffc4000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; + clocks = <&ssc2_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + cs-gpios = <0>, <0>, <0>, <0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ramc: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9260-bus-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <29 30 31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xfffffff7>, /* pioA */ + <0xffffffff 0xfffffff4>, /* pioB */ + <0xffffffff 0xffffff07>; /* pioC */ + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + <AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + <AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>, + <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + ssc2 { + pinctrl_ssc2_tx: ssc2_tx-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_ssc2_rx: ssc2_rx-0 { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + i2c0 { + pinctrl_i2c_bitbang: i2c-0-bitbang { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>, + <AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_i2c_twi: i2c-0-twi { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 5000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 94000000>; + atmel,clk-divisors = <1 2 4 0>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + + prog3: prog3 { + #clock-cells = <0>; + reg = <3>; + interrupts = <AT91_PMC_PCKRDY(3)>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + pck3: pck3 { + #clock-cells = <0>; + reg = <11>; + clocks = <&prog3>; + }; + + hclk0: hclk0 { + #clock-cells = <0>; + reg = <16>; + clocks = <&mck>; + }; + + hclk1: hclk1 { + #clock-cells = <0>; + reg = <17>; + clocks = <&mck>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <9>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk { + reg = <11>; + #clock-cells = <0>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc2_clk: ssc2_clk { + #clock-cells = <0>; + reg = <16>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <19>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <20>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <21>; + }; + }; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_bitbang>; + gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi new file mode 100644 index 0000000000..93446420af --- /dev/null +++ b/arch/arm/dts/at91sam9263.dtsi @@ -0,0 +1,1034 @@ +/* + * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 only. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel AT91SAM9263 family SoC"; + compatible = "atmel,at91sam9263"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram0: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x14000>; + }; + + sram1: sram@00500000 { + compatible = "mmio-sram"; + reg = <0x00500000 0x4000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <30 31>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + clocks = <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 120000000>; + atmel,clk-divisors = <1 2 4 0>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + + prog3: prog3 { + #clock-cells = <0>; + reg = <3>; + interrupts = <AT91_PMC_PCKRDY(3)>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + pck3: pck3 { + #clock-cells = <0>; + reg = <11>; + clocks = <&prog3>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioCDE_clk: pioCDE_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <8>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <9>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <10>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <11>; + }; + + can_clk: can_clk { + #clock-cells = <0>; + reg = <12>; + }; + + twi0_clk: twi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <16>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <17>; + }; + + ac97_clk: ac97_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tcb_clk: tcb_clk { + #clock-cells = <0>; + reg = <19>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <20>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + g2de_clk: g2de_clk { + #clock-cells = <0>; + reg = <23>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <24>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <25>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <26>; + }; + + dma_clk: dma_clk { + #clock-cells = <0>; + reg = <27>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <29>; + }; + }; + }; + + ramc0: ramc@ffffe200 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe200 0x200>; + }; + + ramc1: ramc@ffffe800 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe800 0x200>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfff7c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>, <&slow_xtal>; + clock-names = "t0_clk", "slow_clk"; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; + }; + + pinctrl@fffff200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + + atmel,mux-mask = < + /* A B */ + 0xfffffffb 0xffffe07f /* pioA */ + 0x0007ffff 0x39072fff /* pioB */ + 0xffffffff 0x3ffffff8 /* pioC */ + 0xfffffbff 0xffffffff /* pioD */ + 0xffe00fff 0xfbfcff00 /* pioE */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */ + AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ + AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ + AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ + AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ + AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ + AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ + AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ + AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ + AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ + AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ + AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ + AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_clk: mmc1_clk-0 { + atmel,pins = + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ + }; + + pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ + }; + + pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ + }; + + pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ + AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ + AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ + AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ + AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ + AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ + AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ + AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ + AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ + AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ + AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ + }; + }; + + can { + pinctrl_can_rx_tx: can_rx_tx { + atmel,pins = + <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ + }; + }; + + ac97 { + pinctrl_ac97: ac97-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */ + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + }; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fff98000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfff98000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fff9c000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfff9c000 0x4000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + ac97: sound@fffa0000 { + compatible = "atmel,at91sam9263-ac97c"; + reg = <0xfffa0000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ac97>; + clocks = <&ac97_clk>; + clock-names = "ac97_clk"; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + usb1: gadget@fff78000 { + compatible = "atmel,at91sam9263-udc"; + reg = <0xfff78000 0x4000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + i2c0: i2c@fff88000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfff88000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + mmc0: mmc@fff80000 { + compatible = "atmel,hsmci"; + reg = <0xfff80000 0x600>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + mmc1: mmc@fff84000 { + compatible = "atmel,hsmci"; + reg = <0xfff84000 0x600>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + spi0: spi@fffa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa4000 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffa8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa8000 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + + can: can@fffac000 { + compatible = "atmel,at91sam9263-can"; + reg = <0xfffac000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_rx_tx>; + clocks = <&can_clk>; + clock-names = "can_clk"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + rtc@fffffd50 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd50 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x50>; + status = "disabled"; + }; + }; + + fb0: fb@0x00700000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "lcdc_clk", "hclk"; + status = "disabled"; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe000 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioA 22 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00a00000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00a00000 0x100000>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts new file mode 100644 index 0000000000..f27d77279f --- /dev/null +++ b/arch/arm/dts/at91sam9g20-taurus.dts @@ -0,0 +1,119 @@ +/* + * at91sam9g20-taurus.dts + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "Siemens taurus"; + compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ + }; + + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g20.dtsi b/arch/arm/dts/at91sam9g20.dtsi new file mode 100644 index 0000000000..f593016181 --- /dev/null +++ b/arch/arm/dts/at91sam9g20.dtsi @@ -0,0 +1,68 @@ +/* + * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9260.dtsi" + +/ { + model = "Atmel AT91SAM9G20 family SoC"; + compatible = "atmel,at91sam9g20"; + + memory { + reg = <0x20000000 0x08000000>; + }; + + sram0: sram@002ff000 { + status = "disabled"; + }; + + sram1: sram@002fc000 { + compatible = "mmio-sram"; + reg = <0x002fc000 0x8000>; + }; + + ahb { + apb { + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9g20-i2c"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91sam9rl-ssc"; + }; + + adc0: adc@fffe0000 { + atmel,adc-startup-time = <40>; + }; + + pmc: pmc@fffffc00 { + plla: pllack { + atmel,clk-input-range = <2000000 32000000>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, + <695000000 750000000 1 0>, + <645000000 700000000 2 0>, + <595000000 650000000 3 0>, + <545000000 600000000 0 1>, + <495000000 550000000 1 1>, + <445000000 500000000 2 1>, + <400000000 450000000 3 1>; + }; + + pllb: pllbck { + compatible = "atmel,at91sam9g20-clk-pllb"; + atmel,clk-input-range = <2000000 32000000>; + atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; + }; + + mck: masterck { + atmel,clk-output-range = <0 133000000>; + atmel,clk-divisors = <1 2 4 6>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g45-corvus.dts b/arch/arm/dts/at91sam9g45-corvus.dts new file mode 100644 index 0000000000..c207c02858 --- /dev/null +++ b/arch/arm/dts/at91sam9g45-corvus.dts @@ -0,0 +1,108 @@ +/* + * at91sam9g45-corvus.dts Device Tree file fir Siemens corvus board + * (C) Copyright 2016 Heiko Schocher <hs@denx.de> + * + * based on: + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "at91sam9g45.dtsi" + +/ { + model = "Siemens corvus"; + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x70000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + usart1: serial@fff90000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + spi0: spi@fffa4000{ + status = "okay"; + cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <13000000>; + reg = <0>; + }; + }; + + usb2: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + gpbr: syscon@fffffd60 { + status = "okay"; + }; + + rtc@fffffdb0 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + + usb0: ohci@00700000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW + &pioD 3 GPIO_ACTIVE_LOW>; + }; + + usb1: ehci@00800000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 546a87a0a5..024527e815 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -9,18 +9,6 @@ / { compatible = "fsl,ls1012a"; interrupt-parent = <&gic>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&clockgen 1 0>; - }; - - }; sysclk: sysclk { compatible = "fixed-clock"; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index bf1dfe6db6..a8bffbafa7 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -15,38 +15,6 @@ / { compatible = "fsl,ls1043a"; interrupt-parent = <&gic>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&clockgen 1 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&clockgen 1 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - clocks = <&clockgen 1 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - clocks = <&clockgen 1 0>; - }; - }; sysclk: sysclk { compatible = "fixed-clock"; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 68ed133853..b308c8b982 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -12,67 +12,6 @@ #address-cells = <2>; #size-cells = <2>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - /* - * We expect the enable-method for cpu's to be "psci", but this - * is dependent on the SoC FW, which will fill this in. - * - * Currently supported enable-method is psci v0.2 - */ - - /* We have 4 clusters having 2 Cortex-A57 cores each */ - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x201>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x300>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x301>; - }; - }; - memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>; diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index 7d59112ddd..b0b2b57bb9 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -22,6 +22,7 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; + u-boot,dm-pre-reloc; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -65,9 +66,12 @@ system_bus: system-bus@58c00000 { compatible = "socionext,uniphier-system-bus"; + status = "disabled"; reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59800000 { @@ -109,9 +113,15 @@ interrupt-controller; }; - pinctrl: pinctrl@5f801000 { - /* specify compatible in each SoC DTSI */ - reg = <0x5f801000 0xe00>; + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + /* specify compatible in each SoC DTSI */ + u-boot,dm-pre-reloc; + }; }; sysctrl: sysctrl@61840000 { @@ -124,8 +134,12 @@ nand: nand@68000000 { compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; + status = "disabled"; reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; }; }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index b148e9fbd9..4eb7664a9e 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -1,7 +1,8 @@ /* * Device Tree Source for UniPhier PH1-LD11 Reference Board * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -62,20 +63,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi index e485f90a97..ffe04f5cb6 100644 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi @@ -1,11 +1,14 @@ /* * Device Tree Source for UniPhier PH1-LD11 SoC * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + / { compatible = "socionext,ph1-ld11"; #address-cells = <2>; @@ -16,24 +19,41 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; }; clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + uart_clk: uart_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -60,6 +80,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -183,6 +204,8 @@ reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59800000 { @@ -226,9 +249,20 @@ #clock-cells = <1>; }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-ld11-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld11-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; }; gic: interrupt-controller@5fe00000 { diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 3049016cc7..90c8705fff 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -51,20 +51,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi index f9cc3c4bdb..7497539467 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi @@ -6,6 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + / { compatible = "socionext,ph1-ld20"; #address-cells = <2>; @@ -41,7 +43,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu1: cpu@1 { @@ -49,7 +51,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu2: cpu@100 { @@ -57,7 +59,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu3: cpu@101 { @@ -65,11 +67,17 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; }; clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + uart_clk: uart_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -96,6 +104,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -219,6 +228,8 @@ reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59800000 { @@ -243,9 +254,20 @@ bus-width = <4>; }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-ld20-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld20-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; }; gic: interrupt-controller@5fe00000 { diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 6cae452d7d..36de7e3a0f 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -69,20 +69,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 5ae029ea97..07f315a2b7 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -274,6 +274,11 @@ pinctrl-0 = <&pinctrl_usb2>; clocks = <&mio 5>, <&mio 6>; }; + + aidet@61830000 { + compatible = "simple-mfd", "syscon"; + reg = <0x61830000 0x200>; + }; }; &refclk { @@ -310,7 +315,7 @@ }; &pinctrl { - compatible = "socionext,ph1-ld4-pinctrl", "syscon"; + compatible = "socionext,uniphier-ld4-pinctrl"; }; &sysctrl { diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index e2a2a8c5ce..e29a6ea841 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -71,20 +71,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi index cf02e62021..e8110eefce 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld6b.dtsi @@ -17,7 +17,7 @@ compatible = "socionext,ph1-ld6b"; }; -/* UART3 unavilable: the pads are not wired to the package balls */ +/* UART3 unavailable: the pads are not wired to the package balls */ &serial3 { status = "disabled"; }; @@ -27,5 +27,5 @@ * which makes the pinctrl driver unshareable. */ &pinctrl { - compatible = "socionext,ph1-ld6b-pinctrl", "syscon"; + compatible = "socionext,uniphier-ld6b-pinctrl"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts index 37e0853365..d8740cc9d3 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ace.dts @@ -90,20 +90,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 5be76e2d66..4a2de08e06 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -80,20 +80,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts index 82e2bd02c7..965fe08e38 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts @@ -85,12 +85,6 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; @@ -103,10 +97,6 @@ u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index d5767b6252..e0b28b8291 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -400,6 +400,11 @@ clocks = <&mio 4>, <&mio 6>; }; + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; @@ -452,7 +457,7 @@ }; &pinctrl { - compatible = "socionext,ph1-pro4-pinctrl", "syscon"; + compatible = "socionext,uniphier-pro4-pinctrl"; }; &sysctrl { diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index cbdc3ebbff..682b7958fa 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -56,20 +56,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial1 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart1 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index bd1b4b1b66..05f961f588 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -355,6 +355,11 @@ clock-frequency = <400000>; }; + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + emmc: sdhc@68400000 { compatible = "socionext,uniphier-sdhc"; status = "disabled"; @@ -431,7 +436,7 @@ }; &pinctrl { - compatible = "socionext,ph1-pro5-pinctrl", "syscon"; + compatible = "socionext,uniphier-pro5-pinctrl"; }; &sysctrl { diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 789713db12..c3adaf170b 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -349,6 +349,11 @@ clocks = <&mio 7>, <&mio 6>; }; + aidet@f1830000 { + compatible = "simple-mfd", "syscon"; + reg = <0xf1830000 0x200>; + }; + sysctrl: sysctrl@f1840000 { compatible = "socionext,ph1-sld3-sysctrl"; reg = <0xf1840000 0x4000>; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index 8ceb93e9f5..9af012cab7 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -73,20 +73,10 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial0 { u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 61e0b45781..e0376a1e96 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -274,6 +274,11 @@ pinctrl-0 = <&pinctrl_usb2>; clocks = <&mio 5>, <&mio 6>; }; + + aidet@61830000 { + compatible = "simple-mfd", "syscon"; + reg = <0x61830000 0x200>; + }; }; &refclk { @@ -310,7 +315,7 @@ }; &pinctrl { - compatible = "socionext,ph1-sld8-pinctrl", "syscon"; + compatible = "socionext,uniphier-sld8-pinctrl"; }; &sysctrl { diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index 2d36f98514..2810f3b3e1 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -47,6 +47,11 @@ function = "nand"; }; + pinctrl_nand2cs: nand2cs_grp { + groups = "nand", "nand_cs1"; + function = "nand"; + }; + pinctrl_sd: sd_grp { groups = "sd"; function = "sd"; @@ -67,6 +72,11 @@ function = "sd1"; }; + pinctrl_system_bus: system_bus_grp { + groups = "system_bus", "system_bus_cs1"; + function = "system_bus"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index eb1d2bcc63..61f61641af 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -65,12 +65,6 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial2 { u-boot,dm-pre-reloc; }; @@ -83,10 +77,6 @@ u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart2 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index e7d5db8894..3d5b300716 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -50,12 +50,6 @@ }; /* for U-Boot only */ -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - &serial2 { u-boot,dm-pre-reloc; }; @@ -68,10 +62,6 @@ u-boot,dm-pre-reloc; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pinctrl_uart2 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 12968bdd17..23a6bfac87 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -383,6 +383,11 @@ bus-width = <4>; }; + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; @@ -435,7 +440,7 @@ }; &pinctrl { - compatible = "socionext,proxstream2-pinctrl", "syscon"; + compatible = "socionext,uniphier-pxs2-pinctrl"; }; &sysctrl { diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi index b8960fdc58..6d25104281 100644 --- a/arch/arm/dts/uniphier-ref-daughter.dtsi +++ b/arch/arm/dts/uniphier-ref-daughter.dtsi @@ -7,7 +7,7 @@ */ &i2c0 { - eeprom { + eeprom@50 { compatible = "microchip,24lc128", "i2c-eeprom"; reg = <0x50>; u-boot,i2c-offset-len = <2>; diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index caa45cfabf..bdcda7de93 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -70,7 +70,7 @@ u32 spl_boot_device(void) #if defined(CONFIG_SPL_MMC_SUPPORT) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { switch (spl_boot_device()) { /* for MMC return either RAW or FAT mode */ diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h new file mode 100644 index 0000000000..7e72882725 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h @@ -0,0 +1,15 @@ +/* + * Copyright 2016 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +/* BOOT0 header information */ +#define ARM_SOC_BOOT0_HOOK \ + .word 0xbabeface; \ + .word _end - _start + +#endif /* __BOOT0_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index df877ddc7d..197b0eb5a5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,13 +8,13 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), - CPU_TYPE_ENTRY(LS1043, LS1043, 4), - CPU_TYPE_ENTRY(LS1023, LS1023, 2), - CPU_TYPE_ENTRY(LS2040, LS2040, 4), - CPU_TYPE_ENTRY(LS1012, LS1012, 1), + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 2cb6c5430e..39e8c7a17c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -41,13 +41,13 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012 0x870400 -#define SVR_LS1043 0x879200 -#define SVR_LS1023 0x879208 -#define SVR_LS2045 0x870120 -#define SVR_LS2080 0x870110 -#define SVR_LS2085 0x870100 -#define SVR_LS2040 0x870130 +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 7677358742..76b75d8e46 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -42,11 +42,14 @@ int arch_fixup_fdt(void *blob) } ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); -#ifdef CONFIG_ARMV7_NONSEC if (ret) return ret; +#ifdef CONFIG_ARMV7_NONSEC ret = psci_update_dt(blob); + if (ret) + return ret; #endif - return ret; + + return 0; } diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 6180699fed..13e19ba2fe 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -122,16 +122,28 @@ config TARGET_CORVUS bool "Support corvus" select CPU_ARM926EJS select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO + select DM_ETH config TARGET_TAURUS bool "Support taurus" select CPU_ARM926EJS select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO + select DM_ETH config TARGET_SMARTWEB bool "Support smartweb" select CPU_ARM926EJS select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO + select DM_ETH config TARGET_VINCO bool "Support VINCO" diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h index 2379dd40f8..61e36c46fb 100644 --- a/arch/arm/mach-at91/include/mach/at91_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91_matrix.h @@ -15,7 +15,7 @@ #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) #elif defined(CONFIG_AT91SAM9263) #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) -#elif defined(CONFIG_AT91SAM9G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) #else #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU @@ -33,7 +33,7 @@ #elif defined(CONFIG_AT91SAM9263) #define AT91_MATRIX_MASTERS 9 #define AT91_MATRIX_SLAVES 7 -#elif defined(CONFIG_AT91SAM9G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_MASTERS 11 #define AT91_MATRIX_SLAVES 8 #else @@ -63,7 +63,7 @@ typedef struct at91_matrix { u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; u32 mrcr; /* 0x100 Master Remap Control */ u32 reserve4[3]; -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ u32 womr; /* 0x1E4 Write Protect Mode */ u32 wpsr; /* 0x1E8 Write Protect Status */ @@ -106,14 +106,14 @@ typedef struct at91_matrix { /* Undefined Length Burst Type */ #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ - defined(CONFIG_AT91SAM9G45) + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 #endif -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007 @@ -125,14 +125,15 @@ typedef struct at91_matrix { #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 /* Fixed Index of Default Master */ -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \ + defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) #endif /* Maximum Number of Allowed Cycles for a Burst */ -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263) @@ -147,13 +148,14 @@ typedef struct at91_matrix { /* Master Remap Control Register */ #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ - defined(CONFIG_AT91SAM9G45) + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_MRCR_RCB0 (1 << 0) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ #define AT91_MATRIX_MRCR_RCB1 (1 << 1) #endif -#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ + defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_MRCR_RCB2 0x00000004 #define AT91_MATRIX_MRCR_RCB3 0x00000008 #define AT91_MATRIX_MRCR_RCB4 0x00000010 @@ -162,14 +164,14 @@ typedef struct at91_matrix { #define AT91_MATRIX_MRCR_RCB7 0x00000080 #define AT91_MATRIX_MRCR_RCB8 0x00000100 #endif -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #define AT91_MATRIX_MRCR_RCB9 0x00000200 #define AT91_MATRIX_MRCR_RCB10 0x00000400 #define AT91_MATRIX_MRCR_RCB11 0x00000800 #endif /* TCM Configuration Register */ -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* Size of ITCM enabled memory block */ #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040 @@ -204,7 +206,7 @@ typedef struct at91_matrix { #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 #endif -#if defined(CONFIG_AT91SAM9G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* Video Mode Configuration Register */ #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index f255b59195..98f280cbf7 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -75,9 +75,9 @@ u32 spl_boot_device(void) } #endif -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { - switch (spl_boot_device()) { + switch (boot_device) { #ifdef CONFIG_SYS_USE_MMC case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 49349da179..0aeaa7d8b7 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -45,7 +45,7 @@ void spl_board_init(void) preloader_console_init(); } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 77d3cfec59..af3be59097 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -26,6 +26,6 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x1000 -source "board/hardkernel/odroid-c2/Kconfig" +source "board/amlogic/odroid-c2/Kconfig" endif diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index ac5bb2c209..e1c9cdba50 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -57,7 +57,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index e133cca57a..15f1266a7b 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -66,7 +66,7 @@ fallback: return BOOT_DEVICE_MMC1; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 98c16a000d..fec4c7a991 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -58,7 +58,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) return MMCSD_MODE_FS; diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index bd15b9bfb0..66e028ec14 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -257,7 +257,7 @@ void spl_board_announce_boot_device(void) } /* No confirmation data available in SPL yet. Hardcode bootmode */ -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index e2bb1fcb44..cc34116baa 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -29,7 +29,7 @@ ENTRY(lowlevel_init) bl debug_ll_init #endif - bl setup_init_ram @ RAM area for stack and page talbe + bl setup_init_ram @ RAM area for stack and page table /* * Now we are using the page table embedded in the Boot ROM. diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index f853701f44..d35d38dcbf 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -4,10 +4,47 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <libfdt.h> +#include <linux/io.h> + #include "init.h" #include "micro-support-card.h" #include "soc-info.h" +DECLARE_GLOBAL_DATA_PTR; + +static void uniphier_setup_xirq(void) +{ + const void *fdt = gd->fdt_blob; + int soc_node, aidet_node; + const u32 *val; + unsigned long aidet_base; + u32 tmp; + + soc_node = fdt_path_offset(fdt, "/soc"); + if (soc_node < 0) + return; + + aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5); + if (aidet_node < 0) + return; + + val = fdt_getprop(fdt, aidet_node, "reg", NULL); + if (!val) + return; + + aidet_base = fdt32_to_cpu(*val); + + tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */ + tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */ + writel(tmp, aidet_base + 8); + + tmp = readl(0x55000090); /* IRQCTL */ + tmp |= 0x000000ff; + writel(tmp, 0x55000090); +} + int board_early_init_f(void) { led_puts("U0"); @@ -81,6 +118,8 @@ int board_early_init_f(void) break; } + uniphier_setup_xirq(); + led_puts("U2"); return 0; diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index d34b9af9a1..1d531402d5 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -77,7 +77,7 @@ u32 spl_boot_device(void) return mode; } -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { struct mmc *mmc; diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c index 6066b169cf..645b90151c 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c @@ -43,4 +43,9 @@ void uniphier_ld20_pin_init(void) sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ sg_set_iectrl_range(46, 53); #endif + + sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ + sg_set_iectrl(149); + sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ + sg_set_iectrl(153); } diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 6c5415ac8f..e8added155 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -69,7 +69,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(void) +u32 spl_boot_mode(const u32 boot_device) { return MMCSD_MODE_FS; } diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index b6e870a7cb..d663656bf9 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -18,4 +18,3 @@ obj-y += coreboot.o obj-y += tables.o obj-y += sdram.o obj-y += timestamp.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c deleted file mode 100644 index 7f5087a918..0000000000 --- a/arch/x86/cpu/coreboot/pci.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008,2009 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <pci.h> - -static const struct udevice_id generic_pch_ids[] = { - { .compatible = "intel,pch7" }, - { .compatible = "intel,pch9" }, - { } -}; - -U_BOOT_DRIVER(generic_pch_drv) = { - .name = "pch", - .id = UCLASS_PCH, - .of_match = generic_pch_ids, -}; |
