diff options
Diffstat (limited to 'arch/x86/include/asm/arch-ivybridge')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/me.h | 333 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/microcode.h | 23 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/pch.h | 62 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 |
5 files changed, 1 insertions, 441 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h index eb1b73f92e..bc1bc8e778 100644 --- a/arch/x86/include/asm/arch-ivybridge/me.h +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -9,225 +9,7 @@ #ifndef _ASM_INTEL_ME_H #define _ASM_INTEL_ME_H -#include <linux/compiler.h> -#include <linux/types.h> - -#define ME_RETRY 100000 /* 1 second */ -#define ME_DELAY 10 /* 10 us */ - -/* - * Management Engine PCI registers - */ - -#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ -#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ - -#define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 - -struct me_hfs { - u32 working_state:4; - u32 mfg_mode:1; - u32 fpt_bad:1; - u32 operation_state:3; - u32 fw_init_complete:1; - u32 ft_bup_ld_flr:1; - u32 update_in_progress:1; - u32 error_code:4; - u32 operation_mode:4; - u32 reserved:4; - u32 boot_options_present:1; - u32 ack_data:3; - u32 bios_msg_ack:4; -} __packed; - -#define PCI_ME_UMA 0x44 - -struct me_uma { - u32 size:6; - u32 reserved_1:10; - u32 valid:1; - u32 reserved_0:14; - u32 set_to_one:1; -} __packed; - -#define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 - -struct me_did { - u32 uma_base:16; - u32 reserved:8; - u32 status:4; - u32 init_done:4; -} __packed; - -#define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 - -struct me_gmes { - u32 bist_in_prog:1; - u32 icc_prog_sts:2; - u32 invoke_mebx:1; - u32 cpu_replaced_sts:1; - u32 mbp_rdy:1; - u32 mfs_failure:1; - u32 warm_rst_req_for_df:1; - u32 cpu_replaced_valid:1; - u32 reserved_1:2; - u32 fw_upd_ipu:1; - u32 reserved_2:4; - u32 current_state:8; - u32 current_pmevent:4; - u32 progress_code:4; -} __packed; - -#define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) - -struct me_heres { - u32 extend_reg_algorithm:4; - u32 reserved:26; - u32 extend_feature_present:1; - u32 extend_reg_valid:1; -} __packed; - -/* - * Management Engine MEI registers - */ - -#define MEI_H_CB_WW 0x00 -#define MEI_H_CSR 0x04 -#define MEI_ME_CB_RW 0x08 -#define MEI_ME_CSR_HA 0x0c - -struct mei_csr { - u32 interrupt_enable:1; - u32 interrupt_status:1; - u32 interrupt_generate:1; - u32 ready:1; - u32 reset:1; - u32 reserved:3; - u32 buffer_read_ptr:8; - u32 buffer_write_ptr:8; - u32 buffer_depth:8; -} __packed; - -#define MEI_ADDRESS_CORE 0x01 -#define MEI_ADDRESS_AMT 0x02 -#define MEI_ADDRESS_RESERVED 0x03 -#define MEI_ADDRESS_WDT 0x04 -#define MEI_ADDRESS_MKHI 0x07 -#define MEI_ADDRESS_ICC 0x08 -#define MEI_ADDRESS_THERMAL 0x09 - -#define MEI_HOST_ADDRESS 0 - -struct mei_header { - u32 client_address:8; - u32 host_address:8; - u32 length:9; - u32 reserved:6; - u32 is_complete:1; -} __packed; - -#define MKHI_GROUP_ID_CBM 0x00 -#define MKHI_GROUP_ID_FWCAPS 0x03 -#define MKHI_GROUP_ID_MDES 0x08 -#define MKHI_GROUP_ID_GEN 0xff - -#define MKHI_GLOBAL_RESET 0x0b - -#define MKHI_FWCAPS_GET_RULE 0x02 - -#define MKHI_MDES_ENABLE 0x09 - -#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_END_OF_POST 0x0c -#define MKHI_FEATURE_OVERRIDE 0x14 - -struct mkhi_header { - u32 group_id:8; - u32 command:7; - u32 is_response:1; - u32 reserved:8; - u32 result:8; -} __packed; - -struct me_fw_version { - u16 code_minor; - u16 code_major; - u16 code_build_number; - u16 code_hot_fix; - u16 recovery_minor; - u16 recovery_major; - u16 recovery_build_number; - u16 recovery_hot_fix; -} __packed; - - -#define HECI_EOP_STATUS_SUCCESS 0x0 -#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 - -#define CBM_RR_GLOBAL_RESET 0x01 - -#define GLOBAL_RESET_BIOS_MRC 0x01 -#define GLOBAL_RESET_BIOS_POST 0x02 -#define GLOBAL_RESET_MEBX 0x03 - -struct me_global_reset { - u8 request_origin; - u8 reset_type; -} __packed; - -enum me_bios_path { - ME_NORMAL_BIOS_PATH, - ME_S3WAKE_BIOS_PATH, - ME_ERROR_BIOS_PATH, - ME_RECOVERY_BIOS_PATH, - ME_DISABLE_BIOS_PATH, - ME_FIRMWARE_UPDATE_BIOS_PATH, -}; +#include <asm/me_common.h> struct __packed mbp_fw_version_name { u32 major_version:16; @@ -244,46 +26,6 @@ struct __packed mbp_icc_profile { u32 register_lock_mask[3]; }; -struct __packed mefwcaps_sku { - u32 full_net:1; - u32 std_net:1; - u32 manageability:1; - u32 small_business:1; - u32 l3manageability:1; - u32 intel_at:1; - u32 intel_cls:1; - u32 reserved:3; - u32 intel_mpc:1; - u32 icc_over_clocking:1; - u32 pavp:1; - u32 reserved_1:4; - u32 ipv6:1; - u32 kvm:1; - u32 och:1; - u32 vlan:1; - u32 tls:1; - u32 reserved_4:1; - u32 wlan:1; - u32 reserved_5:8; -}; - -struct __packed tdt_state_flag { - u16 lock_state:1; - u16 authenticate_module:1; - u16 s3authentication:1; - u16 flash_wear_out:1; - u16 flash_variable_security:1; - u16 wwan3gpresent:1; - u16 wwan3goob:1; - u16 reserved:9; -}; - -struct __packed tdt_state_info { - u8 state; - u8 last_theft_trigger; - struct tdt_state_flag flags; -}; - struct __packed platform_type_rule_data { u32 platform_target_usage_type:4; u32 platform_target_market_type:2; @@ -299,16 +41,6 @@ struct __packed mbp_fw_caps { u8 available; }; -struct __packed mbp_rom_bist_data { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; -}; - -struct __packed mbp_platform_key { - u32 key[8]; -}; - struct __packed mbp_plat_type { struct platform_type_rule_data rule_data; u8 available; @@ -325,67 +57,4 @@ struct __packed me_bios_payload { u32 mfsintegrity; }; -struct __packed mbp_header { - u32 mbp_size:8; - u32 num_entries:8; - u32 rsvd:16; -}; - -struct __packed mbp_item_header { - u32 app_id:8; - u32 item_id:8; - u32 length:8; - u32 rsvd:8; -}; - -struct __packed me_fwcaps { - u32 id; - u8 length; - struct mefwcaps_sku caps_sku; - u8 reserved[3]; -}; - -/** - * intel_me_status() - Check Intel Management Engine status - * - * struct hfs: Firmware status - * struct gmes: Management engine status - */ -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); - -/** - * intel_early_me_status() - Check early Management Engine Status - * - * @me_dev: Management engine PCI device - */ -void intel_early_me_status(struct udevice *me_dev); - -/** - * intel_early_me_init() - Early Intel Management Engine init - * - * @me_dev: Management engine PCI device - * @return 0 if OK, -ve on error - */ -int intel_early_me_init(struct udevice *me_dev); - -/** - * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine - * - * @me_dev: Management engine PCI device - * @return UMA size if OK, -EINVAL on error - */ -int intel_early_me_uma_size(struct udevice *me_dev); - -/** - * intel_early_me_init_done() - Complete Intel Management Engine init - * - * @dev: Northbridge device - * @me_dev: Management engine PCI device - * @status: Status result (ME_INIT_...) - * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT - * if ME did not respond - */ -int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, - uint status); - #endif diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h deleted file mode 100644 index 67f32cc38f..0000000000 --- a/arch/x86/include/asm/arch-ivybridge/microcode.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MICROCODE_H -#define __ASM_ARCH_MICROCODE_H - -#ifndef __ASSEMBLY__ - -/** - * microcode_update_intel() - Apply microcode updates - * - * Applies any microcode updates in the device tree. - * - * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if - * not updates were found, -EINVAL if an update was invalid - */ -int microcode_update_intel(void); -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index d2f9006093..22f7929a82 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -15,13 +15,9 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -31,12 +27,8 @@ #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 -#define MSR_PIC_MSG_CONTROL 0x2e -#define PLATFORM_INFO_SET_TDP (1 << 29) - #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKGC3_IRTL 0x60a #define MSR_PKGC6_IRTL 0x60b @@ -50,13 +42,6 @@ #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) -/* long duration in low dword, short duration in high dword */ -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_PP0_CURRENT_CONFIG 0x601 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ #define MSR_PP1_CURRENT_CONFIG 0x602 @@ -65,11 +50,9 @@ #define MSR_PKG_POWER_SKU 0x614 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 -#define MSR_CONFIG_TDP_NOMINAL 0x648 #define MSR_CONFIG_TDP_LEVEL1 0x649 #define MSR_CONFIG_TDP_LEVEL2 0x64a #define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index af3e8e747c..4725250d91 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -69,8 +69,6 @@ #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -99,60 +97,11 @@ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ -#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LPC_GENX_DEC(x) (0x84 + 4 * (x)) -#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ -#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ -#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ -#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ -#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ -#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ -#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ -#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ - /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) -#define INTR_LN 0x3c -#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) -#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ - #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ #define IDE_SSDE1 (1 << 3) #define IDE_SSDE0 (1 << 2) @@ -211,13 +160,6 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) - -/* Root Complex Register Block */ -#define DEFAULT_RCBA 0xfed1c000 -#define RCB_REG(reg) (DEFAULT_RCBA + (reg)) - -#define PCH_RCBA_BASE 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ @@ -339,16 +281,12 @@ #define SPI_FREQ_SWSEQ 0x3893 #define SPI_DESC_COMP0 0x38b0 #define SPI_FREQ_WR_ERA 0x38b4 -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8 #define DIR_ROUTE(a, b, c, d) \ (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) -#define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ -#define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ #define PCH_DISABLE_GBE (1 << 5) #define FD 0x3418 /* 32bit */ diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index d137d6786a..8e0f668f0b 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -38,7 +38,6 @@ #define IED_SIZE 0x400000 /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 @@ -97,8 +96,6 @@ /* * MCHBAR */ -#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) - #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ @@ -116,8 +113,4 @@ */ int bridge_silicon_revision(struct udevice *dev); -void report_platform_info(struct udevice *dev); - -void sandybridge_early_init(int chipset_type); - #endif |
