23 files changed, 527 insertions, 642 deletions

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 5be5491643..a0216f3059 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += early_uart.o
 obj-y += fsp_configs.o
 obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
new file mode 100644
index 0000000000..5ee4868cf8
--- /dev/null
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 25382f9aab..b31f24e262 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -53,14 +53,6 @@ int arch_misc_init(void)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
 #endif
 
 void reset_cpu(ulong addr)
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index f0798a7f9e..317f57d3f9 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -109,7 +109,8 @@ static void pch_enable_ioapic(void)
 {
 	u32 reg32;
 
-	io_apic_set_id(0x02);
+	/* Make sure this is a unique ID within system */
+	io_apic_set_id(0x04);
 
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(0x01);
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 4bf5d15b26..e7befde6ad 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 int dram_init(void)
 {
 	struct pei_data _pei_data __aligned(8);
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 845f86a176..1b042037bb 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,15 +39,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
-	return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -79,6 +71,16 @@ void board_final_cleanup(void)
 	}
 }
 
+int last_stage_init(void)
+{
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
+	board_final_cleanup();
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 233a6c8695..269043dedc 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -24,11 +24,14 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <syscon.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
+#include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
@@ -661,10 +664,20 @@ void show_boot_progress(int val)
 }
 
 #ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	write_tables();
 
+	board_final_cleanup();
+
 	return 0;
 }
 #endif
@@ -739,5 +752,24 @@ int cpu_init_r(void)
 	uclass_first_device(UCLASS_PCH, &dev);
 	uclass_first_device(UCLASS_LPC, &dev);
 
+	/* Set up pin control if available */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
+	return 0;
+}
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+	high_table_reserve();
+#endif
+
 	return 0;
 }
+#endif
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 10dc4d47f0..dd2819a12c 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -15,14 +15,14 @@
 #include <dm.h>
 #include <asm/cache.h>
 #include <asm/control_regs.h>
+#include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/processor.h>
 #include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -266,6 +266,8 @@ int interrupt_init(void)
 	i8259_init();
 #endif
 
+	lapic_setup();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 2950783055..df3cd0abc7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +122,11 @@ static int create_pirq_routing_table(struct udevice *dev)
 	priv->irq_mask = fdtdec_get_int(blob, node,
 					"intel,pirq-mask", PIRQ_BITMAP);
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve IRQ9 for SCI */
+		priv->irq_mask &= ~(1 << 9);
+	}
+
 	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
@@ -142,6 +148,9 @@ static int create_pirq_routing_table(struct udevice *dev)
 		priv->ibase &= ~0xf;
 	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 	if (!cell || len % sizeof(struct pirq_routing))
 		return -EINVAL;
@@ -206,11 +215,30 @@ static int create_pirq_routing_table(struct udevice *dev)
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+	/* Fix up the table checksum */
+	rt->checksum = table_compute_checksum(rt, rt->size);
+
 	pirq_routing_table = rt;
 
 	return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
 	int ret;
@@ -224,6 +252,9 @@ int irq_router_common_init(struct udevice *dev)
 	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		irq_enable_sci(dev);
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 88ab7973fd..ff1faa5014 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <rtc.h>
 #include <pci.h>
-#include <asm/acpi.h>
 #include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index cef425669c..38e244b05e 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,10 +12,8 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
@@ -419,7 +417,6 @@ static int model_206ax_init(struct udevice *dev)
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index f7e0bc3f18..491f2894f9 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/msr.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e35e543c3e..9d9f63d70c 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -201,11 +201,6 @@ static int recovery_mode_enabled(void)
 	return false;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
 	const void *data;
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d23130eb..fbea2d1572 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v)
 
 void enable_lapic(void)
 {
-	msr_t msr;
-
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.hi &= 0xffffff00;
-	msr.lo |= MSR_IA32_APICBASE_ENABLE;
-	msr.lo &= ~MSR_IA32_APICBASE_BASE;
-	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(MSR_IA32_APICBASE, msr);
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
+
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.hi &= 0xffffff00;
+		msr.lo |= MSR_IA32_APICBASE_ENABLE;
+		msr.lo &= ~MSR_IA32_APICBASE_BASE;
+		msr.lo |= LAPIC_DEFAULT_BASE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 void disable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 unsigned long lapicid(void)
@@ -120,7 +124,6 @@ int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 
 void lapic_setup(void)
 {
-#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
@@ -150,11 +153,7 @@ void lapic_setup(void)
 		    LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
-	/* Only Pentium Pro and later have those MSR stuff */
-	debug("Disabling local apic: ");
-	disable_lapic();
-#endif /* CONFIG_SMP */
+
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2604a687ab..2b6b3bd04e 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
@@ -21,7 +22,6 @@
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/sipi.h>
-#include <asm/fw_cfg.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 #include <dm/lists.h>
@@ -408,8 +408,6 @@ static int init_bsp(struct udevice **devp)
 	cpu_get_name(processor_name);
 	debug("CPU: %s\n", processor_name);
 
-	lapic_setup();
-
 	apic_id = lapicid();
 	ret = find_cpu_by_apic_id(apic_id, devp);
 	if (ret) {
@@ -420,7 +418,7 @@ static int init_bsp(struct udevice **devp)
 	return 0;
 }
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 static int qemu_cpu_fixup(void)
 {
 	int ret;
@@ -496,7 +494,7 @@ int mp_init(struct mp_params *p)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 	ret = qemu_cpu_fixup();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 6eeddf154e..a080c5e2f4 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,4 +7,5 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index a1b70c6bde..b1a965e715 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,8 +8,8 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
+#include <qfw.h>
 #include <asm/cpu.h>
-#include <asm/fw_cfg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
new file mode 100644
index 0000000000..63853e4b22
--- /dev/null
+++ b/arch/x86/cpu/qemu/e820.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
deleted file mode 100644
index 2e2794ebd7..0000000000
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/fw_cfg.h>
-#include <asm/tables.h>
-#include <asm/e820.h>
-#include <linux/list.h>
-#include <memalign.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
-		uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
- *          memory allocation request is 'ZONE_HIGH' then this parameter will
- *          be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
-{
-	uint32_t size, align;
-	struct fw_file *file;
-	unsigned long aligned_addr;
-
-	align = le32_to_cpu(entry->alloc.align);
-	/* align must be power of 2 */
-	if (align & (align - 1)) {
-		printf("error: wrong alignment %u\n", align);
-		return -EINVAL;
-	}
-
-	file = qemu_fwcfg_find_file(entry->alloc.file);
-	if (!file) {
-		printf("error: can't find file %s\n", entry->alloc.file);
-		return -ENOENT;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-
-	/*
-	 * ZONE_HIGH means we need to allocate from high memory, since
-	 * malloc space is already at the end of RAM, so we directly use it.
-	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
-	 * in which is low memory
-	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
-		aligned_addr = (unsigned long)memalign(align, size);
-		if (!aligned_addr) {
-			printf("error: allocating resource\n");
-			return -ENOMEM;
-		}
-	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
-		aligned_addr = ALIGN(*addr, align);
-	} else {
-		printf("error: invalid allocation zone\n");
-		return -EINVAL;
-	}
-
-	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
-	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, (void *)aligned_addr);
-	file->addr = aligned_addr;
-
-	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
-		*addr = (aligned_addr + size);
-
-	return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- *          ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
-{
-	struct fw_file *dest, *src;
-	uint32_t offset = le32_to_cpu(entry->pointer.offset);
-	uint64_t pointer = 0;
-
-	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
-	if (!dest || !dest->addr)
-		return -ENOENT;
-	src = qemu_fwcfg_find_file(entry->pointer.src_file);
-	if (!src || !src->addr)
-		return -ENOENT;
-
-	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
-	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
-	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
-	pointer	= le64_to_cpu(pointer);
-	pointer += (unsigned long)src->addr;
-	pointer	= cpu_to_le64(pointer);
-	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
-	return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- *          checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
-{
-	struct fw_file *file;
-	uint8_t *data, cksum = 0;
-	uint8_t *cksum_start;
-
-	file = qemu_fwcfg_find_file(entry->cksum.file);
-	if (!file || !file->addr)
-		return -ENOENT;
-
-	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
-	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
-	cksum = table_compute_checksum(cksum_start,
-				       le32_to_cpu(entry->cksum.length));
-	*data = cksum;
-
-	return 0;
-}
-
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
-
-/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
-{
-	int i, ret = 0;
-	struct fw_file *file;
-	struct bios_linker_entry *table_loader;
-	struct bios_linker_entry *entry;
-	uint32_t size;
-	struct list_head *list;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret) {
-		printf("error: can't read firmware file list\n");
-		return addr;
-	}
-
-	file = qemu_fwcfg_find_file("etc/table-loader");
-	if (!file) {
-		printf("error: can't find etc/table-loader\n");
-		return addr;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-	if ((size % sizeof(*entry)) != 0) {
-		printf("error: table-loader maybe corrupted\n");
-		return addr;
-	}
-
-	table_loader = malloc(size);
-	if (!table_loader) {
-		printf("error: no memory for table-loader\n");
-		return addr;
-	}
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, table_loader);
-
-	for (i = 0; i < (size / sizeof(*entry)); i++) {
-		entry = table_loader + i;
-		switch (le32_to_cpu(entry->command)) {
-		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(entry, &addr);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
-			ret = bios_linker_add_pointer(entry);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
-			ret = bios_linker_add_checksum(entry);
-			if (ret)
-				goto out;
-			break;
-		default:
-			break;
-		}
-	}
-
-out:
-	if (ret) {
-		list_for_each(list, &fw_list) {
-			file = list_entry(list, struct fw_file, list);
-			if (file->addr)
-				free((void *)file->addr);
-		}
-	}
-
-	free(table_loader);
-	return addr;
-}
-#endif
-
-static int qemu_fwcfg_list_firmware(void)
-{
-	int ret;
-	struct list_head *entry;
-	struct fw_file *file;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		printf("%-56s\n", file->cfg.name);
-	}
-
-	return 0;
-}
-
-void qemu_fwcfg_init(void)
-{
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
-}
-
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
-
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-	}
-
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
-
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
-
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
-
-	if (!fwcfg_present) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
-	}
-
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
-
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
-
-	return cmd_process_error(fwcfg_cmd, ret);
-}
-
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7ad0ee49a1..680e558ee8 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,15 +6,59 @@
 
 #include <common.h>
 #include <pci.h>
+#include <qfw.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
 #include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
 
 static bool i440fx;
 
+#ifdef CONFIG_QFW
+
+/* on x86, the qfw registers are all IO ports */
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 *
+	 * Note: on platform where the control register is IO port, the
+	 * endianness is little endian.
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+	/* the endianness of data register is string-preserving */
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+	/* the DMA address register is big endian */
+	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -88,7 +132,9 @@ static void qemu_chipset_init(void)
 		enable_pm_ich9();
 	}
 
-	qemu_fwcfg_init();
+#ifdef CONFIG_QFW
+	qemu_fwcfg_init(&fwcfg_x86_ops);
+#endif
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 6d670d75c1..93ce412166 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += car.o dram.o irq.o msg_port.o quark.o
 obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
new file mode 100644
index 0000000000..8f69829608
--- /dev/null
+++ b/arch/x86/cpu/quark/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0x00;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index afb3463797..bdd360a99f 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/ioapic.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -338,6 +339,9 @@ int arch_misc_init(void)
 	mrccache_save();
 #endif
 
+	/* Assign a unique I/O APIC ID */
+	io_apic_set_id(1);
+
 	return 0;
 }
 
@@ -360,12 +364,3 @@ void board_final_cleanup(void)
 
 	return;
 }
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}