1 files changed, 34 insertions, 37 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index 8a20a2b1e0..161d274dff 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))
 #define NUMMEMTESTS		8
 #define NUMMEMWORDS		8
 #define MAXBXCR			4
-#define TRUE			1
-#define FALSE			0
 
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
@@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 	unsigned char num_of_bytes;
 	unsigned char total_size;
 
-	dimm_found = FALSE;
+	dimm_found = false;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		num_of_bytes = 0;
 		total_size = 0;
@@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated,
 		total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 
 		if ((num_of_bytes != 0) && (total_size != 0)) {
-			dimm_populated[dimm_num] = TRUE;
-			dimm_found = TRUE;
+			dimm_populated[dimm_num] = true;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated\n", dimm_num);
 		} else {
-			dimm_populated[dimm_num] = FALSE;
+			dimm_populated[dimm_num] = false;
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
 
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 		spd_ddr_init_hang ();
 	}
@@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated,
 	unsigned char dimm_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 			switch (dimm_type) {
 			case 7:
@@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated,
 	unsigned long voltage_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 			if (voltage_type != 0x04) {
 				printf("ERROR: DIMM %lu with unsupported voltage level.\n",
@@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * FIXME: assume the DDR SDRAMs in both banks are the same
 	 */
-	ecc_enabled = TRUE;
+	ecc_enabled = true;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 			if (ecc != 0x02) {
-				ecc_enabled = FALSE;
+				ecc_enabled = false;
 			}
 
 			/*
@@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * program Memory Data Error Checking
 	 */
-	if (ecc_enabled == TRUE) {
+	if (ecc_enabled == true) {
 		cfg0 |= SDRAM_CFG0_MCHK_GEN;
 	} else {
 		cfg0 |= SDRAM_CFG0_MCHK_NON;
@@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated,
 	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 
 	for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 			switch (refresh_rate_type) {
 			case 0x00:
@@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated,
 	t_rp_ns = 0;
 	t_rcd_ns = 0;
 	t_ras_ns = 0;
-	cas_2_0_available = TRUE;
-	cas_2_5_available = TRUE;
-	cas_3_0_available = TRUE;
+	cas_2_0_available = true;
+	cas_2_5_available = true;
+	cas_3_0_available = true;
 	tcyc_2_0_ns_x_10 = 0;
 	tcyc_2_5_ns_x_10 = 0;
 	tcyc_3_0_ns_x_10 = 0;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 			t_rp_ns	 = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 			t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
@@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_3_0_available = FALSE;
+				cas_3_0_available = false;
 			}
 
 			if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
@@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_5_available = FALSE;
+				cas_2_5_available = false;
 			}
 
 			if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
@@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_0_available = FALSE;
+				cas_2_0_available = false;
 			}
 
 			break;
@@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated,
 	/*
 	 * Program SD_CASL field
 	 */
-	if ((cas_2_0_available == TRUE) &&
+	if ((cas_2_0_available == true) &&
 	    (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
-	} else if ((cas_2_5_available == TRUE) &&
+	} else if ((cas_2_5_available == true) &&
 		 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
-	} else if ((cas_3_0_available == TRUE) &&
+	} else if ((cas_3_0_available == true) &&
 		 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 	} else {
@@ -950,9 +948,9 @@ static void program_tr1(void)
 	current_fail_length = 0;
 	current_start = 0;
 	rdclt_offset = 0;
-	window_found = FALSE;
-	fail_found = FALSE;
-	pass_found = FALSE;
+	window_found = false;
+	fail_found = false;
+	pass_found = false;
 	debug("Starting memory test ");
 
 	for (k = 0; k < NUMHALFCYCLES; k++) {
@@ -963,8 +961,8 @@ static void program_tr1(void)
 			mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 
 			if (short_mem_test()) {
-				if (fail_found == TRUE) {
-					pass_found = TRUE;
+				if (fail_found == true) {
+					pass_found = true;
 					if (current_pass_length == 0) {
 						current_start = rdclt_offset + rdclt;
 					}
@@ -983,10 +981,10 @@ static void program_tr1(void)
 				current_fail_length++;
 
 				if (current_fail_length >= (dly_val>>2)) {
-					if (fail_found == FALSE) {
-						fail_found = TRUE;
-					} else if (pass_found == TRUE) {
-						window_found = TRUE;
+					if (fail_found == false) {
+						fail_found = true;
+					} else if (pass_found == true) {
+						window_found = true;
 						break;
 					}
 				}
@@ -994,9 +992,8 @@ static void program_tr1(void)
 		}
 		debug(".");
 
-		if (window_found == TRUE) {
+		if (window_found == true)
 			break;
-		}
 
 		tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
 		rdclt_offset += dly_val;
@@ -1006,7 +1003,7 @@ static void program_tr1(void)
 	/*
 	 * make sure we find the window
 	 */
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		printf("ERROR: Cannot determine a common read delay.\n");
 		spd_ddr_init_hang ();
 	}
@@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 	bank_base_addr = CONFIG_SYS_SDRAM_BASE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
 			num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
 			num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);