diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 233 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 114 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 2 |
8 files changed, 227 insertions, 180 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f70f0d747d..50ddb5040e 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -20,149 +16,128 @@ MINIMAL=y endif endif -START = start.o resetvec.o +extra-y = start.o resetvec.o ifdef MINIMAL -COBJS-y += cpu_init_early.o tlb.o spl_minimal.o +obj-y += cpu_init_early.o tlb.o spl_minimal.o else -SOBJS-$(CONFIG_MP) += release.o -SOBJS = $(SOBJS-y) +obj-$(CONFIG_MP) += release.o -COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o -COBJS-$(CONFIG_CPM2) += commproc.o +obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o +obj-$(CONFIG_CPM2) += commproc.o # supports ddr1 -COBJS-$(CONFIG_MPC8540) += ddr-gen1.o -COBJS-$(CONFIG_MPC8560) += ddr-gen1.o -COBJS-$(CONFIG_MPC8541) += ddr-gen1.o -COBJS-$(CONFIG_MPC8555) += ddr-gen1.o +obj-$(CONFIG_MPC8540) += ddr-gen1.o +obj-$(CONFIG_MPC8560) += ddr-gen1.o +obj-$(CONFIG_MPC8541) += ddr-gen1.o +obj-$(CONFIG_MPC8555) += ddr-gen1.o # supports ddr1/2 -COBJS-$(CONFIG_MPC8548) += ddr-gen2.o -COBJS-$(CONFIG_MPC8568) += ddr-gen2.o -COBJS-$(CONFIG_MPC8544) += ddr-gen2.o +obj-$(CONFIG_MPC8548) += ddr-gen2.o +obj-$(CONFIG_MPC8568) += ddr-gen2.o +obj-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 -COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o -COBJS-$(CONFIG_MPC8572) += ddr-gen3.o -COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -COBJS-$(CONFIG_MPC8569) += ddr-gen3.o -COBJS-$(CONFIG_P1010) += ddr-gen3.o -COBJS-$(CONFIG_P1011) += ddr-gen3.o -COBJS-$(CONFIG_P1012) += ddr-gen3.o -COBJS-$(CONFIG_P1013) += ddr-gen3.o -COBJS-$(CONFIG_P1014) += ddr-gen3.o -COBJS-$(CONFIG_P1020) += ddr-gen3.o -COBJS-$(CONFIG_P1021) += ddr-gen3.o -COBJS-$(CONFIG_P1022) += ddr-gen3.o -COBJS-$(CONFIG_P1023) += ddr-gen3.o -COBJS-$(CONFIG_P1024) += ddr-gen3.o -COBJS-$(CONFIG_P1025) += ddr-gen3.o -COBJS-$(CONFIG_P2010) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o -COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o -COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o -COBJS-$(CONFIG_BSC9131) += ddr-gen3.o -COBJS-$(CONFIG_BSC9132) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T1040) += ddr-gen3.o - -COBJS-$(CONFIG_CPM2) += ether_fcc.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-$(CONFIG_FSL_CORENET) += liodn.o -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o +obj-$(CONFIG_PPC_C29X) += ddr-gen3.o +obj-$(CONFIG_MPC8572) += ddr-gen3.o +obj-$(CONFIG_MPC8536) += ddr-gen3.o +obj-$(CONFIG_MPC8569) += ddr-gen3.o +obj-$(CONFIG_P1010) += ddr-gen3.o +obj-$(CONFIG_P1011) += ddr-gen3.o +obj-$(CONFIG_P1012) += ddr-gen3.o +obj-$(CONFIG_P1013) += ddr-gen3.o +obj-$(CONFIG_P1014) += ddr-gen3.o +obj-$(CONFIG_P1020) += ddr-gen3.o +obj-$(CONFIG_P1021) += ddr-gen3.o +obj-$(CONFIG_P1022) += ddr-gen3.o +obj-$(CONFIG_P1023) += ddr-gen3.o +obj-$(CONFIG_P1024) += ddr-gen3.o +obj-$(CONFIG_P1025) += ddr-gen3.o +obj-$(CONFIG_P2010) += ddr-gen3.o +obj-$(CONFIG_P2020) += ddr-gen3.o +obj-$(CONFIG_PPC_P2041) += ddr-gen3.o +obj-$(CONFIG_PPC_P3041) += ddr-gen3.o +obj-$(CONFIG_PPC_P4080) += ddr-gen3.o +obj-$(CONFIG_PPC_P5020) += ddr-gen3.o +obj-$(CONFIG_PPC_P5040) += ddr-gen3.o +obj-$(CONFIG_PPC_T4240) += ddr-gen3.o +obj-$(CONFIG_PPC_T4160) += ddr-gen3.o +obj-$(CONFIG_PPC_B4420) += ddr-gen3.o +obj-$(CONFIG_PPC_B4860) += ddr-gen3.o +obj-$(CONFIG_BSC9131) += ddr-gen3.o +obj-$(CONFIG_BSC9132) += ddr-gen3.o +obj-$(CONFIG_PPC_T1040) += ddr-gen3.o + +obj-$(CONFIG_CPM2) += ether_fcc.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_FSL_CORENET) += liodn.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o -COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o -COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o -COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o -COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o -COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o -COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o -COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o -COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o -COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o - -COBJS-$(CONFIG_QE) += qe_io.o -COBJS-$(CONFIG_CPM2) += serial_scc.o -COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o -COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o +obj-$(CONFIG_PPC_P2041) += p2041_ids.o +obj-$(CONFIG_PPC_P3041) += p3041_ids.o +obj-$(CONFIG_PPC_P4080) += p4080_ids.o +obj-$(CONFIG_PPC_P5020) += p5020_ids.o +obj-$(CONFIG_PPC_P5040) += p5040_ids.o +obj-$(CONFIG_PPC_T4240) += t4240_ids.o +obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_B4420) += b4860_ids.o +obj-$(CONFIG_PPC_B4860) += b4860_ids.o +obj-$(CONFIG_PPC_T1040) += t1040_ids.o + +obj-$(CONFIG_QE) += qe_io.o +obj-$(CONFIG_CPM2) += serial_scc.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support -COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o -COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o -COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o -COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o -COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o -COBJS-$(CONFIG_P1010) += p1010_serdes.o -COBJS-$(CONFIG_P1011) += p1021_serdes.o -COBJS-$(CONFIG_P1012) += p1021_serdes.o -COBJS-$(CONFIG_P1013) += p1022_serdes.o -COBJS-$(CONFIG_P1014) += p1010_serdes.o -COBJS-$(CONFIG_P1017) += p1023_serdes.o -COBJS-$(CONFIG_P1020) += p1021_serdes.o -COBJS-$(CONFIG_P1021) += p1021_serdes.o -COBJS-$(CONFIG_P1022) += p1022_serdes.o -COBJS-$(CONFIG_P1023) += p1023_serdes.o -COBJS-$(CONFIG_P1024) += p1021_serdes.o -COBJS-$(CONFIG_P1025) += p1021_serdes.o -COBJS-$(CONFIG_P2010) += p2020_serdes.o -COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o -COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o -COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o -COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o -COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o -COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o -COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o -COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o -COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o -COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o -COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o - -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += cpu_init_early.o -COBJS-y += interrupts.o -COBJS-y += speed.o -COBJS-y += tlb.o -COBJS-y += traps.o +obj-$(CONFIG_PPC_C29X) += c29x_serdes.o +obj-$(CONFIG_MPC8536) += mpc8536_serdes.o +obj-$(CONFIG_MPC8544) += mpc8544_serdes.o +obj-$(CONFIG_MPC8548) += mpc8548_serdes.o +obj-$(CONFIG_MPC8568) += mpc8568_serdes.o +obj-$(CONFIG_MPC8569) += mpc8569_serdes.o +obj-$(CONFIG_MPC8572) += mpc8572_serdes.o +obj-$(CONFIG_P1010) += p1010_serdes.o +obj-$(CONFIG_P1011) += p1021_serdes.o +obj-$(CONFIG_P1012) += p1021_serdes.o +obj-$(CONFIG_P1013) += p1022_serdes.o +obj-$(CONFIG_P1014) += p1010_serdes.o +obj-$(CONFIG_P1017) += p1023_serdes.o +obj-$(CONFIG_P1020) += p1021_serdes.o +obj-$(CONFIG_P1021) += p1021_serdes.o +obj-$(CONFIG_P1022) += p1022_serdes.o +obj-$(CONFIG_P1023) += p1023_serdes.o +obj-$(CONFIG_P1024) += p1021_serdes.o +obj-$(CONFIG_P1025) += p1021_serdes.o +obj-$(CONFIG_P2010) += p2020_serdes.o +obj-$(CONFIG_P2020) += p2020_serdes.o +obj-$(CONFIG_PPC_P2041) += p2041_serdes.o +obj-$(CONFIG_PPC_P3041) += p3041_serdes.o +obj-$(CONFIG_PPC_P4080) += p4080_serdes.o +obj-$(CONFIG_PPC_P5020) += p5020_serdes.o +obj-$(CONFIG_PPC_P5040) += p5040_serdes.o +obj-$(CONFIG_PPC_T4240) += t4240_serdes.o +obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_B4420) += b4860_serdes.o +obj-$(CONFIG_PPC_B4860) += b4860_serdes.o +obj-$(CONFIG_BSC9132) += bsc9132_serdes.o +obj-$(CONFIG_PPC_T1040) += t1040_serdes.o + +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += cpu_init_early.o +obj-y += interrupts.o +obj-y += speed.o +obj-y += tlb.o +obj-y += traps.o # Stub implementations of cache management functions for USB -COBJS-y += cache.o +obj-y += cache.o endif # not minimal - -COBJS = $(COBJS-y) - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c441bd2f54..1e5a43f0e0 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include "fsl_corenet_serdes.h" @@ -245,6 +246,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A003571 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6036333eaa..b31efb7610 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> @@ -160,6 +161,12 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ @@ -284,7 +291,7 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) int enable_cluster_l2(void) { int i = 0; @@ -350,7 +357,7 @@ int cpu_init_r(void) #endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -533,7 +540,7 @@ int cpu_init_r(void) } skip_l2: -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (l2cache->l2csr0 & L2CSR0_L2E) print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 533d47ab43..2ccd9c7b95 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -273,7 +273,7 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ if (reg && !((*reg) % 8)) #else diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 39d9409d64..25db899e5f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -201,3 +201,24 @@ void fsl_serdes_init(void) #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: +#if defined(CONFIG_T4240QDS) + return "???"; +#else + return "122.88"; +#endif + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 680b5222bc..ba22f90a6f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -858,3 +858,20 @@ void fsl_serdes_init(void) } #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 4b8d928956..d08a8d212d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -18,6 +18,10 @@ DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif /* --------------------------------------------------------------- */ void get_sys_info(sys_info_t *sys_info) @@ -30,6 +34,9 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; +#endif const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -60,8 +67,11 @@ void get_sys_info(sys_info_t *sys_info) [13] = 2, /* CC4 PPL / 2 */ [14] = 4, /* CC4 PPL / 4 */ }; - uint i, freq_cc_pll[6], rcw_tmp; - uint ratio[6]; + uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) + uint rcw_tmp; +#endif + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; @@ -81,37 +91,36 @@ void get_sys_info(sys_info_t *sys_info) else sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; - ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; - ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; - ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; - ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; - ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f; - ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f; - for (i = 0; i < 6; i++) { + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; if (ratio[i] > 4) - freq_cc_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = sysclk * ratio[i]; else - freq_cc_pll[i] = sys_info->freq_systembus * ratio[i]; + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* + * As per CHASSIS2 architeture total 12 clusters are posible and * Each cluster has up to 4 cores, sharing the same PLL selection. - * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are - * cluster group A, feeding cores on cluster 1 and cluster 2. - * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 - * and cluster 4 if existing. + * The cluster clock assignment is SoC defined. + * + * Total 4 clock groups are possible with 3 PLLs each. + * as per array indices, clock group A has 0, 1, 2 numbered PLLs & + * clock group B has 3, 4, 6 and so on. + * + * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster + * depends upon the SoC architeture. Same applies to other + * clock groups and clusters. + * */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { int cluster = fsl_qoriq_core_to_cluster(cpu); u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - if (cplx_pll > 3) - printf("Unsupported architecture configuration" - " in function %s\n", __func__); - cplx_pll += (cluster / 2) * 3; + cplx_pll += cc_group[cluster] - 1; sys_info->freq_processor[cpu] = - freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } #ifdef CONFIG_PPC_B4860 #define FM1_CLK_SEL 0xe0000000 @@ -122,27 +131,30 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) rcw_tmp = in_be32(&gur->rcwsr[7]); +#endif #ifdef CONFIG_SYS_DPAA_PME +#ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_cc_pll[0]; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_cc_pll[0] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_cc_pll[0] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_cc_pll[0] / 4; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_cc_pll[1] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_cc_pll[1] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -151,6 +163,10 @@ void get_sys_info(sys_info_t *sys_info) break; } +#else + sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + +#endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN @@ -158,27 +174,28 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_cc_pll[3]; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_cc_pll[3] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_cc_pll[3] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_cc_pll[3] / 4; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_cc_pll[4] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_cc_pll[4] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -187,27 +204,28 @@ void get_sys_info(sys_info_t *sys_info) break; } #if (CONFIG_SYS_NUM_FMAN) == 2 +#ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_cc_pll[4]; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_cc_pll[4] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_cc_pll[4] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_cc_pll[4] / 4; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; break; case 6: - sys_info->freq_fman[1] = freq_cc_pll[3] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_cc_pll[3] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -215,8 +233,12 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[1] = sys_info->freq_systembus / 2; break; } +#endif #endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_SYS_DPAA_FMAN */ +#else + sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; +#endif +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ @@ -226,7 +248,7 @@ void get_sys_info(sys_info_t *sys_info) u32 cplx_pll = core_cplx_PLL[c_pll_sel]; sys_info->freq_processor[cpu] = - freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 @@ -246,9 +268,9 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_pme = sys_info->freq_systembus / 2; } @@ -257,18 +279,18 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_fman[1] = sys_info->freq_systembus / 2; } diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d329aa84ab..6a81fa73e4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -699,7 +699,7 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR |