diff options
Diffstat (limited to 'arch/arm')
34 files changed, 840 insertions, 568 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6e5544f9d7..653ecc81b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -368,6 +368,7 @@ config TARGET_AM335X_EVM select DM select DM_SERIAL select DM_GPIO + select TI_I2C_BOARD_DETECT config TARGET_AM335X_SL50 bool "Support am335x_sl50" @@ -380,6 +381,7 @@ config TARGET_AM43XX_EVM bool "Support am43xx_evm" select CPU_V7 select SUPPORT_SPL + select TI_I2C_BOARD_DETECT config TARGET_BAV335X bool "Support bav335x" diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b6db23e981..399b07c542 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -45,10 +45,10 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata lpc32xx_uart[] = { - { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, }; #if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e8d5be32b4..a99cbf9de0 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -40,14 +40,14 @@ DECLARE_GLOBAL_DATA_PTR; #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { - { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM2 - { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM3 - { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # endif # endif }; diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index e28b79568d..367d224361 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -769,7 +769,7 @@ void lock_dpll(u32 const base) wait_for_lock(base); } -void setup_clocks_for_console(void) +static void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, @@ -853,14 +853,31 @@ void do_disable_clocks(u32 const *clk_domains, disable_clock_domain(clk_domains[i]); } -void prcm_init(void) +/** + * setup_early_clocks() - Setup early clocks needed for SoC + * + * Setup clocks for console, SPL basic initialization clocks and initialize + * the timer. This is invoked prior prcm_init. + */ +void setup_early_clocks(void) { switch (omap_hw_init_context()) { case OMAP_INIT_CONTEXT_SPL: case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + setup_clocks_for_console(); enable_basic_clocks(); timer_init(); + /* Fall through */ + } +} + +void prcm_init(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: scale_vcores(*omap_vcores); setup_dplls(); setup_warmreset_time(); diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index bf7bf262c7..697d6e02da 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -163,7 +163,11 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + if (!is_dra7xx()) + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + else + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); @@ -246,33 +250,39 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; - u32 reg, i; + u32 reg, i, phy; emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + phy = readl(&emif->emif_ddr_phy_ctrl_1); /* Update PHY_REG_RDDQS_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; - for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) + for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) + for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) + for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Disable Leveling */ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); @@ -323,8 +333,10 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - if (warm_reset()) + if (warm_reset()) { emif_reset_phy(base); + writel(0x0, &emif->emif_pwr_mgmt_ctrl); + } do_ext_phy_settings(base, regs); writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, @@ -1317,6 +1329,8 @@ void dmm_init(u32 base) &hw_lisa_map_regs->dmm_lisa_map_1); writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); + + setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); } /* diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 80794f9c61..99634fd0e5 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -97,21 +97,36 @@ int arch_cpu_init(void) } #endif /* CONFIG_ARCH_CPU_INIT */ -/* - * Routine: s_init - * Description: Does early system init of watchdog, muxing, andclocks +/** + * do_board_detect() - Detect board description + * + * Function to detect board description. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak do_board_detect(void) +{ +} + +void s_init(void) +{ +} + +/** + * early_system_init - Does Early system initialization. + * + * Does early system init of watchdog, muxing, andclocks * Watchdog disable is done always. For the rest what gets done - * depends on the boot mode in which this function is executed - * 1. s_init of SPL running from SRAM - * 2. s_init of U-Boot running from FLASH - * 3. s_init of U-Boot loaded to SDRAM by SPL - * 4. s_init of U-Boot loaded to SDRAM by ROM code using the + * depends on the boot mode in which this function is executed when + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. U-Boot loaded to SDRAM by SPL + * 4. U-Boot loaded to SDRAM by ROM code using the * Configuration Header feature * Please have a look at the respective functions to see what gets * done in each of these cases * This function is called with SRAM stack. */ -void s_init(void) +void early_system_init(void) { init_omap_revision(); hw_data_init(); @@ -125,16 +140,17 @@ void s_init(void) set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD srcomp_enable(); - setup_clocks_for_console(); - do_io_settings(); #endif + setup_early_clocks(); + do_board_detect(); prcm_init(); } #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + early_system_init(); #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(); #endif @@ -143,6 +159,12 @@ void board_init_f(ulong dummy) } #endif +int arch_cpu_init_dm(void) +{ + early_system_init(); + return 0; +} + /* * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index bfa264eccc..026bf24ddc 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,9 +12,11 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" + select TI_I2C_BOARD_DETECT config TARGET_BEAGLE_X15 bool "BeagleBoard X15" + select TI_I2C_BOARD_DETECT endchoice diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index a8d63c23c8..7dc5bb7e4a 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -137,81 +137,6 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 }; -const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851ab2, - .sdram_config = 0x61851ab2, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851B32, - .sdram_config = 0x61851B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61862B32, - .sdram_config = 0x61862B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000514C, - .ref_ctrl_final = 0x0000144A, - .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x305A7FDA, - .sdram_tim3 = 0x409F86A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400D, - .emif_ddr_phy_ctlr_1 = 0x0E24400D, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, - .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, - .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, - .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -220,53 +145,6 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 }; -/* - * DRA752 EVM board has 1.5 GB of memory - * EMIF1 --> 2Gb * 2 = 512MB - * EMIF2 --> 2Gb * 4 = 1GB - * so mapping 1GB interleaved and 512MB non-interleaved - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x80640300, - .dmm_lisa_map_2 = 0xC0500220, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF1 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80500100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF2 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600200, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA722 EVM EMIF1 CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -280,25 +158,9 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - switch (emif_nr) { - case 1: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; - break; - case 2: - *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; - break; - } - break; - case DRA722_ES1_0: - *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; - break; - default: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } } @@ -313,16 +175,9 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs case OMAP5430_ES2_0: case OMAP5432_ES1_0: case OMAP5432_ES2_0: + default: *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; - break; - case DRA722_ES1_0: - default: - *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -643,11 +498,12 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_base = 0; u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; - u32 i, hw_leveling, size; + u32 i, hw_leveling, size, phy; emif_nr = (base == EMIF1_BASE) ? 1 : 2; hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + phy = regs->emif_ddr_phy_ctlr_1_init; emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); @@ -657,18 +513,35 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); - if (!hw_leveling) { - /* - * Copy the predefined PHY register values - * in case of sw leveling - */ - for (i = 1; i < 25; i++) { + /* + * Copy the predefined PHY register values + * if leveling is disabled. + */ + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK) + for (i = 1; i < 6; i++) { writel(ext_phy_ctrl_const_regs[i], &emif_ext_phy_ctrl_base[i * 2]); writel(ext_phy_ctrl_const_regs[i], &emif_ext_phy_ctrl_base[i * 2 + 1]); } - } else { + + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK) + for (i = 6; i < 11; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK) + for (i = 11; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (hw_leveling) { /* * Write the init value for HW levling to occur */ diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index 4df339c84a..cc427c3583 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -54,6 +54,8 @@ SECTIONS *(.__end) } >.sram + _image_binary_end = .; + .bss_start : { . = ALIGN(8); KEEP(*(.__bss_start)); diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi index bbc2cf91b9..a3ed444d3c 100644 --- a/arch/arm/dts/k2g.dtsi +++ b/arch/arm/dts/k2g.dtsi @@ -81,5 +81,12 @@ }; #include "k2g-netcp.dtsi" + + pmmc: pmmc@2900000 { + compatible = "ti,power-processor"; + reg = <0x02900000 0x40000>; + ti,lpsc_module = <1>; + }; + }; }; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index f30f865391..fbb52093c6 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,8 +37,9 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void setup_clocks_for_console(void); +void setup_early_clocks(void); void prcm_init(void); +void do_board_detect(void); void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); @@ -51,7 +52,6 @@ void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); -void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 7fcb783894..23a33cb233 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -48,8 +48,9 @@ void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void setup_clocks_for_console(void); +void setup_early_clocks(void); void prcm_init(void); +void do_board_detect(void); void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); @@ -62,7 +63,6 @@ void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); -void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7986e6e794..31831302aa 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -478,6 +478,12 @@ #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) /* DDR_PHY_CTRL_2 */ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 @@ -539,6 +545,9 @@ /* Memory Adapter */ #define MA_BASE 0x482AF040 +#define MA_PRIORITY 0x482A2000 +#define MA_HIMEM_INTERLEAVE_UN_SHIFT 8 +#define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8) /* DMM_LISA_MAP */ #define EMIF_SYS_ADDR_SHIFT 24 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 0da0599738..a32a1d7222 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -20,17 +20,12 @@ #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif -#ifndef CONFIG_DM -#define CONFIG_DM -#endif - #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d7b81c101b..aef31266ce 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -617,6 +617,9 @@ void disable_edma3_clocks(void); void omap_die_id(unsigned int *die_id); +/* Initialize general purpose I2C(0) on the SoC */ +void gpi2c_init(void); + /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1 @@ -710,7 +713,9 @@ static inline u8 is_dra72x(void) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#define OMAP_SRAM_SCRATCH_SPACE_END (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END) /* Boot parameters */ #define DEVICE_DATA_OFFSET 0x18 diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index a8d3e2f230..5d1c5c5ccb 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -22,6 +22,9 @@ config TARGET_OMAPL138_LCDK config TARGET_CALIMAIN bool "Calimain board" +config TARGET_LEGOEV3 + bool "LEGO MINDSTORMS EV3" + endchoice config SYS_SOC @@ -31,5 +34,6 @@ source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" source "board/davinci/ea20/Kconfig" source "board/omicron/calimain/Kconfig" +source "board/lego/ev3/Kconfig" endif diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c index 6105f6390c..758109e98d 100644 --- a/arch/arm/mach-davinci/da850_pinmux.c +++ b/arch/arm/mach-davinci/da850_pinmux.c @@ -12,6 +12,16 @@ #include <asm/arch/pinmux_defs.h> /* SPI pin muxer settings */ +const struct pinmux_config spi0_pins_base[] = { + { pinmux(3), 1, 0 }, /* SPI0_CLK */ + { pinmux(3), 1, 2 }, /* SPI0_SOMI */ + { pinmux(3), 1, 3 }, /* SPI0_SIMO */ +}; + +const struct pinmux_config spi0_pins_scs0[] = { + { pinmux(4), 1, 1 }, /* SPI0_SCS[0] */ +}; + const struct pinmux_config spi1_pins_base[] = { { pinmux(5), 1, 2 }, /* SPI1_CLK */ { pinmux(5), 1, 4 }, /* SPI1_SOMI */ diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index a4eb0bd89b..2a0360a785 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -503,6 +503,7 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) +#define DAVINCI_SYSCFG_SUSPSRC_UART1 (1 << 19) #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index ffd9eadb0a..9713fe4d68 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -13,3 +13,5 @@ obj-y += cmd_mon.o obj-y += msmc.o obj-y += ddr3.o cmd_ddr3.o obj-y += keystone.o +obj-$(CONFIG_K2E_EVM) += ddr3_spd.o +obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c deleted file mode 100644 index 7d163a4b1a..0000000000 --- a/arch/arm/mach-keystone/clock-k2e.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Keystone2: get clk rate for K2E - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/clock_defs.h> - -/** - * pll_freq_get - get pll frequency - * Fout = Fref * NF(mult) / NR(prediv) / OD - * @pll: pll identifier - */ -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, output_div = 2; - unsigned long ret; - u32 tmp, reg; - - if (pll == CORE_PLL) { - ret = external_clk[sys_clk]; - if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { - /* PLL mode */ - tmp = __raw_readl(KS2_MAINPLLCTL0); - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | - (pllctl_reg_read(pll, mult) & - PLLM_MULT_LO_MASK)) + 1; - output_div = ((pllctl_reg_read(pll, secctl) >> - PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; - - ret = ret / prediv / output_div * mult; - } - } else { - switch (pll) { - case PASS_PLL: - ret = external_clk[pa_clk]; - reg = KS2_PASSPLLCTL0; - break; - case DDR3_PLL: - ret = external_clk[ddr3a_clk]; - reg = KS2_DDR3APLLCTL0; - break; - default: - return 0; - } - - tmp = __raw_readl(reg); - - if (!(tmp & PLLCTL_BYPASS)) { - /* Bypass disabled */ - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; - output_div = ((tmp >> PLL_CLKOD_SHIFT) & - PLL_CLKOD_MASK) + 1; - ret = ((ret / prediv) * mult) / output_div; - } - } - - return ret; -} - -unsigned long clk_get_rate(unsigned int clk) -{ - switch (clk) { - case core_pll_clk: return pll_freq_get(CORE_PLL); - case pass_pll_clk: return pll_freq_get(PASS_PLL); - case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); - case sys_clk0_1_clk: - case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); - case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); - case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); - case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); - case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; - case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; - case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; - case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; - case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; - case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; - case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; - case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; - case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; - case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; - case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; - default: - break; - } - - return 0; -} diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c deleted file mode 100644 index 2e368910bf..0000000000 --- a/arch/arm/mach-keystone/clock-k2hk.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Keystone2: get clk rate for K2HK - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/clock_defs.h> - -/** - * pll_freq_get - get pll frequency - * Fout = Fref * NF(mult) / NR(prediv) / OD - * @pll: pll identifier - */ -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, output_div = 2; - unsigned long ret; - u32 tmp, reg; - - if (pll == CORE_PLL) { - ret = external_clk[sys_clk]; - if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { - /* PLL mode */ - tmp = __raw_readl(KS2_MAINPLLCTL0); - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | - (pllctl_reg_read(pll, mult) & - PLLM_MULT_LO_MASK)) + 1; - output_div = ((pllctl_reg_read(pll, secctl) >> - PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; - - ret = ret / prediv / output_div * mult; - } - } else { - switch (pll) { - case PASS_PLL: - ret = external_clk[pa_clk]; - reg = KS2_PASSPLLCTL0; - break; - case TETRIS_PLL: - ret = external_clk[tetris_clk]; - reg = KS2_ARMPLLCTL0; - break; - case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; - reg = KS2_DDR3APLLCTL0; - break; - case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; - reg = KS2_DDR3BPLLCTL0; - break; - default: - return 0; - } - - tmp = __raw_readl(reg); - - if (!(tmp & PLLCTL_BYPASS)) { - /* Bypass disabled */ - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; - output_div = ((tmp >> PLL_CLKOD_SHIFT) & - PLL_CLKOD_MASK) + 1; - ret = ((ret / prediv) * mult) / output_div; - } - } - - return ret; -} - -unsigned long clk_get_rate(unsigned int clk) -{ - switch (clk) { - case core_pll_clk: return pll_freq_get(CORE_PLL); - case pass_pll_clk: return pll_freq_get(PASS_PLL); - case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); - case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); - case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); - case sys_clk0_1_clk: - case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); - case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); - case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); - case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); - case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; - case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; - case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; - case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; - case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; - case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; - case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; - case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; - case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; - case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; - case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; - default: - break; - } - - return 0; -} diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c deleted file mode 100644 index 0004059192..0000000000 --- a/arch/arm/mach-keystone/clock-k2l.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Keystone2: get clk rate for K2L - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/clock_defs.h> - -/** - * pll_freq_get - get pll frequency - * Fout = Fref * NF(mult) / NR(prediv) / OD - * @pll: pll identifier - */ -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, output_div = 2; - unsigned long ret; - u32 tmp, reg; - - if (pll == CORE_PLL) { - ret = external_clk[sys_clk]; - if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { - /* PLL mode */ - tmp = __raw_readl(KS2_MAINPLLCTL0); - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | - (pllctl_reg_read(pll, mult) & - PLLM_MULT_LO_MASK)) + 1; - output_div = ((pllctl_reg_read(pll, secctl) >> - PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; - - ret = ret / prediv / output_div * mult; - } - } else { - switch (pll) { - case PASS_PLL: - ret = external_clk[pa_clk]; - reg = KS2_PASSPLLCTL0; - break; - case TETRIS_PLL: - ret = external_clk[tetris_clk]; - reg = KS2_ARMPLLCTL0; - break; - case DDR3_PLL: - ret = external_clk[ddr3a_clk]; - reg = KS2_DDR3APLLCTL0; - break; - default: - return 0; - } - - tmp = __raw_readl(reg); - if (!(tmp & PLLCTL_BYPASS)) { - /* Bypass disabled */ - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; - output_div = ((tmp >> PLL_CLKOD_SHIFT) & - PLL_CLKOD_MASK) + 1; - ret = ((ret / prediv) * mult) / output_div; - } - } - - return ret; -} - -unsigned long clk_get_rate(unsigned int clk) -{ - switch (clk) { - case core_pll_clk: return pll_freq_get(CORE_PLL); - case pass_pll_clk: return pll_freq_get(PASS_PLL); - case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); - case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); - case sys_clk0_1_clk: - case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); - case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); - case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); - case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); - case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; - case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; - case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; - case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; - case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; - case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; - case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; - case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; - case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; - case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; - case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; - default: - break; - } - - return 0; -} diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 5c6051e76d..b25db1e3fe 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -228,18 +228,21 @@ void init_plls(void) } } -static int get_max_speed(u32 val, u32 speed_supported) +static int get_max_speed(u32 val, u32 speed_supported, int *spds) { int speed; /* Left most setbit gives the speed */ for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { if ((val & BIT(speed)) & speed_supported) - return speeds[speed]; + return spds[speed]; } - /* If no bit is set, use SPD800 */ - return SPD800; + /* If no bit is set, return minimum speed */ + if (cpu_is_k2g()) + return SPD200; + else + return SPD800; } static inline u32 read_efuse_bootrom(void) @@ -250,24 +253,24 @@ static inline u32 read_efuse_bootrom(void) return __raw_readl(KS2_EFUSE_BOOTROM); } -int get_max_arm_speed(void) +int get_max_arm_speed(int *spds) { u32 armspeed = read_efuse_bootrom(); armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> DEVSPEED_ARMSPEED_SHIFT; - return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); + return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds); } -int get_max_dev_speed(void) +int get_max_dev_speed(int *spds) { u32 devspeed = read_efuse_bootrom(); devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> DEVSPEED_DEVSPEED_SHIFT; - return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); + return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds); } /** diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c new file mode 100644 index 0000000000..c541886787 --- /dev/null +++ b/arch/arm/mach-keystone/ddr3_spd.c @@ -0,0 +1,463 @@ +/* + * Keystone2: DDR3 SPD configuration + * + * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <i2c.h> +#include <ddr_spd.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +#define DUMP_DDR_CONFIG 0 /* set to 1 to debug */ +#define debug_ddr_cfg(fmt, args...) \ + debug_cond(DUMP_DDR_CONFIG, fmt, ##args) + +static void dump_phy_config(struct ddr3_phy_config *ptr) +{ + debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr); + debug_ddr_cfg("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask); + debug_ddr_cfg("pgcr1_val 0x%08X\n", ptr->pgcr1_val); + debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0); + debug_ddr_cfg("ptr1 0x%08X\n", ptr->ptr1); + debug_ddr_cfg("ptr2 0x%08X\n", ptr->ptr2); + debug_ddr_cfg("ptr3 0x%08X\n", ptr->ptr3); + debug_ddr_cfg("ptr4 0x%08X\n", ptr->ptr4); + debug_ddr_cfg("dcr_mask 0x%08X\n", ptr->dcr_mask); + debug_ddr_cfg("dcr_val 0x%08X\n", ptr->dcr_val); + debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0); + debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1); + debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); + debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0); + debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1); + debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); + debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr); + debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2); + debug_ddr_cfg("zq0cr1 0x%08X\n", ptr->zq0cr1); + debug_ddr_cfg("zq1cr1 0x%08X\n", ptr->zq1cr1); + debug_ddr_cfg("zq2cr1 0x%08X\n", ptr->zq2cr1); + debug_ddr_cfg("pir_v1 0x%08X\n", ptr->pir_v1); + debug_ddr_cfg("pir_v2 0x%08X\n\n", ptr->pir_v2); +}; + +static void dump_emif_config(struct ddr3_emif_config *ptr) +{ + debug_ddr_cfg("\nsdcfg 0x%08X\n", ptr->sdcfg); + debug_ddr_cfg("sdtim1 0x%08X\n", ptr->sdtim1); + debug_ddr_cfg("sdtim2 0x%08X\n", ptr->sdtim2); + debug_ddr_cfg("sdtim3 0x%08X\n", ptr->sdtim3); + debug_ddr_cfg("sdtim4 0x%08X\n", ptr->sdtim4); + debug_ddr_cfg("zqcfg 0x%08X\n", ptr->zqcfg); + debug_ddr_cfg("sdrfc 0x%08X\n\n", ptr->sdrfc); +}; + +#define TEMP NORMAL_TEMP +#define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */ +#define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */ +#define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */ +#define PLLLOCK_VAL (100000.0 / VBUS_CLKPERIOD) /* 100 us */ +#define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */ +#define PHYRST_VAL 0x10 +#define DDR_TERM RZQ_4_TERM +#define SDRAM_DRIVE RZQ_7_IMP +#define DYN_ODT ODT_DISABLE + +enum srt { + NORMAL_TEMP, + EXTENDED_TEMP +}; + +enum out_impedance { + RZQ_6_IMP = 0, + RZQ_7_IMP +}; + +enum die_term { + ODT_DISABLE = 0, + RZQ_4_TERM, + RZQ_2_TERM, + RZQ_6_TERM, + RZQ_12_TERM, + RZQ_8_TERM +}; + +struct ddr3_sodimm { + u32 t_ck; + u32 freqsel; + u32 t_xp; + u32 t_cke; + u32 t_pllpd; + u32 t_pllgs; + u32 t_phyrst; + u32 t_plllock; + u32 t_pllrst; + u32 t_rfc; + u32 t_xs; + u32 t_dinit0; + u32 t_dinit1; + u32 t_dinit2; + u32 t_dinit3; + u32 t_rtp; + u32 t_wtr; + u32 t_rp; + u32 t_rcd; + u32 t_ras; + u32 t_rrd; + u32 t_rc; + u32 t_faw; + u32 t_mrd; + u32 t_mod; + u32 t_wlo; + u32 t_wlmrd; + u32 t_xsdll; + u32 t_xpdll; + u32 t_ckesr; + u32 t_dllk; + u32 t_wr; + u32 t_wr_bin; + u32 cas; + u32 cwl; + u32 asr; + u32 pasr; + u32 t_refprd; + u8 sdram_type; + u8 ibank; + u8 pagesize; + u8 t_rrd2; + u8 t_ras_max; + u8 t_zqcs; + u32 refresh_rate; + u8 t_csta; + + u8 rank; + u8 mirrored; + u8 buswidth; +}; + +static u8 cas_latancy(u16 temp) +{ + int loop; + u8 cas_bin = 0; + + for (loop = 0; loop < 32; loop += 2, temp >>= 1) { + if (temp & 0x0001) + cas_bin = (loop > 15) ? loop - 15 : loop; + } + + return cas_bin; +} + +static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf) +{ + return (((buf->organization & 0x38) >> 3) + 1) * + (256 << (buf->density_banks & 0xf)); +} + +static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd, + struct ddr3_spd_cb *spd_cb) +{ + u32 mtb, clk_freq; + + if ((buf->mem_type != 0x0b) || + ((buf->density_banks & 0x70) != 0x00)) + return 1; + + spd->sdram_type = 0x03; + spd->ibank = 0x03; + + mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor; + + spd->t_ck = buf->tck_min * mtb; + + spd_cb->ddrspdclock = 2000000 / spd->t_ck; + clk_freq = spd_cb->ddrspdclock / 2; + + spd->rank = ((buf->organization & 0x38) >> 3) + 1; + if (spd->rank > 2) + return 1; + + spd->pagesize = (buf->addressing & 0x07) + 1; + if (spd->pagesize > 3) + return 1; + + spd->buswidth = 8 << (buf->bus_width & 0x7); + if ((spd->buswidth < 16) || (spd->buswidth > 64)) + return 1; + + spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1; + + printf("DDR3A Speed will be configured for %d Operation.\n", + spd_cb->ddrspdclock); + if (spd_cb->ddrspdclock == 1333) { + spd->t_xp = ((3 * spd->t_ck) > 6000) ? + 3 : ((5999 / spd->t_ck) + 1); + spd->t_cke = ((3 * spd->t_ck) > 5625) ? + 3 : ((5624 / spd->t_ck) + 1); + } else if (spd_cb->ddrspdclock == 1600) { + spd->t_xp = ((3 * spd->t_ck) > 6000) ? + 3 : ((5999 / spd->t_ck) + 1); + spd->t_cke = ((3 * spd->t_ck) > 5000) ? + 3 : ((4999 / spd->t_ck) + 1); + } else { + printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock); + return 1; + } + + spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck; + spd->t_ckesr = spd->t_cke + 1; + + /* SPD Calculated Values */ + spd->cas = cas_latancy((buf->caslat_msb << 8) | + buf->caslat_lsb); + + spd->t_wr = (buf->twr_min * mtb) / spd->t_ck; + spd->t_wr_bin = (spd->t_wr / 2) & 0x07; + + spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1; + spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1; + spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1; + + spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) * + mtb) / spd->t_ck; + + spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) * + mtb) - 1) / spd->t_ck + 1; + + spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb / + 1000; + spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck; + spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck; + + spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck); + spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1; + + spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck; + spd->t_rrd2 = ((((buf->tfaw_msb << 8) | + buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1; + + /* Hard-coded values */ + spd->t_mrd = 0x00; + spd->t_mod = 0x00; + spd->t_wlo = 0x0C; + spd->t_wlmrd = 0x28; + spd->t_xsdll = 0x200; + spd->t_ras_max = 0x0F; + spd->t_csta = 0x05; + spd->t_dllk = 0x200; + + /* CAS Write Latency */ + if (spd->t_ck >= 2500) + spd->cwl = 0; + else if (spd->t_ck >= 1875) + spd->cwl = 1; + else if (spd->t_ck >= 1500) + spd->cwl = 2; + else if (spd->t_ck >= 1250) + spd->cwl = 3; + else if (spd->t_ck >= 1071) + spd->cwl = 4; + else + spd->cwl = 5; + + /* SD:RAM Thermal and Refresh Options */ + spd->asr = (buf->therm_ref_opt & 0x04) >> 2; + spd->pasr = (buf->therm_ref_opt & 0x80) >> 7; + spd->t_zqcs = 64; + + spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250; + spd->t_refprd = spd->t_refprd / spd->t_ck; + + spd->refresh_rate = spd->t_refprd; + spd->t_refprd = spd->t_refprd * 5; + + /* Set MISC PHY space registers fields */ + if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275)) + spd->freqsel = 0x03; + else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385)) + spd->freqsel = 0x01; + else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534)) + spd->freqsel = 0x00; + + spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */ + spd->t_dinit1 = spd->t_xs; + spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */ + /* Time from ZQ initialization command to first command (1 us) */ + spd->t_dinit3 = 1000000 / spd->t_ck; + + spd->t_pllgs = PLLGS_VAL + 1; + spd->t_pllpd = PLLPD_VAL + 1; + spd->t_plllock = PLLLOCK_VAL + 1; + spd->t_pllrst = PLLRST_VAL; + spd->t_phyrst = PHYRST_VAL; + + spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024; + + return 0; +} + +static void init_ddr3param(struct ddr3_spd_cb *spd_cb, + struct ddr3_sodimm *spd) +{ + spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; + spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK); + spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)); + spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | + ((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f); + spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) | + (spd->t_pllrst & 0x1fff); + spd_cb->phy_cfg.ptr2 = 0; + spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) | + (spd->t_dinit0 & 0xfffff); + spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) | + (spd->t_dinit2 & 0x3ffff); + + spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK; + spd_cb->phy_cfg.dcr_val = 1 << 10; + + if (spd->mirrored) { + spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK; + spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29); + } + + spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | + (spd->t_rrd & 0xf) << 22 | + (spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 | + (spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 | + (spd->t_rtp & 0xf); + spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | + (spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 | + (spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 | + (spd->t_mrd & 0x3); + + spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | + (spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15; + + spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? + spd->t_xp : spd->t_xpdll) & + 0x1f) << 10; + + spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? + spd->t_xs : spd->t_xsdll) & + 0x3ff); + + spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | + 0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 | + (spd->cas & 0x01) << 2; + + spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | + ((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 | + (DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 | + (SDRAM_DRIVE & 1) << 1 | 0 << 0; + + spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | + (spd->cwl & 7) << 3 | (spd->pasr & 7); + + spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; + spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff); + + spd_cb->phy_cfg.zq0cr1 = 0x0000005D; + spd_cb->phy_cfg.zq1cr1 = 0x0000005B; + spd_cb->phy_cfg.zq2cr1 = 0x0000005B; + + spd_cb->phy_cfg.pir_v1 = 0x00000033; + spd_cb->phy_cfg.pir_v2 = 0x0000FF81; + + /* EMIF Registers */ + spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 | + (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | + (spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 | + (spd->buswidth & 3) << 12 | (spd->pagesize & 3); + + if (spd->rank == 2) + spd_cb->emif_cfg.sdcfg |= 1 << 3; + + spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | + ((spd->t_ras - 1) & 0x7f) << 18 | + ((spd->t_rc - 1) & 0xff) << 10 | + (spd->t_rrd2 & 0x3f) << 4 | + ((spd->t_wtr - 1) & 0xf); + + spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 | + ((spd->t_rcd - 1) & 0x1f); + + spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 | + ((spd->t_xs - 1) & 0x3ff) << 18 | + ((spd->t_xsdll - 1) & 0x3ff) << 8 | + ((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf); + + spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 | + ((spd->t_ckesr - 1) & 0xf) << 24 | + ((spd->t_zqcs - 1) & 0xff) << 16 | + ((spd->t_rfc - 1) & 0x3ff) << 4 | + (spd->t_ras_max & 0xf); + + spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff; + + /* TODO zqcfg value fixed ,May be required correction for K2E evm. */ + spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; +} + +static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) +{ + int ret; + int old_bus; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256); + + i2c_set_bus_num(old_bus); + + if (ret) { + printf("Cannot read DIMM params\n"); + return 1; + } + + if (ddr3_spd_check(spd_params)) + return 1; + + return 0; +} + +int ddr3_get_size(void) +{ + ddr3_spd_eeprom_t spd_params; + + if (ddr3_read_spd(&spd_params)) + return 0; + + return ddr3_get_size_in_mb(&spd_params) / 1024; +} + +int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb) +{ + struct ddr3_sodimm spd; + ddr3_spd_eeprom_t spd_params; + + memset(&spd, 0, sizeof(spd)); + + if (ddr3_read_spd(&spd_params)) + return 1; + + if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) { + printf("Timing caclulation error\n"); + return 1; + } + + strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18); + spd_cb->dimm_name[18] = '\0'; + + init_ddr3param(spd_cb, &spd); + + dump_emif_config(&spd_cb->emif_cfg); + dump_phy_config(&spd_cb->phy_cfg); + + return 0; +} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h index 214c1d3a83..74de6202fe 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2g.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -12,8 +12,8 @@ #define PLLSET_CMD_LIST "<pa|arm|ddr3>" -#define DEV_SUPPORTED_SPEEDS 0xfff -#define ARM_SUPPORTED_SPEEDS 0xfff +#define DEV_SUPPORTED_SPEEDS 0x1ff +#define ARM_SUPPORTED_SPEEDS 0xff #define KS2_CLK1_6 sys_clk0_6_clk diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index cdcff3baee..72724aa4a9 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -63,8 +63,12 @@ #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) enum { + SPD200, + SPD400, + SPD600, SPD800, SPD850, + SPD900, SPD1000, SPD1200, SPD1250, @@ -124,8 +128,8 @@ struct pll_init_data *get_pll_init_data(int pll); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); -int get_max_dev_speed(void); -int get_max_arm_speed(void); +int get_max_dev_speed(int *spds); +int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); #endif diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h index a22c237c80..5feffe825b 100644 --- a/arch/arm/mach-keystone/include/mach/ddr3.h +++ b/arch/arm/mach-keystone/include/mach/ddr3.h @@ -48,6 +48,14 @@ struct ddr3_emif_config { unsigned int sdrfc; }; +struct ddr3_spd_cb { + char dimm_name[32]; + struct ddr3_phy_config phy_cfg; + struct ddr3_emif_config emif_cfg; + unsigned int ddrspdclock; + int ddr_size_gbyte; +}; + u32 ddr3_init(void); void ddr3_reset_ddrphy(void); void ddr3_init_ecc(u32 base, u32 ddr3_size); @@ -58,5 +66,6 @@ void ddr3_err_reset_workaround(void); void ddr3_enable_ecc(u32 base, int test); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); +int ddr3_get_size(void); #endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index fa4162fe99..ca2a119d39 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARCH_HARDWARE_K2G_H #define __ASM_ARCH_HARDWARE_K2G_H -#define KS2_NUM_DSPS 0 +#define KS2_NUM_DSPS 1 /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_ALWAYSON 0 @@ -30,7 +30,10 @@ #define KS2_LPSC_MCASP 15 #define KS2_LPSC_SR 16 #define KS2_LPSC_MSMC 17 -#define KS2_LPSC_GEM 18 +#ifdef KS2_LPSC_GEM_0 +#undef KS2_LPSC_GEM_0 +#endif +#define KS2_LPSC_GEM_0 18 #define KS2_LPSC_ARM 19 #define KS2_LPSC_ASRC 20 #define KS2_LPSC_ICSS 21 diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h index 4f1197ea92..a59e071359 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h @@ -105,4 +105,11 @@ /* NETCP */ #define KS2_NETCP_BASE 0x26000000 +#ifndef __ASSEMBLY__ +static inline int ddr3_get_size(void) +{ + return 2; +} +#endif + #endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index edebcd7bc5..8ca19bbcdb 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -160,6 +160,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_LPSC_GEM_0 15 #define KS2_LPSC_TETRIS 52 #define KS2_TETRIS_PWR_DOMAIN 31 +#define KS2_GEM_0_PWR_DOMAIN 8 /* Chip configuration unlock codes and registers */ #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 70d22cf217..6e6e7fd433 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -30,9 +30,9 @@ #define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ (u32)1)) << ((u32)y))) -#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) -#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ - ((((u32)f) << (y)) & BOOTBITMASK(x, y)) +#define BOOT_READ_BITFIELD(z, x, y) ((((u32)z) & BOOTBITMASK(x, y)) >> (y)) +#define BOOT_SET_BITFIELD(z, f, x, y) ((((u32)z) & ~BOOTBITMASK(x, y)) | \ + ((((u32)f) << (y)) & BOOTBITMASK(x, y))) /* PDCTL */ #define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) @@ -56,6 +56,8 @@ #define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) #define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) #define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) +#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10) +#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11) /* PDCTL states */ #define PSC_REG_VAL_PDCTL_NEXT_ON 1 @@ -86,5 +88,7 @@ u32 psc_get_domain_num(u32 mod_num); int psc_enable_module(u32 mod_num); int psc_disable_module(u32 mod_num); int psc_disable_domain(u32 domain_num); +int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks); +int psc_module_release_from_reset(u32 mod_num); #endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 11a9357db4..a8071270e9 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -54,7 +54,7 @@ static void turn_off_all_dsps(int num_dsps) if (psc_disable_module(i + KS2_LPSC_GEM_0)) printf("Cannot disable module for #%d DSP", i); - if (psc_disable_domain(i + 8)) + if (psc_disable_domain(i + KS2_GEM_0_PWR_DOMAIN)) printf("Cannot disable domain for #%d DSP", i); } } diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c index 237e776e87..ff042a6db2 100644 --- a/arch/arm/mach-keystone/psc.c +++ b/arch/arm/mach-keystone/psc.c @@ -13,24 +13,27 @@ #include <asm/processor.h> #include <asm/arch/psc_defs.h> +/** + * psc_delay() - delay for psc + * + * Return: 10 + */ int psc_delay(void) { udelay(10); return 10; } -/* - * FUNCTION PURPOSE: Wait for end of transitional state - * - * DESCRIPTION: Polls pstat for the selected domain and waits for transitions - * to be complete. +/** + * psc_wait() - Wait for end of transitional state + * @domain_num: GPSC domain number * - * Since this is boot loader code it is *ASSUMED* that interrupts - * are disabled and no other core is mucking around with the psc - * at the same time. + * Polls pstat for the selected domain and waits for transitions to be complete. + * Since this is boot loader code it is *ASSUMED* that interrupts are disabled + * and no other core is mucking around with the psc at the same time. * - * Returns 0 when the domain is free. Returns -1 if a timeout - * occurred waiting for the completion. + * Return: 0 when the domain is free. Returns -1 if a timeout occurred waiting + * for the completion. */ int psc_wait(u32 domain_num) { @@ -59,6 +62,10 @@ int psc_wait(u32 domain_num) return 0; } +/** + * psc_get_domain_num() - Get the domain number + * @mod_num: LPSC module number + */ u32 psc_get_domain_num(u32 mod_num) { u32 domain_num; @@ -70,20 +77,19 @@ u32 psc_get_domain_num(u32 mod_num) return domain_num; } -/* - * FUNCTION PURPOSE: Power up/down a module - * - * DESCRIPTION: Powers up/down the requested module and the associated power - * domain if required. No action is taken it the module is - * already powered up/down. +/** + * psc_set_state() - powers up/down a module + * @mod_num: LPSC module number + * @state: 1 to enable, 0 to disable. * - * This only controls modules. The domain in which the module - * resides will be left in the power on state. Multiple modules - * can exist in a power domain, so powering down the domain based - * on a single module is not done. + * Powers up/down the requested module and the associated power domain if + * required. No action is taken it the module is already powered up/down. + * This only controls modules. The domain in which the module resides will + * be left in the power on state. Multiple modules can exist in a power + * domain, so powering down the domain based on a single module is not done. * - * Returns 0 on success, -1 if the module can't be powered up, or - * if there is a timeout waiting for the transition. + * Return: 0 on success, -1 if the module can't be powered up, or if there is a + * timeout waiting for the transition. */ int psc_set_state(u32 mod_num, u32 state) { @@ -136,15 +142,16 @@ int psc_set_state(u32 mod_num, u32 state) return psc_wait(domain_num); } -/* - * FUNCTION PURPOSE: Power up a module +/** + * psc_enable_module() - power up a module + * @mod_num: LPSC module number + * + * Powers up the requested module and the associated power domain + * if required. No action is taken it the module is already powered up. * - * DESCRIPTION: Powers up the requested module and the associated power domain - * if required. No action is taken it the module is already - * powered up. + * Return: 0 on success, -1 if the module can't be powered up, or + * if there is a timeout waiting for the transition. * - * Returns 0 on success, -1 if the module can't be powered up, or - * if there is a timeout waiting for the transition. */ int psc_enable_module(u32 mod_num) { @@ -158,12 +165,11 @@ int psc_enable_module(u32 mod_num) return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON); } -/* - * FUNCTION PURPOSE: Power down a module +/** + * psc_disable_module() - Power down a module + * @mod_num: LPSC module number * - * DESCRIPTION: Powers down the requested module. - * - * Returns 0 on success, -1 on failure or timeout. + * Return: 0 on success, -1 on failure or timeout. */ int psc_disable_module(u32 mod_num) { @@ -179,13 +185,16 @@ int psc_disable_module(u32 mod_num) return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE); } -/* - * FUNCTION PURPOSE: Set the reset isolation bit in mdctl +/** + * psc_set_reset_iso() - Set the reset isolation bit in mdctl + * @mod_num: LPSC module number + * + * The reset isolation enable bit is set. The state of the module is not + * changed. * - * DESCRIPTION: The reset isolation enable bit is set. The state of the module - * is not changed. Returns 0 if the module config showed that - * reset isolation is supported. Returns 1 otherwise. This is not - * an error, but setting the bit in mdctl has no effect. + * Return: 0 if the module config showed that reset isolation is supported. + * Returns 1 otherwise. This is not an error, but setting the bit in mdctl + * has no effect. */ int psc_set_reset_iso(u32 mod_num) { @@ -204,10 +213,9 @@ int psc_set_reset_iso(u32 mod_num) return 1; } -/* - * FUNCTION PURPOSE: Disable a power domain - * - * DESCRIPTION: The power domain is disabled +/** + * psc_disable_domain() - Disable a power domain + * @domain_num: GPSC domain number */ int psc_disable_domain(u32 domain_num) { @@ -225,3 +233,107 @@ int psc_disable_domain(u32 domain_num) return psc_wait(domain_num); } + +/** + * psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state + * @mod_num: LPSC module number + * @gate_clocks: Can the clocks be gated on this module? + * + * Enable the module, but do not release the module from local reset. This is + * necessary for many processor systems on keystone SoCs to allow for system + * initialization from a master processor prior to releasing the processor + * from reset. + */ +int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks) +{ + u32 mdctl, ptcmd, mdstat; + u32 next_state; + int domain_num = psc_get_domain_num(mod_num); + int timeout = 100000; + + /* Wait for any previous transitions to complete */ + psc_wait(domain_num); + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Should be set 0 to assert Local reset */ + if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) { + mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Wait for transition to take place */ + psc_wait(domain_num); + } + + /* Clear Module reset */ + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF : + PSC_REG_VAL_MDCTL_NEXT_ON; + mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Trigger PD transition */ + ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); + ptcmd |= (u32)(1 << domain_num); + __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); + psc_wait(domain_num); + + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + while (timeout) { + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + + if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) && + PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) && + PSC_REG_MDSTAT_GET_LRSTDONE(mdstat)) + break; + timeout--; + } + + if (!timeout) { + printf("%s: Timedout waiting for mdstat(0x%08x) to change\n", + __func__, mdstat); + return -ETIMEDOUT; + } + return 0; +} + +/** + * psc_module_release_from_reset() - Release the module from reset + * @mod_num: LPSC module number + * + * This is the follow through for the command 'psc_module_keep_in_reset_enabled' + * Allowing the module to be released from reset once all required inits are + * complete for the module. Typically, this allows the processor module to start + * execution. + */ +int psc_module_release_from_reset(u32 mod_num) +{ + u32 mdctl, mdstat; + int domain_num = psc_get_domain_num(mod_num); + int timeout = 100000; + + /* Wait for any previous transitions to complete */ + psc_wait(domain_num); + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Should be set to 1 to de-assert Local reset */ + if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) { + mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Wait for transition to take place */ + psc_wait(domain_num); + } + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + while (timeout) { + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + + if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) && + PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) && + PSC_REG_MDSTAT_GET_LRSTDONE(mdstat)) + break; + timeout--; + } + + if (!timeout) { + printf("%s: Timedout waiting for mdstat(0x%08x) to change\n", + __func__, mdstat); + return -ETIMEDOUT; + } + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 17daecaf2b..71330cb26d 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -756,7 +756,7 @@ static int veyron_init(struct dram_info *priv) struct udevice *pmic; int ret; - ret = uclass_first_device(UCLASS_PMIC, &pmic); + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); if (ret) return ret; |
