diff options
Diffstat (limited to 'arch/arm')
128 files changed, 1031 insertions, 623 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 06b8e58a32..7ed0e20521 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS +config TARGET_WORK_92105 + bool "Support work_92105" + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS @@ -286,13 +291,8 @@ config TARGET_MX35PDK bool "Support mx35pdk" select CPU_ARM1136 -config TARGET_RPI - bool "Support rpi" - select CPU_ARM1176 - -config TARGET_RPI_2 - bool "Support rpi_2" - select CPU_V7 +config ARCH_BCM283X + bool "Broadcom BCM283X family" config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" @@ -731,9 +731,9 @@ endchoice source "arch/arm/mach-at91/Kconfig" -source "arch/arm/mach-davinci/Kconfig" +source "arch/arm/mach-bcm283x/Kconfig" -source "arch/arm/cpu/arm1176/bcm2835/Kconfig" +source "arch/arm/mach-davinci/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" @@ -848,8 +848,6 @@ source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" -source "board/raspberrypi/rpi/Kconfig" -source "board/raspberrypi/rpi_2/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" @@ -885,6 +883,7 @@ source "board/vpac270/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/woodburn/Kconfig" +source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 08946de244..bd4749c55e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -2,9 +2,47 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +CONFIG_CPU_V7= +CONFIG_CPU_ARM720T=y +endif + +# This selects which instruction set is used. +arch-$(CONFIG_CPU_ARM720T) =-march=armv4 +arch-$(CONFIG_CPU_ARM920T) =-march=armv4 +arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te +arch-$(CONFIG_CPU_ARM946ES) =-march=armv4 +arch-$(CONFIG_CPU_SA1100) =-march=armv4 +arch-$(CONFIG_CPU_PXA) = +arch-$(CONFIG_CPU_ARM1136) =-march=armv5 +arch-$(CONFIG_CPU_ARM1176) =-march=armv5t +arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, -march=armv5) +arch-$(CONFIG_ARM64) =-march=armv8-a + +# Evaluate arch cc-option calls now +arch-y := $(arch-y) + +# This selects how we optimise for the processor. +tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi +tune-$(CONFIG_CPU_ARM920T) = +tune-$(CONFIG_CPU_ARM926EJS) = +tune-$(CONFIG_CPU_ARM946ES) = +tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 +tune-$(CONFIG_CPU_PXA) =-mcpu=xscale +tune-$(CONFIG_CPU_ARM1136) = +tune-$(CONFIG_CPU_ARM1176) = +tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_ARM64) = + +# Evaluate tune cc-option calls now +tune-y := $(tune-y) + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) + # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_AT91) += at91 +machine-$(CONFIG_ARCH_BCM283X) += bcm283x machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 0667984b69..c005ce4905 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -19,9 +19,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -# Support generic board on ARM -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk deleted file mode 100644 index a82c6cec9c..0000000000 --- a/arch/arm/cpu/arm1136/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 1cfcca9fa6..1ec79a6f35 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -14,7 +14,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index 480e130489..deec427447 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -10,5 +10,3 @@ extra-y = start.o obj-y = cpu.o - -obj-$(CONFIG_BCM2835) += bcm2835/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig deleted file mode 100644 index 73cc72b411..0000000000 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RPI || TARGET_RPI_2 - -config DM - default y - -config DM_SERIAL - default y - -config DM_GPIO - default y - -endif diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk deleted file mode 100644 index 5dc2ebb27b..0000000000 --- a/arch/arm/cpu/arm1176/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5t diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ac937bf5b0..4c0ab4d0ee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -16,7 +16,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk deleted file mode 100644 index 772fb413e8..0000000000 --- a/arch/arm/cpu/arm720t/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 01c85be64b..ec8e88d4b3 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/hardware.h> /* diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk deleted file mode 100644 index 799afff028..0000000000 --- a/arch/arm/cpu/arm920t/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk deleted file mode 100644 index bdb3da183e..0000000000 --- a/arch/arm/cpu/arm926ejs/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv5te diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 314f004eba..48373776ff 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -6,3 +6,5 @@ # obj-y = cpu.o clk.o devices.o timer.o + +obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c index b7a44d59da..1ef8a36669 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void) return get_hclk_pll_rate() / get_periph_clk_div(); } +unsigned int get_sdram_clk_rate(void) +{ + unsigned int src_clk; + + if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) + return get_sys_clk_rate(); + + src_clk = get_hclk_pll_rate(); + + if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) { + /* using DDR */ + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { + case CLK_HCLK_DDRAM_HALF: + return src_clk/2; + case CLK_HCLK_DDRAM_NOMINAL: + return src_clk; + default: + return 0; + } + } else { + /* using SDR */ + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { + case CLK_HCLK_ARM_PLL_DIV_4: + return src_clk/4; + case CLK_HCLK_ARM_PLL_DIV_2: + return src_clk/2; + case CLK_HCLK_ARM_PLL_DIV_1: + return src_clk; + default: + return 0; + } + } +} + int get_serial_clock(void) { return get_periph_clk_rate(); diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index 35095a9583..f757474076 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -5,9 +5,11 @@ */ #include <common.h> +#include <netdev.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/wdt.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; @@ -55,3 +57,11 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_LPC32XX_ETH +int cpu_eth_init(bd_t *bis) +{ + lpc32xx_eth_initialize(bis); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b5676578fd..5a453e303d 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,10 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> +#include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE; void lpc32xx_uart_init(unsigned int uart_id) { @@ -37,3 +40,43 @@ void lpc32xx_uart_init(unsigned int uart_id) writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), &clk->u3clk + (uart_id - 3)); } + +void lpc32xx_mac_init(void) +{ + /* Enable MAC interface */ + writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER + | CLK_MAC_MII, &clk->macclk_ctrl); +} + +void lpc32xx_mlc_nand_init(void) +{ + /* Enable NAND interface */ + writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); +} + +void lpc32xx_i2c_init(unsigned int devnum) +{ + /* Enable I2C interface */ + uint32_t ctrl = readl(&clk->i2cclk_ctrl); + if (devnum == 1) + ctrl |= CLK_I2C1_ENABLE; + if (devnum == 2) + ctrl |= CLK_I2C2_ENABLE; + writel(ctrl, &clk->i2cclk_ctrl); +} + +U_BOOT_DEVICE(lpc32xx_gpios) = { + .name = "gpio_lpc32xx" +}; + +/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ + +#define P_MUX_SET_SSP0 0x1600 + +void lpc32xx_ssp_init(void) +{ + /* Enable SSP0 interface */ + writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); + /* Mux SSP0 pins */ + writel(P_MUX_SET_SSP0, &mux->p_mux_set); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/dram.c b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c new file mode 100644 index 0000000000..1eea8e2bbf --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c @@ -0,0 +1,77 @@ +/* + * LPC32xx dram init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * This is called by SPL to gain access to the SDR DRAM. + * + * This code runs from SRAM. + * + * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided + * by the board configuration file. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/arch/emc.h> +#include <asm/io.h> + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; + +void ddr_init(struct emc_dram_settings *dram) +{ + uint32_t ck; + + /* Enable EMC interface and choose little endian mode */ + writel(1, &emc->ctrl); + writel(0, &emc->config); + /* Select maximum EMC Dynamic Memory Refresh Time */ + writel(0x7FF, &emc->refresh); + /* Determine CLK */ + ck = get_sdram_clk_rate(); + /* Configure SDRAM */ + writel(dram->cmddelay, &clk->sdramclk_ctrl); + writel(dram->config0, &emc->config0); + writel(dram->rascas0, &emc->rascas0); + writel(dram->rdconfig, &emc->read_config); + /* Set timings */ + writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); + writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); + writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); + writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); + writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); + writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); + writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); + writel(dram->trrd, &emc->t_rrd); + writel(dram->tmrd, &emc->t_mrd); + writel(dram->tcdlr, &emc->t_cdlr); + /* Dynamic refresh */ + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* Force all clocks, enable inverted ck, issue NOP command */ + writel(0x00000193, &emc->control); + udelay(100); + /* Keep all clocks enabled, issue a PRECHARGE ALL command */ + writel(0x00000113, &emc->control); + /* Fast dynamic refresh for at least a few SDRAM ck cycles */ + writel((((128) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* set correct dynamic refresh timing */ + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* set normal mode to CAS=3 */ + writel(0x00000093, &emc->control); + readl(EMC_DYCS0_BASE | dram->mode); + /* set extended mode to all zeroes */ + writel(0x00000093, &emc->control); + readl(EMC_DYCS0_BASE | dram->emode); + /* stop forcing clocks, keep inverted clock, issue normal mode */ + writel(0x00000010, &emc->control); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S new file mode 100644 index 0000000000..4b8053e3f9 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -0,0 +1,45 @@ +/* + * WORK Microwave work_92105 board low level init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Low level init is called from SPL to set up the clocks. + * On entry, the LPC3250 is in Direct Run mode with all clocks + * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is + * 104 MHz and PCLK is 13 MHz. + * + * This code must run from SRAM so that the clock changes do + * not prevent it from executing. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl lowlevel_init + +lowlevel_init: + + /* Set ARM, HCLK, PCLK dividers for normal mode */ + ldr r0, =0x0000003D + ldr r1, =0x40004040 + str r0, [r1] + + /* Start HCLK PLL for 208 MHz */ + ldr r0, =0x0001401E + ldr r1, =0x40004058 + str r0, [r1] + + /* wait for HCLK PLL to lock */ +1: + ldr r0, [r1] + ands r0, r0, #1 + beq 1b + + /* switch to normal mode */ + ldr r1, =0x40004044 + ldr r0, [r1] + orr r0, #0x00000004 + str r0, [r1] + + /* Return to U-boot via saved link register */ + mov pc, lr diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 9b60436539..48abcd5260 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -22,7 +22,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 8eb249475e..82cc1c9477 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -18,7 +18,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk deleted file mode 100644 index 438668d6ff..0000000000 --- a/arch/arm/cpu/arm946es/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 41123716a7..b55395aa53 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -17,7 +17,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 1312a9db9e..21fc03b97e 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -39,7 +39,6 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_BCM2835) += bcm2835/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 85cceae152..f5b16b4b72 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -164,9 +164,9 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S index 1febd7bac5..69da7fe7af 100644 --- a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S +++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S @@ -3,11 +3,10 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> ENTRY(save_boot_params) - bx lr + b save_boot_params_ret ENDPROC(save_boot_params) /* diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile deleted file mode 100644 index ed1ee4753d..0000000000 --- a/arch/arm/cpu/armv7/bcm2835/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0+ -# - -src_dir := ../../arm1176/bcm2835/ - -obj-y := -obj-y += $(src_dir)/init.o -obj-y += $(src_dir)/reset.o -obj-y += $(src_dir)/timer.o -obj-y += $(src_dir)/mbox.o diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 6c82c3b537..63591d4a29 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -5,11 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# If armv7-a is not supported by GCC fall-back to armv5, which is -# supported by more tool-chains -PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) - # On supported platforms we set the bit which causes us to trap on unaligned # memory access. This is the opposite of what the compiler expects to be # the default so we must pass in -mno-unaligned-access so that it is aware diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index eb86a7fe7d..bd7540ac61 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -80,12 +80,6 @@ config DM_SPI_FLASH config DM_GPIO default y -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c6455c2f3c..df4d4739ff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -14,7 +14,6 @@ #define PLL_DIV_1024 1024 #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 - /* * * This structure is to store the src bit, div bit and prediv bit * positions of the peripheral clocks of the src and div registers @@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: src = EXYNOS_SRC_MPLL; - div = readl(&clk->div_top0); - sub_div = readl(&clk->div_top1); + div = readl(&clk->div_top1); + sub_div = readl(&clk->div_top0); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); @@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; } +static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * CLKMUX_FIMD1 [6:4] + */ + sel = (readl(&clk->src_disp10) >> 4) & 0x7; + + if (sel) { + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, + RPLL}; + sclk = get_pll_clk(reg_map[sel]); + } else + sclk = CONFIG_SYS_CLK_FREQ; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); } +void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (0x7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1660,8 +1717,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } } diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c index 31610909f8..584e4bac09 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c @@ -25,7 +25,6 @@ #include <common.h> #include <config.h> -#include <version.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0d0c..0200fd154f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h index b633e56603..9f29d94c10 100644 --- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h @@ -10,7 +10,6 @@ #define _ORIGEN_SETUP_H #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> #ifdef CONFIG_CLK_800_330_165 diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 65da6e2c17..1f96498fb8 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -106,12 +106,6 @@ config DM_GPIO config DM_SERIAL default y if DM -config SYS_MALLOC_F - default y if DM - -config SYS_MALLOC_F_LEN - default 0x400 if DM - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 7a691519bb..249761308e 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -12,7 +12,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/mem.h> #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index afed773c63..b4d0627871 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> /* Set up the platform, once the cpu has been initialized */ .globl lowlevel_init diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index bd9f338301..6a8c15d91f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -8,7 +8,6 @@ #include <asm/io.h> #include <asm/u-boot.h> #include <asm/utils.h> -#include <version.h> #include <image.h> #include <asm/arch/reset_manager.h> #include <spl.h> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5050021e02..5ed0f45a26 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -15,7 +15,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/system.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032e9c..c3e04af36d 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -100,22 +100,23 @@ static struct { unsigned int freq; } pll1_para[] = { /* This array must be ordered by frequency. */ - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000}, - /* Final catchall entry */ - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + }; void clock_set_pll1(unsigned int hz) @@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Find target frequency */ - while (pll1_para[i].freq < hz) + while (pll1_para[i].freq > hz) i++; hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; /* Calculate system clock divisors */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 5be497b7be..e0a524e10c 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -37,7 +37,7 @@ .arch_extension sec -#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) #define TEN_MS (10 * ONE_MS) #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c index 14de9f98bd..524f25ce83 100644 --- a/arch/arm/cpu/armv7/sunxi/usbc.c +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -182,6 +182,13 @@ static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) return; } +void sunxi_usbc_enable_squelch_detect(int index, int enable) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2); +} + int sunxi_usbc_request_resources(int index) { struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index fa447bce16..d846236500 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk index f5b95591af..685025881c 100644 --- a/arch/arm/cpu/armv8/config.mk +++ b/arch/arm/cpu/armv8/config.mk @@ -6,7 +6,5 @@ # PLATFORM_RELFLAGS += -fno-common -ffixed-x18 -PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a) PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8) PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index b91a1b662f..baf9401e64 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/ptrace.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index b4eab0b0f2..e5f2766a4a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index f840b04df5..945445bc37 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ade1cdead8..253a39bd11 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index 525f5d33b7..7fb5316d8f 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mcpu=xscale - # # !WARNING! # The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index c77d51e6d8..879390be2d 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -21,7 +21,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk deleted file mode 100644 index 3afa685b3f..0000000000 --- a/arch/arm/cpu/sa1100/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 78e0cb8868..eebff661f8 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -11,7 +11,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b86755..f897e6d969 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -24,7 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ - tegra20-colibri_t20_iris.dtb \ + tegra20-colibri.dtb \ tegra30-apalis.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index b801de9787..3ad4728138 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -67,6 +67,8 @@ edp-lvds-bridge@48 { compatible = "parade,ps8625"; reg = <0x48>; + sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 916cf3a5b6..31fabb190e 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -168,6 +168,7 @@ fimd@14400000 { /* sysmmu is not used in U-Boot */ samsung,disable-sysmmu; + samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>; }; dp@145b0000 { diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100995..494f7641e7 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,10 +144,13 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <30000>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; samsung,dual-lcd-enabled = <0>; + + samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri.dts index 3131b9201b..3131b9201b 100644 --- a/arch/arm/dts/tegra20-colibri_t20_iris.dts +++ b/arch/arm/dts/tegra20-colibri.dts diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 2a17dfc6de..d20b7d2ae3 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4)) diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 92f6c15f20..94498695a0 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -71,6 +71,7 @@ struct clk_pm_regs { }; /* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) #define CLK_HCLK_DDRAM_HALF (0x2 << 7) #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) @@ -123,6 +124,10 @@ struct clk_pm_regs { #define CLK_MAC_SLAVE (1 << 1) #define CLK_MAC_REG (1 << 0) +/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0) + /* Timer Clock Control1 Register bits */ #define CLK_TIMCLK_MOTOR (1 << 6) #define CLK_TIMCLK_TIMER3 (1 << 5) @@ -147,11 +152,22 @@ struct clk_pm_regs { /* DMA Clock Control Register bits */ #define CLK_DMA_ENABLE (1 << 0) +/* NAND Clock Control Register bits */ +#define CLK_NAND_MLC (1 << 1) +#define CLK_NAND_MLC_INT (1 << 5) + +/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + +/* SDRAMCLK register bits */ +#define CLK_SDRAM_DDR_SEL (1 << 1) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); unsigned int get_hclk_clk_rate(void); unsigned int get_periph_clk_div(void); unsigned int get_periph_clk_rate(void); +unsigned int get_sdram_clk_rate(void); #endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 564441cbfa..d57bc4877e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -52,6 +52,9 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } +/* Ethernet */ +#define LPC32XX_ETH_BASE ETHERNET_BASE + /* NOR Flash */ #if defined(CONFIG_SYS_FLASH_CFI) #define CONFIG_FLASH_CFI_DRIVER diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 199b4a026b..0b5dca11b8 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -27,6 +27,7 @@ #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ #define RTC_BASE 0x40024000 /* RTC registers base */ #define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define MUX_BASE 0x40028100 /* MUX registers base */ #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ @@ -37,6 +38,8 @@ #define UART4_BASE 0x40088000 /* UART 4 registers base */ #define UART5_BASE 0x40090000 /* UART 5 registers base */ #define UART6_BASE 0x40098000 /* UART 6 registers base */ +#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ +#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ /* External SDRAM Memory Bank base addresses */ #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h index 82d9bcce50..1a2bab251f 100644 --- a/arch/arm/include/asm/arch-lpc32xx/emc.h +++ b/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -76,4 +76,25 @@ struct emc_regs { #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) +/* EMC settings for DRAM */ +struct emc_dram_settings { + u32 cmddelay; + u32 config0; + u32 rascas0; + u32 rdconfig; + u32 trp; + u32 tras; + u32 tsrex; + u32 twr; + u32 trc; + u32 trfc; + u32 txsr; + u32 trrd; + u32 tmrd; + u32 tcdlr; + u32 refresh; + u32 mode; + u32 emode; +}; + #endif /* _LPC32XX_EMC_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h new file mode 100644 index 0000000000..3bd94e31a5 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h @@ -0,0 +1,43 @@ +/* + * LPC32xx GPIO interface + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * GPIO Register map for LPC32xx + */ + +struct gpio_regs { + u32 p3_inp_state; + u32 p3_outp_set; + u32 p3_outp_clr; + u32 p3_outp_state; + /* Watch out! the following are shared between p2 and p3 */ + u32 p2_p3_dir_set; + u32 p2_p3_dir_clr; + u32 p2_p3_dir_state; + /* Now back to 'one register for one port' */ + u32 p2_inp_state; + u32 p2_outp_set; + u32 p2_outp_clr; + u32 reserved1[6]; + u32 p0_inp_state; + u32 p0_outp_set; + u32 p0_outp_clr; + u32 p0_outp_state; + u32 p0_dir_set; + u32 p0_dir_clr; + u32 p0_dir_state; + u32 reserved2; + u32 p1_inp_state; + u32 p1_outp_set; + u32 p1_outp_clr; + u32 p1_outp_state; + u32 p1_dir_set; + u32 p1_dir_clr; + u32 p1_dir_state; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h new file mode 100644 index 0000000000..dc1b5bcdfd --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -0,0 +1,18 @@ +/* + * LPC32xx MUX interface + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * MUX register map for LPC32xx + */ + +struct mux_regs { + u32 p_mux_set; + u32 p_mux_clr; + u32 p_mux_state; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 28812be3cb..c3d890dde4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -7,6 +7,14 @@ #ifndef _LPC32XX_SYS_PROTO_H #define _LPC32XX_SYS_PROTO_H -void lpc32xx_uart_init(unsigned int uart_id); +#include <asm/arch/emc.h> +void lpc32xx_uart_init(unsigned int uart_id); +void lpc32xx_mac_init(void); +void lpc32xx_mlc_nand_init(void); +void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void); +#if defined(CONFIG_SPL_BUILD) +void ddr_init(const struct emc_dram_settings *dram); +#endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h index cb538cdc7d..133073321b 100644 --- a/arch/arm/include/asm/arch-sunxi/usbc.h +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -20,3 +20,4 @@ void sunxi_usbc_enable(int index); void sunxi_usbc_disable(int index); void sunxi_usbc_vbus_enable(int index); void sunxi_usbc_vbus_disable(int index); +void sunxi_usbc_enable_squelch_detect(int index, int enable); diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4212e57699..3cc52dd773 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, int len); +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define PMUX_SLWF_MIN 0 @@ -219,14 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +struct pmux_mipipadctrlgrp_config { + u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ + u32 func:8; /* function to assign PMUX_FUNC_... */ }; -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len); + +struct pmux_mipipadctrlgrp_desc { + u8 funcs[2]; +}; + +extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 78bc9e6f17..9fcbb0f80b 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -246,6 +246,11 @@ enum pmux_drvgrp { PMUX_DRVGRP_COUNT, }; +enum pmux_mipipadctrlgrp { + PMUX_MIPIPADCTRLGRP_DSI_B, + PMUX_MIPIPADCTRLGRP_COUNT, +}; + enum pmux_func { PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, @@ -255,6 +260,7 @@ enum pmux_func { PMUX_FUNC_CLK, PMUX_FUNC_CLK12, PMUX_FUNC_CPU, + PMUX_FUNC_CSI, PMUX_FUNC_DAP, PMUX_FUNC_DAP1, PMUX_FUNC_DAP2, @@ -263,6 +269,7 @@ enum pmux_func { PMUX_FUNC_DISPLAYA_ALT, PMUX_FUNC_DISPLAYB, PMUX_FUNC_DP, + PMUX_FUNC_DSI_B, PMUX_FUNC_DTV, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, @@ -336,8 +343,10 @@ enum pmux_func { }; #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS #define TEGRA_PMX_GRPS_HAVE_LPMD #define TEGRA_PMX_GRPS_HAVE_SCHMT #define TEGRA_PMX_GRPS_HAVE_HSM diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index be80434dee..7a34a0186c 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,10 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#ifdef __aarch64__ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d4a447b2b8..c424a22442 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CWME9210 3320 #define MACH_TYPE_CWME9210JS 3321 #define MACH_TYPE_PGS_SITARA 3322 -#define MACH_TYPE_COLIBRI_TEGRA2 3323 +#define MACH_TYPE_COLIBRI_T20 3323 #define MACH_TYPE_W21 3324 #define MACH_TYPE_POLYSAT1 3325 #define MACH_TYPE_DATAWAY 3326 @@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type; # define machine_is_pgs_v1() (0) #endif -#ifdef CONFIG_MACH_COLIBRI_TEGRA2 +#ifdef CONFIG_MACH_COLIBRI_T20 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2 +# define machine_arch_type MACH_TYPE_COLIBRI_T20 # endif -# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2) +# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20) #else -# define machine_is_colibri_tegra2() (0) +# define machine_is_colibri_t20() (0) #endif #ifdef CONFIG_MACH_W21 diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h deleted file mode 100644 index 835ca7e4b6..0000000000 --- a/arch/arm/include/asm/semihosting.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2014 Broadcom Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SEMIHOSTING_H__ -#define __SEMIHOSTING_H__ - -/* - * ARM semihosting functions for loading images to memory. See the source - * code for more information. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose); -long smh_len(const char *fname); - -#endif /* __SEMIHOSTING_H__ */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 77563967e5..1654011432 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -62,9 +62,18 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) - sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + sub x18, x0, #GD_SIZE /* allocate one GD above SP */ + bic x18, x18, #0x7 /* 8-byte alignment for GD */ +zero_gd: + sub x0, x0, #0x8 + str xzr, [x0] + cmp x0, x18 + b.gt zero_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + str x0, [x18, #GD_MALLOC_BASE] +#endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index fd6d8573f5..c3e964eabc 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -13,7 +13,7 @@ * for them. */ #include <common.h> -#include <asm/semihosting.h> +#include <command.h> #define SYSOPEN 0x01 #define SYSCLOSE 0x02 @@ -26,7 +26,7 @@ /* * Call the handler */ -static long smh_trap(unsigned int sysnum, void *addr) +static noinline long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); #if defined(CONFIG_ARM64) @@ -144,93 +144,71 @@ static long smh_len_fd(long fd) return ret; } -/* - * Open, load a file into memory, and close it. Check that the available space - * is sufficient to store the entire file. Return the bytes actually read from - * the file as seen by the read function. The verbose flag enables some extra - * printing of successful read status. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose) +static int smh_load_file(const char * const name, ulong load_addr, + ulong *end_addr) { - long ret; long fd; - size_t len; - - ret = -1; - - debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname, - avail, memp); + long len; + long ret; - /* Open the file */ - fd = smh_open(fname, "rb"); + fd = smh_open(name, "rb"); if (fd == -1) return -1; - /* Get the file length */ - ret = smh_len_fd(fd); - if (ret == -1) { - smh_close(fd); - return -1; - } - - /* Check that the file will fit in the supplied buffer */ - if (ret > avail) { - printf("%s: ERROR ret %ld, avail %u\n", __func__, ret, - avail); + len = smh_len_fd(fd); + if (len < 0) { smh_close(fd); return -1; } - len = ret; + ret = smh_read(fd, (void *)load_addr, len); + smh_close(fd); - /* Read the file into the buffer */ - ret = smh_read(fd, memp, len); if (ret == 0) { - /* Print successful load information if requested */ - if (verbose) { - printf("\n%s\n", fname); - printf(" 0x%8p dest\n", memp); - printf(" 0x%08lx size\n", len); - printf(" 0x%08x avail\n", avail); - } + *end_addr = load_addr + len - 1; + printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", + name, + load_addr, + *end_addr, + len); + } else { + printf("read failed\n"); + return 0; } - /* Close the file */ - smh_close(fd); - - return ret; + return 0; } -/* - * Get the file length from the filename - */ -long smh_len(const char *fname) +static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long ret; - long fd; - long len; - - debug("%s: file \'%s\'\n", __func__, fname); - - /* Open the file */ - fd = smh_open(fname, "rb"); - if (fd < 0) - return fd; - - /* Get the file length */ - len = smh_len_fd(fd); - if (len < 0) { - smh_close(fd); - return len; + if (argc == 3 || argc == 4) { + ulong load_addr; + ulong end_addr = 0; + ulong ret; + char end_str[64]; + + load_addr = simple_strtoul(argv[2], NULL, 16); + if (!load_addr) + return -1; + + ret = smh_load_file(argv[1], load_addr, &end_addr); + if (ret < 0) + return 1; + + /* Optionally save returned end to the environment */ + if (argc == 4) { + sprintf(end_str, "0x%08lx", end_addr); + setenv(argv[3], end_str); + } + } else { + return CMD_RET_USAGE; } - - /* Close the file */ - ret = smh_close(fd); - if (ret < 0) - return ret; - - debug("%s: returning len %ld\n", __func__, len); - - /* Return the file length (or -1 error indication) */ - return len; + return 0; } + +U_BOOT_CMD(smhload, 4, 0, do_smhload, "load a file using semihosting", + "<file> 0x<address> [end var]\n" + " - load a semihosted file to the address specified\n" + " if the optional [end var] is specified, the end\n" + " address of the file will be stored in this environment\n" + " variable.\n"); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 30945c101b..30c4e17ec9 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -66,6 +66,7 @@ config TARGET_STAMP9G20 config TARGET_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_PM9G45 bool "Ronetix pm9g45 board" @@ -74,6 +75,7 @@ config TARGET_PM9G45 config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_AT91SAM9RLEK bool "Atmel at91sam9rl reference board" @@ -82,6 +84,7 @@ config TARGET_AT91SAM9RLEK config TARGET_AT91SAM9X5EK bool "Atmel AT91SAM9X5-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index e596ba6ce8..0d3ee48493 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,6 +2,8 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o +obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o obj-y += spl.o diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index f363982d03..8d6934e324 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock) void at91_plla_init(u32 pllar) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) + ; } void at91_pllb_init(u32 pllbr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllbr, &pmc->pllbr); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) + ; } void at91_mck_init(u32 mckr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; u32 tmp; tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); + tmp &= ~AT91_PMC_MCKR_PRES_MASK; + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK; writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { - timeout--; - if (timeout == 0) - break; - } + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_MDIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_CSS_MASK; + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; } void at91_periph_clk_enable(int id) diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index b0b7fb93fb..31ce646260 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -33,22 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define TIMER_LOAD_VAL 0xfffff -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - /* * Use the PITC in full 32 bit incrementing mode */ @@ -64,54 +48,11 @@ int timer_init(void) writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; - gd->arch.tbu = gd->arch.tbl = 0; return 0; } /* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* * Return the number of timer ticks per second. */ ulong get_tbclk(void) diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds new file mode 100644 index 0000000000..acadd1d4c4 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index 19bf80ba7e..a4a3817aa6 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -36,22 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define TIMER_LOAD_VAL 0xfffff -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - /* * Use the PITC in full 32 bit incrementing mode */ @@ -67,55 +51,10 @@ int timer_init(void) gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; - gd->arch.tbu = 0; - gd->arch.tbl = 0; - return 0; } /* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* * Return the number of timer ticks per second. */ ulong get_tbclk(void) diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 65691aba01..ebb7decd22 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -97,7 +97,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 #define AT91_PMC_MCKR_PRES_4 0x00000020 @@ -126,7 +127,8 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_MDIV_3 0x00000300 #endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 8950d67409..1a4e84b050 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -133,6 +133,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 6dfcf4c0c8..914a3b0460 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -117,6 +117,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 64a3888e22..71675abf82 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -132,6 +132,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 6df8cdb56d..cf1c73f3d9 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -136,6 +136,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 3a8e6d62ce..70bbf4edaa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -116,6 +116,9 @@ #define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 36a5cdf476..8100ebed4b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -124,6 +124,16 @@ #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ #endif +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 + /* 9x5 series chip id definitions */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_VERSION_MASK 0x1f @@ -154,6 +164,9 @@ #define ATMEL_CPU_NAME get_cpu_name() #endif +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 227ba80825..b749cb3359 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -189,6 +189,9 @@ #define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c + /* * PMECC table in ROM */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index f30cb5fed1..7773ace439 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -193,6 +193,9 @@ #define cpu_is_sama5d44() (cpu_is_sama5d4() && \ (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c + /* * No PMECC Galois table in ROM */ diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index beec13db8c..e2b6a49eb9 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) static int ddr2_decodtype_is_seq(u32 cr) { -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) return 0; #endif diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index aaa5eec2e6..27a405a42b 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; #elif CONFIG_SYS_USE_NANDFLASH return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH +#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_NONE; diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 89f588be45..a79a9dce75 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void) { } -void spl_board_init(void) +void __weak spl_board_init(void) +{ +} + +void board_init_f(ulong dummy) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -111,9 +115,14 @@ void spl_board_init(void) timer_init(); /* enable clocks for all PIOs */ +#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) + at91_periph_clk_enable(ATMEL_ID_PIOAB); + at91_periph_clk_enable(ATMEL_ID_PIOCD); +#else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); +#endif /* init console */ at91_seriald_hw_init(); preloader_console_init(); diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 9cc1111234..8ac53353e6 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -70,8 +70,13 @@ __weak void redirect_int_from_saic_to_aic(void) /* This only be used for sama5d4 soc now */ } +/* empty stub to satisfy current lowlevel_init, can be removed any time */ void s_init(void) { +} + +void board_init_f(ulong dummy) +{ switch_to_main_crystal_osc(); /* disable watchdog */ @@ -93,4 +98,9 @@ void s_init(void) preloader_console_init(); mem_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); } diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig new file mode 100644 index 0000000000..b43f2d91fd --- /dev/null +++ b/arch/arm/mach-bcm283x/Kconfig @@ -0,0 +1,40 @@ +menu "Broadcom BCM283X family" + depends on ARCH_BCM283X + +choice + prompt "Broadcom BCM283X board select" + +config TARGET_RPI + bool "Raspberry Pi" + select CPU_ARM1176 + +config TARGET_RPI_2 + bool "Raspberry Pi 2" + select CPU_V7 + +endchoice + +config DM + default y + +config DM_SERIAL + default y + +config DM_GPIO + default y + +config SYS_BOARD + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm283x" + +config SYS_CONFIG_NAME + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +endmenu diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/mach-bcm283x/Makefile index 7e5dbe1fde..2505428bab 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/mach-bcm283x/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := lowlevel_init.o +obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o obj-y += init.o reset.o timer.o mbox.o diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h index c8ef8f528a..c8ef8f528a 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/mach-bcm283x/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 04bf480a54..54d369c46c 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -132,7 +132,7 @@ struct bcm2835_mbox_tag_hdr { * 0x2..0xf from: * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 - * 0x10, 0x11 from swarren's testing + * http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796 */ #define BCM2835_BOARD_REV_B_I2C0_2 0x2 #define BCM2835_BOARD_REV_B_I2C0_3 0x3 @@ -148,6 +148,8 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_B_PLUS 0x10 #define BCM2835_BOARD_REV_CM 0x11 #define BCM2835_BOARD_REV_A_PLUS 0x12 +#define BCM2835_BOARD_REV_B_PLUS_13 0x13 +#define BCM2835_BOARD_REV_CM_14 0x14 #endif struct bcm2835_mbox_tag_get_board_rev { diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h index 2a21ccbf66..2a21ccbf66 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h index fc7aec7b7c..fc7aec7b7c 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/mach-bcm283x/include/mach/timer.h diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h index beb6a08206..beb6a08206 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/mach-bcm283x/include/mach/wdog.h diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/mach-bcm283x/init.c index e90d3bba1f..e90d3bba1f 100644 --- a/arch/arm/cpu/arm1176/bcm2835/init.c +++ b/arch/arm/mach-bcm283x/init.c diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S index c7b0843281..c7b0843281 100644 --- a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S +++ b/arch/arm/mach-bcm283x/lowlevel_init.S diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/mach-bcm283x/mbox.c index 3b17a31eac..3b17a31eac 100644 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/mach-bcm283x/reset.c index 8c37ad9fd4..8c37ad9fd4 100644 --- a/arch/arm/cpu/arm1176/bcm2835/reset.c +++ b/arch/arm/mach-bcm283x/reset.c diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/mach-bcm283x/timer.c index 017907cfb8..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/mach-bcm283x/timer.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fccfd79648..fce1c1dc87 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -17,9 +17,6 @@ config TEGRA124 endchoice -config SYS_MALLOC_F - default y - config SYS_MALLOC_F_LEN default 0x1800 diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index a211bb3b1a..4bc0a3f5a1 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> .align 5 diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 912f65e98b..b4a1432afc 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -108,6 +108,8 @@ #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) +#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4)) + /* * We could force arch-tegraNN/pinmux.h to define all of these. However, * that's a lot of defines, and for now it's manageable to just put a @@ -695,4 +697,59 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, for (i = 0; i < len; i++) pinmux_config_drvgrp(&config[i]); } -#endif /* TEGRA_PMX_HAS_DRVGRPS */ +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ + +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS + +#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT)) + +static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, + enum pmux_func func) +{ + u32 *reg = MIPIPADCTRL_REG(grp); + int i, mux = -1; + u32 val; + + if (func == PMUX_FUNC_DEFAULT) + return; + + /* Error check grp and func */ + assert(pmux_mipipadctrlgrp_isvalid(grp)); + assert(pmux_func_isvalid(func)); + + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 1; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 2; i++) { + if (tegra_soc_mipipadctrl_groups[grp].funcs[i] + == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + val = readl(reg); + val &= ~(1 << 1); + val |= (mux << 1); + writel(val, reg); +} + +static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config) +{ + enum pmux_mipipadctrlgrp grp = config->grp; + + pinmux_mipipadctrl_set_func(grp, config->func); +} + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_mipipadctrlgrp(&config[i]); +} +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index c6685eaae1..4629b4676c 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = { PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; + +#define MIPIPADCTRL_GRP(grp, f0, f1) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + }, \ + } + +#define MIPIPADCTRL_RESERVED {} + +static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { + /* pin, f0, f1 */ + /* Offset 0x820 */ + MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), +}; +const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a354e2ad1f..7f09f819cc 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -30,7 +30,7 @@ config TARGET_VENTANA config TARGET_WHISTLER bool "NVIDIA Tegra20 Whistler evaluation board" -config TARGET_COLIBRI_T20_IRIS +config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" endchoice @@ -47,6 +47,6 @@ source "board/avionic-design/tec/Kconfig" source "board/compulab/trimslice/Kconfig" source "board/nvidia/ventana/Kconfig" source "board/nvidia/whistler/Kconfig" -source "board/toradex/colibri_t20_iris/Kconfig" +source "board/toradex/colibri_t20/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a0738d..44a85c5f1d 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE); diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c index a29c76b1fa..a29c76b1fa 100644 --- a/arch/arm/cpu/tegra210-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra210/pinmux.c diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 8335685e32..288e6aba79 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -1,9 +1,6 @@ menu "Panasonic UniPhier platform" depends on ARCH_UNIPHIER -config SYS_SOC - default "uniphier" - config SYS_CONFIG_NAME default "uniphier" @@ -48,12 +45,6 @@ config DCC_MICRO_SUPPORT_CARD endchoice -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - config CMD_PINMON bool "Enable boot mode pins monitor command" default y diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index e7a801b2ac..24591d6ee5 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -12,6 +12,7 @@ obj-y += ddrphy_training.o else +obj-y += late_lowlevel_init.o obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o @@ -21,7 +22,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index 52f3c7c7a6..d8b8228853 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,36 +120,7 @@ void v7_outer_cache_disable(void) writel(tmp, SSCC); } -void wakeup_secondary(void); - void enable_caches(void) { - uint32_t reg; - -#ifdef CONFIG_UNIPHIER_SMP - /* - * The secondary CPU must move to DDR, - * before L2 disable. - * On SPL, the Page Table is located on the L2. - */ - wakeup_secondary(); -#endif - /* - * UniPhier SoCs must use L2 cache for init stack pointer. - * We disable L2 and L1 in this order. - * If CONFIG_SYS_DCACHE_OFF is not defined, - * caches are enabled again with a new page table. - */ - - /* L2 disable */ - v7_outer_cache_disable(); - - /* L1 disable */ - reg = get_cr(); - reg &= ~(CR_C | CR_M); - set_cr(reg); - -#ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); -#endif } diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S index 2638bcd779..ac2959a17d 100644 --- a/arch/arm/mach-uniphier/init_page_table.S +++ b/arch/arm/mach-uniphier/init_page_table.S @@ -1,3 +1,11 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <config.h> #include <linux/linkage.h> @@ -8,7 +16,7 @@ #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ #define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) -#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT)) +#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT)) .section ".rodata" .align 14 diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S new file mode 100644 index 0000000000..1363364c80 --- /dev/null +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/ssc-regs.h> + +ENTRY(lowlevel_init) + ldr r1, = SSCC + ldr r0, [r1] + bic r0, r0, #SSCC_ON @ L2 disable + str r0, [r1] + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 92299fe64d..825b160762 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,8 +25,8 @@ ENTRY(lowlevel_init) * First we need to turn on MMU and Dcache again to get back * data access to L2. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 #ifdef CONFIG_DEBUG_LL @@ -40,13 +41,32 @@ ENTRY(lowlevel_init) ldr r3, =init_page_table @ page table must be 16KB aligned /* Disable MMU and Dcache before switching Page Table */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 bl enable_mmu #ifdef CONFIG_UNIPHIER_SMP +secondary_startup: + /* + * Entry point for secondary CPUs + * + * The Boot ROM has already enabled MMU for the secondary CPUs as well + * as for the primary one. The MMU table embedded in the Boot ROM + * prohibits the DRAM access, so it is impossible to bring the + * secondary CPUs into DRAM directly. They must jump here into SPL, + * which is run on L2 cache. + * + * Boot Sequence + * [primary CPU] [secondary CPUs] + * start from Boot ROM start from Boot ROM + * jump to SPL sleep in Boot ROM + * kick secondaries ---(sev)---> jump to SPL + * jump to U-Boot main sleep in SPL + * jump to Linux + * kick secondaries ---(sev)---> jump to Linux + */ /* * ACTLR (Auxiliary Control Register) for Cortex-A9 * bit[9] Parity on @@ -54,7 +74,7 @@ ENTRY(lowlevel_init) * bit[7] EXCL (Exclusive cache bit) * bit[6] SMP * bit[3] Write full line of zeros mode - * bit[2] L1 Prefetch enable + * bit[2] L1 prefetch enable * bit[1] L2 prefetch enable * bit[0] FW (Cache and TLB maintenance broadcast) */ @@ -67,20 +87,31 @@ ENTRY(lowlevel_init) and r0, r0, #0x3 cmp r0, #0x0 beq primary_cpu - ldr r1, =ROM_BOOT_ROMRSV2 + /* only for secondary CPUs */ + ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #CR_I @ Enable ICache + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled + mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux mov r0, #0 str r0, [r1] -0: wfe - ldr r0, [r1] + b 1f + /* + * L2 cache is shared among all the CPUs and it might be disabled by + * the primary one. Before that, the following 5 lines must be cached + * on the Icaches of the secondary CPUs. + */ +0: wfe @ kicked by Linux +1: ldr r0, [r1] cmp r0, #0 - beq 0b - bx r0 @ r0: entry point of U-Boot main for the secondary CPU + bxne r0 @ r0: Linux entry for secondary CPUs + b 0b primary_cpu: ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =_start @ entry for the secondary CPU + ldr r0, =secondary_startup str r0, [r1] ldr r0, [r1] @ make sure str is complete before sev - sev @ kick the sedoncary CPU + sev @ kick the secondary CPU mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register bfc r1, #0, #13 @ clear bit 12-0 mov r0, #-1 @@ -117,7 +148,7 @@ ENTRY(enable_mmu) * TLBs was already invalidated in "../start.S" * So, we don't need to invalidate it here. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable mcr p15, 0, r0, c1, c0, 0 @@ -142,7 +173,7 @@ ENTRY(setup_init_ram) ldr r0, = 0x00408006 @ touch to zero with address range ldr r1, = SSCOQM str r0, [r1] - ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address ldr r1, = SSCOQAD str r0, [r1] ldr r0, = BOOT_RAM_SIZE @@ -154,7 +185,7 @@ ENTRY(setup_init_ram) ldr r1, = SSCOPPQSEF ldr r0, [r1] cmp r0, #0 @ check if the command is successfully set - bne 0b @ try again if an error occurres + bne 0b @ try again if an error occurs ldr r1, = SSCOLPQS 1: diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index 5ce3d8a520..af815c3260 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c new file mode 100644 index 0000000000..e5e86bb363 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c index 15d81ebb3d..3074d0a8d2 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -14,20 +14,6 @@ void pin_init(void) /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ - sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ - - sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ - sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ - - sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ - sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index b88525c82d..f6a584e1f0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c new file mode 100644 index 0000000000..85bb6a0b9c --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c index f382ef4842..4df9098ef0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,17 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ - sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ - sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ - sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ - sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ - sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ - sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile index 5ce3d8a520..8eb575e1d3 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -1,16 +1 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o -endif - -obj-y += boot-mode.o +include $(src)/../ph1-ld4/Makefile diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c new file mode 100644 index 0000000000..28cc4296fc --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c index 4c494ffa40..57a8093048 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,20 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ - sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ - - sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ - - sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ - sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_SYS_I2C_UNIPHIER { u32 tmp; diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S deleted file mode 100644 index 18e3a9d21e..0000000000 --- a/arch/arm/mach-uniphier/smp.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2013 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> -#include <asm/system.h> -#include <mach/led.h> -#include <mach/sbc-regs.h> - -/* Entry point of U-Boot main program for the secondary CPU */ -LENTRY(secondary_entry) - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable - mcr p15, 0, r0, c1, c0, 0 - mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - dsb - led_write(C,0,,) - ldr r1, =ROM_BOOT_ROMRSV2 - mov r0, #0 - str r0, [r1] -0: wfe - ldr r4, [r1] @ r4: entry point for secondary CPUs - cmp r4, #0 - beq 0b - led_write(C, P, U, 1) - bx r4 @ secondary CPUs jump to linux -ENDPROC(secondary_entry) - -ENTRY(wakeup_secondary) - ldr r1, =ROM_BOOT_ROMRSV2 -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - - /* set entry address and send event to the secondary CPU */ - ldr r0, =secondary_entry - str r0, [r1] - ldr r0, [r1] @ make sure store is complete - mov r0, #0x100 -0: subs r0, r0, #1 @ I don't know the reason, but without this wait - bne 0b @ fails to wake up the secondary CPU - sev - - /* wait until the secondary CPU reach to secondary_entry */ -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - bx lr -ENDPROC(wakeup_secondary) diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index c3d90d03d0..a34d3a167c 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2013-2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,6 +21,7 @@ void pll_init(void); void pin_init(void); void memconf_init(void); void early_clkrst_init(void); +void early_pin_init(void); int umc_init(void); void enable_dpll_ssc(void); @@ -47,6 +49,16 @@ void spl_board_init(void) led_write(L, 2, , ); + early_pin_init(); + + led_write(L, 3, , ); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_write(L, 4, , ); + { int res; @@ -56,9 +68,9 @@ void spl_board_init(void) ; } } - led_write(L, 3, , ); + led_write(L, 5, , ); enable_dpll_ssc(); - led_write(L, 4, , ); + led_write(L, 6, , ); } diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index e7b4158636..77cc794e61 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -94,7 +95,7 @@ void support_card_init(void) /* * After power on, we need to keep the LAN controller in reset state * for a while. (200 usec) - * Fortunatelly, enough wait time is already inserted in pll_init() + * Fortunately, enough wait time is already inserted in pll_init() * function. So we do not have to wait here. */ support_card_reset_deassert(); @@ -213,11 +214,11 @@ static void detect_num_flash_banks(void) debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); } -#else /* ONFIG_SYS_NO_FLASH */ +#else /* CONFIG_SYS_NO_FLASH */ void detect_num_flash_banks(void) { }; -#endif /* ONFIG_SYS_NO_FLASH */ +#endif /* CONFIG_SYS_NO_FLASH */ void support_card_late_init(void) { |
