diff options
Diffstat (limited to 'arch/arm')
71 files changed, 2277 insertions, 546 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 3479541020..e0f9d5b6b4 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -15,7 +15,7 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/board.h> -#include <asm/arch/spl.h> +#include <asm/spl.h> #include "cpu.h" void spl_board_init(void) diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index b91e948ce3..19730cef8c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -14,7 +14,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/davinci_misc.h> #include <asm/arch/ddr2_defs.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/pll_defs.h> void davinci_enable_uart0(void) diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index ee096fe721..c8b44988d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -11,6 +11,7 @@ #include <nand.h> #include <ns16550.h> #include <post.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/dm365_lowlevel.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index d4711c070c..da80240052 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -13,7 +13,6 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> -#include <hush.h> #define BUFLEN 16 @@ -211,7 +210,7 @@ static void kw_sysrst_action(void) debug("Starting %s process...\n", __FUNCTION__); ret = run_command(s, 0); - if (ret < 0) + if (ret != 0) debug("Error.. %s failed\n", __FUNCTION__); else debug("%s process finished\n", __FUNCTION__); diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index b55c5f0943..f88db3b1f9 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -15,7 +15,6 @@ #include <asm/io.h> #include <u-boot/md5.h> #include <asm/arch/cpu.h> -#include <hush.h> #define BUFLEN 16 diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 7fe049e513..828d10bb5a 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -255,11 +255,3 @@ void s_init(void) #endif } #endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 9a625c4661..bbe9d1a8de 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -95,6 +95,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) &emif_reg[nr]->emif_rd_wr_exec_thresh); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c index 2fbf60d542..8d86f97e3d 100644 --- a/arch/arm/cpu/armv7/at91/cpu.c +++ b/arch/arm/cpu/armv7/at91/cpu.c @@ -61,6 +61,8 @@ int print_cpuinfo(void) void enable_caches(void) { + icache_enable(); + dcache_enable(); } unsigned int get_chip_id(void) diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index ade45fd5d3..79166303d1 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include<common.h> -#include<config.h> +#include <common.h> +#include <config.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index b1bd0224ea..c4af252110 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += aemif.o obj-y += init.o obj-y += psc.o obj-y += clock.o diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c deleted file mode 100644 index 9b26886dba..0000000000 --- a/arch/arm/cpu/armv7/keystone/aemif.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Keystone2: Asynchronous EMIF Configuration - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/emif_defs.h> - -#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) -#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) -#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~AEMIF_CFG_##field(0xffffffff); \ - reg |= AEMIF_CFG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(&davinci_emif_regs->nandfcr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->nandfcr); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(&davinci_emif_regs->one_nand_cr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->one_nand_cr); - } - - tmp = __raw_readl(&davinci_emif_regs->abncr[cs]); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, &davinci_emif_regs->abncr[cs]); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index d7285fc2cc..6dc9f8ec21 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -8,4 +8,5 @@ # obj-y := soc.o clock.o +obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_SECURE_BOOT) += hab.o diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c new file mode 100644 index 0000000000..0434211110 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/types.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/types.h> + +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +/* Configure MX6DQ mmdc iomux */ +void mx6dq_dram_iocfg(unsigned width, + const struct mx6dq_iomux_ddr_regs *ddr, + const struct mx6dq_iomux_grp_regs *grp) +{ + volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +/* Configure MX6SDL mmdc iomux */ +void mx6sdl_dram_iocfg(unsigned width, + const struct mx6sdl_iomux_ddr_regs *ddr, + const struct mx6sdl_iomux_grp_regs *grp) +{ + volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +/* + * Configure mx6 mmdc registers based on: + * - board-specific memory configuration + * - board-specific calibration data + * - ddr3 chip details + * + * The various calculations here are derived from the Freescale + * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC + * configuration registers based on memory system and memory chip parameters. + * + * The defaults here are those which were specified in the spreadsheet. + * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM + * section titled MMDC initialization + */ +#define MR(val, ba, cmd, cs1) \ + ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, + const struct mx6_mmdc_calibration *c, + const struct mx6_ddr3_cfg *m) +{ + volatile struct mmdc_p_regs *mmdc0; + volatile struct mmdc_p_regs *mmdc1; + u32 reg; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; + u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ + u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; + u16 CS0_END; + u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ + int clkper; /* clock period in picoseconds */ + int clock; /* clock freq in mHz */ + int cs; + + mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; + + /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + clock = 528; + tcwl = 4; + } + /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ + else { + clock = 400; + tcwl = 3; + } + clkper = (1000*1000)/clock; /* ps */ + todtlon = tcwl; + taxpd = tcwl; + tanpd = tcwl; + tcwl = tcwl; + + switch (m->density) { + case 1: /* 1Gb per chip */ + trfc = DIV_ROUND_UP(110000, clkper) - 1; + txs = DIV_ROUND_UP(120000, clkper) - 1; + break; + case 2: /* 2Gb per chip */ + trfc = DIV_ROUND_UP(160000, clkper) - 1; + txs = DIV_ROUND_UP(170000, clkper) - 1; + break; + case 4: /* 4Gb per chip */ + trfc = DIV_ROUND_UP(260000, clkper) - 1; + txs = DIV_ROUND_UP(270000, clkper) - 1; + break; + case 8: /* 8Gb per chip */ + trfc = DIV_ROUND_UP(350000, clkper) - 1; + txs = DIV_ROUND_UP(360000, clkper) - 1; + break; + default: + /* invalid density */ + printf("invalid chip density\n"); + hang(); + break; + } + txpr = txs; + + switch (m->mem_speed) { + case 800: + txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } + break; + case 1066: + txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(37500, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } + break; + case 1333: + txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(45000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } + break; + case 1600: + txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } + break; + default: + printf("invalid memory speed\n"); + hang(); + break; + } + txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1; + tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3; + tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper); + tcksrx = tcksre; + taonpd = DIV_ROUND_UP(2000, clkper) - 1; + taofpd = taonpd; + trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1; + trcd = trp; + trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1; + tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1; + twr = DIV_ROUND_UP(15000, clkper) - 1; + tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1; + twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1; + trtp = twtr; + CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127; + debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density); + debug("clock: %dMHz (%d ps)\n", clock, clkper); + debug("memspd:%d\n", m->mem_speed); + debug("tcke=%d\n", tcke); + debug("tcksrx=%d\n", tcksrx); + debug("tcksre=%d\n", tcksre); + debug("taofpd=%d\n", taofpd); + debug("taonpd=%d\n", taonpd); + debug("todtlon=%d\n", todtlon); + debug("tanpd=%d\n", tanpd); + debug("taxpd=%d\n", taxpd); + debug("trfc=%d\n", trfc); + debug("txs=%d\n", txs); + debug("txp=%d\n", txp); + debug("txpdll=%d\n", txpdll); + debug("tfaw=%d\n", tfaw); + debug("tcl=%d\n", tcl); + debug("trcd=%d\n", trcd); + debug("trp=%d\n", trp); + debug("trc=%d\n", trc); + debug("tras=%d\n", tras); + debug("twr=%d\n", twr); + debug("tmrd=%d\n", tmrd); + debug("tcwl=%d\n", tcwl); + debug("tdllk=%d\n", tdllk); + debug("trtp=%d\n", trtp); + debug("twtr=%d\n", twtr); + debug("trrd=%d\n", trrd); + debug("txpr=%d\n", txpr); + debug("CS0_END=%d\n", CS0_END); + debug("ncs=%d\n", i->ncs); + debug("Rtt_wr=%d\n", i->rtt_wr); + debug("Rtt_nom=%d\n", i->rtt_nom); + debug("SRT=%d\n", m->SRT); + debug("tcl=%d\n", tcl); + debug("twr=%d\n", twr); + + /* + * board-specific configuration: + * These values are determined empirically and vary per board layout + * see: + * appnote, ddr3 spreadsheet + */ + mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; + mmdc0->mprddlctl = c->p0_mprddlctl; + mmdc0->mpwrdlctl = c->p0_mpwrdlctl; + if (i->dsize > 1) { + mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; + mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; + mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; + mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; + mmdc1->mprddlctl = c->p1_mprddlctl; + mmdc1->mpwrdlctl = c->p1_mpwrdlctl; + } + + /* Read data DQ Byte0-3 delay */ + mmdc0->mprddqby0dl = (u32)0x33333333; + mmdc0->mprddqby1dl = (u32)0x33333333; + if (i->dsize > 0) { + mmdc0->mprddqby2dl = (u32)0x33333333; + mmdc0->mprddqby3dl = (u32)0x33333333; + } + if (i->dsize > 1) { + mmdc1->mprddqby0dl = (u32)0x33333333; + mmdc1->mprddqby1dl = (u32)0x33333333; + mmdc1->mprddqby2dl = (u32)0x33333333; + mmdc1->mprddqby3dl = (u32)0x33333333; + } + + /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ + reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227; + mmdc0->mpodtctrl = reg; + if (i->dsize > 1) + mmdc1->mpodtctrl = reg; + + /* complete calibration */ + reg = (1 << 11); /* Force measurement on delay-lines */ + mmdc0->mpmur0 = reg; + if (i->dsize > 1) + mmdc1->mpmur0 = reg; + + /* Step 1: configuration request */ + mmdc0->mdscr = (u32)(1 << 15); /* config request */ + + /* Step 2: Timing configuration */ + reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | + (tfaw << 4) | tcl; + mmdc0->mdcfg0 = reg; + reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) | + (1 << 15) | /* trpa */ + (twr << 9) | (tmrd << 5) | tcwl; + mmdc0->mdcfg1 = reg; + reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; + mmdc0->mdcfg2 = reg; + reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) | + (todtlon << 12) | (todt_idle_off << 4); + mmdc0->mdotc = reg; + mmdc0->mdasp = CS0_END; /* CS addressing */ + + /* Step 3: Configure DDR type */ + reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) | + (i->mif3_mode << 9) | (i->ralat << 6); + mmdc0->mdmisc = reg; + + /* Step 4: Configure delay while leaving reset */ + reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0); + mmdc0->mdor = reg; + + /* Step 5: Configure DDR physical parameters (density and burst len) */ + reg = (m->rowaddr - 11) << 24 | /* ROW */ + (m->coladdr - 9) << 20 | /* COL */ + (1 << 19) | /* Burst Length = 8 for DDR3 */ + (i->dsize << 16); /* DDR data bus size */ + mmdc0->mdctl = reg; + + /* Step 6: Perform ZQ calibration */ + reg = (u32)0xa1390001; /* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = reg; + if (i->dsize > 1) + mmdc1->mpzqhwctrl = reg; + + /* Step 7: Enable MMDC with desired chip select */ + reg = mmdc0->mdctl | + (1 << 31) | /* SDE_0 for CS0 */ + ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ + mmdc0->mdctl = reg; + + /* Step 8: Write Mode Registers to Init DDR3 devices */ + for (cs = 0; cs < i->ncs; cs++) { + /* MR2 */ + reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 | + ((tcwl - 3) & 3) << 3; + mmdc0->mdscr = (u32)MR(reg, 2, 3, cs); + /* MR3 */ + mmdc0->mdscr = (u32)MR(0, 3, 3, cs); + /* MR1 */ + reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 | + ((i->rtt_nom & 2) ? 1 : 0) << 6; + mmdc0->mdscr = (u32)MR(reg, 1, 3, cs); + reg = ((tcl - 1) << 4) | /* CAS */ + (1 << 8) | /* DLL Reset */ + ((twr - 3) << 9); /* Write Recovery */ + /* MR0 */ + mmdc0->mdscr = (u32)MR(reg, 0, 3, cs); + /* ZQ calibration */ + reg = (1 << 10); + mmdc0->mdscr = (u32)MR(reg, 0, 4, cs); + } + + /* Step 10: Power down control and self-refresh */ + reg = (tcke & 0x7) << 16 | + 5 << 12 | /* PWDT_1: 256 cycles */ + 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 6 | /* BOTH_CS_PD */ + (tcksrx & 0x7) << 3 | + (tcksre & 0x7); + mmdc0->mdpdc = reg; + mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */ + + /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ + mmdc0->mpzqhwctrl = (u32)0xa1390003; + if (i->dsize > 1) + mmdc1->mpzqhwctrl = (u32)0xa1390003; + + /* Step 12: Configure and activate periodic refresh */ + reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */ + (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + mmdc0->mdref = reg; + + /* Step 13: Deassert config request - init complete */ + mmdc0->mdscr = (u32)0x00000000; + + /* wait for auto-ZQ calibration to complete */ + mdelay(1); +} diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c index 5187775365..f6810a680d 100644 --- a/arch/arm/cpu/armv7/mx6/hab.c +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -7,15 +7,69 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hab.h> +#include <asm/arch/sys_proto.h> /* -------- start of HAB API updates ------------*/ -#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) -#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) -#define hab_rvt_authenticate_image \ - ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) -#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) -#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) -#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT + +#define hab_rvt_report_event_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ +) + +#define hab_rvt_report_status_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ +) + +#define hab_rvt_authenticate_image_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ +) + +#define hab_rvt_entry_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ +) + +#define hab_rvt_exit_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ +) bool is_hab_enabled(void) { @@ -52,6 +106,11 @@ int get_hab_status(void) size_t bytes = sizeof(event_data); /* Event size in bytes */ enum hab_config config = 0; enum hab_state state = 0; + hab_rvt_report_event_t *hab_rvt_report_event; + hab_rvt_report_status_t *hab_rvt_report_status; + + hab_rvt_report_event = hab_rvt_report_event_p; + hab_rvt_report_status = hab_rvt_report_status_p; if (is_hab_enabled()) puts("\nSecure boot enabled\n"); diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 5f5132f661..7695e16d36 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -22,6 +22,10 @@ obj-y += pipe3-phy.o obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o endif +ifeq ($(CONFIG_SYS_DCACHE_OFF),) +obj-y += omap-cache.o +endif + ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index ba97d9ec56..5f50a19801 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -18,13 +18,8 @@ #include <asm/emif.h> #include <asm/omap_common.h> #include <linux/compiler.h> -#include <asm/cache.h> #include <asm/system.h> -#define ARMV7_DCACHE_WRITEBACK 0xe -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - DECLARE_GLOBAL_DATA_PTR; void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) @@ -263,40 +258,3 @@ int print_cpuinfo(void) return 0; } #endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); - -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 944ef840a1..5bc7e1f19b 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -121,7 +121,8 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); - writel(0x00000000, &gpmc_cfg->timeout_control); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); #ifdef CONFIG_NOR writel(0x00000200, &gpmc_cfg->config); #else @@ -133,5 +134,6 @@ void gpmc_init(void) writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); + if (base != 0) + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c new file mode 100644 index 0000000000..579bebf93f --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -0,0 +1,56 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/cache.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9bb1a1c8f9..667e77ff05 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -147,7 +147,7 @@ void secure_unlock_mem(void) * configure secure registers and exit secure world * general use. *****************************************************************************/ -void secureworld_exit() +void secureworld_exit(void) { unsigned long i; @@ -178,7 +178,7 @@ void secureworld_exit() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. *****************************************************************************/ -void try_unlock_memory() +void try_unlock_memory(void) { int mode; int in_sdram = is_running_in_sdram(); @@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index 69500a64e2..4dc9bb0102 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55546152b9..61527a2b80 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb +dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi new file mode 100644 index 0000000000..2f66deda9f --- /dev/null +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + }; + + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; + }; + + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts new file mode 100644 index 0000000000..197cadf72d --- /dev/null +++ b/arch/arm/dts/am335x-boneblack.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi new file mode 100644 index 0000000000..f9c5da9c7f --- /dev/null +++ b/arch/arm/dts/am33xx.dtsi @@ -0,0 +1,649 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/am33xx.h> + +#include "skeleton.dtsi" + +/ { + compatible = "ti,am33xx"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + d_can0 = &dcan0; + d_can1 = &dcan1; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + am33xx_pinmux: pinmux@44e10800 { + compatible = "pinctrl-single"; + reg = <0x44e10800 0x0238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex.Since + * that will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <128>; + reg = <0x48200000 0x1000>; + }; + + gpio0: gpio@44e07000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x44e07000 0x1000>; + interrupts = <96>; + }; + + gpio1: gpio@4804c000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x4804c000 0x1000>; + interrupts = <98>; + }; + + gpio2: gpio@481ac000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x481ac000 0x1000>; + interrupts = <32>; + }; + + gpio3: gpio@481ae000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x481ae000 0x1000>; + interrupts = <62>; + }; + + uart0: serial@44e09000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + reg = <0x44e09000 0x2000>; + interrupts = <72>; + status = "disabled"; + }; + + uart1: serial@48022000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + reg = <0x48022000 0x2000>; + interrupts = <73>; + status = "disabled"; + }; + + uart2: serial@48024000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + reg = <0x48024000 0x2000>; + interrupts = <74>; + status = "disabled"; + }; + + uart3: serial@481a6000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + reg = <0x481a6000 0x2000>; + interrupts = <44>; + status = "disabled"; + }; + + uart4: serial@481a8000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + reg = <0x481a8000 0x2000>; + interrupts = <45>; + status = "disabled"; + }; + + uart5: serial@481aa000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + reg = <0x481aa000 0x2000>; + interrupts = <46>; + status = "disabled"; + }; + + i2c0: i2c@44e0b000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + reg = <0x44e0b000 0x1000>; + interrupts = <70>; + status = "disabled"; + }; + + i2c1: i2c@4802a000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + interrupts = <71>; + status = "disabled"; + }; + + i2c2: i2c@4819c000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + reg = <0x4819c000 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + + wdt2: wdt@44e35000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + reg = <0x44e35000 0x1000>; + interrupts = <91>; + }; + + dcan0: d_can@481cc000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can0"; + reg = <0x481cc000 0x2000 + 0x44e10644 0x4>; + interrupts = <52>; + status = "disabled"; + }; + + dcan1: d_can@481d0000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can1"; + reg = <0x481d0000 0x2000 + 0x44e10644 0x4>; + interrupts = <55>; + status = "disabled"; + }; + + timer1: timer@44e31000 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x44e31000 0x400>; + interrupts = <67>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48040000 { + compatible = "ti,am335x-timer"; + reg = <0x48040000 0x400>; + interrupts = <68>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,am335x-timer"; + reg = <0x48042000 0x400>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48044000 { + compatible = "ti,am335x-timer"; + reg = <0x48044000 0x400>; + interrupts = <92>; + ti,hwmods = "timer4"; + ti,timer-pwm; + }; + + timer5: timer@48046000 { + compatible = "ti,am335x-timer"; + reg = <0x48046000 0x400>; + interrupts = <93>; + ti,hwmods = "timer5"; + ti,timer-pwm; + }; + + timer6: timer@48048000 { + compatible = "ti,am335x-timer"; + reg = <0x48048000 0x400>; + interrupts = <94>; + ti,hwmods = "timer6"; + ti,timer-pwm; + }; + + timer7: timer@4804a000 { + compatible = "ti,am335x-timer"; + reg = <0x4804a000 0x400>; + interrupts = <95>; + ti,hwmods = "timer7"; + ti,timer-pwm; + }; + + rtc@44e3e000 { + compatible = "ti,da830-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = <75 + 76>; + ti,hwmods = "rtc"; + }; + + spi0: spi@48030000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x48030000 0x400>; + interrupts = <65>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi0"; + status = "disabled"; + }; + + spi1: spi@481a0000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x481a0000 0x400>; + interrupts = <125>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi1"; + status = "disabled"; + }; + + usb: usb@47400000 { + compatible = "ti,am33xx-usb"; + reg = <0x47400000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "usb_otg_hs"; + status = "disabled"; + + ctrl_mod: control@44e10000 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x44e10620 0x10 + 0x44e10648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + status = "disabled"; + }; + + usb0_phy: usb-phy@47401300 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401300 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb0: usb@47401000 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb0_phy>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1_phy: usb-phy@47401b00 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401b00 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb1_phy>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@07402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; + status = "disabled"; + }; + }; + + epwmss0: epwmss@48300000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + ecap0: ecap@48300100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: ehrpwm@48300200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48302000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48302000 0x10>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48302100 0x48302100 0x80 /* ECAP */ + 0x48302180 0x48302180 0x80 /* EQEP */ + 0x48302200 0x48302200 0x80>; /* EHRPWM */ + + ecap1: ecap@48302100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48302100 0x80>; + ti,hwmods = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: ehrpwm@48302200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48302200 0x80>; + ti,hwmods = "ehrpwm1"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48304000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48304000 0x10>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48304100 0x48304100 0x80 /* ECAP */ + 0x48304180 0x48304180 0x80 /* EQEP */ + 0x48304200 0x48304200 0x80>; /* EHRPWM */ + + ecap2: ecap@48304100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48304100 0x80>; + ti,hwmods = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: ehrpwm@48304200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48304200 0x80>; + ti,hwmods = "ehrpwm2"; + status = "disabled"; + }; + }; + + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "cpgmac0"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x4a100000 0x800 + 0x4a101200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges; + + davinci_mdio: mdio@4a101000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x4a101000 0x100>; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + ocmcram: ocmcram@40300000 { + compatible = "ti,am3352-ocmcram"; + reg = <0x40300000 0x10000>; + ti,hwmods = "ocmcram"; + }; + + wkup_m3: wkup_m3@44d00000 { + compatible = "ti,am3353-wkup-m3"; + reg = <0x44d00000 0x4000 /* M3 UMEM */ + 0x44d80000 0x2000>; /* M3 DMEM */ + ti,hwmods = "wkup_m3"; + }; + + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + reg = <0x48080000 0x2000>; + interrupts = <4>; + ti,hwmods = "elm"; + status = "disabled"; + }; + + tscadc: tscadc@44e0d000 { + compatible = "ti,am3359-tscadc"; + reg = <0x44e0d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <16>; + ti,hwmods = "adc_tsc"; + status = "disabled"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + am335x_adc: adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h new file mode 100644 index 0000000000..e6b1e0a808 --- /dev/null +++ b/arch/arm/dts/dt-bindings/gpio/gpio.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +#endif diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h new file mode 100644 index 0000000000..2fbc804e1a --- /dev/null +++ b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h @@ -0,0 +1,42 @@ +/* + * This header provides constants specific to AM33XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H +#define _DT_BINDINGS_PINCTRL_AM33XX_H + +#include <dt-bindings/pinctrl/omap.h> + +/* am33xx specific mux bit defines */ +#undef PULL_ENA +#undef INPUT_EN + +#define PULL_DISABLE (1 << 3) +#define INPUT_EN (1 << 5) +#define SLEWCTRL_FAST (1 << 6) + +/* update macro depending on INPUT_EN and PULL_ENA */ +#undef PIN_OUTPUT +#undef PIN_OUTPUT_PULLUP +#undef PIN_OUTPUT_PULLDOWN +#undef PIN_INPUT +#undef PIN_INPUT_PULLUP +#undef PIN_INPUT_PULLDOWN + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +/* undef non-existing modes */ +#undef PIN_OFF_NONE +#undef PIN_OFF_OUTPUT_HIGH +#undef PIN_OFF_OUTPUT_LOW +#undef PIN_OFF_INPUT_PULLUP +#undef PIN_OFF_INPUT_PULLDOWN +#undef PIN_OFF_WAKEUPENABLE + +#endif + diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/arch/arm/dts/dt-bindings/pinctrl/omap.h new file mode 100644 index 0000000000..edbd250809 --- /dev/null +++ b/arch/arm/dts/dt-bindings/pinctrl/omap.h @@ -0,0 +1,55 @@ +/* + * This header provides constants for OMAP pinctrl bindings. + * + * Copyright (C) 2009 Nokia + * Copyright (C) 2009-2010 Texas Instruments + */ + +#ifndef _DT_BINDINGS_PINCTRL_OMAP_H +#define _DT_BINDINGS_PINCTRL_OMAP_H + +/* 34xx mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +/* 24xx/34xx mux bit defines */ +#define PULL_ENA (1 << 3) +#define PULL_UP (1 << 4) +#define ALTELECTRICALSEL (1 << 5) + +/* 34xx specific mux bit defines */ +#define INPUT_EN (1 << 8) +#define OFF_EN (1 << 9) +#define OFFOUT_EN (1 << 10) +#define OFFOUT_VAL (1 << 11) +#define OFF_PULL_EN (1 << 12) +#define OFF_PULL_UP (1 << 13) +#define WAKEUP_EN (1 << 14) + +/* 44xx specific mux bit defines */ +#define WAKEUP_EVENT (1 << 15) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + +#endif + diff --git a/arch/arm/dts/include/dt-bindings b/arch/arm/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/arm/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings
\ No newline at end of file diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index f52fcf14dd..59434e0a8f 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + #include "skeleton.dtsi" / { @@ -46,17 +49,17 @@ 0 143 0x04>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 18a8b24b71..4561c5f839 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + #include "skeleton.dtsi" / { @@ -49,14 +52,14 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 3805750581..a524f6eed4 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + #include "skeleton.dtsi" / { @@ -139,10 +142,18 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 64 65 66 67 87 119 121 >; + reg = <0x6000d000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; pinmux: pinmux@70000000 { diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index fee1c36efb..7be3791fc9 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + #include "skeleton.dtsi" / { @@ -47,17 +50,17 @@ clocks = <&tegra_car 34>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi new file mode 100644 index 0000000000..a63272422d --- /dev/null +++ b/arch/arm/dts/tps65217.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65217.pdf + */ + +&tps { + compatible = "ti,tps65217"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; + }; + }; +}; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 0e713952dc..25a9d4ce12 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o +obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o @@ -33,10 +34,6 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) -quiet_cmd_mkimage = MKIMAGE $@ -cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SYS_TEXT_BASE) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a77c4decc9..5a09107c5a 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -58,6 +58,7 @@ char *get_reset_cause(void) static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; static const unsigned char bank_lookup[] = {3, 2}; +/* these MMDC registers are common to the IMX53 and IMX6 */ struct esd_mmdc_regs { uint32_t ctl; uint32_t pdc; @@ -66,15 +67,6 @@ struct esd_mmdc_regs { uint32_t cfg1; uint32_t cfg2; uint32_t misc; - uint32_t scr; - uint32_t ref; - uint32_t rsvd1; - uint32_t rsvd2; - uint32_t rwd; - uint32_t or; - uint32_t mrr; - uint32_t cfg3lp; - uint32_t mr4; }; #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) @@ -83,6 +75,12 @@ struct esd_mmdc_regs { #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ unsigned imx_ddr_size(void) { struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 6e46ea8dcd..22cd11aa04 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -11,6 +11,9 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610) +#include <asm/arch/sys_proto.h> +#endif #include <asm/imx-common/iomux-v3.h> static void *base = (void *)IOMUXC_BASE_ADDR; @@ -54,12 +57,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif } +/* configures a list of pads within declared with IOMUX_PADS macro */ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count) { iomux_v3_cfg_t const *p = pad_list; + int stride; int i; - for (i = 0; i < count; i++) - imx_iomux_v3_setup_pad(*p++); +#if defined(CONFIG_MX6QDL) + stride = 2; + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + p += 1; +#else + stride = 1; +#endif + for (i = 0; i < count; i++) { + imx_iomux_v3_setup_pad(*p); + p += stride; + } } diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c index 2e694866e0..c10dd28f61 100644 --- a/arch/arm/imx-common/sata.c +++ b/arch/arm/imx-common/sata.c @@ -8,13 +8,18 @@ #include <asm/arch/iomux.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> int setup_sata(void) { struct iomuxc_base_regs *const iomuxc_regs = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + int ret; - int ret = enable_sata_clock(); + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + return 1; + + ret = enable_sata_clock(); if (ret) return ret; diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c new file mode 100644 index 0000000000..9a02a644bc --- /dev/null +++ b/arch/arm/imx-common/spl.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/spl.h> +#include <spl.h> + +#if defined(CONFIG_MX6) +/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */ +u32 spl_boot_device(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1); + + /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ + switch ((reg & 0x000000FF) >> 4) { + /* EIM: See 8.5.1, Table 8-9 */ + case 0x0: + /* BOOT_CFG1[3]: NOR/OneNAND Selection */ + if ((reg & 0x00000008) >> 3) + return BOOT_DEVICE_ONENAND; + else + return BOOT_DEVICE_NOR; + break; + /* SATA: See 8.5.4, Table 8-20 */ + case 0x2: + return BOOT_DEVICE_SATA; + /* Serial ROM: See 8.5.5.1, Table 8-22 */ + case 0x3: + /* BOOT_CFG4[2:0] */ + switch ((reg & 0x07000000) >> 24) { + case 0x0 ... 0x4: + return BOOT_DEVICE_SPI; + case 0x5 ... 0x7: + return BOOT_DEVICE_I2C; + } + break; + /* SD/eSD: 8.5.3, Table 8-15 */ + case 0x4: + case 0x5: + return BOOT_DEVICE_MMC1; + /* MMC/eMMC: 8.5.3 */ + case 0x6: + case 0x7: + return BOOT_DEVICE_MMC1; + /* NAND Flash: 8.5.2 */ + case 0x8 ... 0xf: + return BOOT_DEVICE_NAND; + } + return BOOT_DEVICE_NONE; +} +#endif + +#if defined(CONFIG_SPL_MMC_SUPPORT) +/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + /* for MMC return either RAW or FAT mode */ + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + break; + default: + puts("spl: ERROR: unsupported device\n"); + hang(); + } +} +#endif diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h deleted file mode 100644 index d8a87daa4a..0000000000 --- a/arch/arm/include/asm/arch-at91/spl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -enum { - BOOT_DEVICE_NONE, -#ifdef CONFIG_SYS_USE_MMC - BOOT_DEVICE_MMC1, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC2_2, -#elif CONFIG_SYS_USE_NANDFLASH - BOOT_DEVICE_NAND, -#elif CONFIG_SYS_USE_SERIALFLASH - BOOT_DEVICE_SPI, -#endif -}; - -#endif diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h deleted file mode 100644 index 7e19cfeed4..0000000000 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include <asm/arch/hardware.h> - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 98fe56e686..a4eb0bd89b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void) #if defined(CONFIG_SOC_DM365) #include <asm/arch/aintc_defs.h> #include <asm/arch/ddr2_defs.h> -#include <asm/arch/emif_defs.h> #include <asm/arch/gpio.h> #include <asm/arch/pll_defs.h> #include <asm/arch/psc_defs.h> diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h deleted file mode 100644 index dee1c6f814..0000000000 --- a/arch/arm/include/asm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#ifdef CONFIG_SYS_NAND_MASK_CLE -#undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE -#endif -#ifdef CONFIG_SYS_NAND_MASK_ALE -#undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h deleted file mode 100644 index 5afe0d4ba5..0000000000 --- a/arch/arm/include/asm/arch-davinci/spl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NAND 1 -#define BOOT_DEVICE_SPI 2 -#define BOOT_DEVICE_MMC1 3 -#define BOOT_DEVICE_MMC2 4 /* dummy */ -#define BOOT_DEVICE_MMC2_2 5 /* dummy */ - -#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 7ac2662f1f..50ce649d4c 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -9,13 +9,6 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE -#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000 -#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000 -#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000 - #define K2HK_PLL_CNTRL_BASE 0x02310000 #define CLOCK_BASE K2HK_PLL_CNTRL_BASE #define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 6c532ca870..ffdecbfcd6 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -22,32 +22,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int *dv_reg_p; -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - struct ddr3_phy_config { unsigned int pllcr; unsigned int pgcr1_mask; @@ -145,6 +119,10 @@ struct ddr3_emif_config { #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* AEMIF */ +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> #endif diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h deleted file mode 100644 index 58417dbc0b..0000000000 --- a/arch/arm/include/asm/arch-keystone/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * nand driver definitions to re-use davinci nand driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <linux/mtd/nand.h> - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -#endif diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h deleted file mode 100644 index d0efec21ab..0000000000 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_NOR 8 -#define BOOT_DEVICE_I2C 9 -#define BOOT_DEVICE_SPI 10 - -#endif diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h deleted file mode 100644 index 20c6cae938..0000000000 --- a/arch/arm/include/asm/arch-mx5/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_SPL_H__ -#define __ASM_ARCH_SPL_H__ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_NAND 1 - -#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h index d724f206f0..1f12695f67 100644 --- a/arch/arm/include/asm/arch-mx6/hab.h +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, void **, size_t *, hab_loader_callback_f_t); typedef void hapi_clock_init_t(void); -#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) -#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) -#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) -#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) -#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) -#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) +#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) +#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) + +#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8) +#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC) +#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8) +#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C) +#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0) #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 1f19727b58..a69a7530c3 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -217,6 +217,8 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_5 0x15 #define IRAM_SIZE 0x00040000 #define FEC_QUIRK_ENET_MAC diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f9ee0d9839..6a4a632199 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -39,7 +39,7 @@ #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) /* diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 43d377af35..d544d2e708 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -6,6 +6,7 @@ #ifndef __ASM_ARCH_MX6_DDR_H__ #define __ASM_ARCH_MX6_DDR_H__ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else @@ -15,6 +16,236 @@ #error "Please select cpu" #endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ +#else + +/* MMDC P0/P1 Registers */ +struct mmdc_p_regs { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdscr; + u32 mdref; + u32 res1[2]; + u32 mdrwd; + u32 mdor; + u32 res2[3]; + u32 mdasp; + u32 res3[240]; + u32 mapsr; + u32 res4[254]; + u32 mpzqhwctrl; + u32 res5[2]; + u32 mpwldectrl0; + u32 mpwldectrl1; + u32 res6; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; + u32 res7[4]; + u32 mpdgctrl0; + u32 mpdgctrl1; + u32 res8; + u32 mprddlctl; + u32 res9; + u32 mpwrdlctl; + u32 res10[25]; + u32 mpmur0; +}; + +/* + * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) + */ +#define MX6DQ_IOM_DDR_BASE 0x020e0500 +struct mx6dq_iomux_ddr_regs { + u32 res1[3]; + u32 dram_sdqs5; + u32 dram_dqm5; + u32 dram_dqm4; + u32 dram_sdqs4; + u32 dram_sdqs3; + u32 dram_dqm3; + u32 dram_sdqs2; + u32 dram_dqm2; + u32 res2[16]; + u32 dram_cas; + u32 res3[2]; + u32 dram_ras; + u32 dram_reset; + u32 res4[2]; + u32 dram_sdclk_0; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdclk_1; + u32 dram_sdcke1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 res5; + u32 dram_sdqs0; + u32 dram_dqm0; + u32 dram_sdqs1; + u32 dram_dqm1; + u32 dram_sdqs6; + u32 dram_dqm6; + u32 dram_sdqs7; + u32 dram_dqm7; +}; + +#define MX6DQ_IOM_GRP_BASE 0x020e0700 +struct mx6dq_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 res2; + u32 grp_ddrpke; + u32 res3[6]; + u32 grp_ddrmode; + u32 res4[3]; + u32 grp_b0ds; + u32 grp_b1ds; + u32 grp_ctlds; + u32 res5; + u32 grp_b2ds; + u32 grp_ddr_type; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 grp_b6ds; +}; + +#define MX6SDL_IOM_DDR_BASE 0x020e0400 +struct mx6sdl_iomux_ddr_regs { + u32 res1[25]; + u32 dram_cas; + u32 res2[2]; + u32 dram_dqm0; + u32 dram_dqm1; + u32 dram_dqm2; + u32 dram_dqm3; + u32 dram_dqm4; + u32 dram_dqm5; + u32 dram_dqm6; + u32 dram_dqm7; + u32 dram_ras; + u32 dram_reset; + u32 res3[2]; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdclk_0; + u32 dram_sdclk_1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 dram_sdqs0; + u32 dram_sdqs1; + u32 dram_sdqs2; + u32 dram_sdqs3; + u32 dram_sdqs4; + u32 dram_sdqs5; + u32 dram_sdqs6; + u32 dram_sdqs7; +}; + +#define MX6SDL_IOM_GRP_BASE 0x020e0700 +struct mx6sdl_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 grp_ddrpke; + u32 res2[2]; + u32 grp_ddrmode; + u32 grp_b0ds; + u32 res3; + u32 grp_ctlds; + u32 grp_b1ds; + u32 grp_ddr_type; + u32 grp_b2ds; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 res4; + u32 grp_b6ds; +}; + +/* Device Information: Varies per DDR3 part number and speed grade */ +struct mx6_ddr3_cfg { + u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ + u8 density; /* chip density (Gb) (1,2,4,8) */ + u8 width; /* bus width (bits) (4,8,16) */ + u8 banks; /* number of banks */ + u8 rowaddr; /* row address bits (11-16)*/ + u8 coladdr; /* col address bits (9-12) */ + u8 pagesz; /* page size (K) (1-2) */ + u16 trcd; /* tRCD=tRP=CL (ns*100) */ + u16 trcmin; /* tRC min (ns*100) */ + u16 trasmin; /* tRAS min (ns*100) */ + u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ +}; + +/* System Information: Varies per board design, layout, and term choices */ +struct mx6_ddr_sysinfo { + u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ + u8 cs_density; /* density per chip select (Gb) */ + u8 ncs; /* number chip selects used (1|2) */ + char cs1_mirror;/* enable address mirror (0|1) */ + char bi_on; /* Bank interleaving enable */ + u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ + u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ + u8 ralat; /* Read Additional Latency (0-7) */ + u8 walat; /* Write Additional Latency (0-3) */ + u8 mif3_mode; /* Command prediction working mode */ + u8 rst_to_cke; /* Time from SDE enable to CKE rise */ + u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ +}; + +/* + * Board specific calibration: + * This includes write leveling calibration values as well as DQS gating + * and read/write delays. These values are board/layout/device specific. + * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 + * (DOC-96412) to determine these values over a range of boards and + * temperatures. + */ +struct mx6_mmdc_calibration { + /* write leveling calibration */ + u32 p0_mpwldectrl0; + u32 p0_mpwldectrl1; + u32 p1_mpwldectrl0; + u32 p1_mpwldectrl1; + /* read DQS gating */ + u32 p0_mpdgctrl0; + u32 p0_mpdgctrl1; + u32 p1_mpdgctrl0; + u32 p1_mpdgctrl1; + /* read delay */ + u32 p0_mprddlctl; + u32 p1_mprddlctl; + /* write delay */ + u32 p0_mpwrdlctl; + u32 p1_mpwrdlctl; +}; + +/* configure iomux (pinctl/padctl) */ +void mx6dq_dram_iocfg(unsigned width, + const struct mx6dq_iomux_ddr_regs *, + const struct mx6dq_iomux_grp_regs *); +void mx6sdl_dram_iocfg(unsigned width, + const struct mx6sdl_iomux_ddr_regs *, + const struct mx6sdl_iomux_grp_regs *); + +/* configure mx6 mmdc registers */ +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, + const struct mx6_mmdc_calibration *, + const struct mx6_ddr3_cfg *); + +#endif /* CONFIG_SPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 38851a135c..42d30f5021 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -11,7 +11,9 @@ #include <asm/imx-common/regs-common.h> #include "../arch-imx/cpu.h" -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#define soc_rev() (get_cpu_rev() & 0xFF) +#define is_soc_rev(rev) (soc_rev() - rev) + u32 get_cpu_rev(void); /* returns MXC_CPU_ value */ diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h deleted file mode 100644 index ebb16fe1dd..0000000000 --- a/arch/arm/include/asm/arch-tegra114/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h deleted file mode 100644 index e2663954bf..0000000000 --- a/arch/arm/include/asm/arch-tegra124/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra20/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra30/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h deleted file mode 100644 index 9969a018e7..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm/arch-davinci/emif_defs.h> diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h index 2a7ca4e00c..d458e0bdf0 100644 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h @@ -155,4 +155,6 @@ int wdt_kick(void); #define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) #define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h deleted file mode 100644 index b298fba905..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * TNETV107X: NAND definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 1b22eeb5fc..34c07fe500 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -25,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } #ifdef __KERNEL__ -#include <asm/proc/system.h> +#include <asm/proc-armv/system.h> #define atomic_read(v) ((v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 879e20e024..597dafbf9d 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -17,7 +17,7 @@ #ifdef __KERNEL__ -#include <asm/proc/system.h> +#include <asm/proc-armv/system.h> #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index ff45618e45..e91d4acb18 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -177,4 +177,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_MX6QDL) +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD(def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#define IOMUX_PADS(x) MX6Q_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS(x) MX6DL_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif + #endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 6a1f05ac3e..9f35fd694b 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -437,4 +437,7 @@ out: #endif /* __mem_isa */ #endif /* __KERNEL__ */ + +#include <iotrace.h> + #endif /* __ASM_ARM_IO_H */ diff --git a/arch/arm/include/asm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h index 5bfab7fb90..532f2079e6 100644 --- a/arch/arm/include/asm/proc-armv/processor.h +++ b/arch/arm/include/asm/proc-armv/processor.h @@ -18,7 +18,7 @@ #ifndef __ASM_PROC_PROCESSOR_H #define __ASM_PROC_PROCESSOR_H -#include <asm/proc/domain.h> +#include <asm/proc-armv/domain.h> #define KERNEL_STACK_SIZE PAGE_SIZE diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 445d4495be..83481c6cda 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t; /* domain register */ #if 0 /* XXX###XXX */ #include <asm/arch/memory.h> #endif /* XXX###XXX */ -#include <asm/proc/processor.h> +#include <asm/proc-armv/processor.h> #include <asm/types.h> union debug_insn { diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 73c9087b50..a836f6cc60 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -11,7 +11,7 @@ /* options set using PTRACE_SETOPTIONS */ #define PTRACE_O_TRACESYSGOOD 0x00000001 -#include <asm/proc/ptrace.h> +#include <asm/proc-armv/ptrace.h> #ifndef __ASSEMBLY__ #define pc_pointer(v) \ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 90e5a9dde1..18a319de2f 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -7,9 +7,29 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \ + || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ + || defined(CONFIG_EXYNOS4210) /* Platform-specific defines */ #include <asm/arch/spl.h> +#else +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_NONE +}; +#endif + /* Linker symbols. */ extern char __bss_start[], __bss_end[]; diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/ti-common/davinci_nand.h index a3378aa30e..11407be144 100644 --- a/arch/arm/include/asm/arch-keystone/emif_defs.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -1,23 +1,45 @@ /* - * emif definitions to re-use davinci emif driver on Keystone2 + * NAND Flash Driver * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> + * Copyright (C) 2006-2014 Texas Instruments. * - * SPDX-License-Identifier: GPL-2.0+ + * Based on Linux DaVinci NAND driver by TI. */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ +#ifndef _DAVINCI_NAND_H_ +#define _DAVINCI_NAND_H_ + +#include <linux/mtd/nand.h> #include <asm/arch/hardware.h> +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 + +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + struct davinci_emif_regs { uint32_t ercsr; uint32_t awccr; uint32_t sdbcr; uint32_t sdrcr; - uint32_t abncr[4]; + union { + uint32_t abncr[4]; + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; uint32_t sdtimr; uint32_t ddrsr; uint32_t ddrphycr; @@ -56,18 +78,21 @@ struct davinci_emif_regs { #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) /* Chip Select setup */ #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) #define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) ((n) << 26) -#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) -#define DAVINCI_ABCR_WHOLD(n) ((n) << 17) -#define DAVINCI_ABCR_RSETUP(n) ((n) << 13) -#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) -#define DAVINCI_ABCR_RHOLD(n) ((n) << 4) -#define DAVINCI_ABCR_TA(n) ((n) << 2) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) #define DAVINCI_ABCR_ASIZE_16BIT 1 #define DAVINCI_ABCR_ASIZE_8BIT 0 +void davinci_nand_init(struct nand_chip *nand); + #endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h new file mode 100644 index 0000000000..4a311d4a2f --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -0,0 +1,39 @@ +/* + * AEMIF definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AEMIF_H_ +#define _AEMIF_H_ + +#define AEMIF_NUM_CS 4 +#define AEMIF_MODE_NOR 0 +#define AEMIF_MODE_NAND 1 +#define AEMIF_MODE_ONENAND 2 +#define AEMIF_PRESERVE -1 + +struct aemif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + AEMIF_WIDTH_8 = 0, + AEMIF_WIDTH_16 = 1, + AEMIF_WIDTH_32 = 2, + } width; +}; + +void aemif_init(int num_cs, struct aemif_config *config); + +#endif diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 9b473b5eab..76adaf3aa4 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -277,7 +277,7 @@ void board_init_f(ulong bootflag) gd->mon_len = (ulong)&__bss_end - (ulong)_start; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = __dtb_db_begin; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = &_end; |
