diff options
Diffstat (limited to 'arch/arm')
83 files changed, 2820 insertions, 1861 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 45f9dca5d5..3c5f987167 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -70,13 +70,6 @@ PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \ endif endif -ifdef CONFIG_SYS_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else -LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds -endif - # needed for relocation ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index d60afc9a33..8873fb719d 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -210,6 +210,8 @@ static char *get_reset_cause(void) return "WDOG"; case 0x0006: return "JTAG"; + case 0x0007: + return "ARM11P power gating"; default: return "unknown reset"; } diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds deleted file mode 100644 index d1e28518ad..0000000000 --- a/arch/arm/cpu/arm1136/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - * - * Copyright (C) 2005-2007 Samsung Electronics - * Kyungin Park <kyugnmin.park@samsung.com> - * - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds deleted file mode 100644 index 27d66380bd..0000000000 --- a/arch/arm/cpu/arm1176/u-boot.lds +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm720t/u-boot.lds b/arch/arm/cpu/arm720t/u-boot.lds deleted file mode 100644 index 9370fadcf5..0000000000 --- a/arch/arm/cpu/arm720t/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 9571870b11..d8668bec5e 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -35,19 +35,7 @@ #include <asm/io.h> #include <asm/arch/s3c24x0_cpu.h> -int timer_load_val = 0; -static ulong timer_clk; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - - return readl(&timers->tcnto4) & 0xffff; -} - -static ulong timestamp; -static ulong lastdec; +DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { @@ -57,27 +45,27 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ writel(0x0f00, &timers->tcfg0); - if (timer_load_val == 0) { + if (gd->tbu == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 * (default) and prescaler = 16. Should be 10390 * @33.25MHz and 15625 @ 50 MHz */ - timer_load_val = get_PCLK() / (2 * 16 * 100); - timer_clk = get_PCLK() / (2 * 16); + gd->tbu = get_PCLK() / (2 * 16 * 100); + gd->timer_rate_hz = get_PCLK() / (2 * 16); } /* load value for 10 ms timeout */ - lastdec = timer_load_val; - writel(timer_load_val, &timers->tcntb4); + writel(gd->tbu, &timers->tcntb4); /* auto load, manual update of timer 4 */ tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; writel(tmr, &timers->tcon); /* auto load, start timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; writel(tmr, &timers->tcon); - timestamp = 0; + gd->lastinc = 0; + gd->tbl = 0; - return (0); + return 0; } /* @@ -94,7 +82,7 @@ void __udelay (unsigned long usec) ulong start = get_ticks(); tmo = usec / 1000; - tmo *= (timer_load_val * 100); + tmo *= (gd->tbu * 100); tmo /= 1000; while ((ulong) (get_ticks() - start) < tmo) @@ -105,7 +93,7 @@ ulong get_timer_masked(void) { ulong tmr = get_ticks(); - return tmr / (timer_clk / CONFIG_SYS_HZ); + return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ); } void udelay_masked(unsigned long usec) @@ -116,10 +104,10 @@ void udelay_masked(unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= (timer_load_val * 100); + tmo *= (gd->tbu * 100); tmo /= 1000; } else { - tmo = usec * (timer_load_val * 100); + tmo = usec * (gd->tbu * 100); tmo /= (1000 * 1000); } @@ -137,18 +125,19 @@ void udelay_masked(unsigned long usec) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER(); + struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); + ulong now = readl(&timers->tcnto4) & 0xffff; - if (lastdec >= now) { + if (gd->lastinc >= now) { /* normal mode */ - timestamp += lastdec - now; + gd->tbl += gd->lastinc - now; } else { /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; + gd->tbl += gd->lastinc + gd->tbu - now; } - lastdec = now; + gd->lastinc = now; - return timestamp; + return gd->tbl; } /* @@ -157,20 +146,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - -#if defined(CONFIG_SMDK2400) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SBC2410X) || \ - defined(CONFIG_SMDK2410) || \ - defined(CONFIG_S3C2440) || \ - defined(CONFIG_VCMA9) - tbclk = CONFIG_SYS_HZ; -#else -# error "tbclk not configured" -#endif - - return tbclk; + return CONFIG_SYS_HZ; } /* diff --git a/arch/arm/cpu/arm920t/u-boot.lds b/arch/arm/cpu/arm920t/u-boot.lds deleted file mode 100644 index 17ba60423b..0000000000 --- a/arch/arm/cpu/arm920t/u-boot.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm925t/u-boot.lds b/arch/arm/cpu/arm925t/u-boot.lds deleted file mode 100644 index 64e76f55e3..0000000000 --- a/arch/arm/cpu/arm925t/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, <wg@denx.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 504f604684..5b23e3a71b 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -23,29 +23,71 @@ #include <common.h> #ifndef CONFIG_SYS_DCACHE_OFF -static inline void dcache_noop(void) + +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + +void invalidate_dcache_all(void) { - if (dcache_status()) { - puts("WARNING: cache operations are not implemented!\n" - "WARNING: disabling D-Cache now, you can re-enable it" - "later with 'dcache on' command\n"); - dcache_disable(); - } + asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); } -void invalidate_dcache_all(void) +void flush_dcache_all(void) { - dcache_noop(); + asm volatile( + "0:" + "mrc p15, 0, r15, c7, c14, 3\n" + "bne 0b\n" + "mcr p15, 0, %0, c7, c10, 4\n" + ::"r"(0):"memory" + ); +} + +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; } void invalidate_dcache_range(unsigned long start, unsigned long stop) { - dcache_noop(); + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } } void flush_dcache_range(unsigned long start, unsigned long stop) { - dcache_noop(); + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } + + asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); } #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -64,7 +106,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { } -void flush_cache(unsigned long start, unsigned long size) +void flush_cache(unsigned long start, unsigned long size) { } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c index f698506007..0439f9c0ea 100644 --- a/arch/arm/cpu/arm926ejs/mx28/clock.c +++ b/arch/arm/cpu/arm926ejs/mx28/clock.c @@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkctrl, clkseq, clkfrac; - uint32_t frac, div; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); @@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void) } /* REF Path */ - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); - frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t frac, div; - uint32_t clkctrl, clkseq, clkfrac; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); @@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void) return XTAL_FREQ_MHZ / div; } - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); - /* REF Path */ - frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >> - CLKCTRL_FRAC0_EMIFRAC_OFFSET; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t frac, div; - uint32_t clkctrl, clkseq, clkfrac; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); @@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void) return XTAL_FREQ_MHZ / div; } - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1); - /* REF Path */ - frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >> - CLKCTRL_FRAC1_GPMIFRAC_OFFSET; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_GPMI_DIV_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t div; + int io_reg; if (freq == 0) return; - if (io > MXC_IOCLK1) + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) return; div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; @@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) if (div > 35) div = 35; - if (io == MXC_IOCLK0) { - writel(CLKCTRL_FRAC0_CLKGATEIO0, - &clkctrl_regs->hw_clkctrl_frac0_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_IO0FRAC_MASK, - div << CLKCTRL_FRAC0_IO0FRAC_OFFSET); - writel(CLKCTRL_FRAC0_CLKGATEIO0, - &clkctrl_regs->hw_clkctrl_frac0_clr); - } else { - writel(CLKCTRL_FRAC0_CLKGATEIO1, - &clkctrl_regs->hw_clkctrl_frac0_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_IO1FRAC_MASK, - div << CLKCTRL_FRAC0_IO1FRAC_OFFSET); - writel(CLKCTRL_FRAC0_CLKGATEIO1, - &clkctrl_regs->hw_clkctrl_frac0_clr); - } + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); } /* @@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) { struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t tmp, ret; + uint8_t ret; + int io_reg; - if (io > MXC_IOCLK1) + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) return 0; - tmp = readl(&clkctrl_regs->hw_clkctrl_frac0); + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - if (io == MXC_IOCLK0) - ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >> - CLKCTRL_FRAC0_IO0FRAC_OFFSET; - else - ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >> - CLKCTRL_FRAC0_IO1FRAC_OFFSET; + ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & + CLKCTRL_FRAC_FRAC_MASK; return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; } @@ -223,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register)); + (ssp * sizeof(struct mx28_register_32)); clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) @@ -272,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) return XTAL_FREQ_KHZ; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register)); + (ssp * sizeof(struct mx28_register_32)); tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c index 9ea411f22a..12916b6d60 100644 --- a/arch/arm/cpu/arm926ejs/mx28/iomux.c +++ b/arch/arm/cpu/arm926ejs/mx28/iomux.c @@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) { u32 reg, ofs, bp, bm; void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register *mxs_reg; + struct mx28_register_32 *mxs_reg; /* muxsel */ ofs = 0x100; @@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) /* vol */ if (PAD_VOL_VALID(pad)) { bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); if (PAD_VOL(pad)) writel(1 << bp, &mxs_reg->reg_set); else @@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs = PULL_OFFSET; ofs += PAD_BANK(pad) * 0x10; bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); if (PAD_PULL(pad)) writel(1 << bp, &mxs_reg->reg_set); else diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index 683777f50c..cf6d4e9bd4 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -63,7 +63,17 @@ void reset_cpu(ulong ignored) ; } -int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == mask) @@ -74,7 +84,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) +int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == 0) @@ -85,7 +95,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_reset_block(struct mx28_register *reg) +int mx28_reset_block(struct mx28_register_32 *reg) { /* Clear SFTRST */ writel(MX28_BLOCK_SFTRST, ®->reg_clr); @@ -261,14 +271,14 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -#define HW_DIGCTRL_SCRATCH0 0x8001c280 -#define HW_DIGCTRL_SCRATCH1 0x8001c290 int mx28_dram_init(void) { + struct mx28_digctl_regs *digctl_regs = + (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz[2]; - sz[0] = readl(HW_DIGCTRL_SCRATCH0); - sz[1] = readl(HW_DIGCTRL_SCRATCH1); + sz[0] = readl(&digctl_regs->hw_digctl_scratch0); + sz[1] = readl(&digctl_regs->hw_digctl_scratch1); if (sz[0] != sz[1]) { printf("MX28:\n" diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 00493b8bf9..911bbefc06 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -32,44 +32,54 @@ #include "mx28_init.h" uint32_t dram_vals[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, - 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, - 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, - 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, - 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, - 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, - 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, - 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, - 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, - 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, - 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, - 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, + 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000F02, + 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, + 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, + 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, + 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, + 0x00000004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, + 0x00040004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010001 }; void init_m28_200mhz_ddr2(void) @@ -86,22 +96,20 @@ void mx28_mem_init_clock(void) (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Gate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_set); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - /* EMI = 205MHz */ - writel(CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_set); - writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) & - CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_clr); + /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ + writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); /* Ungate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_clr); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); early_delay(11000); + /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), &clkctrl_regs->hw_clkctrl_emi); @@ -118,10 +126,10 @@ void mx28_mem_setup_cpu_and_hbus(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - /* CPU = 454MHz and ungate CPU clock */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU, - 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET); + /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz + * and ungate CPU clock */ + writeb(19 & CLKCTRL_FRAC_FRAC_MASK, + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); /* Set CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, @@ -165,26 +173,22 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -#define HW_DIGCTRL_SCRATCH0 0x8001c280 -#define HW_DIGCTRL_SCRATCH1 0x8001c290 -void data_abort_memdetect_handler(void) __attribute__((naked)); -void data_abort_memdetect_handler(void) -{ - asm volatile("subs pc, r14, #4"); -} - void mx28_mem_get_size(void) { + struct mx28_digctl_regs *digctl_regs = + (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; + /* The following is "subs pc, r14, #4", used as return from DABT. */ + const uint32_t data_abort_memdetect_handler = 0xe25ef004; /* Replace the DABT handler. */ da = vt[4]; - vt[4] = (uint32_t)&data_abort_memdetect_handler; + vt[4] = data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - writel(sz, HW_DIGCTRL_SCRATCH0); - writel(sz, HW_DIGCTRL_SCRATCH1); + writel(sz, &digctl_regs->hw_digctl_scratch0); + writel(sz, &digctl_regs->hw_digctl_scratch1); /* Restore the old DABT handler. */ vt[4] = da; diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 271da8dd76..aa4117d3a2 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -729,7 +729,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -766,7 +766,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -826,7 +826,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -863,7 +863,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c index 1cd0e1f12a..bc2e4d506d 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/timer.c +++ b/arch/arm/cpu/arm926ejs/nomadik/timer.c @@ -75,3 +75,13 @@ void __udelay(unsigned long usec) while ((signed)(end - READ_TIMER()) > 0) ; } + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds deleted file mode 100644 index 1480e0c960..0000000000 --- a/arch/arm/cpu/arm926ejs/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm926ejs/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm946es/u-boot.lds b/arch/arm/cpu/arm946es/u-boot.lds deleted file mode 100644 index ff938e44d8..0000000000 --- a/arch/arm/cpu/arm946es/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm946es/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm_intcm/u-boot.lds b/arch/arm/cpu/arm_intcm/u-boot.lds deleted file mode 100644 index f4a146c9a8..0000000000 --- a/arch/arm/cpu/arm_intcm/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm_intcm/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index f97fa3d448..6b2addca11 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,9 +27,7 @@ LIB = $(obj)lib$(CPU).o START := start.o -ifndef CONFIG_SPL_BUILD COBJS += cache_v7.o -endif COBJS += cpu.o COBJS += syslib.o diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 662c4962e6..c6fa8ef136 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -52,7 +52,9 @@ int cleanup_before_linux(void) * * we turn off caches etc ... */ +#ifndef CONFIG_SPL_BUILD disable_interrupts(); +#endif /* * Turn off I-cache and invalidate it diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile index 76faeb0fe1..917c3a36ba 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/cpu/armv7/highbank/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := timer.o +COBJS := timer.o bootcount.o SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/highbank/bootcount.c b/arch/arm/cpu/armv7/highbank/bootcount.c new file mode 100644 index 0000000000..9ca06567a8 --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/bootcount.c @@ -0,0 +1,36 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> + +#ifdef CONFIG_BOOTCOUNT_LIMIT +void bootcount_store(ulong a) +{ + writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR); +} + +ulong bootcount_load(void) +{ + u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR); + + if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return tmp & 0x0000ffff; +} +#endif diff --git a/arch/arm/cpu/armv7/highbank/config.mk b/arch/arm/cpu/armv7/highbank/config.mk new file mode 100644 index 0000000000..935a147c59 --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/config.mk @@ -0,0 +1 @@ +PLATFORM_CPPFLAGS += -march=armv7-a diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d8a02888a2..0f985e298b 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -66,10 +66,10 @@ static inline unsigned long long time_to_tick(unsigned long long time) static inline unsigned long long us_to_tick(unsigned long long us) { - unsigned long long tick = us << 16; + unsigned long long tick = us * 1000; tick += NS_PER_TICK - 1; do_div(tick, NS_PER_TICK); - return tick >> 16; + return tick; } unsigned long long get_ticks(void) @@ -121,3 +121,8 @@ ulong get_timer_masked(void) { return tick_to_time(get_ticks()); } + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 1e30ae501a..3d58d8ae91 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -44,6 +44,7 @@ static char *get_reset_cause(void) switch (cause) { case 0x00001: + case 0x00011: return "POR"; case 0x00004: return "CSU"; @@ -63,13 +64,33 @@ static char *get_reset_cause(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +static char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case 0x63: + return "6Q"; /* Quad-core version of the mx6 */ + case 0x61: + return "6DS"; /* Dual/Solo version of the mx6 */ + case 0x60: + return "6SL"; /* Solo-Lite version of the mx6 */ + case 0x51: + return "51"; + case 0x53: + return "53"; + default: + return "unknown"; + } +} + int print_cpuinfo(void) { u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", - (cpurev & 0xFF000) >> 12, + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 01f6d759b9..74ab753a4a 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -284,10 +284,24 @@ ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] #elif defined(CONFIG_MX53) + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00808145 + orr r1, r1, #(2 << 10) + orr r1, r1, #(0 << 16) + orr r1, r1, #(1 << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, =0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + /* Change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] ldr r1, [r0, #CLKCTL_CSCDR1] - orr r1, r1, #0x3f - eor r1, r1, #0x3f - orr r1, r1, #0x21 + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] #endif /* make sure divider effective */ diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124807..ef98563ff7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -36,6 +36,19 @@ enum pll_clocks { struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; +void enable_usboh3_clk(unsigned char enable) +{ + u32 reg; + + reg = __raw_readl(&imx_ccm->CCGR6); + if (enable) + reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET; + else + reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET); + __raw_writel(reg, &imx_ccm->CCGR6); + +} + static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div; diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ac74b5945..a81e2bc01a 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,7 +32,13 @@ u32 get_cpu_rev(void) { - int system_rev = 0x61000 | CHIP_REV_1_0; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg = readl(&anatop->digprog); + + /* Read mx6 variant: quad, dual or solo */ + int system_rev = (reg >> 4) & 0xFF000; + /* Read mx6 silicon revision */ + system_rev |= (reg & 0xFF) + 0x10; return system_rev; } diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 3f7a0b25f0..447fcd5eff 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -52,6 +52,9 @@ endif ifdef CONFIG_SPL_MMC_SUPPORT COBJS += spl_mmc.o endif +ifdef CONFIG_SPL_YMODEM_SUPPORT +COBJS += spl_ymodem.o +endif endif ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 4cfe11991a..4e7456992f 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -320,11 +320,9 @@ static void setup_dplls(void) #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL static void setup_non_essential_dplls(void) { - u32 sys_clk_khz, abe_ref_clk; + u32 abe_ref_clk; const struct dpll_params *params; - sys_clk_khz = get_sys_clk_freq() / 1000; - /* IVA */ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 9c1f7e3eda..0f2e0a2d27 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -65,6 +65,25 @@ void board_init_f(ulong dummy) relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); } +/* + * Default function to determine if u-boot or the OS should + * be started. This implementation always returns 1. + * + * Please implement your own board specific funcion to do this. + * + * RETURN + * 0 to not start u-boot + * positive if u-boot should start + */ +#ifdef CONFIG_SPL_OS_BOOT +__weak int spl_start_uboot(void) +{ + printf("SPL: Please implement spl_start_uboot() for your board\n"); + printf("SPL: Direct Linux boot not active!\n"); + return 1; +} +#endif + void spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -82,7 +101,7 @@ void spl_parse_image_header(const struct image_header *header) /* Signature not found - assume u-boot.bin */ printf("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - puts("Assuming u-boot.bin ..\n"); + debug("Assuming u-boot.bin ..\n"); /* Let's assume U-Boot will not be more than 200 KB */ spl_image.size = 200 * 1024; spl_image.entry_point = CONFIG_SYS_TEXT_BASE; @@ -92,9 +111,27 @@ void spl_parse_image_header(const struct image_header *header) } } -static void jump_to_image_no_args(void) +/* + * This function jumps to an image with argument. Normally an FDT or ATAGS + * image. + * arg: Pointer to paramter image in RAM + */ +#ifdef CONFIG_SPL_OS_BOOT +static void __noreturn jump_to_image_linux(void *arg) +{ + debug("Entering kernel arg pointer: 0x%p\n", arg); + typedef void (*image_entry_arg_t)(int, int, void *) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t) spl_image.entry_point; + cleanup_before_linux(); + image_entry(0, CONFIG_MACH_TYPE, arg); +} +#endif + +static void __noreturn jump_to_image_no_args(void) { - typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn)); + typedef void __noreturn (*image_entry_noargs_t)(u32 *); image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image.entry_point; @@ -107,7 +144,6 @@ static void jump_to_image_no_args(void) image_entry((u32 *)boot_params_ptr_addr); } -void jump_to_image_no_args(void) __attribute__ ((noreturn)); void board_init_r(gd_t *id, ulong dummy) { u32 boot_device; @@ -134,6 +170,11 @@ void board_init_r(gd_t *id, ulong dummy) spl_nand_load_image(); break; #endif +#ifdef CONFIG_SPL_YMODEM_SUPPORT + case BOOT_DEVICE_UART: + spl_ymodem_load_image(); + break; +#endif default: printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); hang(); @@ -145,6 +186,13 @@ void board_init_r(gd_t *id, ulong dummy) debug("Jumping to U-Boot\n"); jump_to_image_no_args(); break; +#ifdef CONFIG_SPL_OS_BOOT + case IH_OS_LINUX: + debug("Jumping to Linux\n"); + spl_board_prepare_for_linux(); + jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR); + break; +#endif default: puts("Unsupported OS image.. Jumping nevertheless..\n"); jump_to_image_no_args(); diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c index 38d06b1ea8..1295e88752 100644 --- a/arch/arm/cpu/armv7/omap-common/spl_nand.c +++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c @@ -24,14 +24,17 @@ #include <asm/u-boot.h> #include <asm/utils.h> #include <asm/arch/sys_proto.h> +#include <asm/io.h> #include <nand.h> #include <version.h> #include <asm/omap_common.h> - void spl_nand_load_image(void) { struct image_header *header; + int *src __attribute__((unused)); + int *dst __attribute__((unused)); + switch (omap_boot_mode()) { case NAND_MODE_HW_ECC: debug("spl: nand - using hw ecc\n"); @@ -45,19 +48,57 @@ void spl_nand_load_image(void) /*use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); +#ifdef CONFIG_SPL_OS_BOOT + if (!spl_start_uboot()) { + /* + * load parameter image + * load to temp position since nand_spl_load_image reads + * a whole block which is typically larger than + * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite + * following sections like BSS + */ + nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS, + CONFIG_CMD_SPL_WRITE_SIZE, + (void *)CONFIG_SYS_TEXT_BASE); + /* copy to destintion */ + for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR, + src = (int *)CONFIG_SYS_TEXT_BASE; + src < (int *)(CONFIG_SYS_TEXT_BASE + + CONFIG_CMD_SPL_WRITE_SIZE); + src++, dst++) { + writel(readl(src), dst); + } + /* load linux */ + nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + if (header->ih_os == IH_OS_LINUX) { + /* happy - was a linux */ + nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, + spl_image.size, (void *)spl_image.load_addr); + nand_deselect(); + return; + } else { + printf("The Expected Linux image was not" + "found. Please check your NAND" + "configuration.\n"); + printf("Trying to start u-boot now...\n"); + } + } +#endif #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, - (void *)image_load_addr); + (void *)spl_image.load_addr); #ifdef CONFIG_ENV_OFFSET_REDUND nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, - (void *)image_load_addr); + (void *)spl_image.load_addr); #endif #endif /* Load u-boot */ diff --git a/arch/arm/cpu/armv7/omap-common/spl_ymodem.c b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c new file mode 100644 index 0000000000..47663f7edf --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Matt Porter <mporter@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <xyzModem.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> + +#define BUF_SIZE 1024 + +static int getcymodem(void) { + if (tstc()) + return (getc()); + return -1; +} + +void spl_ymodem_load_image(void) +{ + int size = 0; + int err; + int res; + int ret; + connection_info_t info; + char buf[BUF_SIZE]; + ulong store_addr = ~0; + ulong addr = 0; + + info.mode = xyzModem_ymodem; + ret = xyzModem_stream_open(&info, &err); + + if (!ret) { + while ((res = + xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { + if (addr == 0) + spl_parse_image_header((struct image_header *)buf); + store_addr = addr + spl_image.load_addr; + size += res; + addr += res; + memcpy((char *)(store_addr), buf, res); + } + } else { + printf("spl: ymodem err - %s\n", xyzModem_error(err)); + hang(); + } + + xyzModem_stream_close(&err); + xyzModem_stream_terminate(false, &getcymodem); + + printf("Loaded %d bytes\n", size); +} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index aabc651413..1fee574364 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -92,7 +92,9 @@ u32 omap_boot_device(void) void spl_board_init(void) { +#ifdef CONFIG_SPL_I2C_SUPPORT i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 91f42c0e2c..f6d9b97bb4 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -180,7 +180,7 @@ void do_sdrc_init(u32 cs, u32 early) write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr); make_cs1_contiguous(); - write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, rfr_ctrl, mr); #endif diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f668a818fb..e9ac6c9a71 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 4c44bb3637..b749821e5a 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; /* Remove the clamps on the CPU I/O signals */ @@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void) static void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; @@ -157,7 +157,7 @@ static void powerup_cpu(void) static void enable_cpu_power_rail(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_cntrl); @@ -277,7 +277,7 @@ void enable_scu(void) void init_pmc_scratch(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; int i; /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ @@ -298,11 +298,11 @@ void tegra2_start(void) writel(0xC0, &pmt->pmt_cfg_ctl); /* - * If we are ARM7 - give it a different stack. We are about to - * start up the A9 which will want to use this one. - */ - asm volatile("ldr sp, =%c0\n" - : : "i"(AVP_EARLY_BOOT_STACK_LIMIT)); + * If we are ARM7 - give it a different stack. We are about to + * start up the A9 which will want to use this one. + */ + asm volatile("mov sp, %0\n" + : : "r"(AVP_EARLY_BOOT_STACK_LIMIT)); start_cpu((u32)_start); halt_avp(); diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 349d50e1ac..a797e6fc30 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -47,7 +47,7 @@ enum { unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_scratch20); diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 11d2346d83..39376ab86e 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -28,6 +28,7 @@ #include <asm/arch/tegra2.h> #include <common.h> #include <div64.h> +#include <fdtdec.h> /* * This is our record of the current clock rate of each clock. We don't @@ -67,6 +68,7 @@ enum clock_type_id { CLOCK_TYPE_MCPT, CLOCK_TYPE_PCM, CLOCK_TYPE_PCMT, + CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */ CLOCK_TYPE_PCXTS, CLOCK_TYPE_PDCT, @@ -98,6 +100,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = { { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) }, { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) }, { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) }, { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) }, }; @@ -211,8 +214,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { /* 0x08 */ TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), + TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), @@ -246,7 +249,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), /* 0x28 */ @@ -256,7 +259,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), /* 0x30 */ @@ -518,14 +521,16 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) * Given the parent's rate and the required rate for the children, this works * out the peripheral clock divider to use, in 7.1 binary format. * + * @param divider_bits number of divider bits (8 or 16) * @param parent_rate clock rate of parent clock in Hz * @param rate required clock rate for this clock * @return divider which should be used */ -static int clk_div7_1_get_divider(unsigned long parent_rate, - unsigned long rate) +static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, + unsigned long rate) { u64 divider = parent_rate * 2; + unsigned max_divider = 1 << divider_bits; divider += rate - 1; do_div(divider, rate); @@ -533,7 +538,7 @@ static int clk_div7_1_get_divider(unsigned long parent_rate, if ((s64)divider - 2 < 0) return 0; - if ((s64)divider - 2 > 255) + if ((s64)divider - 2 >= max_divider) return -1; return divider - 2; @@ -571,6 +576,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * required child clock rate. This function assumes that a second-stage * divisor is available which can divide by powers of 2 from 1 to 256. * + * @param divider_bits number of divider bits (8 or 16) * @param parent_rate clock rate of parent clock in Hz * @param rate required clock rate for this clock * @param extra_div value for the second-stage divisor (not set if this @@ -578,8 +584,8 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * @return divider which should be used, or -1 if nothing is valid * */ -static int find_best_divider(unsigned long parent_rate, unsigned long rate, - int *extra_div) +static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, + unsigned long rate, int *extra_div) { int shift; int best_divider = -1; @@ -588,7 +594,8 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate, /* try dividers from 1 to 256 and find closest match */ for (shift = 0; shift <= 8 && best_error > 0; shift++) { unsigned divided_parent = parent_rate >> shift; - int divider = clk_div7_1_get_divider(divided_parent, rate); + int divider = clk_get_divider(divider_bits, divided_parent, + rate); unsigned effective_rate = get_rate_from_divider(divided_parent, divider); int error = rate - effective_rate; @@ -614,10 +621,11 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate, * @param periph_id peripheral to start * @param source PLL id of required parent clock * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) * @return mux value (0-4, or -1 if not found) */ static int get_periph_clock_source(enum periph_id periph_id, - enum clock_id parent, int *mux_bits) + enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; enum periphc_internal_id internal_id; @@ -631,11 +639,18 @@ static int get_periph_clock_source(enum periph_id periph_id, type = clock_periph_type[internal_id]; assert(clock_type_id_isvalid(type)); - /* Special case here for the clock with a 4-bit source mux */ + /* + * Special cases here for the clock with a 4-bit source mux and I2C + * with its 16-bit divisor + */ if (type == CLOCK_TYPE_PCXTS) *mux_bits = 4; else *mux_bits = 2; + if (type == CLOCK_TYPE_PCMT16) + *divider_bits = 16; + else + *divider_bits = 8; for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) @@ -661,24 +676,22 @@ static int get_periph_clock_source(enum periph_id periph_id, * Adjust peripheral PLL to use the given divider and source. * * @param periph_id peripheral to adjust - * @param parent Required parent clock (for source mux) - * @param divider Required divider in 7.1 format + * @param source Source number (0-3 or 0-7) + * @param mux_bits Number of mux bits (2 or 4) + * @param divider Required divider in 7.1 or 15.1 format * @return 0 if ok, -1 on error (requesting a parent clock which is not valid * for this peripheral) */ -static int adjust_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned divider) +static int adjust_periph_pll(enum periph_id periph_id, int source, + int mux_bits, unsigned divider) { u32 *reg = get_periph_source_reg(periph_id); - unsigned source; - int mux_bits; clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, divider << OUT_CLK_DIVISOR_SHIFT); udelay(1); /* work out the source clock and set it */ - source = get_periph_clock_source(periph_id, parent, &mux_bits); if (source < 0) return -1; if (mux_bits == 4) { @@ -696,14 +709,21 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div) { unsigned effective_rate; + int mux_bits, divider_bits, source; int divider; + /* work out the source clock and set it */ + source = get_periph_clock_source(periph_id, parent, &mux_bits, + ÷r_bits); + if (extra_div) - divider = find_best_divider(pll_rate[parent], rate, extra_div); + divider = find_best_divider(divider_bits, pll_rate[parent], + rate, extra_div); else - divider = clk_div7_1_get_divider(pll_rate[parent], rate); + divider = clk_get_divider(divider_bits, pll_rate[parent], + rate); assert(divider >= 0); - if (adjust_periph_pll(periph_id, parent, divider)) + if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, get_periph_source_reg(periph_id), @@ -918,6 +938,63 @@ void clock_ll_start_uart(enum periph_id periph_id) reset_set_enable(periph_id, 0); } +#ifdef CONFIG_OF_CONTROL +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra2 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +static enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > 95) + return PERIPH_ID_NONE; + + switch (clk_id) { + case 1: + case 2: + case 7: + case 10: + case 20: + case 30: + case 35: + case 49: + case 56: + case 74: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 91: + case 95: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} + +int clock_decode_periph_id(const void *blob, int node) +{ + enum periph_id id; + u32 cell[2]; + int err; + + err = fdtdec_get_int_array(blob, node, "clocks", cell, + ARRAY_SIZE(cell)); + if (err) + return -1; + id = clk_id_to_periph_id(cell[1]); + assert(clock_periph_id_isvalid(id)); + return id; +} +#endif /* CONFIG_OF_CONTROL */ + int clock_verify(void) { struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 2303dba079..fe9ef5b763 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t endif USE_PRIVATE_LIBGCC = yes + +CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c new file mode 100644 index 0000000000..c80de7f6a3 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/uart.h> +#include <asm/arch/usb.h> +#include <libfdt.h> +#include <fdtdec.h> + +enum { + USB_PORTS_MAX = 4, /* Maximum ports we allow */ +}; + +/* Parameters we need for USB */ +enum { + PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ + PARAM_DIVM, /* PLL INPUT DIVIDER */ + PARAM_DIVP, /* POST DIVIDER (2^N) */ + PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ + PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ + PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ + PARAM_STABLE_COUNT, /* PLL-U STABLE count */ + PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ + PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ + PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ + PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ + + PARAM_COUNT +}; + +/* Possible port types (dual role mode) */ +enum dr_mode { + DR_MODE_NONE = 0, + DR_MODE_HOST, /* supports host operation */ + DR_MODE_DEVICE, /* supports device operation */ + DR_MODE_OTG, /* supports both */ +}; + +/* Information about a USB port */ +struct fdt_usb { + struct usb_ctlr *reg; /* address of registers in physical memory */ + unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ + unsigned enabled:1; /* 1 to enable, 0 to disable */ + unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + enum dr_mode dr_mode; /* dual role mode */ + enum periph_id periph_id;/* peripheral id */ + struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ +}; + +static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ +static unsigned port_count; /* Number of available ports */ +static int port_current; /* Current port (-1 = none) */ + +/* + * This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * ---------------------------------------------------------------------- + * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) + * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) + * Filter frequency (MHz) 1 4.8 6 2 + * CPCON 1100b 0011b 1100b 1100b + * LFCON0 0 0 0 0 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * --------------------------------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) + * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) + * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) + * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * <n> ms = <n> *1000 / (1/19.2MHz) / 4 + * + * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + */ +static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +/* UTMIP Idle Wait Delay */ +static const u8 utmip_idle_wait_delay = 17; + +/* UTMIP Elastic limit */ +static const u8 utmip_elastic_limit = 16; + +/* UTMIP High Speed Sync Start Delay */ +static const u8 utmip_hs_sync_start_delay = 9; + +/* Put the port into host mode (this only works for OTG ports) */ +static void set_host_mode(struct fdt_usb *config) +{ + if (config->dr_mode == DR_MODE_OTG) { + /* Check whether remote host from USB1 is driving VBus */ + if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, 1); + debug("set_host_mode: GPIO %d high\n", + config->vbus_gpio.gpio); + } + } +} + +void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +{ + /* Reset the USB controller with 2us delay */ + reset_periph(config->periph_id, 2); + + /* + * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under + * base address + */ + if (config->has_legacy_mode) + setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); + + /* Put UTMIP1/3 in reset */ + setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Enable the UTMIP PHY */ + if (config->utmi) + setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); + + /* + * TODO: where do we take the USB1 out of reset? The old code would + * take USB3 out of reset, but not USB1. This code doesn't do either. + */ +} + +/* set up the USB controller with the parameters provided */ +static int init_usb_controller(struct fdt_usb *config, + struct usb_ctlr *usbctlr, const u32 timing[]) +{ + u32 val; + int loop_count; + + clock_enable(config->periph_id); + + /* Reset the usb controller */ + usbf_reset_controller(config, usbctlr); + + /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ + clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Follow the crystal clock disable by >100ns delay */ + udelay(1); + + /* + * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP + * mux must be switched to actually use a_sess_vld threshold. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, + VBUS_SENSE_CTL_MASK, + VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); + } + + /* + * PLL Delay CONFIGURATION settings. The following parameters control + * the bring up of the plls. + */ + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + + /* Setting the tracking length time */ + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_PDTRK_COUNT_MASK, + timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); + + /* Program debounce time for VBUS to become valid */ + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); + + /* Disable battery charge enabling bit */ + setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); + + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + /* + * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT + * Setting these fields, together with default values of the + * other fields, results in programming the registers below as + * follows: + * UTMIP_HSRX_CFG0 = 0x9168c000 + * UTMIP_HSRX_CFG1 = 0x13 + */ + + /* Set PLL enable delay count and Crystal frequency count */ + val = readl(&usbctlr->utmip_hsrx_cfg0); + clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, + utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, + utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + writel(val, &usbctlr->utmip_hsrx_cfg0); + + /* Configure the UTMIP_HS_SYNC_START_DLY */ + clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, + UTMIP_HS_SYNC_START_DLY_MASK, + utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + + /* Preceed the crystal clock disable by >100ns delay. */ + udelay(1); + + /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ + setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Finished the per-controller init. */ + + /* De-assert UTMIP_RESET to bring out of reset. */ + clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Wait for the phy clock to become valid in 100 ms */ + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (loop_count == 100000) + return -1; + + return 0; +} + +static void power_up_port(struct usb_ctlr *usbctlr) +{ + /* Deassert power down state */ + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); + clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | + UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); +} + +static void config_clock(const u32 timing[]) +{ + clock_start_pll(CLOCK_ID_USB, + timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], + timing[PARAM_CPCON], timing[PARAM_LFCON]); +} + +/** + * Add a new USB port to the list of available ports. + * + * @param config USB port configuration + * @return 0 if ok, -1 if error (too many ports) + */ +static int add_port(struct fdt_usb *config, const u32 timing[]) +{ + struct usb_ctlr *usbctlr = config->reg; + + if (port_count == USB_PORTS_MAX) { + debug("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + if (init_usb_controller(config, usbctlr, timing)) { + debug("tegrausb: Cannot init port\n"); + return -1; + } + if (config->utmi) { + /* Disable ICUSB FS/LS transceiver */ + clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); + + /* Select UTMI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + power_up_port(usbctlr); + } + port[port_count++] = *config; + + return 0; +} + +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) +{ + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + tegrausb_stop_port(); + set_host_mode(&port[portnum]); + + usbctlr = port[portnum].reg; + *hccr = (u32)&usbctlr->cap_length; + *hcor = (u32)&usbctlr->usb_cmd; + port_current = portnum; + return 0; +} + +int tegrausb_stop_port(void) +{ + struct usb_ctlr *usbctlr; + + if (port_current == -1) + return -1; + + usbctlr = port[port_current].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + port_current = -1; + return 0; +} + +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, + struct fdt_usb *config) +{ + const char *phy, *mode; + + config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode) { + if (0 == strcmp(mode, "host")) + config->dr_mode = DR_MODE_HOST; + else if (0 == strcmp(mode, "peripheral")) + config->dr_mode = DR_MODE_DEVICE; + else if (0 == strcmp(mode, "otg")) + config->dr_mode = DR_MODE_OTG; + else { + debug("%s: Cannot decode dr_mode '%s'\n", __func__, + mode); + return -FDT_ERR_NOTFOUND; + } + } else { + config->dr_mode = DR_MODE_HOST; + } + + phy = fdt_getprop(blob, node, "phy_type", NULL); + config->utmi = phy && 0 == strcmp("utmi", phy); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->has_legacy_mode = fdtdec_get_bool(blob, node, + "nvidia,has-legacy-mode"); + config->periph_id = clock_decode_periph_id(blob, node); + if (config->periph_id == PERIPH_ID_NONE) { + debug("%s: Missing/invalid peripheral ID\n", __func__); + return -FDT_ERR_NOTFOUND; + } + fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); + debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, " + "dr_mode=%d\n", config->enabled, config->has_legacy_mode, + config->utmi, config->periph_id, config->vbus_gpio.gpio, + config->dr_mode); + + return 0; +} + +int board_usb_init(const void *blob) +{ + struct fdt_usb config; + unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); + enum clock_osc_freq freq; + int node_list[USB_PORTS_MAX]; + int node, count, i; + + /* Set up the USB clocks correctly based on our oscillator frequency */ + freq = clock_get_osc_freq(); + config_clock(usb_pll[freq]); + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + for (i = 0; i < count; i++) { + debug("USB %d: ", i); + node = node_list[i]; + if (!node) + continue; + if (fdt_decode_usb(blob, node, osc_freq, &config)) { + debug("Cannot decode USB node %s\n", + fdt_get_name(blob, node, NULL)); + return -1; + } + + if (add_port(&config, usb_pll[freq])) + return -1; + set_host_mode(&config); + } + port_current = -1; + + return 0; +} diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index 9149665999..b02e8af6ec 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -28,6 +28,9 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 +PLATFORM_LDFLAGS += -EB +USE_PRIVATE_LIBGCC = yes + # -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error PLATFORM_RELFLAGS += -ffunction-sections LDFLAGS_u-boot += --gc-sections diff --git a/arch/arm/cpu/ixp/npe/IxEthAcc.c b/arch/arm/cpu/ixp/npe/IxEthAcc.c index 061b24bb50..20d3d9e9b1 100644 --- a/arch/arm/cpu/ixp/npe/IxEthAcc.c +++ b/arch/arm/cpu/ixp/npe/IxEthAcc.c @@ -102,7 +102,7 @@ PUBLIC IxEthAccStatus ixEthAccInit() /* * Initialize Control plane */ - if (ixEthDBInit() != IX_ETH_ACC_SUCCESS) + if (ixEthDBInit() != IX_ETH_DB_SUCCESS) { IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0); diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c index 25633a3d56..36bc200a3f 100644 --- a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c +++ b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c @@ -630,7 +630,6 @@ IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) { IxNpeMhMessage message; - IxOsalMutex *ackPortAddressLock; IX_STATUS result; /* use this macro instead CHECK_PORT @@ -644,8 +643,6 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd return IX_ETH_DB_PORT_UNINITIALIZED; } - ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock; - /* Operation stops here when Ethernet Learning is not enabled */ if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c index 642e67ae81..9cb143998d 100644 --- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c +++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c @@ -1191,7 +1191,6 @@ ixQMgrLLPShow (int resetStats) { #ifndef NDEBUG UINT8 i = 0; - IxQMgrQInfo *q; UINT32 intEnableRegVal = 0; printf ("Livelock statistics are printed on the fly.\n"); @@ -1200,8 +1199,6 @@ ixQMgrLLPShow (int resetStats) for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) { - q = &dispatchQInfo[i]; - if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER) { printf (" %2d ", i); diff --git a/arch/arm/cpu/lh7a40x/u-boot.lds b/arch/arm/cpu/lh7a40x/u-boot.lds deleted file mode 100644 index 30934ff3e3..0000000000 --- a/arch/arm/cpu/lh7a40x/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/lh7a40x/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index b7b0da98a4..a8f7462c1b 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -94,3 +94,8 @@ void __udelay(unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +ulong get_tbclk(void) +{ + return TIMER_FREQ_HZ; +} diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds deleted file mode 100644 index e86e7818e6..0000000000 --- a/arch/arm/cpu/pxa/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - . = ALIGN(4096); - - .mmutable : { - *(.mmutable) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/s3c44b0/u-boot.lds b/arch/arm/cpu/s3c44b0/u-boot.lds deleted file mode 100644 index 74a259c0d5..0000000000 --- a/arch/arm/cpu/s3c44b0/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/s3c44b0/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/sa1100/u-boot.lds b/arch/arm/cpu/sa1100/u-boot.lds deleted file mode 100644 index e6381dacf6..0000000000 --- a/arch/arm/cpu/sa1100/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * MontaVista Software, Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/u-boot.lds index 40ecf78b34..e49ca0c552 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -1,5 +1,4 @@ /* - * January 2004 - Changed to support H4 device * Copyright (c) 2004-2008 Texas Instruments * * (C) Copyright 2002 @@ -32,9 +31,10 @@ SECTIONS . = 0x00000000; . = ALIGN(4); - .text : + .text : { - arch/arm/cpu/armv7/start.o (.text) + __image_copy_start = .; + CPUDIR/start.o (.text) *(.text) } @@ -70,6 +70,15 @@ SECTIONS _end = .; + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; *(.bss) diff --git a/arch/arm/dts/skeleton.dtsi b/arch/arm/dts/skeleton.dtsi new file mode 100644 index 0000000000..b41d241de2 --- /dev/null +++ b/arch/arm/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi new file mode 100644 index 0000000000..d5ca02c5f5 --- /dev/null +++ b/arch/arm/dts/tegra20.dtsi @@ -0,0 +1,196 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + intc: interrupt-controller@50041000 { + compatible = "nvidia,tegra20-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 70 >; + /* PERIPH_ID_I2C1, PLL_P_OUT3 */ + clocks = <&tegra_car 12>, <&tegra_car 124>; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ + clocks = <&tegra_car 54>, <&tegra_car 124>; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 124 >; + /* PERIPH_ID_I2C3, PLL_P_OUT3 */ + clocks = <&tegra_car 67>, <&tegra_car 124>; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000D000 0x200>; + interrupts = < 85 >; + /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ + clocks = <&tegra_car 47>, <&tegra_car 124>; + }; + + i2s@70002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 45 >; + dma-channel = < 2 >; + }; + + i2s@70002a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 35 >; + dma-channel = < 1 >; + }; + + das@70000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; + #gpio-cells = <2>; + gpio-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 46 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 47 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 51 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 63 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + nvidia,has-legacy-mode; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + }; + +}; diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index debbe50310..bd52d16c9d 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -2,6 +2,115 @@ #define __DMC_H__ #ifndef __ASSEMBLY__ +struct exynos4_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int memconfig0; + unsigned int memconfig1; + unsigned int directcmd; + unsigned int prechconfig; + unsigned int phycontrol0; + unsigned int phycontrol1; + unsigned int phycontrol2; + unsigned int phycontrol3; + unsigned int pwrdnconfig; + unsigned char res1[0x4]; + unsigned int timingref; + unsigned int timingrow; + unsigned int timingdata; + unsigned int timingpower; + unsigned int phystatus; + unsigned int phyzqcontrol; + unsigned int chip0status; + unsigned int chip1status; + unsigned int arefstatus; + unsigned int mrstatus; + unsigned int phytest0; + unsigned int phytest1; + unsigned int qoscontrol0; + unsigned int qosconfig0; + unsigned int qoscontrol1; + unsigned int qosconfig1; + unsigned int qoscontrol2; + unsigned int qosconfig2; + unsigned int qoscontrol3; + unsigned int qosconfig3; + unsigned int qoscontrol4; + unsigned int qosconfig4; + unsigned int qoscontrol5; + unsigned int qosconfig5; + unsigned int qoscontrol6; + unsigned int qosconfig6; + unsigned int qoscontrol7; + unsigned int qosconfig7; + unsigned int qoscontrol8; + unsigned int qosconfig8; + unsigned int qoscontrol9; + unsigned int qosconfig9; + unsigned int qoscontrol10; + unsigned int qosconfig10; + unsigned int qoscontrol11; + unsigned int qosconfig11; + unsigned int qoscontrol12; + unsigned int qosconfig12; + unsigned int qoscontrol13; + unsigned int qosconfig13; + unsigned int qoscontrol14; + unsigned int qosconfig14; + unsigned int qoscontrol15; + unsigned int qosconfig15; + unsigned int qostimeout0; + unsigned int qostimeout1; + unsigned char res2[0x8]; + unsigned int ivcontrol; + unsigned char res3[0x8]; + unsigned int perevconfig; + unsigned char res4[0xDF00]; + unsigned int pmnc_ppc_a; + unsigned char res5[0xC]; + unsigned int cntens_ppc_a; + unsigned char res6[0xC]; + unsigned int cntenc_ppc_a; + unsigned char res7[0xC]; + unsigned int intens_ppc_a; + unsigned char res8[0xC]; + unsigned int intenc_ppc_a; + unsigned char res9[0xC]; + unsigned int flag_ppc_a; + unsigned char res10[0xAC]; + unsigned int ccnt_ppc_a; + unsigned char res11[0xC]; + unsigned int pmcnt0_ppc_a; + unsigned char res12[0xC]; + unsigned int pmcnt1_ppc_a; + unsigned char res13[0xC]; + unsigned int pmcnt2_ppc_a; + unsigned char res14[0xC]; + unsigned int pmcnt3_ppc_a; + unsigned char res15[0xEBC]; + unsigned int pmnc_ppc_m; + unsigned char res16[0xC]; + unsigned int cntens_ppc_m; + unsigned char res17[0xC]; + unsigned int cntenc_ppc_m; + unsigned char res18[0xC]; + unsigned int intens_ppc_m; + unsigned char res19[0xC]; + unsigned int intenc_ppc_m; + unsigned char res20[0xC]; + unsigned int flag_ppc_m; + unsigned char res21[0xAC]; + unsigned int ccnt_ppc_m; + unsigned char res22[0xC]; + unsigned int pmcnt0_ppc_m; + unsigned char res23[0xC]; + unsigned int pmcnt1_ppc_m; + unsigned char res24[0xC]; + unsigned int pmcnt2_ppc_m; + unsigned char res25[0xC]; + unsigned int pmcnt3_ppc_m; +}; + struct exynos5_dmc { unsigned int concontrol; unsigned int memcontrol; diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h index 5132607c6a..c2e9c82049 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ b/arch/arm/include/asm/arch-ixp/ixp425.h @@ -358,6 +358,9 @@ #define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) #define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) +#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ + IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) + /* * Macros to make it easy to access the GPIO registers */ @@ -365,8 +368,11 @@ #define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) #define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) #define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \ - (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3)) +#define GPIO_INT_ACT_LOW_SET(line) \ + *IXP425_GPIO_GPITR(line) = \ + (*IXP425_GPIO_GPITR(line) & \ + ~(0x7 << (((line) & 0x7) * 3))) | \ + (0x1 << (((line) & 0x7) * 3)) \ /* * Constants to make it easy to access Timer Control/Status registers diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h index 9561b5e485..f9e6c535f2 100644 --- a/arch/arm/include/asm/arch-mx28/imx-regs.h +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h @@ -27,6 +27,7 @@ #include <asm/arch/regs-base.h> #include <asm/arch/regs-bch.h> #include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-digctl.h> #include <asm/arch/regs-gpmi.h> #include <asm/arch/regs-i2c.h> #include <asm/arch/regs-ocotp.h> diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h index a7fa1ec1ca..91d7bc8400 100644 --- a/arch/arm/include/asm/arch-mx28/regs-apbh.h +++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h @@ -30,142 +30,142 @@ #ifndef __ASSEMBLY__ struct mx28_apbh_regs { - mx28_reg(hw_apbh_ctrl0) - mx28_reg(hw_apbh_ctrl1) - mx28_reg(hw_apbh_ctrl2) - mx28_reg(hw_apbh_channel_ctrl) - mx28_reg(hw_apbh_devsel) - mx28_reg(hw_apbh_dma_burst_size) - mx28_reg(hw_apbh_debug) + mx28_reg_32(hw_apbh_ctrl0) + mx28_reg_32(hw_apbh_ctrl1) + mx28_reg_32(hw_apbh_ctrl2) + mx28_reg_32(hw_apbh_channel_ctrl) + mx28_reg_32(hw_apbh_devsel) + mx28_reg_32(hw_apbh_dma_burst_size) + mx28_reg_32(hw_apbh_debug) uint32_t reserved[36]; union { struct { - mx28_reg(hw_apbh_ch_curcmdar) - mx28_reg(hw_apbh_ch_nxtcmdar) - mx28_reg(hw_apbh_ch_cmd) - mx28_reg(hw_apbh_ch_bar) - mx28_reg(hw_apbh_ch_sema) - mx28_reg(hw_apbh_ch_debug1) - mx28_reg(hw_apbh_ch_debug2) + mx28_reg_32(hw_apbh_ch_curcmdar) + mx28_reg_32(hw_apbh_ch_nxtcmdar) + mx28_reg_32(hw_apbh_ch_cmd) + mx28_reg_32(hw_apbh_ch_bar) + mx28_reg_32(hw_apbh_ch_sema) + mx28_reg_32(hw_apbh_ch_debug1) + mx28_reg_32(hw_apbh_ch_debug2) } ch[16]; struct { - mx28_reg(hw_apbh_ch0_curcmdar) - mx28_reg(hw_apbh_ch0_nxtcmdar) - mx28_reg(hw_apbh_ch0_cmd) - mx28_reg(hw_apbh_ch0_bar) - mx28_reg(hw_apbh_ch0_sema) - mx28_reg(hw_apbh_ch0_debug1) - mx28_reg(hw_apbh_ch0_debug2) - mx28_reg(hw_apbh_ch1_curcmdar) - mx28_reg(hw_apbh_ch1_nxtcmdar) - mx28_reg(hw_apbh_ch1_cmd) - mx28_reg(hw_apbh_ch1_bar) - mx28_reg(hw_apbh_ch1_sema) - mx28_reg(hw_apbh_ch1_debug1) - mx28_reg(hw_apbh_ch1_debug2) - mx28_reg(hw_apbh_ch2_curcmdar) - mx28_reg(hw_apbh_ch2_nxtcmdar) - mx28_reg(hw_apbh_ch2_cmd) - mx28_reg(hw_apbh_ch2_bar) - mx28_reg(hw_apbh_ch2_sema) - mx28_reg(hw_apbh_ch2_debug1) - mx28_reg(hw_apbh_ch2_debug2) - mx28_reg(hw_apbh_ch3_curcmdar) - mx28_reg(hw_apbh_ch3_nxtcmdar) - mx28_reg(hw_apbh_ch3_cmd) - mx28_reg(hw_apbh_ch3_bar) - mx28_reg(hw_apbh_ch3_sema) - mx28_reg(hw_apbh_ch3_debug1) - mx28_reg(hw_apbh_ch3_debug2) - mx28_reg(hw_apbh_ch4_curcmdar) - mx28_reg(hw_apbh_ch4_nxtcmdar) - mx28_reg(hw_apbh_ch4_cmd) - mx28_reg(hw_apbh_ch4_bar) - mx28_reg(hw_apbh_ch4_sema) - mx28_reg(hw_apbh_ch4_debug1) - mx28_reg(hw_apbh_ch4_debug2) - mx28_reg(hw_apbh_ch5_curcmdar) - mx28_reg(hw_apbh_ch5_nxtcmdar) - mx28_reg(hw_apbh_ch5_cmd) - mx28_reg(hw_apbh_ch5_bar) - mx28_reg(hw_apbh_ch5_sema) - mx28_reg(hw_apbh_ch5_debug1) - mx28_reg(hw_apbh_ch5_debug2) - mx28_reg(hw_apbh_ch6_curcmdar) - mx28_reg(hw_apbh_ch6_nxtcmdar) - mx28_reg(hw_apbh_ch6_cmd) - mx28_reg(hw_apbh_ch6_bar) - mx28_reg(hw_apbh_ch6_sema) - mx28_reg(hw_apbh_ch6_debug1) - mx28_reg(hw_apbh_ch6_debug2) - mx28_reg(hw_apbh_ch7_curcmdar) - mx28_reg(hw_apbh_ch7_nxtcmdar) - mx28_reg(hw_apbh_ch7_cmd) - mx28_reg(hw_apbh_ch7_bar) - mx28_reg(hw_apbh_ch7_sema) - mx28_reg(hw_apbh_ch7_debug1) - mx28_reg(hw_apbh_ch7_debug2) - mx28_reg(hw_apbh_ch8_curcmdar) - mx28_reg(hw_apbh_ch8_nxtcmdar) - mx28_reg(hw_apbh_ch8_cmd) - mx28_reg(hw_apbh_ch8_bar) - mx28_reg(hw_apbh_ch8_sema) - mx28_reg(hw_apbh_ch8_debug1) - mx28_reg(hw_apbh_ch8_debug2) - mx28_reg(hw_apbh_ch9_curcmdar) - mx28_reg(hw_apbh_ch9_nxtcmdar) - mx28_reg(hw_apbh_ch9_cmd) - mx28_reg(hw_apbh_ch9_bar) - mx28_reg(hw_apbh_ch9_sema) - mx28_reg(hw_apbh_ch9_debug1) - mx28_reg(hw_apbh_ch9_debug2) - mx28_reg(hw_apbh_ch10_curcmdar) - mx28_reg(hw_apbh_ch10_nxtcmdar) - mx28_reg(hw_apbh_ch10_cmd) - mx28_reg(hw_apbh_ch10_bar) - mx28_reg(hw_apbh_ch10_sema) - mx28_reg(hw_apbh_ch10_debug1) - mx28_reg(hw_apbh_ch10_debug2) - mx28_reg(hw_apbh_ch11_curcmdar) - mx28_reg(hw_apbh_ch11_nxtcmdar) - mx28_reg(hw_apbh_ch11_cmd) - mx28_reg(hw_apbh_ch11_bar) - mx28_reg(hw_apbh_ch11_sema) - mx28_reg(hw_apbh_ch11_debug1) - mx28_reg(hw_apbh_ch11_debug2) - mx28_reg(hw_apbh_ch12_curcmdar) - mx28_reg(hw_apbh_ch12_nxtcmdar) - mx28_reg(hw_apbh_ch12_cmd) - mx28_reg(hw_apbh_ch12_bar) - mx28_reg(hw_apbh_ch12_sema) - mx28_reg(hw_apbh_ch12_debug1) - mx28_reg(hw_apbh_ch12_debug2) - mx28_reg(hw_apbh_ch13_curcmdar) - mx28_reg(hw_apbh_ch13_nxtcmdar) - mx28_reg(hw_apbh_ch13_cmd) - mx28_reg(hw_apbh_ch13_bar) - mx28_reg(hw_apbh_ch13_sema) - mx28_reg(hw_apbh_ch13_debug1) - mx28_reg(hw_apbh_ch13_debug2) - mx28_reg(hw_apbh_ch14_curcmdar) - mx28_reg(hw_apbh_ch14_nxtcmdar) - mx28_reg(hw_apbh_ch14_cmd) - mx28_reg(hw_apbh_ch14_bar) - mx28_reg(hw_apbh_ch14_sema) - mx28_reg(hw_apbh_ch14_debug1) - mx28_reg(hw_apbh_ch14_debug2) - mx28_reg(hw_apbh_ch15_curcmdar) - mx28_reg(hw_apbh_ch15_nxtcmdar) - mx28_reg(hw_apbh_ch15_cmd) - mx28_reg(hw_apbh_ch15_bar) - mx28_reg(hw_apbh_ch15_sema) - mx28_reg(hw_apbh_ch15_debug1) - mx28_reg(hw_apbh_ch15_debug2) + mx28_reg_32(hw_apbh_ch0_curcmdar) + mx28_reg_32(hw_apbh_ch0_nxtcmdar) + mx28_reg_32(hw_apbh_ch0_cmd) + mx28_reg_32(hw_apbh_ch0_bar) + mx28_reg_32(hw_apbh_ch0_sema) + mx28_reg_32(hw_apbh_ch0_debug1) + mx28_reg_32(hw_apbh_ch0_debug2) + mx28_reg_32(hw_apbh_ch1_curcmdar) + mx28_reg_32(hw_apbh_ch1_nxtcmdar) + mx28_reg_32(hw_apbh_ch1_cmd) + mx28_reg_32(hw_apbh_ch1_bar) + mx28_reg_32(hw_apbh_ch1_sema) + mx28_reg_32(hw_apbh_ch1_debug1) + mx28_reg_32(hw_apbh_ch1_debug2) + mx28_reg_32(hw_apbh_ch2_curcmdar) + mx28_reg_32(hw_apbh_ch2_nxtcmdar) + mx28_reg_32(hw_apbh_ch2_cmd) + mx28_reg_32(hw_apbh_ch2_bar) + mx28_reg_32(hw_apbh_ch2_sema) + mx28_reg_32(hw_apbh_ch2_debug1) + mx28_reg_32(hw_apbh_ch2_debug2) + mx28_reg_32(hw_apbh_ch3_curcmdar) + mx28_reg_32(hw_apbh_ch3_nxtcmdar) + mx28_reg_32(hw_apbh_ch3_cmd) + mx28_reg_32(hw_apbh_ch3_bar) + mx28_reg_32(hw_apbh_ch3_sema) + mx28_reg_32(hw_apbh_ch3_debug1) + mx28_reg_32(hw_apbh_ch3_debug2) + mx28_reg_32(hw_apbh_ch4_curcmdar) + mx28_reg_32(hw_apbh_ch4_nxtcmdar) + mx28_reg_32(hw_apbh_ch4_cmd) + mx28_reg_32(hw_apbh_ch4_bar) + mx28_reg_32(hw_apbh_ch4_sema) + mx28_reg_32(hw_apbh_ch4_debug1) + mx28_reg_32(hw_apbh_ch4_debug2) + mx28_reg_32(hw_apbh_ch5_curcmdar) + mx28_reg_32(hw_apbh_ch5_nxtcmdar) + mx28_reg_32(hw_apbh_ch5_cmd) + mx28_reg_32(hw_apbh_ch5_bar) + mx28_reg_32(hw_apbh_ch5_sema) + mx28_reg_32(hw_apbh_ch5_debug1) + mx28_reg_32(hw_apbh_ch5_debug2) + mx28_reg_32(hw_apbh_ch6_curcmdar) + mx28_reg_32(hw_apbh_ch6_nxtcmdar) + mx28_reg_32(hw_apbh_ch6_cmd) + mx28_reg_32(hw_apbh_ch6_bar) + mx28_reg_32(hw_apbh_ch6_sema) + mx28_reg_32(hw_apbh_ch6_debug1) + mx28_reg_32(hw_apbh_ch6_debug2) + mx28_reg_32(hw_apbh_ch7_curcmdar) + mx28_reg_32(hw_apbh_ch7_nxtcmdar) + mx28_reg_32(hw_apbh_ch7_cmd) + mx28_reg_32(hw_apbh_ch7_bar) + mx28_reg_32(hw_apbh_ch7_sema) + mx28_reg_32(hw_apbh_ch7_debug1) + mx28_reg_32(hw_apbh_ch7_debug2) + mx28_reg_32(hw_apbh_ch8_curcmdar) + mx28_reg_32(hw_apbh_ch8_nxtcmdar) + mx28_reg_32(hw_apbh_ch8_cmd) + mx28_reg_32(hw_apbh_ch8_bar) + mx28_reg_32(hw_apbh_ch8_sema) + mx28_reg_32(hw_apbh_ch8_debug1) + mx28_reg_32(hw_apbh_ch8_debug2) + mx28_reg_32(hw_apbh_ch9_curcmdar) + mx28_reg_32(hw_apbh_ch9_nxtcmdar) + mx28_reg_32(hw_apbh_ch9_cmd) + mx28_reg_32(hw_apbh_ch9_bar) + mx28_reg_32(hw_apbh_ch9_sema) + mx28_reg_32(hw_apbh_ch9_debug1) + mx28_reg_32(hw_apbh_ch9_debug2) + mx28_reg_32(hw_apbh_ch10_curcmdar) + mx28_reg_32(hw_apbh_ch10_nxtcmdar) + mx28_reg_32(hw_apbh_ch10_cmd) + mx28_reg_32(hw_apbh_ch10_bar) + mx28_reg_32(hw_apbh_ch10_sema) + mx28_reg_32(hw_apbh_ch10_debug1) + mx28_reg_32(hw_apbh_ch10_debug2) + mx28_reg_32(hw_apbh_ch11_curcmdar) + mx28_reg_32(hw_apbh_ch11_nxtcmdar) + mx28_reg_32(hw_apbh_ch11_cmd) + mx28_reg_32(hw_apbh_ch11_bar) + mx28_reg_32(hw_apbh_ch11_sema) + mx28_reg_32(hw_apbh_ch11_debug1) + mx28_reg_32(hw_apbh_ch11_debug2) + mx28_reg_32(hw_apbh_ch12_curcmdar) + mx28_reg_32(hw_apbh_ch12_nxtcmdar) + mx28_reg_32(hw_apbh_ch12_cmd) + mx28_reg_32(hw_apbh_ch12_bar) + mx28_reg_32(hw_apbh_ch12_sema) + mx28_reg_32(hw_apbh_ch12_debug1) + mx28_reg_32(hw_apbh_ch12_debug2) + mx28_reg_32(hw_apbh_ch13_curcmdar) + mx28_reg_32(hw_apbh_ch13_nxtcmdar) + mx28_reg_32(hw_apbh_ch13_cmd) + mx28_reg_32(hw_apbh_ch13_bar) + mx28_reg_32(hw_apbh_ch13_sema) + mx28_reg_32(hw_apbh_ch13_debug1) + mx28_reg_32(hw_apbh_ch13_debug2) + mx28_reg_32(hw_apbh_ch14_curcmdar) + mx28_reg_32(hw_apbh_ch14_nxtcmdar) + mx28_reg_32(hw_apbh_ch14_cmd) + mx28_reg_32(hw_apbh_ch14_bar) + mx28_reg_32(hw_apbh_ch14_sema) + mx28_reg_32(hw_apbh_ch14_debug1) + mx28_reg_32(hw_apbh_ch14_debug2) + mx28_reg_32(hw_apbh_ch15_curcmdar) + mx28_reg_32(hw_apbh_ch15_nxtcmdar) + mx28_reg_32(hw_apbh_ch15_cmd) + mx28_reg_32(hw_apbh_ch15_bar) + mx28_reg_32(hw_apbh_ch15_sema) + mx28_reg_32(hw_apbh_ch15_debug1) + mx28_reg_32(hw_apbh_ch15_debug2) }; }; - mx28_reg(hw_apbh_version) + mx28_reg_32(hw_apbh_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h index cac04709da..9243bdd1c0 100644 --- a/arch/arm/include/asm/arch-mx28/regs-bch.h +++ b/arch/arm/include/asm/arch-mx28/regs-bch.h @@ -30,30 +30,30 @@ #ifndef __ASSEMBLY__ struct mx28_bch_regs { - mx28_reg(hw_bch_ctrl) - mx28_reg(hw_bch_status0) - mx28_reg(hw_bch_mode) - mx28_reg(hw_bch_encodeptr) - mx28_reg(hw_bch_dataptr) - mx28_reg(hw_bch_metaptr) + mx28_reg_32(hw_bch_ctrl) + mx28_reg_32(hw_bch_status0) + mx28_reg_32(hw_bch_mode) + mx28_reg_32(hw_bch_encodeptr) + mx28_reg_32(hw_bch_dataptr) + mx28_reg_32(hw_bch_metaptr) uint32_t reserved[4]; - mx28_reg(hw_bch_layoutselect) - mx28_reg(hw_bch_flash0layout0) - mx28_reg(hw_bch_flash0layout1) - mx28_reg(hw_bch_flash1layout0) - mx28_reg(hw_bch_flash1layout1) - mx28_reg(hw_bch_flash2layout0) - mx28_reg(hw_bch_flash2layout1) - mx28_reg(hw_bch_flash3layout0) - mx28_reg(hw_bch_flash3layout1) - mx28_reg(hw_bch_dbgkesread) - mx28_reg(hw_bch_dbgcsferead) - mx28_reg(hw_bch_dbgsyndegread) - mx28_reg(hw_bch_dbgahbmread) - mx28_reg(hw_bch_blockname) - mx28_reg(hw_bch_version) + mx28_reg_32(hw_bch_layoutselect) + mx28_reg_32(hw_bch_flash0layout0) + mx28_reg_32(hw_bch_flash0layout1) + mx28_reg_32(hw_bch_flash1layout0) + mx28_reg_32(hw_bch_flash1layout1) + mx28_reg_32(hw_bch_flash2layout0) + mx28_reg_32(hw_bch_flash2layout1) + mx28_reg_32(hw_bch_flash3layout0) + mx28_reg_32(hw_bch_flash3layout1) + mx28_reg_32(hw_bch_dbgkesread) + mx28_reg_32(hw_bch_dbgcsferead) + mx28_reg_32(hw_bch_dbgsyndegread) + mx28_reg_32(hw_bch_dbgahbmread) + mx28_reg_32(hw_bch_blockname) + mx28_reg_32(hw_bch_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h index 93d0397ef7..3c4947df26 100644 --- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h +++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h @@ -30,38 +30,38 @@ #ifndef __ASSEMBLY__ struct mx28_clkctrl_regs { - mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */ - mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */ - mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */ - mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */ - mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mx28_reg(hw_clkctrl_cpu) /* 0x50 */ - mx28_reg(hw_clkctrl_hbus) /* 0x60 */ - mx28_reg(hw_clkctrl_xbus) /* 0x70 */ - mx28_reg(hw_clkctrl_xtal) /* 0x80 */ - mx28_reg(hw_clkctrl_ssp0) /* 0x90 */ - mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */ - mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */ - mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */ - mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */ - mx28_reg(hw_clkctrl_spdif) /* 0xe0 */ - mx28_reg(hw_clkctrl_emi) /* 0xf0 */ - mx28_reg(hw_clkctrl_saif0) /* 0x100 */ - mx28_reg(hw_clkctrl_saif1) /* 0x110 */ - mx28_reg(hw_clkctrl_lcdif) /* 0x120 */ - mx28_reg(hw_clkctrl_etm) /* 0x130 */ - mx28_reg(hw_clkctrl_enet) /* 0x140 */ - mx28_reg(hw_clkctrl_hsadc) /* 0x150 */ - mx28_reg(hw_clkctrl_flexcan) /* 0x160 */ + mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mx28_reg_32(hw_clkctrl_etm) /* 0x130 */ + mx28_reg_32(hw_clkctrl_enet) /* 0x140 */ + mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */ uint32_t reserved[16]; - mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */ - mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */ - mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */ - mx28_reg(hw_clkctrl_reset) /* 0x1e0 */ - mx28_reg(hw_clkctrl_status) /* 0x1f0 */ - mx28_reg(hw_clkctrl_version) /* 0x200 */ + mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mx28_reg_32(hw_clkctrl_version) /* 0x200 */ }; #endif @@ -248,35 +248,17 @@ struct mx28_clkctrl_regs { #define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) #define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) -#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31) -#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30) -#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24) -#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24 -#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23) -#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22) -#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16) -#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16 -#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15) -#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14) -#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8) -#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8 -#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7) -#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6) -#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f -#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0 - -#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23) -#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22) -#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16) -#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16 -#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15) -#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14) -#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8) -#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8 -#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7) -#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6) -#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f -#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0 +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 #define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index efe975b4bb..94b512d18a 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -47,20 +47,36 @@ * */ -#define __mx28_reg(name) \ +#define __mx28_reg_8(name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ + +#define __mx28_reg_32(name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; -struct mx28_register { - __mx28_reg(reg) +struct mx28_register_8 { + __mx28_reg_8(reg) +}; + +struct mx28_register_32 { + __mx28_reg_32(reg) }; -#define mx28_reg(name) \ +#define mx28_reg_8(name) \ + union { \ + struct { __mx28_reg_8(name) }; \ + struct mx28_register_32 name##_reg; \ + }; + +#define mx28_reg_32(name) \ union { \ - struct { __mx28_reg(name) }; \ - struct mx28_register name##_reg; \ + struct { __mx28_reg_32(name) }; \ + struct mx28_register_32 name##_reg; \ }; #endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-digctl.h b/arch/arm/include/asm/arch-mx28/regs-digctl.h new file mode 100644 index 0000000000..9a63594d04 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-digctl.h @@ -0,0 +1,155 @@ +/* + * Freescale i.MX28 DIGCTL Register Definitions + * + * Copyright (C) 2012 Robert Delien <robert@delien.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_DIGCTL_H__ +#define __MX28_REGS_DIGCTL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_digctl_regs { + mx28_reg_32(hw_digctl_ctrl) /* 0x000 */ + mx28_reg_32(hw_digctl_status) /* 0x010 */ + mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */ + mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */ + mx28_reg_32(hw_digctl_emi_status) /* 0x040 */ + mx28_reg_32(hw_digctl_read_margin) /* 0x050 */ + uint32_t hw_digctl_writeonce; /* 0x060 */ + uint32_t reserved_writeonce[3]; + mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */ + mx28_reg_32(hw_digctl_bist_status) /* 0x080 */ + uint32_t hw_digctl_entropy; /* 0x090 */ + uint32_t reserved_entropy[3]; + uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ + uint32_t reserved_entropy_latched[3]; + + uint32_t reserved1[4]; + + mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + uint32_t hw_digctl_dbgrd; /* 0x0d0 */ + uint32_t reserved_hw_digctl_dbgrd[3]; + uint32_t hw_digctl_dbg; /* 0x0e0 */ + uint32_t reserved_hw_digctl_dbg[3]; + + uint32_t reserved2[4]; + + mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */ + mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */ + mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */ + mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */ + mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */ + mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */ + mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */ + mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */ + mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */ + mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */ + mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ + mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ + mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ + mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ + mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + + uint32_t reserved3[36]; + + uint32_t hw_digctl_scratch0; /* 0x280 */ + uint32_t reserved_hw_digctl_scratch0[3]; + uint32_t hw_digctl_scratch1; /* 0x290 */ + uint32_t reserved_hw_digctl_scratch1[3]; + uint32_t hw_digctl_armcache; /* 0x2a0 */ + uint32_t reserved_hw_digctl_armcache[3]; + mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; + uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; + uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; + uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; + uint32_t hw_digctl_fsl; /* 0x300 */ + uint32_t reserved_hw_digctl_fsl[3]; + uint32_t hw_digctl_chipid; /* 0x310 */ + uint32_t reserved_hw_digctl_chipid[3]; + + uint32_t reserved4[4]; + + uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ + uint32_t reserved_hw_digctl_ahb_stats_select[3]; + + uint32_t reserved5[12]; + + uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ + uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; + uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ + uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; + uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ + uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; + uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ + uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; + uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; + uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; + uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ + uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; + uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; + uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; + + uint32_t reserved6[64]; + + uint32_t hw_digctl_mpte0_loc; /* 0x500 */ + uint32_t reserved_hw_digctl_mpte0_loc[3]; + uint32_t hw_digctl_mpte1_loc; /* 0x510 */ + uint32_t reserved_hw_digctl_mpte1_loc[3]; + uint32_t hw_digctl_mpte2_loc; /* 0x520 */ + uint32_t reserved_hw_digctl_mpte2_loc[3]; + uint32_t hw_digctl_mpte3_loc; /* 0x530 */ + uint32_t reserved_hw_digctl_mpte3_loc[3]; + uint32_t hw_digctl_mpte4_loc; /* 0x540 */ + uint32_t reserved_hw_digctl_mpte4_loc[3]; + uint32_t hw_digctl_mpte5_loc; /* 0x550 */ + uint32_t reserved_hw_digctl_mpte5_loc[3]; + uint32_t hw_digctl_mpte6_loc; /* 0x560 */ + uint32_t reserved_hw_digctl_mpte6_loc[3]; + uint32_t hw_digctl_mpte7_loc; /* 0x570 */ + uint32_t reserved_hw_digctl_mpte7_loc[3]; + uint32_t hw_digctl_mpte8_loc; /* 0x580 */ + uint32_t reserved_hw_digctl_mpte8_loc[3]; + uint32_t hw_digctl_mpte9_loc; /* 0x590 */ + uint32_t reserved_hw_digctl_mpte9_loc[3]; + uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ + uint32_t reserved_hw_digctl_mpte10_loc[3]; + uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ + uint32_t reserved_hw_digctl_mpte11_loc[3]; + uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ + uint32_t reserved_hw_digctl_mpte12_loc[3]; + uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ + uint32_t reserved_hw_digctl_mpte13_loc[3]; + uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ + uint32_t reserved_hw_digctl_mpte14_loc[3]; + uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ + uint32_t reserved_hw_digctl_mpte15_loc[3]; +}; +#endif + +#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h index 00967938f5..1b487f46c6 100644 --- a/arch/arm/include/asm/arch-mx28/regs-gpmi.h +++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h @@ -30,22 +30,22 @@ #ifndef __ASSEMBLY__ struct mx28_gpmi_regs { - mx28_reg(hw_gpmi_ctrl0) - mx28_reg(hw_gpmi_compare) - mx28_reg(hw_gpmi_eccctrl) - mx28_reg(hw_gpmi_ecccount) - mx28_reg(hw_gpmi_payload) - mx28_reg(hw_gpmi_auxiliary) - mx28_reg(hw_gpmi_ctrl1) - mx28_reg(hw_gpmi_timing0) - mx28_reg(hw_gpmi_timing1) + mx28_reg_32(hw_gpmi_ctrl0) + mx28_reg_32(hw_gpmi_compare) + mx28_reg_32(hw_gpmi_eccctrl) + mx28_reg_32(hw_gpmi_ecccount) + mx28_reg_32(hw_gpmi_payload) + mx28_reg_32(hw_gpmi_auxiliary) + mx28_reg_32(hw_gpmi_ctrl1) + mx28_reg_32(hw_gpmi_timing0) + mx28_reg_32(hw_gpmi_timing1) uint32_t reserved[4]; - mx28_reg(hw_gpmi_data) - mx28_reg(hw_gpmi_stat) - mx28_reg(hw_gpmi_debug) - mx28_reg(hw_gpmi_version) + mx28_reg_32(hw_gpmi_data) + mx28_reg_32(hw_gpmi_stat) + mx28_reg_32(hw_gpmi_debug) + mx28_reg_32(hw_gpmi_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h index 30e0ed7433..2e2e81453d 100644 --- a/arch/arm/include/asm/arch-mx28/regs-i2c.h +++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h @@ -27,20 +27,20 @@ #ifndef __ASSEMBLY__ struct mx28_i2c_regs { - mx28_reg(hw_i2c_ctrl0) - mx28_reg(hw_i2c_timing0) - mx28_reg(hw_i2c_timing1) - mx28_reg(hw_i2c_timing2) - mx28_reg(hw_i2c_ctrl1) - mx28_reg(hw_i2c_stat) - mx28_reg(hw_i2c_queuectrl) - mx28_reg(hw_i2c_queuestat) - mx28_reg(hw_i2c_queuecmd) - mx28_reg(hw_i2c_queuedata) - mx28_reg(hw_i2c_data) - mx28_reg(hw_i2c_debug0) - mx28_reg(hw_i2c_debug1) - mx28_reg(hw_i2c_version) + mx28_reg_32(hw_i2c_ctrl0) + mx28_reg_32(hw_i2c_timing0) + mx28_reg_32(hw_i2c_timing1) + mx28_reg_32(hw_i2c_timing2) + mx28_reg_32(hw_i2c_ctrl1) + mx28_reg_32(hw_i2c_stat) + mx28_reg_32(hw_i2c_queuectrl) + mx28_reg_32(hw_i2c_queuestat) + mx28_reg_32(hw_i2c_queuecmd) + mx28_reg_32(hw_i2c_queuedata) + mx28_reg_32(hw_i2c_data) + mx28_reg_32(hw_i2c_debug0) + mx28_reg_32(hw_i2c_debug1) + mx28_reg_32(hw_i2c_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h index ea2fd7b167..2738035519 100644 --- a/arch/arm/include/asm/arch-mx28/regs-ocotp.h +++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h @@ -30,49 +30,49 @@ #ifndef __ASSEMBLY__ struct mx28_ocotp_regs { - mx28_reg(hw_ocotp_ctrl) /* 0x0 */ - mx28_reg(hw_ocotp_data) /* 0x10 */ - mx28_reg(hw_ocotp_cust0) /* 0x20 */ - mx28_reg(hw_ocotp_cust1) /* 0x30 */ - mx28_reg(hw_ocotp_cust2) /* 0x40 */ - mx28_reg(hw_ocotp_cust3) /* 0x50 */ - mx28_reg(hw_ocotp_crypto0) /* 0x60 */ - mx28_reg(hw_ocotp_crypto1) /* 0x70 */ - mx28_reg(hw_ocotp_crypto2) /* 0x80 */ - mx28_reg(hw_ocotp_crypto3) /* 0x90 */ - mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */ - mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */ - mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */ - mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */ - mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */ - mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */ - mx28_reg(hw_ocotp_swcap) /* 0x100 */ - mx28_reg(hw_ocotp_custcap) /* 0x110 */ - mx28_reg(hw_ocotp_lock) /* 0x120 */ - mx28_reg(hw_ocotp_ops0) /* 0x130 */ - mx28_reg(hw_ocotp_ops1) /* 0x140 */ - mx28_reg(hw_ocotp_ops2) /* 0x150 */ - mx28_reg(hw_ocotp_ops3) /* 0x160 */ - mx28_reg(hw_ocotp_un0) /* 0x170 */ - mx28_reg(hw_ocotp_un1) /* 0x180 */ - mx28_reg(hw_ocotp_un2) /* 0x190 */ - mx28_reg(hw_ocotp_rom0) /* 0x1a0 */ - mx28_reg(hw_ocotp_rom1) /* 0x1b0 */ - mx28_reg(hw_ocotp_rom2) /* 0x1c0 */ - mx28_reg(hw_ocotp_rom3) /* 0x1d0 */ - mx28_reg(hw_ocotp_rom4) /* 0x1e0 */ - mx28_reg(hw_ocotp_rom5) /* 0x1f0 */ - mx28_reg(hw_ocotp_rom6) /* 0x200 */ - mx28_reg(hw_ocotp_rom7) /* 0x210 */ - mx28_reg(hw_ocotp_srk0) /* 0x220 */ - mx28_reg(hw_ocotp_srk1) /* 0x230 */ - mx28_reg(hw_ocotp_srk2) /* 0x240 */ - mx28_reg(hw_ocotp_srk3) /* 0x250 */ - mx28_reg(hw_ocotp_srk4) /* 0x260 */ - mx28_reg(hw_ocotp_srk5) /* 0x270 */ - mx28_reg(hw_ocotp_srk6) /* 0x280 */ - mx28_reg(hw_ocotp_srk7) /* 0x290 */ - mx28_reg(hw_ocotp_version) /* 0x2a0 */ + mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */ + mx28_reg_32(hw_ocotp_data) /* 0x10 */ + mx28_reg_32(hw_ocotp_cust0) /* 0x20 */ + mx28_reg_32(hw_ocotp_cust1) /* 0x30 */ + mx28_reg_32(hw_ocotp_cust2) /* 0x40 */ + mx28_reg_32(hw_ocotp_cust3) /* 0x50 */ + mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */ + mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */ + mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */ + mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */ + mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ + mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ + mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ + mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ + mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ + mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ + mx28_reg_32(hw_ocotp_swcap) /* 0x100 */ + mx28_reg_32(hw_ocotp_custcap) /* 0x110 */ + mx28_reg_32(hw_ocotp_lock) /* 0x120 */ + mx28_reg_32(hw_ocotp_ops0) /* 0x130 */ + mx28_reg_32(hw_ocotp_ops1) /* 0x140 */ + mx28_reg_32(hw_ocotp_ops2) /* 0x150 */ + mx28_reg_32(hw_ocotp_ops3) /* 0x160 */ + mx28_reg_32(hw_ocotp_un0) /* 0x170 */ + mx28_reg_32(hw_ocotp_un1) /* 0x180 */ + mx28_reg_32(hw_ocotp_un2) /* 0x190 */ + mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */ + mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */ + mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */ + mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */ + mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */ + mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */ + mx28_reg_32(hw_ocotp_rom6) /* 0x200 */ + mx28_reg_32(hw_ocotp_rom7) /* 0x210 */ + mx28_reg_32(hw_ocotp_srk0) /* 0x220 */ + mx28_reg_32(hw_ocotp_srk1) /* 0x230 */ + mx28_reg_32(hw_ocotp_srk2) /* 0x240 */ + mx28_reg_32(hw_ocotp_srk3) /* 0x250 */ + mx28_reg_32(hw_ocotp_srk4) /* 0x260 */ + mx28_reg_32(hw_ocotp_srk5) /* 0x270 */ + mx28_reg_32(hw_ocotp_srk6) /* 0x280 */ + mx28_reg_32(hw_ocotp_srk7) /* 0x290 */ + mx28_reg_32(hw_ocotp_version) /* 0x2a0 */ }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h index 73739cad54..80dcdf6619 100644 --- a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h +++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h @@ -30,129 +30,129 @@ #ifndef __ASSEMBLY__ struct mx28_pinctrl_regs { - mx28_reg(hw_pinctrl_ctrl) /* 0x0 */ + mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */ uint32_t reserved1[60]; - mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */ - mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */ - mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */ - mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */ - mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */ - mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */ - mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */ - mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */ - mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */ - mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */ - mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */ - mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */ - mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */ - mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */ + mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ + mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ + mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ + mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ + mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ + mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ + mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ + mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ + mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ + mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ + mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ + mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ + mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ + mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ uint32_t reserved2[72]; - mx28_reg(hw_pinctrl_drive0) /* 0x300 */ - mx28_reg(hw_pinctrl_drive1) /* 0x310 */ - mx28_reg(hw_pinctrl_drive2) /* 0x320 */ - mx28_reg(hw_pinctrl_drive3) /* 0x330 */ - mx28_reg(hw_pinctrl_drive4) /* 0x340 */ - mx28_reg(hw_pinctrl_drive5) /* 0x350 */ - mx28_reg(hw_pinctrl_drive6) /* 0x360 */ - mx28_reg(hw_pinctrl_drive7) /* 0x370 */ - mx28_reg(hw_pinctrl_drive8) /* 0x380 */ - mx28_reg(hw_pinctrl_drive9) /* 0x390 */ - mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */ - mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */ - mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */ - mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */ - mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */ - mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */ - mx28_reg(hw_pinctrl_drive16) /* 0x400 */ - mx28_reg(hw_pinctrl_drive17) /* 0x410 */ - mx28_reg(hw_pinctrl_drive18) /* 0x420 */ - mx28_reg(hw_pinctrl_drive19) /* 0x430 */ + mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */ + mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */ + mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */ + mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */ + mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */ + mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */ + mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */ + mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */ + mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */ + mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */ + mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ + mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ + mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ + mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ + mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ + mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ + mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */ + mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */ + mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */ + mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */ uint32_t reserved3[112]; - mx28_reg(hw_pinctrl_pull0) /* 0x600 */ - mx28_reg(hw_pinctrl_pull1) /* 0x610 */ - mx28_reg(hw_pinctrl_pull2) /* 0x620 */ - mx28_reg(hw_pinctrl_pull3) /* 0x630 */ - mx28_reg(hw_pinctrl_pull4) /* 0x640 */ - mx28_reg(hw_pinctrl_pull5) /* 0x650 */ - mx28_reg(hw_pinctrl_pull6) /* 0x660 */ + mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */ + mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */ + mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */ + mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */ + mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */ + mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */ + mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */ uint32_t reserved4[36]; - mx28_reg(hw_pinctrl_dout0) /* 0x700 */ - mx28_reg(hw_pinctrl_dout1) /* 0x710 */ - mx28_reg(hw_pinctrl_dout2) /* 0x720 */ - mx28_reg(hw_pinctrl_dout3) /* 0x730 */ - mx28_reg(hw_pinctrl_dout4) /* 0x740 */ + mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */ + mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */ + mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */ + mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */ + mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */ uint32_t reserved5[108]; - mx28_reg(hw_pinctrl_din0) /* 0x900 */ - mx28_reg(hw_pinctrl_din1) /* 0x910 */ - mx28_reg(hw_pinctrl_din2) /* 0x920 */ - mx28_reg(hw_pinctrl_din3) /* 0x930 */ - mx28_reg(hw_pinctrl_din4) /* 0x940 */ + mx28_reg_32(hw_pinctrl_din0) /* 0x900 */ + mx28_reg_32(hw_pinctrl_din1) /* 0x910 */ + mx28_reg_32(hw_pinctrl_din2) /* 0x920 */ + mx28_reg_32(hw_pinctrl_din3) /* 0x930 */ + mx28_reg_32(hw_pinctrl_din4) /* 0x940 */ uint32_t reserved6[108]; - mx28_reg(hw_pinctrl_doe0) /* 0xb00 */ - mx28_reg(hw_pinctrl_doe1) /* 0xb10 */ - mx28_reg(hw_pinctrl_doe2) /* 0xb20 */ - mx28_reg(hw_pinctrl_doe3) /* 0xb30 */ - mx28_reg(hw_pinctrl_doe4) /* 0xb40 */ + mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */ + mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */ + mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */ + mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */ + mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */ uint32_t reserved7[300]; - mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */ - mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */ - mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */ - mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */ - mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */ + mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ + mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ + mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ + mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ + mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ uint32_t reserved8[44]; - mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */ - mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */ - mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */ - mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */ - mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */ + mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ + mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ + mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ + mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ + mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ uint32_t reserved9[44]; - mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */ - mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */ - mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */ - mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */ - mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */ + mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ + mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ + mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ + mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ + mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ uint32_t reserved10[44]; - mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */ - mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */ - mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */ - mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */ - mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */ + mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ + mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ + mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ + mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ + mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ uint32_t reserved11[44]; - mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */ - mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */ - mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */ - mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */ - mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */ + mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ + mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ + mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ + mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ + mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ uint32_t reserved12[380]; - mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ uint32_t reserved13[76]; - mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ + mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h index 9da63adc2e..8eadc6d552 100644 --- a/arch/arm/include/asm/arch-mx28/regs-power.h +++ b/arch/arm/include/asm/arch-mx28/regs-power.h @@ -26,10 +26,10 @@ #ifndef __ASSEMBLY__ struct mx28_power_regs { - mx28_reg(hw_power_ctrl) - mx28_reg(hw_power_5vctrl) - mx28_reg(hw_power_minpwr) - mx28_reg(hw_power_charge) + mx28_reg_32(hw_power_ctrl) + mx28_reg_32(hw_power_5vctrl) + mx28_reg_32(hw_power_minpwr) + mx28_reg_32(hw_power_charge) uint32_t hw_power_vdddctrl; uint32_t reserved_vddd[3]; uint32_t hw_power_vddactrl; @@ -44,23 +44,23 @@ struct mx28_power_regs { uint32_t reserved_misc[3]; uint32_t hw_power_dclimits; uint32_t reserved_dclimits[3]; - mx28_reg(hw_power_loopctrl) + mx28_reg_32(hw_power_loopctrl) uint32_t hw_power_sts; uint32_t reserved_sts[3]; - mx28_reg(hw_power_speed) + mx28_reg_32(hw_power_speed) uint32_t hw_power_battmonitor; uint32_t reserved_battmonitor[3]; uint32_t reserved[4]; - mx28_reg(hw_power_reset) - mx28_reg(hw_power_debug) - mx28_reg(hw_power_thermal) - mx28_reg(hw_power_usb1ctrl) - mx28_reg(hw_power_special) - mx28_reg(hw_power_version) - mx28_reg(hw_power_anaclkctrl) - mx28_reg(hw_power_refctrl) + mx28_reg_32(hw_power_reset) + mx28_reg_32(hw_power_debug) + mx28_reg_32(hw_power_thermal) + mx28_reg_32(hw_power_usb1ctrl) + mx28_reg_32(hw_power_special) + mx28_reg_32(hw_power_version) + mx28_reg_32(hw_power_anaclkctrl) + mx28_reg_32(hw_power_refctrl) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h index fe2fda9655..e605a03953 100644 --- a/arch/arm/include/asm/arch-mx28/regs-rtc.h +++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h @@ -27,20 +27,20 @@ #ifndef __ASSEMBLY__ struct mx28_rtc_regs { - mx28_reg(hw_rtc_ctrl) - mx28_reg(hw_rtc_stat) - mx28_reg(hw_rtc_milliseconds) - mx28_reg(hw_rtc_seconds) - mx28_reg(hw_rtc_rtc_alarm) - mx28_reg(hw_rtc_watchdog) - mx28_reg(hw_rtc_persistent0) - mx28_reg(hw_rtc_persistent1) - mx28_reg(hw_rtc_persistent2) - mx28_reg(hw_rtc_persistent3) - mx28_reg(hw_rtc_persistent4) - mx28_reg(hw_rtc_persistent5) - mx28_reg(hw_rtc_debug) - mx28_reg(hw_rtc_version) + mx28_reg_32(hw_rtc_ctrl) + mx28_reg_32(hw_rtc_stat) + mx28_reg_32(hw_rtc_milliseconds) + mx28_reg_32(hw_rtc_seconds) + mx28_reg_32(hw_rtc_rtc_alarm) + mx28_reg_32(hw_rtc_watchdog) + mx28_reg_32(hw_rtc_persistent0) + mx28_reg_32(hw_rtc_persistent1) + mx28_reg_32(hw_rtc_persistent2) + mx28_reg_32(hw_rtc_persistent3) + mx28_reg_32(hw_rtc_persistent4) + mx28_reg_32(hw_rtc_persistent5) + mx28_reg_32(hw_rtc_debug) + mx28_reg_32(hw_rtc_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h index ab3870c149..be71d48947 100644 --- a/arch/arm/include/asm/arch-mx28/regs-ssp.h +++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h @@ -29,26 +29,26 @@ #ifndef __ASSEMBLY__ struct mx28_ssp_regs { - mx28_reg(hw_ssp_ctrl0) - mx28_reg(hw_ssp_cmd0) - mx28_reg(hw_ssp_cmd1) - mx28_reg(hw_ssp_xfer_size) - mx28_reg(hw_ssp_block_size) - mx28_reg(hw_ssp_compref) - mx28_reg(hw_ssp_compmask) - mx28_reg(hw_ssp_timing) - mx28_reg(hw_ssp_ctrl1) - mx28_reg(hw_ssp_data) - mx28_reg(hw_ssp_sdresp0) - mx28_reg(hw_ssp_sdresp1) - mx28_reg(hw_ssp_sdresp2) - mx28_reg(hw_ssp_sdresp3) - mx28_reg(hw_ssp_ddr_ctrl) - mx28_reg(hw_ssp_dll_ctrl) - mx28_reg(hw_ssp_status) - mx28_reg(hw_ssp_dll_sts) - mx28_reg(hw_ssp_debug) - mx28_reg(hw_ssp_version) + mx28_reg_32(hw_ssp_ctrl0) + mx28_reg_32(hw_ssp_cmd0) + mx28_reg_32(hw_ssp_cmd1) + mx28_reg_32(hw_ssp_xfer_size) + mx28_reg_32(hw_ssp_block_size) + mx28_reg_32(hw_ssp_compref) + mx28_reg_32(hw_ssp_compmask) + mx28_reg_32(hw_ssp_timing) + mx28_reg_32(hw_ssp_ctrl1) + mx28_reg_32(hw_ssp_data) + mx28_reg_32(hw_ssp_sdresp0) + mx28_reg_32(hw_ssp_sdresp1) + mx28_reg_32(hw_ssp_sdresp2) + mx28_reg_32(hw_ssp_sdresp3) + mx28_reg_32(hw_ssp_ddr_ctrl) + mx28_reg_32(hw_ssp_dll_ctrl) + mx28_reg_32(hw_ssp_status) + mx28_reg_32(hw_ssp_dll_sts) + mx28_reg_32(hw_ssp_debug) + mx28_reg_32(hw_ssp_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h index 1b941cf289..3e8dfe782f 100644 --- a/arch/arm/include/asm/arch-mx28/regs-timrot.h +++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h @@ -29,25 +29,25 @@ #ifndef __ASSEMBLY__ struct mx28_timrot_regs { - mx28_reg(hw_timrot_rotctrl) - mx28_reg(hw_timrot_rotcount) - mx28_reg(hw_timrot_timctrl0) - mx28_reg(hw_timrot_running_count0) - mx28_reg(hw_timrot_fixed_count0) - mx28_reg(hw_timrot_match_count0) - mx28_reg(hw_timrot_timctrl1) - mx28_reg(hw_timrot_running_count1) - mx28_reg(hw_timrot_fixed_count1) - mx28_reg(hw_timrot_match_count1) - mx28_reg(hw_timrot_timctrl2) - mx28_reg(hw_timrot_running_count2) - mx28_reg(hw_timrot_fixed_count2) - mx28_reg(hw_timrot_match_count2) - mx28_reg(hw_timrot_timctrl3) - mx28_reg(hw_timrot_running_count3) - mx28_reg(hw_timrot_fixed_count3) - mx28_reg(hw_timrot_match_count3) - mx28_reg(hw_timrot_version) + mx28_reg_32(hw_timrot_rotctrl) + mx28_reg_32(hw_timrot_rotcount) + mx28_reg_32(hw_timrot_timctrl0) + mx28_reg_32(hw_timrot_running_count0) + mx28_reg_32(hw_timrot_fixed_count0) + mx28_reg_32(hw_timrot_match_count0) + mx28_reg_32(hw_timrot_timctrl1) + mx28_reg_32(hw_timrot_running_count1) + mx28_reg_32(hw_timrot_fixed_count1) + mx28_reg_32(hw_timrot_match_count1) + mx28_reg_32(hw_timrot_timctrl2) + mx28_reg_32(hw_timrot_running_count2) + mx28_reg_32(hw_timrot_fixed_count2) + mx28_reg_32(hw_timrot_match_count2) + mx28_reg_32(hw_timrot_timctrl3) + mx28_reg_32(hw_timrot_running_count3) + mx28_reg_32(hw_timrot_fixed_count3) + mx28_reg_32(hw_timrot_match_count3) + mx28_reg_32(hw_timrot_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h index e823e1997d..0291d815c6 100644 --- a/arch/arm/include/asm/arch-mx28/regs-usbphy.h +++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h @@ -24,16 +24,16 @@ #define __REGS_USBPHY_H__ struct mx28_usbphy_regs { - mx28_reg(hw_usbphy_pwd) - mx28_reg(hw_usbphy_tx) - mx28_reg(hw_usbphy_rx) - mx28_reg(hw_usbphy_ctrl) - mx28_reg(hw_usbphy_status) - mx28_reg(hw_usbphy_debug) - mx28_reg(hw_usbphy_debug0_status) - mx28_reg(hw_usbphy_debug1) - mx28_reg(hw_usbphy_version) - mx28_reg(hw_usbphy_ip) + mx28_reg_32(hw_usbphy_pwd) + mx28_reg_32(hw_usbphy_tx) + mx28_reg_32(hw_usbphy_rx) + mx28_reg_32(hw_usbphy_ctrl) + mx28_reg_32(hw_usbphy_status) + mx28_reg_32(hw_usbphy_debug) + mx28_reg_32(hw_usbphy_debug0_status) + mx28_reg_32(hw_usbphy_debug1) + mx28_reg_32(hw_usbphy_version) + mx28_reg_32(hw_usbphy_ip) }; #define USBPHY_PWD_RXPWDRX (1 << 20) diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h index f10149477a..15d8de31ee 100644 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -23,9 +23,13 @@ #ifndef __MX28_H__ #define __MX28_H__ -int mx28_reset_block(struct mx28_register *reg); -int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout); -int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout); +int mx28_reset_block(struct mx28_register_32 *reg); +int mx28_wait_mask_set(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); +int mx28_wait_mask_clr(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 636458f8a0..613809bdd6 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -46,5 +46,6 @@ enum mxc_clock { u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void enable_usboh3_clk(unsigned char enable); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6b7589b78a..cad957a3b7 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -111,8 +111,10 @@ #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) @@ -292,5 +294,147 @@ struct aipstz_regs { u32 opacr4; }; +struct anatop_regs { + u32 pll_sys; /* 0x000 */ + u32 pll_sys_set; /* 0x004 */ + u32 pll_sys_clr; /* 0x008 */ + u32 pll_sys_tog; /* 0x00c */ + u32 usb1_pll_480_ctrl; /* 0x010 */ + u32 usb1_pll_480_ctrl_set; /* 0x014 */ + u32 usb1_pll_480_ctrl_clr; /* 0x018 */ + u32 usb1_pll_480_ctrl_tog; /* 0x01c */ + u32 usb2_pll_480_ctrl; /* 0x020 */ + u32 usb2_pll_480_ctrl_set; /* 0x024 */ + u32 usb2_pll_480_ctrl_clr; /* 0x028 */ + u32 usb2_pll_480_ctrl_tog; /* 0x02c */ + u32 pll_528; /* 0x030 */ + u32 pll_528_set; /* 0x034 */ + u32 pll_528_clr; /* 0x038 */ + u32 pll_528_tog; /* 0x03c */ + u32 pll_528_ss; /* 0x040 */ + u32 rsvd0[3]; + u32 pll_528_num; /* 0x050 */ + u32 rsvd1[3]; + u32 pll_528_denom; /* 0x060 */ + u32 rsvd2[3]; + u32 pll_audio; /* 0x070 */ + u32 pll_audio_set; /* 0x074 */ + u32 pll_audio_clr; /* 0x078 */ + u32 pll_audio_tog; /* 0x07c */ + u32 pll_audio_num; /* 0x080 */ + u32 rsvd3[3]; + u32 pll_audio_denom; /* 0x090 */ + u32 rsvd4[3]; + u32 pll_video; /* 0x0a0 */ + u32 pll_video_set; /* 0x0a4 */ + u32 pll_video_clr; /* 0x0a8 */ + u32 pll_video_tog; /* 0x0ac */ + u32 pll_video_num; /* 0x0b0 */ + u32 rsvd5[3]; + u32 pll_video_denom; /* 0x0c0 */ + u32 rsvd6[3]; + u32 pll_mlb; /* 0x0d0 */ + u32 pll_mlb_set; /* 0x0d4 */ + u32 pll_mlb_clr; /* 0x0d8 */ + u32 pll_mlb_tog; /* 0x0dc */ + u32 pll_enet; /* 0x0e0 */ + u32 pll_enet_set; /* 0x0e4 */ + u32 pll_enet_clr; /* 0x0e8 */ + u32 pll_enet_tog; /* 0x0ec */ + u32 pfd_480; /* 0x0f0 */ + u32 pfd_480_set; /* 0x0f4 */ + u32 pfd_480_clr; /* 0x0f8 */ + u32 pfd_480_tog; /* 0x0fc */ + u32 pfd_528; /* 0x100 */ + u32 pfd_528_set; /* 0x104 */ + u32 pfd_528_clr; /* 0x108 */ + u32 pfd_528_tog; /* 0x10c */ + u32 reg_1p1; /* 0x110 */ + u32 reg_1p1_set; /* 0x114 */ + u32 reg_1p1_clr; /* 0x118 */ + u32 reg_1p1_tog; /* 0x11c */ + u32 reg_3p0; /* 0x120 */ + u32 reg_3p0_set; /* 0x124 */ + u32 reg_3p0_clr; /* 0x128 */ + u32 reg_3p0_tog; /* 0x12c */ + u32 reg_2p5; /* 0x130 */ + u32 reg_2p5_set; /* 0x134 */ + u32 reg_2p5_clr; /* 0x138 */ + u32 reg_2p5_tog; /* 0x13c */ + u32 reg_core; /* 0x140 */ + u32 reg_core_set; /* 0x144 */ + u32 reg_core_clr; /* 0x148 */ + u32 reg_core_tog; /* 0x14c */ + u32 ana_misc0; /* 0x150 */ + u32 ana_misc0_set; /* 0x154 */ + u32 ana_misc0_clr; /* 0x158 */ + u32 ana_misc0_tog; /* 0x15c */ + u32 ana_misc1; /* 0x160 */ + u32 ana_misc1_set; /* 0x164 */ + u32 ana_misc1_clr; /* 0x168 */ + u32 ana_misc1_tog; /* 0x16c */ + u32 ana_misc2; /* 0x170 */ + u32 ana_misc2_set; /* 0x174 */ + u32 ana_misc2_clr; /* 0x178 */ + u32 ana_misc2_tog; /* 0x17c */ + u32 tempsense0; /* 0x180 */ + u32 tempsense0_set; /* 0x184 */ + u32 tempsense0_clr; /* 0x188 */ + u32 tempsense0_tog; /* 0x18c */ + u32 tempsense1; /* 0x190 */ + u32 tempsense1_set; /* 0x194 */ + u32 tempsense1_clr; /* 0x198 */ + u32 tempsense1_tog; /* 0x19c */ + u32 usb1_vbus_detect; /* 0x1a0 */ + u32 usb1_vbus_detect_set; /* 0x1a4 */ + u32 usb1_vbus_detect_clr; /* 0x1a8 */ + u32 usb1_vbus_detect_tog; /* 0x1ac */ + u32 usb1_chrg_detect; /* 0x1b0 */ + u32 usb1_chrg_detect_set; /* 0x1b4 */ + u32 usb1_chrg_detect_clr; /* 0x1b8 */ + u32 usb1_chrg_detect_tog; /* 0x1bc */ + u32 usb1_vbus_det_stat; /* 0x1c0 */ + u32 usb1_vbus_det_stat_set; /* 0x1c4 */ + u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ + u32 usb1_vbus_det_stat_tog; /* 0x1cc */ + u32 usb1_chrg_det_stat; /* 0x1d0 */ + u32 usb1_chrg_det_stat_set; /* 0x1d4 */ + u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ + u32 usb1_chrg_det_stat_tog; /* 0x1dc */ + u32 usb1_loopback; /* 0x1e0 */ + u32 usb1_loopback_set; /* 0x1e4 */ + u32 usb1_loopback_clr; /* 0x1e8 */ + u32 usb1_loopback_tog; /* 0x1ec */ + u32 usb1_misc; /* 0x1f0 */ + u32 usb1_misc_set; /* 0x1f4 */ + u32 usb1_misc_clr; /* 0x1f8 */ + u32 usb1_misc_tog; /* 0x1fc */ + u32 usb2_vbus_detect; /* 0x200 */ + u32 usb2_vbus_detect_set; /* 0x204 */ + u32 usb2_vbus_detect_clr; /* 0x208 */ + u32 usb2_vbus_detect_tog; /* 0x20c */ + u32 usb2_chrg_detect; /* 0x210 */ + u32 usb2_chrg_detect_set; /* 0x214 */ + u32 usb2_chrg_detect_clr; /* 0x218 */ + u32 usb2_chrg_detect_tog; /* 0x21c */ + u32 usb2_vbus_det_stat; /* 0x220 */ + u32 usb2_vbus_det_stat_set; /* 0x224 */ + u32 usb2_vbus_det_stat_clr; /* 0x228 */ + u32 usb2_vbus_det_stat_tog; /* 0x22c */ + u32 usb2_chrg_det_stat; /* 0x230 */ + u32 usb2_chrg_det_stat_set; /* 0x234 */ + u32 usb2_chrg_det_stat_clr; /* 0x238 */ + u32 usb2_chrg_det_stat_tog; /* 0x23c */ + u32 usb2_loopback; /* 0x240 */ + u32 usb2_loopback_set; /* 0x244 */ + u32 usb2_loopback_clr; /* 0x248 */ + u32 usb2_loopback_tog; /* 0x24c */ + u32 usb2_misc; /* 0x250 */ + u32 usb2_misc_set; /* 0x254 */ + u32 usb2_misc_clr; /* 0x258 */ + u32 usb2_misc_tog; /* 0x25c */ + u32 digprog; /* 0x260 */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 0b6e004fbc..415e420012 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -125,9 +125,15 @@ struct clk_rst_ctlr { #define OSC_FREQ_SHIFT 30 #define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) -/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */ +/* + * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits + * but can be 16. We could use knowledge we have to restrict the mask in + * the 8-bit cases (the divider_bits value returned by + * get_periph_clock_source()) but it does not seem worth it since the code + * already checks the ranges of values it is writing, in clk_get_divider(). + */ #define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT) +#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) #define OUT_CLK_SOURCE_SHIFT 30 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 080ef18e81..6b12c76e8d 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -177,6 +177,7 @@ enum periph_id { PERIPH_ID_CRAM2, PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, }; /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ @@ -355,6 +356,18 @@ unsigned clock_get_rate(enum clock_id clkid); */ void clock_ll_start_uart(enum periph_id periph_id); +/** + * Decode a peripheral ID from a device tree node. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return peripheral ID, or PERIPH_ID_NONE if none + */ +enum periph_id clock_decode_periph_id(const void *blob, int node); + /* * Checks that clocks are valid and prints a warning if not * diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 8941443ad8..ca1881e3a2 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -39,8 +39,10 @@ #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_PMC_BASE 0x7000E400 +#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_CSITE_BASE 0x70040000 +#define TEGRA_USB1_BASE 0xC5000000 +#define TEGRA_USB3_BASE 0xC5008000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC @@ -53,7 +55,7 @@ struct timerus { unsigned int cntr_1us; }; #else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL NV_PA_PMC_BASE +#define PRM_RSTCTRL TEGRA2_PMC_BASE #endif #endif /* TEGRA2_H */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h new file mode 100644 index 0000000000..0a7d99c585 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h @@ -0,0 +1,157 @@ +/* + * NVIDIA Tegra2 I2C controller + * + * Copyright 2010-2011 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_I2C_H_ +#define _TEGRA_I2C_H_ + +#include <asm/types.h> + +enum { + I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ + I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ +}; + +enum i2c_transaction_flags { + I2C_IS_WRITE = 0x1, /* for I2C write operation */ + I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ + I2C_USE_REPEATED_START = 0x4, /* for repeat start */ + I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ + I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ + I2C_NO_STOP = 0x20, +}; + +/* Contians the I2C transaction details */ +struct i2c_trans_info { + /* flags to indicate the transaction details */ + enum i2c_transaction_flags flags; + u32 address; /* I2C slave device address */ + u32 num_bytes; /* number of bytes to be transferred */ + /* + * Send/receive buffer. For the I2C send operation this buffer should + * be filled with the data to be sent to the slave device. For the I2C + * receive operation this buffer is filled with the data received from + * the slave device. + */ + u8 *buf; + int is_10bit_address; +}; + +struct i2c_control { + u32 tx_fifo; + u32 rx_fifo; + u32 packet_status; + u32 fifo_control; + u32 fifo_status; + u32 int_mask; + u32 int_status; +}; + +struct dvc_ctlr { + u32 ctrl1; /* 00: DVC_CTRL_REG1 */ + u32 ctrl2; /* 04: DVC_CTRL_REG2 */ + u32 ctrl3; /* 08: DVC_CTRL_REG3 */ + u32 status; /* 0C: DVC_STATUS_REG */ + u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ + u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ + u32 reserved_0[2]; /* 18: */ + u32 req; /* 20: DVC_REQ_REGISTER */ + u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ + u32 reserved_1[6]; /* 28: */ + u32 cnfg; /* 40: DVC_I2C_CNFG */ + u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ + u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ + u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ + u32 reserved_2[2]; /* 54: */ + u32 i2c_status; /* 5C: DVC_I2C_STATUS */ + struct i2c_control control; /* 60 ~ 78 */ +}; + +struct i2c_ctlr { + u32 cnfg; /* 00: I2C_I2C_CNFG */ + u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ + u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ + u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ + u32 reserved_0[2]; /* 14: */ + u32 status; /* 1C: I2C_I2C_STATUS */ + u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ + u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ + u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ + u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ + u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ + u32 reserved_1[2]; /* 34: */ + u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ + u32 reserved_2[4]; /* 40: */ + struct i2c_control control; /* 50 ~ 68 */ +}; + +/* bit fields definitions for IO Packet Header 1 format */ +#define PKT_HDR1_PROTOCOL_SHIFT 4 +#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) +#define PKT_HDR1_CTLR_ID_SHIFT 12 +#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) +#define PKT_HDR1_PKT_ID_SHIFT 16 +#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) +#define PROTOCOL_TYPE_I2C 1 + +/* bit fields definitions for IO Packet Header 2 format */ +#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 +#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) + +/* bit fields definitions for IO Packet Header 3 format */ +#define PKT_HDR3_READ_MODE_SHIFT 19 +#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 +#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) + +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ + (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) + +/* I2C_CNFG */ +#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 +#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) +#define I2C_CNFG_PACKET_MODE_SHIFT 10 +#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) + +/* I2C_SL_CNFG */ +#define I2C_SL_CNFG_NEWSL_SHIFT 2 +#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) + +/* I2C_FIFO_STATUS */ +#define TX_FIFO_FULL_CNT_SHIFT 0 +#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) +#define TX_FIFO_EMPTY_CNT_SHIFT 4 +#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) + +/* I2C_INTERRUPT_STATUS */ +#define I2C_INT_XFER_COMPLETE_SHIFT 7 +#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) +#define I2C_INT_NO_ACK_SHIFT 3 +#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) +#define I2C_INT_ARBITRATION_LOST_SHIFT 2 +#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h new file mode 100644 index 0000000000..638033be50 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/usb.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* USBx_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULP 2 +#define PTS_ICUSB_SER 3 + +#define STS (1 << 29) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Change the USB host port into host mode */ +void usb_set_host_mode(void); + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param portnum port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) + */ +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); + +/** + * Stop the current port + * + * @return 0 if ok, -1 if no port was active + */ +int tegrausb_stop_port(void); + +#endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h new file mode 100644 index 0000000000..db2ff94c62 --- /dev/null +++ b/arch/arm/include/asm/bootm.h @@ -0,0 +1,26 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef ARM_BOOTM_H +#define ARM_BOOTM_H + +#ifdef CONFIG_USB_DEVICE +extern void udc_disconnect(void); +#endif + +#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 34bec4568d..6f25948e20 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -92,6 +92,8 @@ u32 omap_boot_mode(void); /* SPL common function s*/ void spl_parse_image_header(const struct image_header *header); void omap_rev_string(void); +void spl_board_prepare_for_linux(void); +int spl_start_uboot(void); /* NAND SPL functions */ void spl_nand_load_image(void); @@ -99,6 +101,9 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +/* YMODEM SPL functions */ +void spl_ymodem_load_image(void); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 300c8fab2d..39a9550376 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -39,8 +39,6 @@ GLCOBJS += div0.o COBJS-y += board.o COBJS-y += bootm.o -COBJS-y += cache.o -COBJS-y += cache-cp15.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o COBJS-y += interrupts.o COBJS-y += reset.o @@ -48,6 +46,9 @@ SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o endif +COBJS-y += cache.o +COBJS-y += cache-cp15.o + SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index b9b35de61a..5270c11262 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -293,6 +293,14 @@ void board_init_f(ulong bootflag) } } +#ifdef CONFIG_OF_CONTROL + /* For now, put this check after the console is ready */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } +#endif + debug("monitor len: %08lX\n", gd->mon_len); /* * Ram is setup, size stored in gd !! diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 2961ab2ac6..160ba55111 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -1,4 +1,8 @@ -/* +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * - Added prep subcommand support + * - Reorganized source - modeled after powerpc version + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> @@ -29,35 +33,26 @@ #include <fdt.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/bootm.h> DECLARE_GLOBAL_DATA_PTR; -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) -static void setup_start_tag (bd_t *bd); - -# ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags (bd_t *bd); -# endif -static void setup_commandline_tag (bd_t *bd, char *commandline); - -# ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag (bd_t *bd, ulong initrd_start, - ulong initrd_end); -# endif -static void setup_end_tag (bd_t *bd); - +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) static struct tag *params; -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ - -static ulong get_sp(void); -#if defined(CONFIG_OF_LIBFDT) -static int bootm_linux_fdt(int machid, bootm_headers_t *images); #endif +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + void arch_lmb_reserve(struct lmb *lmb) { ulong sp; @@ -80,89 +75,7 @@ void arch_lmb_reserve(struct lmb *lmb) gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp); } -static void announce_and_cleanup(void) -{ - printf("\nStarting kernel ...\n\n"); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif - -#ifdef CONFIG_USB_DEVICE - { - extern void udc_disconnect(void); - udc_disconnect(); - } -#endif - cleanup_before_linux(); -} - -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) -{ - bd_t *bd = gd->bd; - char *s; - int machid = bd->bi_arch_number; - void (*kernel_entry)(int zero, int arch, uint params); - -#ifdef CONFIG_CMDLINE_TAG - char *commandline = getenv ("bootargs"); -#endif - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - s = getenv ("machid"); - if (s) { - machid = simple_strtoul (s, NULL, 16); - printf ("Using machid 0x%x from environment\n", machid); - } - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - #ifdef CONFIG_OF_LIBFDT - if (images->ft_len) - return bootm_linux_fdt(machid, images); -#endif - - kernel_entry = (void (*)(int, int, uint))images->ep; - - debug ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) kernel_entry); - -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) - setup_start_tag (bd); -#ifdef CONFIG_SERIAL_TAG - setup_serial_tag (¶ms); -#endif -#ifdef CONFIG_REVISION_TAG - setup_revision_tag (¶ms); -#endif -#ifdef CONFIG_SETUP_MEMORY_TAGS - setup_memory_tags (bd); -#endif -#ifdef CONFIG_CMDLINE_TAG - setup_commandline_tag (bd, commandline); -#endif -#ifdef CONFIG_INITRD_TAG - if (images->rd_start && images->rd_end) - setup_initrd_tag (bd, images->rd_start, images->rd_end); -#endif - setup_end_tag(bd); -#endif - - announce_and_cleanup(); - - kernel_entry(0, machid, bd->bi_boot_params); - /* does not return */ - - return 1; -} - -#if defined(CONFIG_OF_LIBFDT) static int fixup_memory_node(void *blob) { bd_t *bd = gd->bd; @@ -177,60 +90,30 @@ static int fixup_memory_node(void *blob) return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); } +#endif -static int bootm_linux_fdt(int machid, bootm_headers_t *images) +static void announce_and_cleanup(void) { - ulong rd_len; - void (*kernel_entry)(int zero, int dt_machid, void *dtblob); - ulong of_size = images->ft_len; - char **of_flat_tree = &images->ft_addr; - ulong *initrd_start = &images->initrd_start; - ulong *initrd_end = &images->initrd_end; - struct lmb *lmb = &images->lmb; - int ret; - - kernel_entry = (void (*)(int, int, void *))images->ep; - - boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); - - rd_len = images->rd_end - images->rd_start; - ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, - initrd_start, initrd_end); - if (ret) - return ret; - - ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); - if (ret) - return ret; - - debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) kernel_entry); - - fdt_chosen(*of_flat_tree, 1); - - fixup_memory_node(*of_flat_tree); - - fdt_fixup_ethernet(*of_flat_tree); - - fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); - - announce_and_cleanup(); - - kernel_entry(0, machid, *of_flat_tree); - /* does not return */ + printf("\nStarting kernel ...\n\n"); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif - return 1; -} +#ifdef CONFIG_USB_DEVICE + udc_disconnect(); #endif + cleanup_before_linux(); +} -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd) { - params = (struct tag *) bd->bi_boot_params; + params = (struct tag *)bd->bi_boot_params; params->hdr.tag = ATAG_CORE; params->hdr.size = tag_size (tag_core); @@ -241,10 +124,10 @@ static void setup_start_tag (bd_t *bd) params = tag_next (params); } - +#endif #ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags (bd_t *bd) +static void setup_memory_tags(bd_t *bd) { int i; @@ -258,10 +141,10 @@ static void setup_memory_tags (bd_t *bd) params = tag_next (params); } } -#endif /* CONFIG_SETUP_MEMORY_TAGS */ - +#endif -static void setup_commandline_tag (bd_t *bd, char *commandline) +#ifdef CONFIG_CMDLINE_TAG +static void setup_commandline_tag(bd_t *bd, char *commandline) { char *p; @@ -285,10 +168,10 @@ static void setup_commandline_tag (bd_t *bd, char *commandline) params = tag_next (params); } - +#endif #ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) +static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) { /* an ATAG_INITRD node tells the kernel where the compressed * ramdisk can be found. ATAG_RDIMG is a better name, actually. @@ -301,10 +184,10 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) params = tag_next (params); } -#endif /* CONFIG_INITRD_TAG */ +#endif #ifdef CONFIG_SERIAL_TAG -void setup_serial_tag (struct tag **tmp) +void setup_serial_tag(struct tag **tmp) { struct tag *params = *tmp; struct tag_serialnr serialnr; @@ -332,19 +215,147 @@ void setup_revision_tag(struct tag **in_params) params->u.revision.rev = rev; params = tag_next (params); } -#endif /* CONFIG_REVISION_TAG */ +#endif -static void setup_end_tag (bd_t *bd) +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +static void setup_end_tag(bd_t *bd) { params->hdr.tag = ATAG_NONE; params->hdr.size = 0; } -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +#endif -static ulong get_sp(void) +#ifdef CONFIG_OF_LIBFDT +static int create_fdt(bootm_headers_t *images) { - ulong ret; + ulong of_size = images->ft_len; + char **of_flat_tree = &images->ft_addr; + ulong *initrd_start = &images->initrd_start; + ulong *initrd_end = &images->initrd_end; + struct lmb *lmb = &images->lmb; + ulong rd_len; + int ret; - asm("mov %0, sp" : "=r"(ret) : ); - return ret; + debug("using: FDT\n"); + + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + + rd_len = images->rd_end - images->rd_start; + ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, + initrd_start, initrd_end); + if (ret) + return ret; + + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + if (ret) + return ret; + + fdt_chosen(*of_flat_tree, 1); + fixup_memory_node(*of_flat_tree); + fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + + return 0; +} +#endif + +/* Subcommand: PREP */ +static void boot_prep_linux(bootm_headers_t *images) +{ +#ifdef CONFIG_CMDLINE_TAG + char *commandline = getenv("bootargs"); +#endif + +#ifdef CONFIG_OF_LIBFDT + if (images->ft_len) { + debug("using: FDT\n"); + if (create_fdt(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } + } else +#endif + { +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) + debug("using: ATAGS\n"); + setup_start_tag(gd->bd); +#ifdef CONFIG_SERIAL_TAG + setup_serial_tag(¶ms); +#endif +#ifdef CONFIG_CMDLINE_TAG + setup_commandline_tag(gd->bd, commandline); +#endif +#ifdef CONFIG_REVISION_TAG + setup_revision_tag(¶ms); +#endif +#ifdef CONFIG_SETUP_MEMORY_TAGS + setup_memory_tags(gd->bd); +#endif +#ifdef CONFIG_INITRD_TAG + if (images->rd_start && images->rd_end) + setup_initrd_tag(gd->bd, images->rd_start, + images->rd_end); +#endif + setup_end_tag(gd->bd); +#else /* all tags */ + printf("FDT and ATAGS support not compiled in - hanging\n"); + hang(); +#endif /* all tags */ + } +} + +/* Subcommand: GO */ +static void boot_jump_linux(bootm_headers_t *images) +{ + unsigned long machid = gd->bd->bi_arch_number; + char *s; + void (*kernel_entry)(int zero, int arch, uint params); + + kernel_entry = (void (*)(int, int, uint))images->ep; + + s = getenv("machid"); + if (s) { + strict_strtoul(s, 16, &machid); + printf("Using machid 0x%lx from environment\n", machid); + } + + debug("## Transferring control to Linux (at address %08lx)" \ + "...\n", (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + announce_and_cleanup(); + kernel_entry(0, machid, gd->bd->bi_boot_params); +} + +/* Main Entry point for arm bootm implementation + * + * Modeled after the powerpc implementation + * DIFFERENCE: Instead of calling prep and go at the end + * they are called if subcommand is equal 0. + */ +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + /* No need for those on ARM */ + if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & BOOTM_STATE_OS_GO) { + boot_jump_linux(images); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images); + return 0; } |
