15 files changed, 618 insertions, 0 deletions

diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile
new file mode 100644
index 0000000000..5ce3d8a520
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile
@@ -0,0 +1,16 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
+	pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
+obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c
new file mode 100644
index 0000000000..69b172e4e7
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/bcu_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c
new file mode 100644
index 0000000000..d359b56291
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
new file mode 100644
index 0000000000..8d3435d632
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c
new file mode 100644
index 0000000000..304edfb482
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a878400, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x00000000, &phy->mr3);
+#else
+	writel(0x00000800, &phy->mr3);
+#endif
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c
new file mode 100644
index 0000000000..dd236b7e50
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/early_clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S
new file mode 100644
index 0000000000..73f0f63eba
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S
@@ -0,0 +1,29 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/sg-regs.h>
+
+#define UART_CLK		80000000
+#include <mach/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+		init_debug_uart	r0, r1, r2
+
+		/* UART Port 0 */
+		set_pinsel	70, 3, r0, r1
+		set_pinsel	71, 3, r0, r1
+
+		ldr		r0, =SG_IECTRL
+		ldr		r1, [r0]
+		orr		r1, r1, #1
+		str		r1, [r0]
+
+		mov		pc, lr
+ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
new file mode 100644
index 0000000000..4c494ffa40
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
+	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */
+
+	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
+	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */
+
+	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
+	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_SYS_I2C_UNIPHIER
+	{
+		u32 tmp;
+		tmp = readl(SG_IECTRL);
+		tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
+		writel(tmp, SG_IECTRL);
+	}
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(15, 0);	/* XNFRE_GB -> XNFRE_GB */
+	sg_set_pinsel(16, 0);	/* XNFWE_GB -> XNFWE_GB */
+	sg_set_pinsel(17, 0);	/* XFALE_GB -> NFALE_GB */
+	sg_set_pinsel(18, 0);	/* XFCLE_GB -> NFCLE_GB */
+	sg_set_pinsel(19, 0);	/* XNFWP_GB -> XFNWP_GB */
+	sg_set_pinsel(20, 0);	/* XNFCE0_GB -> XNFCE0_GB */
+	sg_set_pinsel(21, 0);	/* NANDRYBY0_GB -> NANDRYBY0_GB */
+	sg_set_pinsel(22, 0);	/* XFNCE1_GB  -> XFNCE1_GB */
+	sg_set_pinsel(23, 0);	/* NANDRYBY1_GB  -> NANDRYBY1_GB */
+	sg_set_pinsel(24, 0);	/* NFD0_GB -> NFD0_GB */
+	sg_set_pinsel(25, 0);	/* NFD1_GB -> NFD1_GB */
+	sg_set_pinsel(26, 0);	/* NFD2_GB -> NFD2_GB */
+	sg_set_pinsel(27, 0);	/* NFD3_GB -> NFD3_GB */
+	sg_set_pinsel(28, 0);	/* NFD4_GB -> NFD4_GB */
+	sg_set_pinsel(29, 0);	/* NFD5_GB -> NFD5_GB */
+	sg_set_pinsel(30, 0);	/* NFD6_GB -> NFD6_GB */
+	sg_set_pinsel(31, 0);	/* NFD7_GB -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	sg_set_pinsel(41, 0);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(42, 0);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(43, 0);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(44, 0);	/* USB1OD   -> USB1OD */
+	/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
+	/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/platdevice.c b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c
new file mode 100644
index 0000000000..aa334a1ca4
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <mach/platdevice.h>
+
+#define UART_MASTER_CLK		80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c
new file mode 100644
index 0000000000..885100747d
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+static void dpll_init(void)
+{
+	u32 tmp;
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL3
+	 * [23]    DIVN_TEST    0x1
+	 * [22:16] DIVN         0x50
+	 * [10]    FREFSEL_TEST 0x1
+	 * [9:8]   FREFSEL      0x2
+	 * [4]     ICPD_TEST    0x1
+	 * [3:0]   ICPD         0xb
+	 */
+	tmp = readl(SC_DPLLCTRL3);
+	tmp &= ~0x00ff0717;
+	tmp |= 0x00d0061b;
+	writel(tmp, SC_DPLLCTRL3);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL
+	 *                    <-1%>          <-2%>
+	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
+	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
+	 */
+	tmp = readl(SC_DPLLCTRL);
+	tmp &= ~0x3ff07fff;
+#ifdef CONFIG_DPLL_SSC_RATE_1PER
+	tmp |= 0x084018bf;
+#else
+	tmp |= 0x084031a6;
+#endif
+	writel(tmp, SC_DPLLCTRL);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL2
+	 * [31:29]  SSC_STEP     0
+	 * [27]     SSC_REG_REF  1
+	 * [26:20]  SSC_M        79     (0x4f)
+	 * [19:0]   SSC_K        964689 (0xeb851)
+	 */
+	tmp = readl(SC_DPLLCTRL2);
+	tmp &= ~0xefffffff;
+	tmp |= 0x0cfeb851;
+	writel(tmp, SC_DPLLCTRL2);
+}
+
+static void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+	dpll_init();
+	upll_init();
+	vpll_init();
+
+	/*
+	 * Wait 500 usec until dpll get stable
+	 * We wait 10 usec in upll_init() and vpll_init()
+	 * so 20 usec can be saved here.
+	 */
+	udelay(480);
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c
new file mode 100644
index 0000000000..9b8c4855e5
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/pll_spectrum.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
new file mode 100644
index 0000000000..225c0d24de
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/sbc_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
new file mode 100644
index 0000000000..fdef88e126
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
+	/*
+	 * SBCTRL0* does not need settings because PH1-sLD8 has no support for
+	 * XECS0.  The boot swap must be enabled to boot from the support card.
+	 */
+
+	if (boot_is_swapped()) {
+		/* XECS1 : boot memory if boot swap is on */
+		writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+		writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+		writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+		writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+	}
+
+	/* XECS4 : sub memory */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
+
+	/* XECS5 : peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0); /* boot memory */
+	writel(0x0900bfff, SBBASE1); /* dummy */
+	writel(0x0400bc01, SBBASE4); /* sub memory */
+	writel(0x0800bf01, SBBASE5); /* peripherals */
+
+	sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
+	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
+
+	/* dummy read to assure write process */
+	readl(SG_PINCTRL(0));
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
new file mode 100644
index 0000000000..a808289a56
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c
new file mode 100644
index 0000000000..302611e5d2
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+	writel(0x00000000, ssif_base + 0x0000b004);
+	writel(0xffffffff, ssif_base + 0x0000c004);
+	writel(0x000fffcf, ssif_base + 0x0000c008);
+	writel(0x00000001, ssif_base + 0x0000b000);
+	writel(0x00000001, ssif_base + 0x0000c000);
+	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+	writel(0x00000001, ssif_base + UMC_CPURST);
+	writel(0x00000001, ssif_base + UMC_IDSRST);
+	writel(0x00000001, ssif_base + UMC_IXMRST);
+	writel(0x00000001, ssif_base + UMC_MDMRST);
+	writel(0x00000001, ssif_base + UMC_MDDRST);
+	writel(0x00000001, ssif_base + UMC_SIORST);
+	writel(0x00000001, ssif_base + UMC_VIORST);
+	writel(0x00000001, ssif_base + UMC_FRCRST);
+	writel(0x00000001, ssif_base + UMC_RGLRST);
+	writel(0x00000001, ssif_base + UMC_AIORST);
+	writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+			      int size, int freq)
+{
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x55990b11, dramcont + UMC_CMDCTLA);
+	writel(0x16958944, dramcont + UMC_CMDCTLB);
+#else
+	writel(0x45990b11, dramcont + UMC_CMDCTLA);
+	writel(0x16958924, dramcont + UMC_CMDCTLB);
+#endif
+
+	writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+	if (size == 1)
+		writel(0x27028B0A, dramcont + UMC_INITCTLB);
+	else if (size == 2)
+		writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+	writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+	writel(0x00000b51, dramcont + UMC_DRMMR0);
+	writel(0x00000006, dramcont + UMC_DRMMR1);
+	writel(0x00000290, dramcont + UMC_DRMMR2);
+
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x00000000, dramcont + UMC_DRMMR3);
+#else
+	writel(0x00000800, dramcont + UMC_DRMMR3);
+#endif
+
+	if (size == 1)
+		writel(0x00240512, dramcont + UMC_SPCCTLA);
+	else if (size == 2)
+		writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+	writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+	writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+	writel(0x04a02000, dramcont + UMC_DATASET);
+	writel(0x00000000, ca_base + 0x2300);
+	writel(0x00400020, dramcont + UMC_DCCGCTL);
+	writel(0x00000003, dramcont + 0x7000);
+	writel(0x0000004f, dramcont + 0x8000);
+	writel(0x000000c3, dramcont + 0x8004);
+	writel(0x00000077, dramcont + 0x8008);
+	writel(0x0000003b, dramcont + UMC_DICGCTLA);
+	writel(0x020a0808, dramcont + UMC_DICGCTLB);
+	writel(0x00000004, dramcont + UMC_FLOWCTLG);
+	writel(0x80000201, ca_base + 0xc20);
+	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+	writel(0x00200000, dramcont + UMC_FLOWCTLB);
+	writel(0x00004444, dramcont + UMC_FLOWCTLC);
+	writel(0x200a0a00, dramcont + UMC_SPCSETB);
+	writel(0x00000000, dramcont + UMC_SPCSETD);
+	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+	umc_dram_init_start(dramcont0);
+	umc_dram_init_start(dramcont1);
+	umc_dram_init_poll(dramcont0);
+	umc_dram_init_poll(dramcont1);
+
+	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+	ddrphy_init(phy0_0, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_0, 0);
+	ddrphy_training(phy0_0);
+
+	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+	ddrphy_init(phy1_0, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_0, 1);
+	ddrphy_training(phy1_0);
+
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+	umc_start_ssif(ssif_base);
+
+	return 0;
+}
+
+int umc_init(void)
+{
+	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+					CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif