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-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware.h3
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap.h1
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h2
4 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index c617331854..62332f2ded 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -19,8 +19,9 @@
#ifndef __AM33XX_HARDWARE_H
#define __AM33XX_HARDWARE_H
+#include <asm/arch/omap.h>
+
/* Module base addresses */
-#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
#define UART0_BASE 0x44E09000
/* DM Timer base addresses */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index fc2b7a5a28..850f8a551d 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -30,7 +30,6 @@
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000
-#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
/* ROM code defines */
/* Boot device */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 03bd923145..d4b5076108 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -172,7 +172,6 @@ struct control_lpddr2io_regs {
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 7f05cb5b4a..9dce49ac4b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -262,8 +262,6 @@ struct omap_sys_ctrl_regs {
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
-/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/*
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