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-rw-r--r--arch/arm/imx-common/cache.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021cfed..b77548821d 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
/*
+ * Must disable the L2 before changing the latency parameters
+ * and auxiliary control register.
+ */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ /*
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
* accesses as Cacheable no-allocate.
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
}
#endif
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
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