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-rw-r--r--arch/arm/cpu/armv7/Makefile1
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c13
-rw-r--r--arch/arm/cpu/armv7/exynos/Makefile2
-rw-r--r--arch/arm/cpu/armv7/exynos/common_setup.h62
-rw-r--r--arch/arm/cpu/armv7/exynos/exynos5_setup.h3
-rw-r--r--arch/arm/cpu/armv7/exynos/lowlevel_init.c147
-rw-r--r--arch/arm/cpu/armv7/exynos/sec_boot.S128
-rw-r--r--arch/arm/cpu/armv7/exynos/soc.c35
-rw-r--r--arch/arm/cpu/armv7/lowlevel_init.S22
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c6
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c10
-rw-r--r--arch/arm/cpu/armv7/rmobile/Kconfig6
-rw-r--r--arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c1001
-rw-r--r--arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c148
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig89
-rw-r--r--arch/arm/cpu/armv7/uniphier/Makefile36
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_common.c32
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_early_init_f.c22
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_early_init_r.c15
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_late_init.c53
-rw-r--r--arch/arm/cpu/armv7/uniphier/cache_uniphier.c154
-rw-r--r--arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c229
-rw-r--r--arch/arm/cpu/armv7/uniphier/cmd_pinmon.c33
-rw-r--r--arch/arm/cpu/armv7/uniphier/cpu_info.c59
-rw-r--r--arch/arm/cpu/armv7/uniphier/ddrphy_training.c144
-rw-r--r--arch/arm/cpu/armv7/uniphier/dram_init.c16
-rw-r--r--arch/arm/cpu/armv7/uniphier/init_page_table.S26
-rw-r--r--arch/arm/cpu/armv7/uniphier/lowlevel_init.S163
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile14
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c33
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c29
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c70
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S29
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c63
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c27
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c189
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c51
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c28
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c171
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile14
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c66
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c29
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c70
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S39
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c52
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c24
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c168
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c18
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c75
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c28
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c157
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile14
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c29
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c75
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S29
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c66
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c27
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c201
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c58
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c151
-rw-r--r--arch/arm/cpu/armv7/uniphier/print_misc_info.c13
-rw-r--r--arch/arm/cpu/armv7/uniphier/reset.c26
-rw-r--r--arch/arm/cpu/armv7/uniphier/smp.S54
-rw-r--r--arch/arm/cpu/armv7/uniphier/spl.c59
-rw-r--r--arch/arm/cpu/armv7/uniphier/support_card.c225
-rw-r--r--arch/arm/cpu/armv7/uniphier/timer.c39
72 files changed, 1523 insertions, 3648 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index b228ed6a2e..ad22489e1a 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -56,6 +56,5 @@ obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_U8500) += u8500/
-obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ZYNQ) += zynq/
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 81477aa7b0..67bef23ea9 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -275,6 +275,14 @@ static void watchdog_disable(void)
;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ board_early_init_f();
+ sdram_init();
+}
+#endif
+
void s_init(void)
{
/*
@@ -290,6 +298,7 @@ void s_init(void)
setup_clocks_for_console();
uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
+ /* TODO: This does not work, gd is not available yet */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
@@ -298,9 +307,5 @@ void s_init(void)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
-#ifdef CONFIG_SPL_BUILD
- board_early_init_f();
- sdram_init();
-#endif
}
#endif
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index e207bd6af0..8542f896cf 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -7,6 +7,8 @@
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-$(CONFIG_EXYNOS5420) += sec_boot.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h
index e6318c0366..5235abb808 100644
--- a/arch/arm/cpu/armv7/exynos/common_setup.h
+++ b/arch/arm/cpu/armv7/exynos/common_setup.h
@@ -23,6 +23,8 @@
* MA 02111-1307 USA
*/
+#include <asm/arch/system.h>
+
#define DMC_OFFSET 0x10000
/*
@@ -43,3 +45,63 @@ void system_clock_init(void);
int do_lowlevel_init(void);
void sdelay(unsigned long);
+
+enum l2_cache_params {
+ CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
+ CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
+ CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
+ CACHE_DATA_RAM_SETUP = (1 << 5),
+ CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
+ CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
+ CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
+ CACHE_TAG_RAM_SETUP = (1 << 9),
+ CACHE_ECC_AND_PARITY = (1 << 21),
+ CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
+};
+
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Configure L2CTLR to get timings that keep us from hanging/crashing.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_ctlr(void)
+{
+ uint32_t val;
+
+ mrc_l2_ctlr(val);
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY_2_CYCLES |
+ CACHE_DATA_RAM_LATENCY_2_CYCLES;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ val |= CACHE_ECC_AND_PARITY |
+ CACHE_TAG_RAM_LATENCY_3_CYCLES |
+ CACHE_DATA_RAM_LATENCY_3_CYCLES;
+ }
+
+ mcr_l2_ctlr(val);
+}
+
+/*
+ * Configure L2ACTLR.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_actlr(void)
+{
+ uint32_t val;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ mrc_l2_aux_ctlr(val);
+ val |= CACHE_ENABLE_FORCE_L2_LOGIC |
+ CACHE_DISABLE_CLEAN_EVICT;
+ mcr_l2_aux_ctlr(val);
+ }
+}
+#endif
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 2eea48a0cc..9073f50f6b 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -700,6 +700,9 @@
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
/* APLL_CON1 */
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 83e1dcfc1e..120aaf8b96 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -31,7 +31,10 @@
#include <asm/arch/tzpc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/system.h>
+#include <asm/armv7.h>
#include "common_setup.h"
+#include "exynos5_setup.h"
/* These are the things we can do during low-level init */
enum {
@@ -42,6 +45,128 @@ enum {
DO_POWER = 1 << 4,
};
+#ifdef CONFIG_EXYNOS5420
+/*
+ * Power up secondary CPUs.
+ */
+static void secondary_cpu_start(void)
+{
+ v7_enable_smp(EXYNOS5420_INFORM_BASE);
+ svc32_mode_en();
+ branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+}
+
+/*
+ * This is the entry point of hotplug-in and
+ * cluster switching.
+ */
+static void low_power_start(void)
+{
+ uint32_t val, reg_val;
+
+ reg_val = readl(EXYNOS5420_SPARE_BASE);
+ if (reg_val != CPU_RST_FLAG_VAL) {
+ writel(0x0, CONFIG_LOWPOWER_FLAG);
+ branch_bx(0x0);
+ }
+
+ reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
+ if (reg_val != (uint32_t)&low_power_start) {
+ /* Store jump address as low_power_start if not present */
+ writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
+ dsb();
+ sev();
+ }
+
+ /* Set the CPU to SVC32 mode */
+ svc32_mode_en();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val >> 4);
+ val &= 0xf;
+
+ if (val == 0xf) {
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ v7_enable_l2_hazard_detect();
+ }
+#endif
+
+ /* Invalidate L1 & TLB */
+ val = 0x0;
+ mcr_tlb(val);
+ mcr_icache(val);
+
+ /* Disable MMU stuff and caches */
+ mrc_sctlr(val);
+
+ val &= ~((0x2 << 12) | 0x7);
+ val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
+ mcr_sctlr(val);
+
+ /* CPU state is hotplug or reset */
+ secondary_cpu_start();
+
+ /* Core should not enter into WFI here */
+ wfi();
+}
+
+/*
+ * Pointer to this function is stored in iRam which is used
+ * for jump and power down of a specific core.
+ */
+static void power_down_core(void)
+{
+ uint32_t tmp, core_id, core_config;
+
+ /* Get the unique core id */
+ /*
+ * Multiprocessor Affinity Register
+ * [11:8] Cluster ID
+ * [1:0] CPU ID
+ */
+ mrc_mpafr(core_id);
+ tmp = core_id & 0x3;
+ core_id = (core_id >> 6) & ~3;
+ core_id |= tmp;
+ core_id &= 0x3f;
+
+ /* Set the status of the core to low */
+ core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
+ core_config += EXYNOS5420_CPU_CONFIG_BASE;
+ writel(0x0, core_config);
+
+ /* Core enter WFI */
+ wfi();
+}
+
+/*
+ * Configurations for secondary cores are inapt at this stage.
+ * Reconfigure secondary cores. Shutdown and change the status
+ * of all cores except the primary core.
+ */
+static void secondary_cores_configure(void)
+{
+ /* Clear secondary boot iRAM base */
+ writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
+
+ /* set lowpower flag and address */
+ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
+ writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
+ writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
+ /* Store jump address for power down */
+ writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
+
+ /* Need all core power down check */
+ dsb();
+ sev();
+}
+
+extern void relocate_wait_code(void);
+#endif
+
int do_lowlevel_init(void)
{
uint32_t reset_status;
@@ -49,6 +174,28 @@ int do_lowlevel_init(void)
arch_cpu_init();
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /*
+ * Init L2 cache parameters here for use by boot and resume
+ *
+ * These are here instead of in v7_outer_cache_enable() so that the
+ * L2 cache settings get properly set even at resume time or if we're
+ * running U-Boot with the cache off. The kernel still needs us to
+ * set these for it.
+ */
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ dsb();
+ isb();
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+ relocate_wait_code();
+
+ /* Reconfigure secondary cores */
+ secondary_cores_configure();
+#endif
+
reset_status = get_reset_status();
switch (reset_status) {
diff --git a/arch/arm/cpu/armv7/exynos/sec_boot.S b/arch/arm/cpu/armv7/exynos/sec_boot.S
new file mode 100644
index 0000000000..dfc3455929
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/sec_boot.S
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+ .globl relocate_wait_code
+relocate_wait_code:
+ adr r0, code_base @ r0: source address (start)
+ adr r1, code_end @ r1: source address (end)
+ ldr r2, =0x02073000 @ r2: target address
+1:
+ ldmia r0!, {r3-r6}
+ stmia r2!, {r3-r6}
+ cmp r0, r1
+ blt 1b
+ b code_end
+ .ltorg
+/*
+ * Secondary core waits here until Primary wake it up.
+ * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
+ * This is a workaround code which is supposed to act as a
+ * substitute/supplement to the iROM code.
+ *
+ * This workaround code is relocated to the address 0x02073000
+ * because that comes out to be the last 4KB of the iRAM
+ * (Base Address - 0x02020000, Limit Address - 0x020740000).
+ *
+ * U-boot and kernel are aware of this code and flags by the simple
+ * fact that we are implementing a workaround in the last 4KB
+ * of the iRAM and we have already defined these flag and address
+ * values in both kernel and U-boot for our use.
+ */
+code_base:
+ b 1f
+/*
+ * These addresses are being used as flags in u-boot and kernel.
+ *
+ * Jump address for resume and flag to check for resume/reset:
+ * Resume address - 0x2073008
+ * Resume flag - 0x207300C
+ *
+ * Jump address for cluster switching:
+ * Switch address - 0x2073018
+ *
+ * Jump address for core hotplug:
+ * Hotplug address - 0x207301C
+ *
+ * Jump address for C2 state (Reserved for future not being used right now):
+ * C2 address - 0x2073024
+ *
+ * Managed per core status for the active cluster:
+ * CPU0 state - 0x2073028
+ * CPU1 state - 0x207302C
+ * CPU2 state - 0x2073030
+ * CPU3 state - 0x2073034
+ *
+ * Managed per core GIC status for the active cluster:
+ * CPU0 gic state - 0x2073038
+ * CPU1 gic state - 0x207303C
+ * CPU2 gic state - 0x2073040
+ * CPU3 gic state - 0x2073044
+ *
+ * Logic of the code:
+ * Step-1: Read current CPU status.
+ * Step-2: If it's a resume then continue, else jump to step 4.
+ * Step-3: Clear inform1 PMU register and jump to inform0 value.
+ * Step-4: If it's a switch, C2 or reset, get the hotplug address.
+ * Step-5: If address is not available, enter WFE.
+ * Step-6: If address is available, jump to that address.
+ */
+ nop @ for backward compatibility
+ .word 0x0 @ REG0: RESUME_ADDR
+ .word 0x0 @ REG1: RESUME_FLAG
+ .word 0x0 @ REG2
+ .word 0x0 @ REG3
+_switch_addr:
+ .word 0x0 @ REG4: SWITCH_ADDR
+_hotplug_addr:
+ .word 0x0 @ REG5: CPU1_BOOT_REG
+ .word 0x0 @ REG6
+_c2_addr:
+ .word 0x0 @ REG7: REG_C2_ADDR
+_cpu_state:
+ .word 0x1 @ CPU0_STATE : RESET
+ .word 0x2 @ CPU1_STATE : SECONDARY RESET
+ .word 0x2 @ CPU2_STATE : SECONDARY RESET
+ .word 0x2 @ CPU3_STATE : SECONDARY RESET
+_gic_state:
+ .word 0x0 @ CPU0 - GICD_IGROUPR0
+ .word 0x0 @ CPU1 - GICD_IGROUPR0
+ .word 0x0 @ CPU2 - GICD_IGROUPR0
+ .word 0x0 @ CPU3 - GICD_IGROUPR0
+1:
+ adr r0, _cpu_state
+ mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
+ and r7, r7, #0xf @ r7 = cpu id
+/* Read the current cpu state */
+ ldr r10, [r0, r7, lsl #2]
+svc_entry:
+ tst r10, #(1 << 4)
+ adrne r0, _switch_addr
+ bne wait_for_addr
+/* Clear INFORM1 */
+ ldr r0, =(0x10040000 + 0x804)
+ ldr r1, [r0]
+ cmp r1, #0x0
+ movne r1, #0x0
+ strne r1, [r0]
+/* Get INFORM0 */
+ ldrne r1, =(0x10040000 + 0x800)
+ ldrne pc, [r1]
+ tst r10, #(1 << 0)
+ ldrne pc, =0x23e00000
+ adr r0, _hotplug_addr
+wait_for_addr:
+ ldr r1, [r0]
+ cmp r1, #0x0
+ bxne r1
+ wfe
+ b wait_for_addr
+ .ltorg
+code_end:
+ mov pc, lr
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index 8c7d7d893f..0f116b141a 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -9,13 +9,6 @@
#include <asm/io.h>
#include <asm/system.h>
-enum l2_cache_params {
- CACHE_TAG_RAM_SETUP = (1 << 9),
- CACHE_DATA_RAM_SETUP = (1 << 5),
- CACHE_TAG_RAM_LATENCY = (2 << 6),
- CACHE_DATA_RAM_LATENCY = (2 << 0)
-};
-
void reset_cpu(ulong addr)
{
writel(0x1, samsung_get_base_swreset());
@@ -28,31 +21,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-/*
- * Set L2 cache parameters
- */
-static void exynos5_set_l2cache_params(void)
-{
- unsigned int val = 0;
-
- asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
-
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY |
- CACHE_DATA_RAM_LATENCY;
-
- asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-}
-
-/*
- * Sets L2 cache related parameters before enabling data cache
- */
-void v7_outer_cache_enable(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_l2cache_params();
-}
-#endif
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index f1aea05c90..427b0b1321 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -17,10 +17,17 @@
ENTRY(lowlevel_init)
/*
- * Setup a temporary stack
+ * Setup a temporary stack. Global data is not available yet.
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#ifdef CONFIG_DM
+ mov r9, #0
+#else
+ /*
+ * Set up global data for boards that still need it. This will be
+ * removed soon.
+ */
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
@@ -28,13 +35,24 @@ ENTRY(lowlevel_init)
bic sp, sp, #7
mov r9, sp
#endif
+#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
push {ip, lr}
/*
- * go setup pll, mux, memory
+ * Call the very early init function. This should do only the
+ * absolute bare minimum to get started. It should not:
+ *
+ * - set up DRAM
+ * - use global_data
+ * - clear BSS
+ * - try to start a console
+ *
+ * For boards with SPL this should be empty since SPL can do all of
+ * this init in the SPL board_init_f() function which is called
+ * immediately after this.
*/
bl s_init
pop {ip, pc}
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index cb35c198f1..6c8f3bcea4 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -128,14 +128,18 @@ void s_init(void)
do_io_settings();
#endif
prcm_init();
+}
+
#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
-#endif
}
+#endif
/*
* Routine: wait_for_command_complete
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 90d6ae7bb5..347947c4b3 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -240,8 +240,6 @@ void try_unlock_memory(void)
*****************************************************************************/
void s_init(void)
{
- int in_sdram = is_running_in_sdram();
-
watchdog_init();
try_unlock_memory();
@@ -264,10 +262,14 @@ void s_init(void)
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
+}
- if (!in_sdram)
- mem_init();
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ mem_init();
}
+#endif
/*
* Routine: misc_init_r
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 35866508a3..2b333a3d46 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -24,6 +24,9 @@ config TARGET_ALT
config TARGET_SILK
bool "Silk board"
+config TARGET_PORTER
+ bool "Porter board"
+
endchoice
config SYS_SOC
@@ -31,7 +34,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -41,5 +44,6 @@ source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
+source "board/renesas/porter/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
index 1259062a64..580aba39e1 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
@@ -135,7 +135,91 @@ enum {
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
- /* IPSR8 - IPSR16 */
+ /* IPSR8 */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+ FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+ FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+ FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+ FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+ FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+ FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+ FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+ FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+ FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+ FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+ FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+ FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+ FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+ FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+ /* IPSR9 */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+ FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+ FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+ FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+ FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+ FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+ FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+ FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+ FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+ FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+ FN_VI3_CLK_B,
+
+ /* IPSR10 */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+ FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+ FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+ FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+ FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+ /* IPSR11 */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+ FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+ FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+ FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+ FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+ FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+ FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+ FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+ FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+ FN_MOUT0,
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4,
@@ -189,11 +273,110 @@ enum {
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4,
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
-
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
+ VI1_DATA7_VI1_B7_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+ USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+ DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+ D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+ D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+ VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+ VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+ VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+ SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+ VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+ SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+ VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+ SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+ SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+ D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+ VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+ D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+ VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+ SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+ VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+ SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+ VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+ D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+ VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+ D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+ VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+ SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+ VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+ D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+ VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+ A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+ A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+ PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+ TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+ A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+ SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+ A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+ VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+ A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+ VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+ A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+ VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+ A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+ VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+ A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+ VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+ A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+ MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+ VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+ ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+ ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+ A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+ AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+ ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+ VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+ A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+ A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+ VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+ VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+ VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+ VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+ VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+ VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+ CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+ VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+ VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+ MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+ HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+ VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+ VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+ EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+ VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+ EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+ VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+ INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+ MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+ VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+ SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+ CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+ CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+ VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+ INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+ VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+ WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+ VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+ VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+ MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+ VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+ SSI_WS78_B_MARK,
+
DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
@@ -235,12 +418,189 @@ enum {
VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
MII_RXD2_MARK,
+ VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+ MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+ AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+ AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+ AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+ AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+ MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+ MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+ MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+ AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+ SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+ VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+ MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+ AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+ AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+ AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+ SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+ SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+ SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+ SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+ SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+ GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+ SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+ MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+ GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+ SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+ AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+ AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+ SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+ SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+ MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+ AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+ SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+ SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+ TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+ SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+ VI3_CLK_B_MARK,
+
+ SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+ GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+ SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+ VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+ VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+ VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+ TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+ SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+ VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+ TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+ SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+ VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+ TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+ SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+ VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+ GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+ MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+ HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+ VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+ TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+ VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+ GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+ SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+ GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+ TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+ SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+ MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+ SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+ MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+ SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+ VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+ MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+ RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+ RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+ MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+ SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+ SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+ RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+ MOUT0_MARK,
+
+ SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+ SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+ SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+ SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+ SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+ MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+ STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+ CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+ SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+ SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+ MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+ SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+ MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+ SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+ CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+ IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+ CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+ IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+ CAN_DEBUGOUT4_MARK,
+
+ SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+ LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+ SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+ DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+ BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+ SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+ LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+ FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+ CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+ SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+ CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+ SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+ LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+ STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+ TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+ BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+ FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+ STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+ CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+ STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+ SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+ SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+ AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+ DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+ REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+ MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+ SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+ DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+ TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+ HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+ LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+ SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+ MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+ SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+ LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+ CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+ SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+ MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+ HRTS0_N_C_MARK,
+
+ SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+ LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+ DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+ SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+ SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+ DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+ DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+ LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+ LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+ LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+ DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+ SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+ SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+ DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+ DU2_DG6_MARK, LCDOUT14_MARK,
+
+ MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+ DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+ MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+ ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+ USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+ TCLK1_B_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+ PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+ PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+ PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+ PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+ PINMUX_DATA(AVS1_MARK, FN_AVS1),
+ PINMUX_DATA(AVS2_MARK, FN_AVS2),
+ PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+ PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
PINMUX_IPSR_DATA(IP6_2_0, DACK0),
PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
@@ -364,12 +724,267 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+ PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+ PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+ PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+ PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+ PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+ PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+ PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+ PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+ PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+ PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+ PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+ PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+ PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+ PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+ PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+ PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+ PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+ PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+ PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+ PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+ PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+ PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+ PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+ PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+ PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+ PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+ PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+ PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+ PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+ PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+ PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+ PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+ PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+ PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+ PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+ PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+ PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+ PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+ PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+ PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+ PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+ PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+ PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+ PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+ PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+ PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+ PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+ PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+ PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+ PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+ PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+ PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+ PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+ PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+ PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+ PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+ PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+ PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+ PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+ PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+ PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+ PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+ PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+ PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+ PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+ PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+ PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+ PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+ PINMUX_IPSR_DATA(IP11_17_15, VSP),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+ PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+ PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+ PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+ PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+ PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
};
static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO_GP_ALL(),
- /*IPSR0 - IPSR5*/
+ GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS),
+ GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2),
+ GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2),
+
+ /* IPSR0 - IPSR5 */
/*IPSR6*/
GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
@@ -413,7 +1028,97 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
- /*IPSR8 - IPSR16*/
+
+ /*IPSR8*/
+ GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3),
+ GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N),
+ GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N),
+ GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N),
+ GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1),
+ GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER),
+ GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK),
+ GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV),
+ GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D),
+ GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1),
+ GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC),
+ GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO),
+ GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D),
+ GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4),
+ GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC),
+ GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT),
+ GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK),
+ GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD),
+ GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B),
+
+ /*IPSR9*/
+ GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B),
+ GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B),
+ GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B),
+ GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B),
+ GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B),
+ GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B),
+ GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B),
+ GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B),
+ GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B),
+ GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B),
+ GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN),
+ GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER),
+ GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK),
+ GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1),
+ GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B),
+ GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL),
+ GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0),
+ GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD),
+ GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP),
+ GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D),
+ GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B),
+
+ /*IPSR10*/
+ GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1),
+ GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B),
+ GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B),
+ GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK),
+ GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B),
+ GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD),
+ GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E),
+ GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B),
+ GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0),
+ GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E),
+ GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B),
+ GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1),
+ GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B),
+ GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C),
+ GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2),
+ GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK),
+ GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B),
+ GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3),
+ GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B),
+ GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B),
+ GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4),
+ GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0),
+ GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B),
+ GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B),
+
+ /*IPSR11*/
+ GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B),
+ GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B),
+ GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B),
+ GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK),
+ GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0),
+ GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1),
+ GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA),
+ GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD),
+ GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0),
+ GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5),
+ GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B),
+ GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F),
+ GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B),
+ GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D),
+ GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT),
+ GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C),
+ GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129),
+ GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0),
+
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -621,8 +1326,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_IP14_24_22,
GP_5_0_FN, FN_IP14_21_19 }
},
-
- /*IPSR0 - IPSR5*/
+ /* IPSR0 - IPSR5 */
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
/* IP6_31_29 [3] */
@@ -696,7 +1400,288 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
},
- /*IPSR8 - IPSR16*/
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2) {
+ /* IP8_31 [1] */
+ 0, 0,
+ /* IP8_30_29 [2] */
+ FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+ /* IP8_28 [1] */
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+ /* IP8_27 [1] */
+ FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ /* IP8_26 [1] */
+ FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+ /* IP8_25_24 [2] */
+ FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, FN_MII_MAGIC,
+ /* IP8_23_22 [2] */
+ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+ /* IP8_21_20 [2] */
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+ FN_MII_MDIO,
+ /* IP8_19_18 [2] */
+ FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+ /* IP8_17_16 [2] */
+ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+ /* IP8_15_14 [2] */
+ FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+ /* IP8_13_12 [2] */
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+ /* IP8_11_10 [2] */
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+ /* IP8_9_8 [2] */
+ FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+ /* IP8_7_6 [2] */
+ FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+ /* IP8_5_4 [2] */
+ FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+ /* IP8_3_2 [2] */
+ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+ /* IP8_1_0 [2] */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+ /* IP9_31_28 [4] */
+ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+ FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+ FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+ /* IP9_27_26 [2] */
+ FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+ /* IP9_25_24 [2] */
+ FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+ /* IP9_23_22 [2] */
+ FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+ /* IP9_21_20 [2] */
+ FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+ /* IP9_19_18 [2] */
+ FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+ /* IP9_17_16 [2] */
+ FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+ /* IP9_15_12 [4] */
+ FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+ FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_11_8 [4] */
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+ FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_7_6 [2] */
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+ /* IP9_5_4 [2] */
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+ /* IP9_3_2 [2] */
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+ /* IP9_1_0 [2] */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 2, 4, 3, 4, 4, 4, 4, 3, 4) {
+ /* IP10_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP10_29_26 [4] */
+ FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+ /* IP10_25_23 [3] */
+ FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+ /* IP10_22_19 [4] */
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_18_15 [4] */
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ 0, 0, 0, 0, 0, 0,
+ /* IP10_14_11 [4] */
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_10_7 [4] */
+ FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_6_4 [3] */
+ FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, 0,
+ /* IP10_3_0 [4] */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+ /* IP11_31_30 [2] */
+ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+ /* IP11_29_27 [3] */
+ FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ FN_RDS_CLK_B, 0, 0,
+ /* IP11_26_24 [3] */
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+ 0, 0, 0,
+ /* IP11_23_22 [2] */
+ FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+ /* IP11_21_18 [4] */
+ FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+ FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+ /* IP11_17_15 [3] */
+ FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+ /* IP11_14_13 [2] */
+ FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+ /* IP11_12_11 [2] */
+ FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+ /* IP11_10_9 [2] */
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+ /* IP11_8_7 [2] */
+ FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+ /* IP11_6_5 [2] */
+ FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+ /* IP11_4 [1] */
+ FN_SD3_CLK, FN_MMC1_CLK,
+ /* IP11_3_0 [4] */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+ 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+ /* SEL_SCIF1 [3] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIF1_4, 0, 0, 0,
+ /* SEL_SCIFB [2] */
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+ /* SEL_SCIFB2 [2] */
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+ /* SEL_SCIFB1 [3] */
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+ FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+ FN_SEL_SCIFB1_6, 0,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SCIFA1_3,
+ /* SEL_SCIF0 [1] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+ /* SEL_SCIFA [1] */
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ /* SEL_SOF1 [1] */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+ /* SEL_SSI7 [2] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+ /* SEL_SSI6 [1] */
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ /* SEL_SSI5 [2] */
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+ /* SEL_VI3 [1] */
+ FN_SEL_VI3_0, FN_SEL_VI3_1,
+ /* SEL_VI2 [1] */
+ FN_SEL_VI2_0, FN_SEL_VI2_1,
+ /* SEL_VI1 [1] */
+ FN_SEL_VI1_0, FN_SEL_VI1_1,
+ /* SEL_VI0 [1] */
+ FN_SEL_VI0_0, FN_SEL_VI0_1,
+ /* SEL_TSIF1 [2] */
+ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_LBS [1] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_SOF3 [1] */
+ FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+ /* SEL_SOF0 [1] */
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 2, 1, 1, 1, 1, 2, 1, 2, 1,
+ 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) {
+ /* RESEVED [2] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_TMU1 [1] */
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ /* SEL_HSCIF1 [1] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* SEL_SCIFCLK [1] */
+ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+ /* SEL_CAN0 [2] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ /* SEL_CANCLK [1] */
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ /* SEL_SCIFA2 [2] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+ /* SEL_CAN1 [1] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+ /* RESEVED [2] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_ADI [1] */
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ /* SEL_SSP [1] */
+ FN_SEL_SSP_0, FN_SEL_SSP_1,
+ /* SEL_FM [3] */
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+ /* SEL_HSCIF0 [3] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+ FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+ /* SEL_GPS [2] */
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+ /* SEL_RDS [3] */
+ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+ FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+ /* SEL_SIM [2] */
+ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+ /* SEL_SSI8 [2] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 1, 1, 2, 4, 4, 2, 2,
+ 4, 2, 3, 2, 3, 2) {
+ /* SEL_IICDVFS [1] */
+ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+ /* SEL_IIC0 [1] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* RESEVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IIC2 [3] */
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ FN_SEL_IIC2_4, 0, 0, 0,
+ /* SEL_IIC1 [2] */
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+ /* SEL_I2C2 [3] */
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C2_4, 0, 0, 0,
+ /* SEL_I2C1 [2] */
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+ },
{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
0, 0,
@@ -813,7 +1798,7 @@ static struct pinmux_info r8a7790_pinmux_info = {
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
+ .last_gpio = GPIO_FN_MOUT0,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
index e123663333..7ea5edc2e5 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
@@ -151,8 +151,18 @@ enum {
FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+ /* IPSR0 */
+ FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
+ FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
+ FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
+ FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
+ FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
+ FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
+ FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
+ FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@@ -285,8 +295,20 @@ enum {
SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
SD1_DATA2_MARK, SD1_DATA3_MARK,
+ /* IPSR0 */
+ SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
+ MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
+ SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
+ SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
+ MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
+ CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
+ CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
+ SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
+ SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
+ SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@@ -399,8 +421,55 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
+ /* IPSR0 */
+ PINMUX_IPSR_DATA(IP0_0, SD1_CD),
+ PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
+ PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
+ PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
+ PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
+ PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
+ PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
+ PINMUX_IPSR_DATA(IP0_12, MMC_D0),
+ PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
+ PINMUX_IPSR_DATA(IP0_13, MMC_D1),
+ PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
+ PINMUX_IPSR_DATA(IP0_14, MMC_D2),
+ PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
+ PINMUX_IPSR_DATA(IP0_15, MMC_D3),
+ PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
+ PINMUX_IPSR_DATA(IP0_16, MMC_D4),
+ PINMUX_IPSR_DATA(IP0_16, SD2_CD),
+ PINMUX_IPSR_DATA(IP0_17, MMC_D5),
+ PINMUX_IPSR_DATA(IP0_17, SD2_WP),
+ PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
+ PINMUX_IPSR_DATA(IP0_23_22, D0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
+ PINMUX_IPSR_DATA(IP0_24, D1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_25, D2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP0_27_26, D3),
+ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_DATA(IP0_29_28, D4),
+ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_DATA(IP0_31_30, D5),
+ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@@ -674,8 +743,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
+ /* IPSR0 */
+ GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
+ GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
+ GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
+ GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
+ GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
+ GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
+ GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
+ GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
+ GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
+ GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
+ GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
+ GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
+ GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
+
/*
- * From IPSR0 to IPSR5 have been removed because they does not use
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@@ -1017,9 +1101,63 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, FN_SD0_CMD,
GP_6_0_FN, FN_SD0_CLK }
},
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31_30 [2] */
+ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
+ /* IP0_29_28 [2] */
+ FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
+ /* IP0_27_26 [2] */
+ FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
+ /* IP0_25 [1] */
+ FN_D2, FN_SCIFA3_TXD_B,
+ /* IP0_24 [1] */
+ FN_D1, FN_SCIFA3_RXD_B,
+ /* IP0_23_22 [2] */
+ FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
+ /* IP0_21_20 [2] */
+ FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
+ /* IP0_19_18 [2] */
+ FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
+ /* IP0_17 [1] */
+ FN_MMC_D5, FN_SD2_WP,
+ /* IP0_16 [1] */
+ FN_MMC_D4, FN_SD2_CD,
+ /* IP0_15 [1] */
+ FN_MMC_D3, FN_SD2_DATA3,
+ /* IP0_14 [1] */
+ FN_MMC_D2, FN_SD2_DATA2,
+ /* IP0_13 [1] */
+ FN_MMC_D1, FN_SD2_DATA1,
+ /* IP0_12 [1] */
+ FN_MMC_D0, FN_SD2_DATA0,
+ /* IP0_11 [1] */
+ FN_MMC_CMD, FN_SD2_CMD,
+ /* IP0_10 [1] */
+ FN_MMC_CLK, FN_SD2_CLK,
+ /* IP0_9_8 [2] */
+ FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
+ /* IP0_7 [1] */
+ 0, 0,
+ /* IP0_6 [1] */
+ 0, 0,
+ /* IP0_5 [1] */
+ 0, 0,
+ /* IP0_4 [1] */
+ 0, 0,
+ /* IP0_3 [1] */
+ 0, 0,
+ /* IP0_2 [1] */
+ 0, 0,
+ /* IP0_1 [1] */
+ 0, 0,
+ /* IP0_0 [1] */
+ FN_SD1_CD, FN_CAN0_RX, }
+ },
/*
- * From IPSR0 to IPSR5 have been removed because they does not use.
+ * From IPSR1 to IPSR5 have been removed because they does not use.
*/
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
deleted file mode 100644
index 8335685e32..0000000000
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-menu "Panasonic UniPhier platform"
- depends on ARCH_UNIPHIER
-
-config SYS_SOC
- default "uniphier"
-
-config SYS_CONFIG_NAME
- default "uniphier"
-
-config UNIPHIER_SMP
- bool
-
-choice
- prompt "UniPhier SoC select"
-
-config MACH_PH1_PRO4
- bool "PH1-Pro4"
- select UNIPHIER_SMP
-
-config MACH_PH1_LD4
- bool "PH1-LD4"
-
-config MACH_PH1_SLD8
- bool "PH1-sLD8"
-
-endchoice
-
-choice
- prompt "UniPhier Support Card select"
- optional
-
-config PFC_MICRO_SUPPORT_CARD
- bool "Support card with PFC CPLD"
- help
- This option provides support for the expansion board with PFC
- original address mapping.
-
- Say Y to use the on-board UART, Ether, LED devices.
-
-config DCC_MICRO_SUPPORT_CARD
- bool "Support card with DCC CPLD"
- help
- This option provides support for the expansion board with DCC-
- arranged address mapping that is compatible with legacy UniPhier
- reference boards.
-
- Say Y to use the on-board UART, Ether, LED devices.
-
-endchoice
-
-config SYS_MALLOC_F
- default y
-
-config SYS_MALLOC_F_LEN
- default 0x400
-
-config CMD_PINMON
- bool "Enable boot mode pins monitor command"
- default y
- help
- The command "pinmon" shows the state of the boot mode pins.
- The boot mode pins are latched when the system reset is deasserted
- and determine which device the system should load a boot image from.
-
-config CMD_DDRPHY_DUMP
- bool "Enable dump command of DDR PHY parameters"
- help
- The command "ddrphy" shows the resulting parameters of DDR PHY
- training; it is useful for the evaluation of DDR PHY training.
-
-choice
- prompt "DDR3 Frequency select"
-
-config DDR_FREQ_1600
- bool "DDR3 1600"
- depends on MACH_PH1_PRO4 || MACH_PH1_LD4
-
-config DDR_FREQ_1333
- bool "DDR3 1333"
- depends on MACH_PH1_LD4 || MACH_PH1_SLD8
-
-endchoice
-
-config DDR_FREQ
- int
- default 1333 if DDR_FREQ_1333
- default 1600 if DDR_FREQ_1600
-
-endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
deleted file mode 100644
index df418dd3c4..0000000000
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-
-obj-y += lowlevel_init.o
-obj-y += init_page_table.o
-obj-y += spl.o
-obj-y += ddrphy_training.o
-
-else
-
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
-obj-y += dram_init.o
-obj-y += board_common.o
-obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
-obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
-obj-y += reset.o
-obj-y += cache_uniphier.o
-obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
-
-endif
-
-obj-y += timer.o
-
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/cpu/armv7/uniphier/board_common.c
deleted file mode 100644
index 3fb26c6d84..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_common.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/led.h>
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- led_write(U, B, O, O);
-
- return 0;
-}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
- gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
deleted file mode 100644
index d25bbaec08..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void pin_init(void);
-
-int board_early_init_f(void)
-{
- led_write(U, 0, , );
-
- pin_init();
-
- led_write(U, 1, , );
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
deleted file mode 100644
index cb7e04fc36..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/board.h>
-
-int board_early_init_r(void)
-{
- uniphier_board_late_init();
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c
deleted file mode 100644
index 0622a1e16e..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_late_init.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <../drivers/mtd/nand/denali.h>
-
-static void nand_denali_wp_disable(void)
-{
-#ifdef CONFIG_NAND_DENALI
- /*
- * Since the boot rom enables the write protection for NAND boot mode,
- * it must be disabled somewhere for "nand write", "nand erase", etc.
- * The workaround is here to not disturb the Denali NAND controller
- * driver just for a really SoC-specific thing.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-
- writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
-#endif
-}
-
-int board_late_init(void)
-{
- puts("MODE: ");
-
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
- printf("eMMC Boot\n");
- setenv("bootmode", "emmcboot");
- break;
- case BOOT_DEVICE_NAND:
- printf("NAND Boot\n");
- setenv("bootmode", "nandboot");
- nand_denali_wp_disable();
- break;
- case BOOT_DEVICE_NOR:
- printf("NOR Boot\n");
- setenv("bootmode", "norboot");
- break;
- default:
- printf("Unsupported Boot Mode\n");
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
deleted file mode 100644
index e47f977fe5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7.h>
-#include <asm/arch/ssc-regs.h>
-
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
-static void uniphier_cache_maint_all(u32 operation)
-{
- /* try until the command is successfully set */
- do {
- writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
- } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
- /* wait until the operation is completed */
- while (readl(SSCOLPQS) != SSCOLPQS_EF)
- ;
-
- /* clear the complete notification flag */
- writel(SSCOLPQS_EF, SSCOLPQS);
-
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_all(void)
-{
- uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_all(void)
-{
- uniphier_cache_maint_all(SSCOQM_CM_INV);
-}
-
-static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
-{
- /* try until the command is successfully set */
- do {
- writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
- writel(start, SSCOQAD);
- writel(size, SSCOQSZ);
-
- } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
- /* wait until the operation is completed */
- while (readl(SSCOLPQS) != SSCOLPQS_EF)
- ;
-
- /* clear the complete notification flag */
- writel(SSCOLPQS_EF, SSCOLPQS);
-}
-
-static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-{
- u32 size;
-
- /*
- * If start address is not aligned to cache-line,
- * do cache operation for the first cache-line
- */
- start = start & ~(SSC_LINE_SIZE - 1);
-
- if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
- /* this means cache operation for all range */
- uniphier_cache_maint_all(operation);
- return;
- }
-
- /*
- * If end address is not aligned to cache-line,
- * do cache operation for the last cache-line
- */
- size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
-
- while (size) {
- u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
- SSC_RANGE_OP_MAX_SIZE : size;
- __uniphier_cache_maint_range(start, chunk_size, operation);
-
- start += chunk_size;
- size -= chunk_size;
- }
-
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_range(u32 start, u32 end)
-{
- uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_range(u32 start, u32 end)
-{
- uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
-}
-
-void v7_outer_cache_enable(void)
-{
- u32 tmp;
- tmp = readl(SSCC);
- tmp |= SSCC_ON;
- writel(tmp, SSCC);
-}
-#endif
-
-void v7_outer_cache_disable(void)
-{
- u32 tmp;
- tmp = readl(SSCC);
- tmp &= ~SSCC_ON;
- writel(tmp, SSCC);
-}
-
-void wakeup_secondary(void);
-
-void enable_caches(void)
-{
- uint32_t reg;
-
-#ifdef CONFIG_UNIPHIER_SMP
- /*
- * The secondary CPU must move to DDR,
- * before L2 disable.
- * On SPL, the Page Table is located on the L2.
- */
- wakeup_secondary();
-#endif
- /*
- * UniPhier SoCs must use L2 cache for init stack pointer.
- * We disable L2 and L1 in this order.
- * If CONFIG_SYS_DCACHE_OFF is not defined,
- * caches are enabled again with a new page table.
- */
-
- /* L2 disable */
- v7_outer_cache_disable();
-
- /* L1 disable */
- reg = get_cr();
- reg &= ~(CR_C | CR_M);
- set_cr(reg);
-
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c
deleted file mode 100644
index 431d9010f1..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-/* Select either decimal or hexadecimal */
-#if 1
-#define PRINTF_FORMAT "%2d"
-#else
-#define PRINTF_FORMAT "%02x"
-#endif
-/* field separator */
-#define FS " "
-
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
-{
- return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
-}
-
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
-{
- int ch, p, dx;
- struct ddrphy __iomem *phy;
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- printf("CH%dP%dDX%d:", ch, p, dx);
- (*callback)(&phy->dx[dx]);
- printf("\n");
- }
- }
- }
-}
-
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 0; i < 10; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
-}
-
-void wbdl_dump(void)
-{
- printf("\n--- Write Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
-
- dump_loop(&__wbdl_dump);
-}
-
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 15; i < 24; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
-}
-
-void rbdl_dump(void)
-{
- printf("\n--- Read Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
-
- dump_loop(&__rbdl_dump);
-}
-
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr0 = readl(&dx->lcdlr[0]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
- u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
-
- printf(FS PRINTF_FORMAT "%sT", wld,
- wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
- }
-}
-
-void wld_dump(void)
-{
- printf("\n--- Write Leveling Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__wld_dump);
-}
-
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr2 = readl(&dx->lcdlr[2]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
- u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
-
- printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
- }
-}
-
-void dqsgd_dump(void)
-{
- printf("\n--- DQS Gating Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__dqsgd_dump);
-}
-
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
- u32 mdl = readl(&dx->mdlr);
- for (i = 0; i < 3; i++)
- printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
-}
-
-void mdl_dump(void)
-{
- printf("\n--- Master Delay Line ---\n");
- printf(" IPRD TPRD MDLD\n");
-
- dump_loop(&__mdl_dump);
-}
-
-#define REG_DUMP(x) \
- { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
- p - (u32 *)phy, #x, p, readl(p)); }
-
-void reg_dump(void)
-{
- int ch, p;
- struct ddrphy __iomem *phy;
-
- printf("\n--- DDR PHY registers ---\n");
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- printf("== Ch%d, PHY%d ==\n", ch, p);
- printf(" No: Name : Address : Data\n");
-
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
- }
- }
-}
-
-static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *cmd = argv[1];
-
- if (argc == 1)
- cmd = "all";
-
- if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
-
- if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
-
- if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
-
- if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
-
- if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
-
- if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
-
- return 0;
-}
-
-U_BOOT_CMD(
- ddr, 2, 1, do_ddr,
- "UniPhier DDR PHY parameters dumper",
- "- dump all of the followings\n"
- "ddr wbdl - dump Write Bit Delay\n"
- "ddr rbdl - dump Read Bit Delay\n"
- "ddr wld - dump Write Leveling\n"
- "ddr dqsgd - dump DQS Gating Delay\n"
- "ddr mdl - dump Master Delay Line\n"
- "ddr reg - dump registers\n"
-);
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
deleted file mode 100644
index 3c1b325976..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sbc-regs.h>
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int mode_sel, i;
-
- printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; boot_device_table[i].info; i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-
- return 0;
-}
-
-U_BOOT_CMD(
- pinmon, 1, 1, do_pinmon,
- "pin monitor",
- ""
-);
diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/cpu/armv7/uniphier/cpu_info.c
deleted file mode 100644
index 86d079ad56..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cpu_info.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-int print_cpuinfo(void)
-{
- u32 revision, type, model, rev, required_model = 1, required_rev = 1;
-
- revision = readl(SG_REVISION);
- type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
- model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
- rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
-
- puts("CPU: ");
-
- switch (type) {
- case 0x25:
- puts("PH1-sLD3 (MN2WS0220)");
- required_model = 2;
- break;
- case 0x26:
- puts("PH1-LD4 (MN2WS0250)");
- required_rev = 2;
- break;
- case 0x28:
- puts("PH1-Pro4 (MN2WS0230)");
- break;
- case 0x29:
- puts("PH1-sLD8 (MN2WS0270)");
- break;
- default:
- printf("Unknown Processor ID (0x%x)\n", revision);
- return -1;
- }
-
- if (model > 1)
- printf(" model %d", model);
-
- printf(" (rev. %d)\n", rev);
-
- if (model < required_model) {
- printf("Sorry, this model is not supported.\n");
- printf("Required model is %d.", required_model);
- return -1;
- } else if (rev < required_rev) {
- printf("Sorry, this revision is not supported.\n");
- printf("Required revision is %d.", required_rev);
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c
deleted file mode 100644
index cc8b8ad648..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
-{
- int dx;
- u32 __iomem tmp, *p;
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
- /* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
- }
-
- p = &phy->dtcr;
-
- tmp = readl(p);
- /* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
- /* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
- /* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
- writel(tmp, p);
-}
-
-struct ddrphy_init_sequence {
- char *description;
- u32 init_flag;
- u32 done_flag;
- u32 err_flag;
-};
-
-static struct ddrphy_init_sequence init_sequence[] = {
- {
- "DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
- },
- {
- "Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
- },
- {
- "Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
- },
- {
- "Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
- },
- {
- "Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
- },
- {
- "Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
- },
- {
- "Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
- },
- {
- "Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
- }
-};
-
-int ddrphy_training(struct ddrphy __iomem *phy)
-{
- int i;
- u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
- int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
- ulong start = get_timer(0);
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- init_flag |= init_sequence[i].init_flag;
- done_flag |= init_sequence[i].done_flag;
- }
-
- writel(init_flag, &phy->pir);
-
- do {
- if (--timeout < 0) {
-#ifndef CONFIG_SPL_BUILD
- printf("%s: error: timeout during DDR training\n",
- __func__);
-#endif
- return -1;
- }
- udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
- } while ((pgsr0 & done_flag) != done_flag);
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- if (pgsr0 & init_sequence[i].err_flag) {
-#ifndef CONFIG_SPL_BUILD
- printf("%s: error: %s failed\n", __func__,
- init_sequence[i].description);
-#endif
- return -1;
- }
- }
-
-#ifdef DISPLAY_ELAPSED_TIME
- printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c
deleted file mode 100644
index 4b8c938b5e..0000000000
--- a/arch/arm/cpu/armv7/uniphier/dram_init.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.S b/arch/arm/cpu/armv7/uniphier/init_page_table.S
deleted file mode 100644
index 2638bcd779..0000000000
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.S
+++ /dev/null
@@ -1,26 +0,0 @@
-#include <config.h>
-#include <linux/linkage.h>
-
-/* page table */
-#define NR_SECTIONS 4096
-#define SECTION_SHIFT 20
-#define DEVICE 0x00002002 /* Non-shareable Device */
-#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
-#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
-
- .section ".rodata"
- .align 14
-ENTRY(init_page_table)
- section = 0
- .rept NR_SECTIONS
- .if section == TEXT_SECTION || section == STACK_SECTION
- attr = NORMAL
- .else
- attr = DEVICE
- .endif
- .word (section << SECTION_SHIFT) | attr
- section = section + 1
- .endr
-END(init_page_table)
diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
deleted file mode 100644
index c208ab67a1..0000000000
--- a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/arm-mpcore.h>
-#include <asm/arch/sbc-regs.h>
-
-ENTRY(lowlevel_init)
- mov r8, lr @ persevere link reg across call
-
- /*
- * The UniPhier Boot ROM loads SPL code to the L2 cache.
- * But CPUs can only do instruction fetch now because start.S has
- * cleared C and M bits.
- * First we need to turn on MMU and Dcache again to get back
- * data access to L2.
- */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
- mcr p15, 0, r0, c1, c0, 0
-
-#ifdef CONFIG_DEBUG_LL
- bl setup_lowlevel_debug
-#endif
-
- /*
- * Now we are using the page table embedded in the Boot ROM.
- * It is not handy since it is not a straight mapped table for sLD3.
- * What we need to do next is to switch over to the page table in SPL.
- */
- ldr r3, =init_page_table @ page table must be 16KB aligned
-
- /* Disable MMU and Dcache before switching Page Table */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
- mcr p15, 0, r0, c1, c0, 0
-
- bl enable_mmu
-
-#ifdef CONFIG_UNIPHIER_SMP
- /*
- * ACTLR (Auxiliary Control Register) for Cortex-A9
- * bit[9] Parity on
- * bit[8] Alloc in one way
- * bit[7] EXCL (Exclusive cache bit)
- * bit[6] SMP
- * bit[3] Write full line of zeros mode
- * bit[2] L1 Prefetch enable
- * bit[1] L2 prefetch enable
- * bit[0] FW (Cache and TLB maintenance broadcast)
- */
- mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
- orr r0, r0, #0x41 @ enable SMP, FW bit
- mcr p15, 0, r0, c1, c0, 1
-
- /* branch by CPU ID */
- mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
- and r0, r0, #0x3
- cmp r0, #0x0
- beq primary_cpu
- ldr r1, =ROM_BOOT_ROMRSV2
- mov r0, #0
- str r0, [r1]
-0: wfe
- ldr r0, [r1]
- cmp r0, #0
- beq 0b
- bx r0 @ r0: entry point of U-Boot main for the secondary CPU
-primary_cpu:
- ldr r1, =ROM_BOOT_ROMRSV2
- ldr r0, =_start @ entry for the secondary CPU
- str r0, [r1]
- ldr r0, [r1] @ make sure str is complete before sev
- sev @ kick the sedoncary CPU
- mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
- bfc r1, #0, #13 @ clear bit 12-0
- mov r0, #-1
- str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
- mov r0, #1 @ SCU enable
- str r0, [r1, #SCU_CTRL] @ SCU Control Register
-#endif
-
- bl setup_init_ram @ RAM area for temporary stack pointer
-
- mov lr, r8 @ restore link
- mov pc, lr @ back to my caller
-ENDPROC(lowlevel_init)
-
-ENTRY(enable_mmu)
- mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
- bic r0, r0, #0x37
- orr r0, r0, #0x20 @ disable TTBR1
- mcr p15, 0, r0, c2, c0, 2
-
- orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
- mcr p15, 0, r0, c2, c0, 0 @ TTBR0
-
- mov r0, #0
- mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
-
- mov r0, #-1 @ manager for all domains (No permission check)
- mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
-
- dsb
- isb
- /*
- * MMU on:
- * TLBs was already invalidated in "../start.S"
- * So, we don't need to invalidate it here.
- */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
- mcr p15, 0, r0, c1, c0, 0
-
- mov pc, lr
-ENDPROC(enable_mmu)
-
-#include <asm/arch/ssc-regs.h>
-
-#define BOOT_RAM_SIZE (SSC_WAY_SIZE)
-#define BOOT_WAY_BITS (0x00000100) /* way 8 */
-
-ENTRY(setup_init_ram)
- /*
- * Touch to zero for the boot way
- */
-0:
- /*
- * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
- */
- ldr r0, = 0x00408006 @ touch to zero with address range
- ldr r1, = SSCOQM
- str r0, [r1]
- ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
- ldr r1, = SSCOQAD
- str r0, [r1]
- ldr r0, = BOOT_RAM_SIZE
- ldr r1, = SSCOQSZ
- str r0, [r1]
- ldr r0, = BOOT_WAY_BITS
- ldr r1, = SSCOQWN
- str r0, [r1]
- ldr r1, = SSCOPPQSEF
- ldr r0, [r1]
- cmp r0, #0 @ check if the command is successfully set
- bne 0b @ try again if an error occurres
-
- ldr r1, = SSCOLPQS
-1:
- ldr r0, [r1]
- cmp r0, #0x4
- bne 1b @ wait until the operation is completed
- str r0, [r1] @ clear the complete notification flag
-
- mov pc, lr
-ENDPROC(setup_init_ram)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
deleted file mode 100644
index 72f46636fd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
deleted file mode 100644
index 85f37f299b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/bcu-regs.h>
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void bcu_init(void)
-{
- int shift;
-
- writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
-
- /* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
deleted file mode 100644
index d359b56291..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c
deleted file mode 100644
index 60fc5ad6ea..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8253c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a82dbc0, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000800, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
deleted file mode 100644
index c0778a0abb..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 85, 1, r0, r1
- set_pinsel 88, 1, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
deleted file mode 100644
index a7429402f3..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
- sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
-
- sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
- sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
-
- sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
- sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
deleted file mode 100644
index 9d51299308..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 36864000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
- {
- .base = 0x5a820100,
- },
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
deleted file mode 100644
index b83582fee7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT (DPLLCTRL.bit[29:20])
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x000f0000;
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unknown frequency"
-#endif
-
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
- tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
deleted file mode 100644
index 837b2a891b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
deleted file mode 100644
index 4839c943c7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE3);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* enable access to sub memory when boot swap is on */
- sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
- sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
deleted file mode 100644
index 2cc5df608f..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 0x1;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
deleted file mode 100644
index bbc3dcb3da..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- if (freq == 1333) {
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x000FF0FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- } else if (freq == 1600) {
- writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
- writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
- writel(0x5101387F, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x2F030D3F, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x43030D3F, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- }
-
- writel(0x00000006, dramcont + UMC_DRMMR1);
-
- if (freq == 1333)
- writel(0x00000290, dramcont + UMC_DRMMR2);
- else if (freq == 1600)
- writel(0x00000298, dramcont + UMC_DRMMR2);
-
- writel(0x00000800, dramcont + UMC_DRMMR3);
-
- if (freq == 1333) {
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- } else if (freq == 1600) {
- if (size == 1)
- writel(0x002B0617, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- }
-
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
deleted file mode 100644
index e330fda1ed..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
deleted file mode 100644
index c31b74badd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sg-regs.h>
-#include <asm/arch/sbc-regs.h>
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
-};
-
-int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 spl_boot_device(void)
-{
- int boot_mode;
-
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
deleted file mode 100644
index c5d1f606cf..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000000, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
deleted file mode 100644
index a793b7c118..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 73728000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CLK_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 127, 0, r0, r1
- set_pinsel 128, 0, r0, r1
-
- ldr r0, =SG_LOADPINCTRL
- mov r1, #1
- str r1, [r0]
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
deleted file mode 100644
index 4e3d47615b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
- sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
- sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
- sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
- sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
- sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
- sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
deleted file mode 100644
index 31ee2a2100..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 73728000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
deleted file mode 100644
index 1db90f88a0..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT ( DPLLCTRL.bit[29:20] )
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~(0x000f0000);
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unsupported frequency"
-#endif
-
- /*
- * Set Moduration rate
- * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
- */
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~0x00008000;
-#else
- tmp |= 0x00008000;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void stop_mpll(void)
-{
- u32 tmp;
-
- tmp = readl(SC_MPLLOSCCTL);
-
- if (!(tmp & SC_MPLLOSCCTL_MPLLST))
- return; /* already stopped */
-
- tmp &= ~SC_MPLLOSCCTL_MPLLEN;
- writel(tmp, SC_MPLLOSCCTL);
-
- while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
- ;
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- /* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-#if defined(CONFIG_MACH_PH1_PRO4)
- /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
- return;
-#endif
-
- /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
- /* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* wait 1 usec */
- udelay(1);
-
- /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- stop_mpll();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 1 usec in vpll_init() so 1 usec can be saved here.
- */
- udelay(499);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
deleted file mode 100644
index 4538d1af44..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void enable_dpll_ssc(void)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
deleted file mode 100644
index 3c82a1aca4..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x3effffff: memory bank (31MB)
- * 0x03f00000-0x3fffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0400bc01, SBBASE1); /* sub memory */
- writel(0x0800bf01, SBBASE3); /* peripherals */
-
-#if !defined(CONFIG_SPL_BUILD)
- sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
- sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
- writel(0x00000001, SG_LOADPINCTRL);
-
-#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
deleted file mode 100644
index b7c4b10969..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 1 << 6;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
deleted file mode 100644
index 2d1bde6f13..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000001, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x07ffffff, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
-
- writel(0x03010100, ssif_base + UMC_HDMCHSEL);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DVCCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
- writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_HDMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_HDDRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_GIORST);
- writel(0x00000001, ssif_base + UMC_HD2RST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_DVCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_VPERST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
- writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
- writel(0x5101387f, dramcont + UMC_INITCTLA);
- writel(0x43030d3f, dramcont + UMC_INITCTLB);
- writel(0x00ff00ff, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000298, dramcont + UMC_DRMMR2);
- writel(0x00000000, dramcont + UMC_DRMMR3);
- writel(0x003f0617, dramcont + UMC_SPCCTLA);
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
- writel(0x04060802, dramcont + UMC_WDATACTL_D0);
- writel(0x04060802, dramcont + UMC_WDATACTL_D1);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x0000000f, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x00000000, dramcont + 0x0060);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00010000, dramcont + UMC_SPCSETD);
- writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
- void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_1, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_1, 1);
- ddrphy_training(phy0_1);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 0);
- ddrphy_training(phy1_0);
-
- writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_1, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_1, 1);
- ddrphy_training(phy1_1);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
- (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
- ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
- (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
-/* OK */
-#else
- #error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
deleted file mode 100644
index 72f46636fd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
- pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
deleted file mode 100644
index 69b172e4e7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/bcu_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
deleted file mode 100644
index d359b56291..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
- tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
- | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
- | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c
deleted file mode 100644
index a5eafef9a8..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, &phy->mr3);
-#else
- writel(0x00000800, &phy->mr3);
-#endif
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
deleted file mode 100644
index a413e5fd8a..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK 80000000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 70, 3, r0, r1
- set_pinsel 71, 3, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
deleted file mode 100644
index 5e80335b58..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
- sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
-
- sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
-
- sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
- sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_SYS_I2C_UNIPHIER
- {
- u32 tmp;
- tmp = readl(SG_IECTRL);
- tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
- writel(tmp, SG_IECTRL);
- }
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
-#endif
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
deleted file mode 100644
index ea0691dd67..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK 80000000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
- {
- .base = 0x5a800100,
- },
- {
- .base = 0x5a810100,
- },
- {
- .base = 0x5a820100,
- },
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
deleted file mode 100644
index 4b82700f44..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-static void dpll_init(void)
-{
- u32 tmp;
- /*
- * Set DPLL SSC parameters for DPLLCTRL3
- * [23] DIVN_TEST 0x1
- * [22:16] DIVN 0x50
- * [10] FREFSEL_TEST 0x1
- * [9:8] FREFSEL 0x2
- * [4] ICPD_TEST 0x1
- * [3:0] ICPD 0xb
- */
- tmp = readl(SC_DPLLCTRL3);
- tmp &= ~0x00ff0717;
- tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL
- * <-1%> <-2%>
- * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
- * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
- tmp |= 0x084018bf;
-#else
- tmp |= 0x084031a6;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL2
- * [31:29] SSC_STEP 0
- * [27] SSC_REG_REF 1
- * [26:20] SSC_M 79 (0x4f)
- * [19:0] SSC_K 964689 (0xeb851)
- */
- tmp = readl(SC_DPLLCTRL2);
- tmp &= ~0xefffffff;
- tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
deleted file mode 100644
index 9b8c4855e5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
deleted file mode 100644
index 5efee9c505..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
-#if !defined(CONFIG_SPL_BUILD)
- /* XECS0 : dummy */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
- /* XECS1 : boot memory (always boot swap = on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS4 : sub memory */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
- /* XECS5 : peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0900bfff, SBBASE1); /* dummy */
- writel(0x0400bc01, SBBASE4); /* sub memory */
- writel(0x0800bf01, SBBASE5); /* peripherals */
-
- sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
- sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
- /* dummy read to assure write process */
- readl(SG_PINCTRL(33));
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
deleted file mode 100644
index a808289a56..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
deleted file mode 100644
index 2fbc73ab03..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
-#ifdef CONFIG_DDR_STANDARD
- writel(0x55990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
-
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000290, dramcont + UMC_DRMMR2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, dramcont + UMC_DRMMR3);
-#else
- writel(0x00000800, dramcont + UMC_DRMMR3);
-#endif
-
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000004f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000077, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/print_misc_info.c b/arch/arm/cpu/armv7/uniphier/print_misc_info.c
deleted file mode 100644
index 69cfab519f..0000000000
--- a/arch/arm/cpu/armv7/uniphier/print_misc_info.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/board.h>
-
-int misc_init_f(void)
-{
- return check_support_card();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c
deleted file mode 100644
index 50d1fed647..0000000000
--- a/arch/arm/cpu/armv7/uniphier/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void reset_cpu(unsigned long ignored)
-{
- u32 tmp;
-
- writel(5, SC_IRQTIMSET); /* default value */
-
- tmp = readl(SC_SLFRSTSEL);
- tmp &= ~0x3; /* mask [1:0] */
- tmp |= 0x0; /* XRST reboot */
- writel(tmp, SC_SLFRSTSEL);
-
- tmp = readl(SC_SLFRSTCTL);
- tmp |= 0x1;
- writel(tmp, SC_SLFRSTCTL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/cpu/armv7/uniphier/smp.S
deleted file mode 100644
index 25ba981cea..0000000000
--- a/arch/arm/cpu/armv7/uniphier/smp.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2013 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/sbc-regs.h>
-
-/* Entry point of U-Boot main program for the secondary CPU */
-LENTRY(secondary_entry)
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
- mcr p15, 0, r0, c1, c0, 0
- mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
- mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
- dsb
- led_write(C,0,,)
- ldr r1, =ROM_BOOT_ROMRSV2
- mov r0, #0
- str r0, [r1]
-0: wfe
- ldr r4, [r1] @ r4: entry point for secondary CPUs
- cmp r4, #0
- beq 0b
- led_write(C, P, U, 1)
- bx r4 @ secondary CPUs jump to linux
-ENDPROC(secondary_entry)
-
-ENTRY(wakeup_secondary)
- ldr r1, =ROM_BOOT_ROMRSV2
-0: ldr r0, [r1]
- cmp r0, #0
- bne 0b
-
- /* set entry address and send event to the secondary CPU */
- ldr r0, =secondary_entry
- str r0, [r1]
- ldr r0, [r1] @ make sure store is complete
- mov r0, #0x100
-0: subs r0, r0, #1 @ I don't know the reason, but without this wait
- bne 0b @ fails to wake up the secondary CPU
- sev
-
- /* wait until the secondary CPU reach to secondary_entry */
-0: ldr r0, [r1]
- cmp r0, #0
- bne 0b
- bx lr
-ENDPROC(wakeup_secondary)
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
deleted file mode 100644
index 8a4eafc266..0000000000
--- a/arch/arm/cpu/armv7/uniphier/spl.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/compiler.h>
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-int umc_init(void);
-void enable_dpll_ssc(void);
-
-void spl_board_init(void)
-{
- bcu_init();
-
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(L, 0, , );
-
- clkrst_init();
-
- led_write(L, 1, , );
-
- {
- int res;
-
- res = umc_init();
- if (res < 0) {
- while (1)
- ;
- }
- }
- led_write(L, 2, , );
-
- enable_dpll_ssc();
-
- led_write(L, 3, , );
-}
diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c
deleted file mode 100644
index 443224c451..0000000000
--- a/arch/arm/cpu/armv7/uniphier/support_card.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/board.h>
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-
-#define PFC_MICRO_SUPPORT_CARD_RESET \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define PFC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
-/*
- * 0: reset deassert, 1: reset
- *
- * bit[0]: LAN, I2C, LED
- * bit[1]: UART
- */
-void support_card_reset_deassert(void)
-{
- writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-void support_card_reset(void)
-{
- writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
- printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-
-#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
-#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
-#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
-#define DCC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
-
-void support_card_reset_deassert(void)
-{
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-void support_card_reset(void)
-{
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
-
- if (revision >= 0x67) {
- printf("(DCC CPLD version 3.%d.%d)\n",
- revision >> 4, revision & 0xf);
- return 0;
- } else {
- printf("(DCC CPLD unknown version)\n");
- return -1;
- }
-}
-#endif
-
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
-void support_card_init(void)
-{
- /*
- * After power on, we need to keep the LAN controller in reset state
- * for a while. (200 usec)
- * Fortunatelly, enough wait time is already inserted in pll_init()
- * function. So we do not have to wait here.
- */
- support_card_reset_deassert();
-}
-
-#if defined(CONFIG_SMC911X)
-#include <netdev.h>
-
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-#include <mtd/cfi_flash.h>
-#include <asm/arch/sbc-regs.h>
-
-struct memory_bank {
- phys_addr_t base;
- unsigned long size;
-};
-
-static int mem_is_flash(const struct memory_bank *mem)
-{
- const int loop = 128;
- u32 *scratch_addr;
- u32 saved_value;
- int ret = 1;
- int i;
-
- /* just in case, use the tail of the memory bank */
- scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
- sizeof(u32) * loop, MAP_NOCACHE);
-
- for (i = 0; i < loop; i++, scratch_addr++) {
- saved_value = readl(scratch_addr);
- writel(~saved_value, scratch_addr);
- if (readl(scratch_addr) != saved_value) {
- /* We assume no memory or SRAM here. */
- writel(saved_value, scratch_addr);
- ret = 0;
- break;
- }
- }
-
- unmap_physmem(scratch_addr, MAP_NOCACHE);
-
- return ret;
-}
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /* {address, size} */
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x02000000, 0x01f00000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x01f00000},
-};
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x04000000, 0x02000000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x02000000},
- {0x04000000, 0x02000000},
-};
-#endif
-
-static const struct memory_bank
-*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
-
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i]->base;
-}
-
-unsigned long cfi_flash_bank_size(int i)
-{
- return flash_banks_list[i]->size;
-}
-
-static void detect_num_flash_banks(void)
-{
- const struct memory_bank *memory_bank, *end;
-
- cfi_flash_num_flash_banks = 0;
-
- if (boot_is_swapped()) {
- memory_bank = memory_banks_boot_swap_on;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
- } else {
- memory_bank = memory_banks_boot_swap_off;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
- }
-
- for (; memory_bank < end; memory_bank++) {
- if (cfi_flash_num_flash_banks >=
- CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
- break;
-
- if (mem_is_flash(memory_bank)) {
- flash_banks_list[cfi_flash_num_flash_banks] =
- memory_bank;
-
- debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
- memory_bank->base, memory_bank->size);
- cfi_flash_num_flash_banks++;
- }
- }
-
- debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
-}
-#else /* ONFIG_SYS_NO_FLASH */
-void detect_num_flash_banks(void)
-{
-};
-#endif /* ONFIG_SYS_NO_FLASH */
-
-void support_card_late_init(void)
-{
- detect_num_flash_banks();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/cpu/armv7/uniphier/timer.c
deleted file mode 100644
index 6edc0842a9..0000000000
--- a/arch/arm/cpu/armv7/uniphier/timer.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/arm-mpcore.h>
-
-#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
-
-static void *get_global_timer_base(void)
-{
- void *val;
-
- asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
-
- return val + GLOBAL_TIMER_OFFSET;
-}
-
-unsigned long timer_read_counter(void)
-{
- /*
- * ARM 64bit Global Timer is too much for our purpose.
- * We use only lower 32 bit of the timer counter.
- */
- return readl(get_global_timer_base() + GTIMER_CNT_L);
-}
-
-int timer_init(void)
-{
- /* enable timer */
- writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
-
- return 0;
-}
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