diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
22 files changed, 0 insertions, 8018 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5a76100406..6769d8fbfe 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -41,7 +41,6 @@ obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ -obj-$(CONFIG_ARCH_EXYNOS) += exynos/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig deleted file mode 100644 index 37b89b0013..0000000000 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ /dev/null @@ -1,93 +0,0 @@ -if ARCH_EXYNOS - -choice - prompt "EXYNOS board select" - optional - -config TARGET_SMDKV310 - select SUPPORT_SPL - bool "Exynos4210 SMDKV310 board" - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_TRATS - bool "Exynos4210 Trats board" - -config TARGET_S5PC210_UNIVERSAL - bool "EXYNOS4210 Universal C210 board" - -config TARGET_ORIGEN - bool "Exynos4412 Origen board" - select SUPPORT_SPL - -config TARGET_TRATS2 - bool "Exynos4412 Trat2 board" - -config TARGET_ODROID - bool "Exynos4412 Odroid board" - -config TARGET_ODROID_XU3 - bool "Exynos5422 Odroid board" - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_ARNDALE - bool "Exynos5250 Arndale board" - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_SMDK5250 - bool "SMDK5250 board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_SNOW - bool "Snow board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_SPRING - bool "Spring board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_SMDK5420 - bool "SMDK5420 board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_PEACH_PI - bool "Peach Pi board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -config TARGET_PEACH_PIT - bool "Peach Pit board" - select SUPPORT_SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - -endchoice - -config SYS_SOC - default "exynos" - -source "board/samsung/smdkv310/Kconfig" -source "board/samsung/trats/Kconfig" -source "board/samsung/universal_c210/Kconfig" -source "board/samsung/origen/Kconfig" -source "board/samsung/trats2/Kconfig" -source "board/samsung/odroid/Kconfig" -source "board/samsung/arndale/Kconfig" -source "board/samsung/smdk5250/Kconfig" -source "board/samsung/smdk5420/Kconfig" - -endif diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile deleted file mode 100644 index 8542f896cf..0000000000 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (C) 2009 Samsung Electronics -# Minkyu Kang <mk7.kang@samsung.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o - -obj-$(CONFIG_EXYNOS5420) += sec_boot.o - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o -obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o -obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o -obj-y += spl_boot.o -obj-y += lowlevel_init.o -endif diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c deleted file mode 100644 index 1c6baa14b2..0000000000 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ /dev/null @@ -1,1776 +0,0 @@ -/* - * Copyright (C) 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/clk.h> -#include <asm/arch/periph.h> - -#define PLL_DIV_1024 1024 -#define PLL_DIV_65535 65535 -#define PLL_DIV_65536 65536 -/* * - * This structure is to store the src bit, div bit and prediv bit - * positions of the peripheral clocks of the src and div registers - */ -struct clk_bit_info { - enum periph_id id; - int32_t src_mask; - int32_t div_mask; - int32_t prediv_mask; - int8_t src_bit; - int8_t div_bit; - int8_t prediv_bit; -}; - -static struct clk_bit_info exynos5_bit_info[] = { - /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */ - {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1}, - {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1}, - {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1}, - {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1}, - {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0}, - {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8}, - {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24}, - {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8}, - {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8}, - {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24}, - {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8}, - {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24}, - {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4}, - {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16}, - {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4}, - {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16}, - {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8}, - {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1}, - {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1}, - {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1}, - {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1}, - {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1}, - - {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1}, -}; - -static struct clk_bit_info exynos542x_bit_info[] = { - /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */ - {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1}, - {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1}, - {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1}, - {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1}, - {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8}, - {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16}, - {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24}, - {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1}, - {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1}, - {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1}, - {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1}, - {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4}, - {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16}, - {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0}, - {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8}, - {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1}, - {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1}, - {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1}, - {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1}, - {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1}, - {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1}, - - {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1}, -}; - -/* Epll Clock division values to achive different frequency output */ -static struct set_epll_con_val exynos5_epll_div[] = { - { 192000000, 0, 48, 3, 1, 0 }, - { 180000000, 0, 45, 3, 1, 0 }, - { 73728000, 1, 73, 3, 3, 47710 }, - { 67737600, 1, 90, 4, 3, 20762 }, - { 49152000, 0, 49, 3, 3, 9961 }, - { 45158400, 0, 45, 3, 3, 10381 }, - { 180633600, 0, 45, 3, 1, 10381 } -}; - -/* exynos: return pll clock frequency */ -static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) -{ - unsigned long m, p, s = 0, mask, fout; - unsigned int div; - unsigned int freq; - /* - * APLL_CON: MIDV [25:16] - * MPLL_CON: MIDV [25:16] - * EPLL_CON: MIDV [24:16] - * VPLL_CON: MIDV [24:16] - * BPLL_CON: MIDV [25:16]: Exynos5 - */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || - pllreg == SPLL) - mask = 0x3ff; - else - mask = 0x1ff; - - m = (r >> 16) & mask; - - /* PDIV [13:8] */ - p = (r >> 8) & 0x3f; - /* SDIV [2:0] */ - s = r & 0x7; - - freq = CONFIG_SYS_CLK_FREQ; - - if (pllreg == EPLL || pllreg == RPLL) { - k = k & 0xffff; - /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s))); - } else if (pllreg == VPLL) { - k = k & 0xfff; - - /* - * Exynos4210 - * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) - * - * Exynos4412 - * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV) - * - * Exynos5250 - * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) - */ - if (proid_is_exynos4210()) - div = PLL_DIV_1024; - else if (proid_is_exynos4412()) - div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420() - || proid_is_exynos5800()) - div = PLL_DIV_65536; - else - return 0; - - fout = (m + k / div) * (freq / (p * (1 << s))); - } else { - /* - * Exynos4412 / Exynos5250 - * FOUT = MDIV * FIN / (PDIV * 2^SDIV) - * - * Exynos4210 - * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1)) - */ - if (proid_is_exynos4210()) - fout = m * (freq / (p * (1 << (s - 1)))); - else - fout = m * (freq / (p * (1 << s))); - } - return fout; -} - -/* exynos4: return pll clock frequency */ -static unsigned long exynos4_get_pll_clk(int pllreg) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - - return exynos_get_pll_clk(pllreg, r, k); -} - -/* exynos4x12: return pll clock frequency */ -static unsigned long exynos4x12_get_pll_clk(int pllreg) -{ - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - - return exynos_get_pll_clk(pllreg, r, k); -} - -/* exynos5: return pll clock frequency */ -static unsigned long exynos5_get_pll_clk(int pllreg) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long r, k = 0, fout; - unsigned int pll_div2_sel, fout_sel; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - case BPLL: - r = readl(&clk->bpll_con0); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - - fout = exynos_get_pll_clk(pllreg, r, k); - - /* According to the user manual, in EVT1 MPLL and BPLL always gives - * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL || pllreg == BPLL) { - pll_div2_sel = readl(&clk->pll_div2_sel); - - switch (pllreg) { - case MPLL: - fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) - & MPLL_FOUT_SEL_MASK; - break; - case BPLL: - fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) - & BPLL_FOUT_SEL_MASK; - break; - default: - fout_sel = -1; - break; - } - - if (fout_sel == 0) - fout /= 2; - } - - return fout; -} - -/* exynos542x: return pll clock frequency */ -static unsigned long exynos542x_get_pll_clk(int pllreg) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - case BPLL: - r = readl(&clk->bpll_con0); - break; - case RPLL: - r = readl(&clk->rpll_con0); - k = readl(&clk->rpll_con1); - break; - case SPLL: - r = readl(&clk->spll_con0); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - - return exynos_get_pll_clk(pllreg, r, k); -} - -static struct clk_bit_info *get_clk_bit_info(int peripheral) -{ - int i; - struct clk_bit_info *info; - - if (proid_is_exynos5420() || proid_is_exynos5800()) - info = exynos542x_bit_info; - else - info = exynos5_bit_info; - - for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { - if (info[i].id == peripheral) - break; - } - - if (info[i].id == PERIPH_ID_NONE) - debug("ERROR: Peripheral ID %d not found\n", peripheral); - - return &info[i]; -} - -static unsigned long exynos5_get_periph_rate(int peripheral) -{ - struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); - unsigned long sclk = 0; - unsigned int src = 0, div = 0, sub_div = 0; - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric0); - break; - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric3); - break; - case PERIPH_ID_I2S0: - src = readl(&clk->src_mau); - div = sub_div = readl(&clk->div_mau); - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - src = readl(&clk->src_peric1); - div = sub_div = readl(&clk->div_peric1); - break; - case PERIPH_ID_SPI2: - src = readl(&clk->src_peric1); - div = sub_div = readl(&clk->div_peric2); - break; - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - src = readl(&clk->sclk_src_isp); - div = sub_div = readl(&clk->sclk_div_isp); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - src = readl(&clk->src_fsys); - div = sub_div = readl(&clk->div_fsys1); - break; - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - src = readl(&clk->src_fsys); - div = sub_div = readl(&clk->div_fsys2); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - src = EXYNOS_SRC_MPLL; - div = readl(&clk->div_top1); - sub_div = readl(&clk->div_top0); - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - }; - - if (bit_info->src_bit >= 0) - src = (src >> bit_info->src_bit) & bit_info->src_mask; - - switch (src) { - case EXYNOS_SRC_MPLL: - sclk = exynos5_get_pll_clk(MPLL); - break; - case EXYNOS_SRC_EPLL: - sclk = exynos5_get_pll_clk(EPLL); - break; - case EXYNOS_SRC_VPLL: - sclk = exynos5_get_pll_clk(VPLL); - break; - default: - debug("%s: EXYNOS_SRC %d not supported\n", __func__, src); - return 0; - } - - /* Clock divider ratio for this peripheral */ - if (bit_info->div_bit >= 0) - div = (div >> bit_info->div_bit) & bit_info->div_mask; - - /* Clock pre-divider ratio for this peripheral */ - if (bit_info->prediv_bit >= 0) - sub_div = (sub_div >> bit_info->prediv_bit) - & bit_info->prediv_mask; - - /* Calculate and return required clock rate */ - return (sclk / (div + 1)) / (sub_div + 1); -} - -static unsigned long exynos542x_get_periph_rate(int peripheral) -{ - struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); - unsigned long sclk = 0; - unsigned int src = 0, div = 0, sub_div = 0; - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric0); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - src = readl(&clk->src_peric1); - div = readl(&clk->div_peric1); - sub_div = readl(&clk->div_peric4); - break; - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - src = readl(&clk->src_isp); - div = readl(&clk->div_isp1); - sub_div = readl(&clk->div_isp1); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - case PERIPH_ID_I2C8: - case PERIPH_ID_I2C9: - case PERIPH_ID_I2C10: - src = EXYNOS542X_SRC_MPLL; - div = readl(&clk->div_top1); - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - }; - - if (bit_info->src_bit >= 0) - src = (src >> bit_info->src_bit) & bit_info->src_mask; - - switch (src) { - case EXYNOS542X_SRC_MPLL: - sclk = exynos542x_get_pll_clk(MPLL); - break; - case EXYNOS542X_SRC_SPLL: - sclk = exynos542x_get_pll_clk(SPLL); - break; - case EXYNOS542X_SRC_EPLL: - sclk = exynos542x_get_pll_clk(EPLL); - break; - case EXYNOS542X_SRC_RPLL: - sclk = exynos542x_get_pll_clk(RPLL); - break; - default: - debug("%s: EXYNOS542X_SRC %d not supported", __func__, src); - return 0; - } - - /* Clock divider ratio for this peripheral */ - if (bit_info->div_bit >= 0) - div = (div >> bit_info->div_bit) & bit_info->div_mask; - - /* Clock pre-divider ratio for this peripheral */ - if (bit_info->prediv_bit >= 0) - sub_div = (sub_div >> bit_info->prediv_bit) - & bit_info->prediv_mask; - - /* Calculate and return required clock rate */ - return (sclk / (div + 1)) / (sub_div + 1); -} - -unsigned long clock_get_periph_rate(int peripheral) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos542x_get_periph_rate(peripheral); - return exynos5_get_periph_rate(peripheral); - } else { - return 0; - } -} - -/* exynos4: return ARM clock frequency */ -static unsigned long exynos4_get_arm_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long div; - unsigned long armclk; - unsigned int core_ratio; - unsigned int core2_ratio; - - div = readl(&clk->div_cpu0); - - /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ - core_ratio = (div >> 0) & 0x7; - core2_ratio = (div >> 28) & 0x7; - - armclk = get_pll_clk(APLL) / (core_ratio + 1); - armclk /= (core2_ratio + 1); - - return armclk; -} - -/* exynos4x12: return ARM clock frequency */ -static unsigned long exynos4x12_get_arm_clk(void) -{ - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); - unsigned long div; - unsigned long armclk; - unsigned int core_ratio; - unsigned int core2_ratio; - - div = readl(&clk->div_cpu0); - - /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ - core_ratio = (div >> 0) & 0x7; - core2_ratio = (div >> 28) & 0x7; - - armclk = get_pll_clk(APLL) / (core_ratio + 1); - armclk /= (core2_ratio + 1); - - return armclk; -} - -/* exynos5: return ARM clock frequency */ -static unsigned long exynos5_get_arm_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long div; - unsigned long armclk; - unsigned int arm_ratio; - unsigned int arm2_ratio; - - div = readl(&clk->div_cpu0); - - /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ - arm_ratio = (div >> 0) & 0x7; - arm2_ratio = (div >> 28) & 0x7; - - armclk = get_pll_clk(APLL) / (arm_ratio + 1); - armclk /= (arm2_ratio + 1); - - return armclk; -} - -/* exynos4: return pwm clock frequency */ -static unsigned long exynos4_get_pwm_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int sel; - unsigned int ratio; - - if (s5p_get_cpu_rev() == 0) { - /* - * CLK_SRC_PERIL0 - * PWM_SEL [27:24] - */ - sel = readl(&clk->src_peril0); - sel = (sel >> 24) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_PERIL3 - * PWM_RATIO [3:0] - */ - ratio = readl(&clk->div_peril3); - ratio = ratio & 0xf; - } else if (s5p_get_cpu_rev() == 1) { - sclk = get_pll_clk(MPLL); - ratio = 8; - } else - return 0; - - pclk = sclk / (ratio + 1); - - return pclk; -} - -/* exynos4x12: return pwm clock frequency */ -static unsigned long exynos4x12_get_pwm_clk(void) -{ - unsigned long pclk, sclk; - unsigned int ratio; - - sclk = get_pll_clk(MPLL); - ratio = 8; - - pclk = sclk / (ratio + 1); - - return pclk; -} - -/* exynos4: return uart clock frequency */ -static unsigned long exynos4_get_uart_clk(int dev_index) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIL0 - * UART0_SEL [3:0] - * UART1_SEL [7:4] - * UART2_SEL [8:11] - * UART3_SEL [12:15] - * UART4_SEL [16:19] - * UART5_SEL [23:20] - */ - sel = readl(&clk->src_peril0); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_PERIL0 - * UART0_RATIO [3:0] - * UART1_RATIO [7:4] - * UART2_RATIO [8:11] - * UART3_RATIO [12:15] - * UART4_RATIO [16:19] - * UART5_RATIO [23:20] - */ - ratio = readl(&clk->div_peril0); - ratio = (ratio >> (dev_index << 2)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - -/* exynos4x12: return uart clock frequency */ -static unsigned long exynos4x12_get_uart_clk(int dev_index) -{ - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIL0 - * UART0_SEL [3:0] - * UART1_SEL [7:4] - * UART2_SEL [8:11] - * UART3_SEL [12:15] - * UART4_SEL [16:19] - */ - sel = readl(&clk->src_peril0); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_PERIL0 - * UART0_RATIO [3:0] - * UART1_RATIO [7:4] - * UART2_RATIO [8:11] - * UART3_RATIO [12:15] - * UART4_RATIO [16:19] - */ - ratio = readl(&clk->div_peril0); - ratio = (ratio >> (dev_index << 2)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - -static unsigned long exynos4_get_mmc_clk(int dev_index) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel, ratio, pre_ratio; - int shift = 0; - - sel = readl(&clk->src_fsys); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - switch (dev_index) { - case 0: - case 1: - ratio = readl(&clk->div_fsys1); - pre_ratio = readl(&clk->div_fsys1); - break; - case 2: - case 3: - ratio = readl(&clk->div_fsys2); - pre_ratio = readl(&clk->div_fsys2); - break; - case 4: - ratio = readl(&clk->div_fsys3); - pre_ratio = readl(&clk->div_fsys3); - break; - default: - return 0; - } - - if (dev_index == 1 || dev_index == 3) - shift = 16; - - ratio = (ratio >> shift) & 0xf; - pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; - uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); - - return uclk; -} - -/* exynos4: set the mmc clock */ -static void exynos4_set_mmc_clk(int dev_index, unsigned int div) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int addr, clear_bit, set_bit; - - /* - * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] - * CLK_DIV_FSYS3 - * MMC4_RATIO [3:0] - */ - if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; - clear_bit = MASK_PRE_RATIO(dev_index); - set_bit = SET_PRE_RATIO(dev_index, div); - } else if (dev_index == 4) { - addr = (unsigned int)&clk->div_fsys3; - dev_index -= 4; - /* MMC4 is controlled with the MMC4_RATIO value */ - clear_bit = MASK_RATIO(dev_index); - set_bit = SET_RATIO(dev_index, div); - } else { - addr = (unsigned int)&clk->div_fsys2; - dev_index -= 2; - clear_bit = MASK_PRE_RATIO(dev_index); - set_bit = SET_PRE_RATIO(dev_index, div); - } - - clrsetbits_le32(addr, clear_bit, set_bit); -} - -/* exynos5: set the mmc clock */ -static void exynos5_set_mmc_clk(int dev_index, unsigned int div) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int addr; - - /* - * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] - */ - if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; - } else { - addr = (unsigned int)&clk->div_fsys2; - dev_index -= 2; - } - - clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), - (div & 0xff) << ((dev_index << 4) + 8)); -} - -/* exynos5: set the mmc clock */ -static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned int addr; - unsigned int shift; - - /* - * CLK_DIV_FSYS1 - * MMC0_RATIO [9:0] - * MMC1_RATIO [19:10] - * MMC2_RATIO [29:20] - */ - addr = (unsigned int)&clk->div_fsys1; - shift = dev_index * 10; - - clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); -} - -/* get_lcd_clk: return lcd clock frequency */ -static unsigned long exynos4_get_lcd_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_LCD0 - * FIMD0_SEL [3:0] - */ - sel = readl(&clk->src_lcd0); - sel = sel & 0xf; - - /* - * 0x6: SCLK_MPLL - * 0x7: SCLK_EPLL - * 0x8: SCLK_VPLL - */ - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_LCD0 - * FIMD0_RATIO [3:0] - */ - ratio = readl(&clk->div_lcd0); - ratio = ratio & 0xf; - - pclk = sclk / (ratio + 1); - - return pclk; -} - -/* get_lcd_clk: return lcd clock frequency */ -static unsigned long exynos5_get_lcd_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_LCD0 - * FIMD0_SEL [3:0] - */ - sel = readl(&clk->src_disp1_0); - sel = sel & 0xf; - - /* - * 0x6: SCLK_MPLL - * 0x7: SCLK_EPLL - * 0x8: SCLK_VPLL - */ - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_LCD0 - * FIMD0_RATIO [3:0] - */ - ratio = readl(&clk->div_disp1_0); - ratio = ratio & 0xf; - - pclk = sclk / (ratio + 1); - - return pclk; -} - -static unsigned long exynos5420_get_lcd_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_DISP10 - * FIMD1_SEL [4] - * 0: SCLK_RPLL - * 1: SCLK_SPLL - */ - sel = readl(&clk->src_disp10); - sel &= (1 << 4); - - if (sel) - sclk = get_pll_clk(SPLL); - else - sclk = get_pll_clk(RPLL); - - /* - * CLK_DIV_DISP10 - * FIMD1_RATIO [3:0] - */ - ratio = readl(&clk->div_disp10); - ratio = ratio & 0xf; - - pclk = sclk / (ratio + 1); - - return pclk; -} - -static unsigned long exynos5800_get_lcd_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_DISP10 - * CLKMUX_FIMD1 [6:4] - */ - sel = (readl(&clk->src_disp10) >> 4) & 0x7; - - if (sel) { - /* - * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into - * PLLs. The first element is a placeholder to bypass the - * default settig. - */ - const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, - RPLL}; - sclk = get_pll_clk(reg_map[sel]); - } else - sclk = CONFIG_SYS_CLK_FREQ; - /* - * CLK_DIV_DISP10 - * FIMD1_RATIO [3:0] - */ - ratio = readl(&clk->div_disp10) & 0xf; - - return sclk / (ratio + 1); -} - -void exynos4_set_lcd_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - - /* - * CLK_GATE_BLOCK - * CLK_CAM [0] - * CLK_TV [1] - * CLK_MFC [2] - * CLK_G3D [3] - * CLK_LCD0 [4] - * CLK_LCD1 [5] - * CLK_GPS [7] - */ - setbits_le32(&clk->gate_block, 1 << 4); - - /* - * CLK_SRC_LCD0 - * FIMD0_SEL [3:0] - * MDNIE0_SEL [7:4] - * MDNIE_PWM0_SEL [8:11] - * MIPI0_SEL [12:15] - * set lcd0 src clock 0x6: SCLK_MPLL - */ - clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); - - /* - * CLK_GATE_IP_LCD0 - * CLK_FIMD0 [0] - * CLK_MIE0 [1] - * CLK_MDNIE0 [2] - * CLK_DSIM0 [3] - * CLK_SMMUFIMD0 [4] - * CLK_PPMULCD0 [5] - * Gating all clocks for FIMD0 - */ - setbits_le32(&clk->gate_ip_lcd0, 1 << 0); - - /* - * CLK_DIV_LCD0 - * FIMD0_RATIO [3:0] - * MDNIE0_RATIO [7:4] - * MDNIE_PWM0_RATIO [11:8] - * MDNIE_PWM_PRE_RATIO [15:12] - * MIPI0_RATIO [19:16] - * MIPI0_PRE_RATIO [23:20] - * set fimd ratio - */ - clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); -} - -void exynos5_set_lcd_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - /* - * CLK_GATE_BLOCK - * CLK_CAM [0] - * CLK_TV [1] - * CLK_MFC [2] - * CLK_G3D [3] - * CLK_LCD0 [4] - * CLK_LCD1 [5] - * CLK_GPS [7] - */ - setbits_le32(&clk->gate_block, 1 << 4); - - /* - * CLK_SRC_LCD0 - * FIMD0_SEL [3:0] - * MDNIE0_SEL [7:4] - * MDNIE_PWM0_SEL [8:11] - * MIPI0_SEL [12:15] - * set lcd0 src clock 0x6: SCLK_MPLL - */ - clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); - - /* - * CLK_GATE_IP_LCD0 - * CLK_FIMD0 [0] - * CLK_MIE0 [1] - * CLK_MDNIE0 [2] - * CLK_DSIM0 [3] - * CLK_SMMUFIMD0 [4] - * CLK_PPMULCD0 [5] - * Gating all clocks for FIMD0 - */ - setbits_le32(&clk->gate_ip_disp1, 1 << 0); - - /* - * CLK_DIV_LCD0 - * FIMD0_RATIO [3:0] - * MDNIE0_RATIO [7:4] - * MDNIE_PWM0_RATIO [11:8] - * MDNIE_PWM_PRE_RATIO [15:12] - * MIPI0_RATIO [19:16] - * MIPI0_PRE_RATIO [23:20] - * set fimd ratio - */ - clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); -} - -void exynos5420_set_lcd_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned int cfg; - - /* - * CLK_SRC_DISP10 - * FIMD1_SEL [4] - * 0: SCLK_RPLL - * 1: SCLK_SPLL - */ - cfg = readl(&clk->src_disp10); - cfg &= ~(0x1 << 4); - cfg |= (0 << 4); - writel(cfg, &clk->src_disp10); - - /* - * CLK_DIV_DISP10 - * FIMD1_RATIO [3:0] - */ - cfg = readl(&clk->div_disp10); - cfg &= ~(0xf << 0); - cfg |= (0 << 0); - writel(cfg, &clk->div_disp10); -} - -void exynos5800_set_lcd_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned int cfg; - - /* - * Use RPLL for pixel clock - * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] - * ================== - * 111: SCLK_RPLL - */ - cfg = readl(&clk->src_disp10) | (0x7 << 4); - writel(cfg, &clk->src_disp10); - - /* - * CLK_DIV_DISP10 - * FIMD1_RATIO [3:0] - */ - clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); -} - -void exynos4_set_mipi_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - - /* - * CLK_SRC_LCD0 - * FIMD0_SEL [3:0] - * MDNIE0_SEL [7:4] - * MDNIE_PWM0_SEL [8:11] - * MIPI0_SEL [12:15] - * set mipi0 src clock 0x6: SCLK_MPLL - */ - clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); - - /* - * CLK_SRC_MASK_LCD0 - * FIMD0_MASK [0] - * MDNIE0_MASK [4] - * MDNIE_PWM0_MASK [8] - * MIPI0_MASK [12] - * set src mask mipi0 0x1: Unmask - */ - setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); - - /* - * CLK_GATE_IP_LCD0 - * CLK_FIMD0 [0] - * CLK_MIE0 [1] - * CLK_MDNIE0 [2] - * CLK_DSIM0 [3] - * CLK_SMMUFIMD0 [4] - * CLK_PPMULCD0 [5] - * Gating all clocks for MIPI0 - */ - setbits_le32(&clk->gate_ip_lcd0, 1 << 3); - - /* - * CLK_DIV_LCD0 - * FIMD0_RATIO [3:0] - * MDNIE0_RATIO [7:4] - * MDNIE_PWM0_RATIO [11:8] - * MDNIE_PWM_PRE_RATIO [15:12] - * MIPI0_RATIO [19:16] - * MIPI0_PRE_RATIO [23:20] - * set mipi ratio - */ - clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); -} - -int exynos5_set_epll_clk(unsigned long rate) -{ - unsigned int epll_con, epll_con_k; - unsigned int i; - unsigned int lockcnt; - unsigned int start; - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - epll_con = readl(&clk->epll_con0); - epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << - EPLL_CON0_LOCK_DET_EN_SHIFT) | - EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | - EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT | - EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT); - - for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { - if (exynos5_epll_div[i].freq_out == rate) - break; - } - - if (i == ARRAY_SIZE(exynos5_epll_div)) - return -1; - - epll_con_k = exynos5_epll_div[i].k_dsm << 0; - epll_con |= exynos5_epll_div[i].en_lock_det << - EPLL_CON0_LOCK_DET_EN_SHIFT; - epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; - epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; - epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; - - /* - * Required period ( in cycles) to genarate a stable clock output. - * The maximum clock time can be up to 3000 * PDIV cycles of PLLs - * frequency input (as per spec) - */ - lockcnt = 3000 * exynos5_epll_div[i].p_div; - - writel(lockcnt, &clk->epll_lock); - writel(epll_con, &clk->epll_con0); - writel(epll_con_k, &clk->epll_con1); - - start = get_timer(0); - - while (!(readl(&clk->epll_con0) & - (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { - if (get_timer(start) > TIMEOUT_EPLL_LOCK) { - debug("%s: Timeout waiting for EPLL lock\n", __func__); - return -1; - } - } - return 0; -} - -int exynos5_set_i2s_clk_source(unsigned int i2s_id) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass(); - - if (i2s_id == 0) { - setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL); - clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK, - (CLK_SRC_SCLK_EPLL)); - setbits_le32(audio_ass, AUDIO_CLKMUX_ASS); - } else if (i2s_id == 1) { - clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, - (CLK_SRC_SCLK_EPLL)); - } else { - return -1; - } - return 0; -} - -int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, - unsigned int dst_frq, - unsigned int i2s_id) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int div; - - if ((dst_frq == 0) || (src_frq == 0)) { - debug("%s: Invalid requency input for prescaler\n", __func__); - debug("src frq = %d des frq = %d ", src_frq, dst_frq); - return -1; - } - - div = (src_frq / dst_frq); - if (i2s_id == 0) { - if (div > AUDIO_0_RATIO_MASK) { - debug("%s: Frequency ratio is out of range\n", - __func__); - debug("src frq = %d des frq = %d ", src_frq, dst_frq); - return -1; - } - clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, - (div & AUDIO_0_RATIO_MASK)); - } else if (i2s_id == 1) { - if (div > AUDIO_1_RATIO_MASK) { - debug("%s: Frequency ratio is out of range\n", - __func__); - debug("src frq = %d des frq = %d ", src_frq, dst_frq); - return -1; - } - clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, - (div & AUDIO_1_RATIO_MASK)); - } else { - return -1; - } - return 0; -} - -/** - * Linearly searches for the most accurate main and fine stage clock scalars - * (divisors) for a specified target frequency and scalar bit sizes by checking - * all multiples of main_scalar_bits values. Will always return scalars up to or - * slower than target. - * - * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32 - * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32 - * @param input_freq Clock frequency to be scaled in Hz - * @param target_freq Desired clock frequency in Hz - * @param best_fine_scalar Pointer to store the fine stage divisor - * - * @return best_main_scalar Main scalar for desired frequency or -1 if none - * found - */ -static int clock_calc_best_scalar(unsigned int main_scaler_bits, - unsigned int fine_scalar_bits, unsigned int input_rate, - unsigned int target_rate, unsigned int *best_fine_scalar) -{ - int i; - int best_main_scalar = -1; - unsigned int best_error = target_rate; - const unsigned int cap = (1 << fine_scalar_bits) - 1; - const unsigned int loops = 1 << main_scaler_bits; - - debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, - target_rate, cap); - - assert(best_fine_scalar != NULL); - assert(main_scaler_bits <= fine_scalar_bits); - - *best_fine_scalar = 1; - - if (input_rate == 0 || target_rate == 0) - return -1; - - if (target_rate >= input_rate) - return 1; - - for (i = 1; i <= loops; i++) { - const unsigned int effective_div = - max(min(input_rate / i / target_rate, cap), 1U); - const unsigned int effective_rate = input_rate / i / - effective_div; - const int error = target_rate - effective_rate; - - debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div, - effective_rate, error); - - if (error >= 0 && error <= best_error) { - best_error = error; - best_main_scalar = i; - *best_fine_scalar = effective_div; - } - } - - return best_main_scalar; -} - -static int exynos5_set_spi_clk(enum periph_id periph_id, - unsigned int rate) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - int main; - unsigned int fine; - unsigned shift, pre_shift; - unsigned mask = 0xff; - u32 *reg; - - main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); - if (main < 0) { - debug("%s: Cannot set clock rate for periph %d", - __func__, periph_id); - return -1; - } - main = main - 1; - fine = fine - 1; - - switch (periph_id) { - case PERIPH_ID_SPI0: - reg = &clk->div_peric1; - shift = 0; - pre_shift = 8; - break; - case PERIPH_ID_SPI1: - reg = &clk->div_peric1; - shift = 16; - pre_shift = 24; - break; - case PERIPH_ID_SPI2: - reg = &clk->div_peric2; - shift = 0; - pre_shift = 8; - break; - case PERIPH_ID_SPI3: - reg = &clk->sclk_div_isp; - shift = 0; - pre_shift = 4; - break; - case PERIPH_ID_SPI4: - reg = &clk->sclk_div_isp; - shift = 12; - pre_shift = 16; - break; - default: - debug("%s: Unsupported peripheral ID %d\n", __func__, - periph_id); - return -1; - } - clrsetbits_le32(reg, mask << shift, (main & mask) << shift); - clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift); - - return 0; -} - -static int exynos5420_set_spi_clk(enum periph_id periph_id, - unsigned int rate) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - int main; - unsigned int fine; - unsigned shift, pre_shift; - unsigned div_mask = 0xf, pre_div_mask = 0xff; - u32 *reg; - u32 *pre_reg; - - main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); - if (main < 0) { - debug("%s: Cannot set clock rate for periph %d", - __func__, periph_id); - return -1; - } - main = main - 1; - fine = fine - 1; - - switch (periph_id) { - case PERIPH_ID_SPI0: - reg = &clk->div_peric1; - shift = 20; - pre_reg = &clk->div_peric4; - pre_shift = 8; - break; - case PERIPH_ID_SPI1: - reg = &clk->div_peric1; - shift = 24; - pre_reg = &clk->div_peric4; - pre_shift = 16; - break; - case PERIPH_ID_SPI2: - reg = &clk->div_peric1; - shift = 28; - pre_reg = &clk->div_peric4; - pre_shift = 24; - break; - case PERIPH_ID_SPI3: - reg = &clk->div_isp1; - shift = 16; - pre_reg = &clk->div_isp1; - pre_shift = 0; - break; - case PERIPH_ID_SPI4: - reg = &clk->div_isp1; - shift = 20; - pre_reg = &clk->div_isp1; - pre_shift = 8; - break; - default: - debug("%s: Unsupported peripheral ID %d\n", __func__, - periph_id); - return -1; - } - - clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); - clrsetbits_le32(pre_reg, pre_div_mask << pre_shift, - (fine & pre_div_mask) << pre_shift); - - return 0; -} - -static unsigned long exynos4_get_i2c_clk(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long sclk, aclk_100; - unsigned int ratio; - - sclk = get_pll_clk(APLL); - - ratio = (readl(&clk->div_top)) >> 4; - ratio &= 0xf; - aclk_100 = sclk / (ratio + 1); - return aclk_100; -} - -unsigned long get_pll_clk(int pllreg) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos542x_get_pll_clk(pllreg); - return exynos5_get_pll_clk(pllreg); - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) - return exynos4x12_get_pll_clk(pllreg); - return exynos4_get_pll_clk(pllreg); - } - - return 0; -} - -unsigned long get_arm_clk(void) -{ - if (cpu_is_exynos5()) { - return exynos5_get_arm_clk(); - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) - return exynos4x12_get_arm_clk(); - return exynos4_get_arm_clk(); - } - - return 0; -} - -unsigned long get_i2c_clk(void) -{ - if (cpu_is_exynos5()) - return clock_get_periph_rate(PERIPH_ID_I2C0); - else if (cpu_is_exynos4()) - return exynos4_get_i2c_clk(); - - return 0; -} - -unsigned long get_pwm_clk(void) -{ - if (cpu_is_exynos5()) { - return clock_get_periph_rate(PERIPH_ID_PWM0); - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) - return exynos4x12_get_pwm_clk(); - return exynos4_get_pwm_clk(); - } - - return 0; -} - -unsigned long get_uart_clk(int dev_index) -{ - enum periph_id id; - - switch (dev_index) { - case 0: - id = PERIPH_ID_UART0; - break; - case 1: - id = PERIPH_ID_UART1; - break; - case 2: - id = PERIPH_ID_UART2; - break; - case 3: - id = PERIPH_ID_UART3; - break; - default: - debug("%s: invalid UART index %d", __func__, dev_index); - return -1; - } - - if (cpu_is_exynos5()) { - return clock_get_periph_rate(id); - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) - return exynos4x12_get_uart_clk(dev_index); - return exynos4_get_uart_clk(dev_index); - } - - return 0; -} - -unsigned long get_mmc_clk(int dev_index) -{ - enum periph_id id; - - switch (dev_index) { - case 0: - id = PERIPH_ID_SDMMC0; - break; - case 1: - id = PERIPH_ID_SDMMC1; - break; - case 2: - id = PERIPH_ID_SDMMC2; - break; - case 3: - id = PERIPH_ID_SDMMC3; - break; - default: - debug("%s: invalid MMC index %d", __func__, dev_index); - return -1; - } - - if (cpu_is_exynos5()) - return clock_get_periph_rate(id); - else if (cpu_is_exynos4()) - return exynos4_get_mmc_clk(dev_index); - - return 0; -} - -void set_mmc_clk(int dev_index, unsigned int div) -{ - /* If want to set correct value, it needs to substract one from div.*/ - if (div > 0) - div -= 1; - - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - exynos5420_set_mmc_clk(dev_index, div); - else - exynos5_set_mmc_clk(dev_index, div); - } else if (cpu_is_exynos4()) { - exynos4_set_mmc_clk(dev_index, div); - } -} - -unsigned long get_lcd_clk(void) -{ - if (cpu_is_exynos4()) { - return exynos4_get_lcd_clk(); - } else if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) - return exynos5420_get_lcd_clk(); - else if (proid_is_exynos5800()) - return exynos5800_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); - } - - return 0; -} - -void set_lcd_clk(void) -{ - if (cpu_is_exynos4()) { - exynos4_set_lcd_clk(); - } else if (cpu_is_exynos5()) { - if (proid_is_exynos5250()) - exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) - exynos5420_set_lcd_clk(); - else - exynos5800_set_lcd_clk(); - } -} - -void set_mipi_clk(void) -{ - if (cpu_is_exynos4()) - exynos4_set_mipi_clk(); -} - -int set_spi_clk(int periph_id, unsigned int rate) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_set_spi_clk(periph_id, rate); - return exynos5_set_spi_clk(periph_id, rate); - } - - return 0; -} - -int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, - unsigned int i2s_id) -{ - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id); - - return 0; -} - -int set_i2s_clk_source(unsigned int i2s_id) -{ - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_source(i2s_id); - - return 0; -} - -int set_epll_clk(unsigned long rate) -{ - if (cpu_is_exynos5()) - return exynos5_set_epll_clk(rate); - - return 0; -} diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h deleted file mode 100644 index fce502f45a..0000000000 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Clock initialization routines - * - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __EXYNOS_CLOCK_INIT_H -#define __EXYNOS_CLOCK_INIT_H - -enum { -#ifdef CONFIG_EXYNOS5420 - MEM_TIMINGS_MSR_COUNT = 5, -#else - MEM_TIMINGS_MSR_COUNT = 4, -#endif -}; - -/* These are the ratio's for configuring ARM clock */ -struct arm_clk_ratios { - unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ - - unsigned apll_mdiv; - unsigned apll_pdiv; - unsigned apll_sdiv; - - unsigned arm2_ratio; - unsigned apll_ratio; - unsigned pclk_dbg_ratio; - unsigned atb_ratio; - unsigned periph_ratio; - unsigned acp_ratio; - unsigned cpud_ratio; - unsigned arm_ratio; -}; - -/* These are the memory timings for a particular memory type and speed */ -struct mem_timings { - enum mem_manuf mem_manuf; /* Memory manufacturer */ - enum ddr_mode mem_type; /* Memory type */ - unsigned frequency_mhz; /* Frequency of memory in MHz */ - - /* Here follow the timing parameters for the selected memory */ - unsigned apll_mdiv; - unsigned apll_pdiv; - unsigned apll_sdiv; - unsigned mpll_mdiv; - unsigned mpll_pdiv; - unsigned mpll_sdiv; - unsigned cpll_mdiv; - unsigned cpll_pdiv; - unsigned cpll_sdiv; - unsigned gpll_mdiv; - unsigned gpll_pdiv; - unsigned gpll_sdiv; - unsigned epll_mdiv; - unsigned epll_pdiv; - unsigned epll_sdiv; - unsigned vpll_mdiv; - unsigned vpll_pdiv; - unsigned vpll_sdiv; - unsigned bpll_mdiv; - unsigned bpll_pdiv; - unsigned bpll_sdiv; - unsigned kpll_mdiv; - unsigned kpll_pdiv; - unsigned kpll_sdiv; - unsigned dpll_mdiv; - unsigned dpll_pdiv; - unsigned dpll_sdiv; - unsigned ipll_mdiv; - unsigned ipll_pdiv; - unsigned ipll_sdiv; - unsigned spll_mdiv; - unsigned spll_pdiv; - unsigned spll_sdiv; - unsigned rpll_mdiv; - unsigned rpll_pdiv; - unsigned rpll_sdiv; - unsigned pclk_cdrex_ratio; - unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; - - unsigned timing_ref; - unsigned timing_row; - unsigned timing_data; - unsigned timing_power; - - /* DQS, DQ, DEBUG offsets */ - unsigned phy0_dqs; - unsigned phy1_dqs; - unsigned phy0_dq; - unsigned phy1_dq; - unsigned phy0_tFS; - unsigned phy1_tFS; - unsigned phy0_pulld_dqs; - unsigned phy1_pulld_dqs; - - unsigned lpddr3_ctrl_phy_reset; - unsigned ctrl_start_point; - unsigned ctrl_inc; - unsigned ctrl_start; - unsigned ctrl_dll_on; - unsigned ctrl_ref; - - unsigned ctrl_force; - unsigned ctrl_rdlat; - unsigned ctrl_bstlen; - - unsigned fp_resync; - unsigned iv_size; - unsigned dfi_init_start; - unsigned aref_en; - - unsigned rd_fetch; - - unsigned zq_mode_dds; - unsigned zq_mode_term; - unsigned zq_mode_noterm; /* 1 to allow termination disable */ - - unsigned memcontrol; - unsigned memconfig; - - unsigned membaseconfig0; - unsigned membaseconfig1; - unsigned prechconfig_tp_cnt; - unsigned dpwrdn_cyc; - unsigned dsref_cyc; - unsigned concontrol; - /* Channel and Chip Selection */ - uint8_t dmc_channels; /* number of memory channels */ - uint8_t chips_per_channel; /* number of chips per channel */ - uint8_t chips_to_configure; /* number of chips to configure */ - uint8_t send_zq_init; /* 1 to send this command */ - unsigned impedance; /* drive strength impedeance */ - uint8_t gate_leveling_enable; /* check gate leveling is enabled */ - uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ -}; - -/** - * Get the correct memory timings for our selected memory type and speed. - * - * This function can be called from SPL or the main U-Boot. - * - * @return pointer to the memory timings that we should use - */ -struct mem_timings *clock_get_mem_timings(void); - -/* - * Initialize clock for the device - */ -void system_clock_init(void); - -/* - * Set clock divisor value for booting from EMMC. - */ -void emmc_boot_clk_div_set(void); -#endif diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c deleted file mode 100644 index 584e4bac09..0000000000 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Clock Initialization for board based on EXYNOS4210 - * - * Copyright (C) 2013 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clk.h> -#include <asm/arch/clock.h> -#include "common_setup.h" -#include "exynos4_setup.h" - -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -void system_clock_init(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - - writel(CLK_SRC_CPU_VAL, &clk->src_cpu); - - sdelay(0x10000); - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(CLK_SRC_DMC_VAL, &clk->src_dmc); - writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); - writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); - writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); - writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); - writel(CLK_SRC_CAM_VAL, &clk->src_cam); - writel(CLK_SRC_MFC_VAL, &clk->src_mfc); - writel(CLK_SRC_G3D_VAL, &clk->src_g3d); - writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0); - - sdelay(0x10000); - - writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); - writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); - writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); - writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); - writel(CLK_DIV_TOP_VAL, &clk->div_top); - writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); - writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); - writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); - writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); - writel(CLK_DIV_CAM_VAL, &clk->div_cam); - writel(CLK_DIV_MFC_VAL, &clk->div_mfc); - writel(CLK_DIV_G3D_VAL, &clk->div_g3d); - writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0); - - /* Set PLL locktime */ - writel(PLL_LOCKTIME, &clk->apll_lock); - writel(PLL_LOCKTIME, &clk->mpll_lock); - writel(PLL_LOCKTIME, &clk->epll_lock); - writel(PLL_LOCKTIME, &clk->vpll_lock); - - writel(APLL_CON1_VAL, &clk->apll_con1); - writel(APLL_CON0_VAL, &clk->apll_con0); - writel(MPLL_CON1_VAL, &clk->mpll_con1); - writel(MPLL_CON0_VAL, &clk->mpll_con0); - writel(EPLL_CON1_VAL, &clk->epll_con1); - writel(EPLL_CON0_VAL, &clk->epll_con0); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - writel(VPLL_CON0_VAL, &clk->vpll_con0); - - sdelay(0x30000); -} diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c deleted file mode 100644 index 0200fd154f..0000000000 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - * Clock setup for SMDK5250 board based on EXYNOS5 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/clock.h> -#include <asm/arch/spl.h> -#include <asm/arch/dwmmc.h> - -#include "clock_init.h" -#include "common_setup.h" -#include "exynos5_setup.h" - -#define FSYS1_MMC0_DIV_MASK 0xff0f -#define FSYS1_MMC0_DIV_VAL 0x0701 - -DECLARE_GLOBAL_DATA_PTR; - -struct arm_clk_ratios arm_clk_ratios[] = { -#ifdef CONFIG_EXYNOS5420 - { - .arm_freq_mhz = 900, - - .apll_mdiv = 0x96, - .apll_pdiv = 0x2, - .apll_sdiv = 0x1, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x6, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x0, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - } -#else - { - .arm_freq_mhz = 600, - - .apll_mdiv = 0xc8, - .apll_pdiv = 0x4, - .apll_sdiv = 0x1, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x2, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x1, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 800, - - .apll_mdiv = 0x64, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x3, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1000, - - .apll_mdiv = 0x7d, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x4, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1200, - - .apll_mdiv = 0x96, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x5, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1400, - - .apll_mdiv = 0xaf, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -#endif -}; - -struct mem_timings mem_timings[] = { -#ifdef CONFIG_EXYNOS5420 - { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - - /* MPLL @800MHz*/ - .mpll_mdiv = 0xc8, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x1, - /* CPLL @666MHz */ - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x1, - /* EPLL @600MHz */ - .epll_mdiv = 0x64, - .epll_pdiv = 0x2, - .epll_sdiv = 0x1, - /* VPLL @430MHz */ - .vpll_mdiv = 0xd7, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - /* BPLL @800MHz */ - .bpll_mdiv = 0xc8, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x1, - /* KPLL @600MHz */ - .kpll_mdiv = 0x190, - .kpll_pdiv = 0x4, - .kpll_sdiv = 0x2, - /* DPLL @600MHz */ - .dpll_mdiv = 0x190, - .dpll_pdiv = 0x4, - .dpll_sdiv = 0x2, - /* IPLL @370MHz */ - .ipll_mdiv = 0xb9, - .ipll_pdiv = 0x3, - .ipll_sdiv = 0x2, - /* SPLL @400MHz */ - .spll_mdiv = 0xc8, - .spll_pdiv = 0x3, - .spll_sdiv = 0x2, - /* RPLL @141Mhz */ - .rpll_mdiv = 0x5E, - .rpll_pdiv = 0x2, - .rpll_sdiv = 0x3, - - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010046, 0x00000d70, - 0x00000c70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x6836650f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a26, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_DISABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | - DMC_MEMCONFIGX_CHIP_COL_10 | - DMC_MEMCONFIGX_CHIP_ROW_15 | - DMC_MEMCONFIGX_CHIP_BANK_8, - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 1, - .chips_per_channel = 1, - .chips_to_configure = 1, - .send_zq_init = 1, - .gate_leveling_enable = 1, - .read_leveling_enable = 0, - } -#else - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0xc8, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36650e, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGX_CHIP_COL_10 | - DMC_MEMCONFIGX_CHIP_ROW_15 | - DMC_MEMCONFIGX_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0xc8, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36650e, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGX_CHIP_COL_10 | - DMC_MEMCONFIGX_CHIP_ROW_15 | - DMC_MEMCONFIGX_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - } -#endif -}; - -/** - * Get the required memory type and speed (SPL version). - * - * In SPL we have no device tree, so we use the machine parameters - * - * @param mem_type Returns memory type - * @param frequency_mhz Returns memory speed in MHz - * @param arm_freq Returns ARM clock speed in MHz - * @param mem_manuf Return Memory Manufacturer name - */ -static void clock_get_mem_selection(enum ddr_mode *mem_type, - unsigned *frequency_mhz, unsigned *arm_freq, - enum mem_manuf *mem_manuf) -{ - struct spl_machine_param *params; - - params = spl_get_machine_params(); - *mem_type = params->mem_type; - *frequency_mhz = params->frequency_mhz; - *arm_freq = params->arm_freq_mhz; - *mem_manuf = params->mem_manuf; -} - -/* Get the ratios for setting ARM clock */ -struct arm_clk_ratios *get_arm_ratios(void) -{ - struct arm_clk_ratios *arm_ratio; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf); - - for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); - i++, arm_ratio++) { - if (arm_ratio->arm_freq_mhz == arm_freq) - return arm_ratio; - } - - /* will hang if failed to find clock ratio */ - while (1) - ; - - return NULL; -} - -struct mem_timings *clock_get_mem_timings(void) -{ - struct mem_timings *mem; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf); - for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); - i++, mem++) { - if (mem->mem_type == mem_type && - mem->frequency_mhz == frequency_mhz && - mem->mem_manuf == mem_manuf) - return mem; - } - - /* will hang if failed to find memory timings */ - while (1) - ; - - return NULL; -} - -static void exynos5250_system_clock_init(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - struct mem_timings *mem; - struct arm_clk_ratios *arm_clk_ratio; - u32 val, tmp; - - mem = clock_get_mem_timings(); - arm_clk_ratio = get_arm_ratios(); - - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | MUX_APLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_core1); - } while ((val | MUX_MPLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); - tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK - | MUX_GPLL_SEL_MASK; - do { - val = readl(&clk->mux_stat_top2); - } while ((val | tmp) != val); - - clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cdrex); - } while ((val | MUX_BPLL_SEL_MASK) != val); - - /* PLL locktime */ - writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); - writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); - writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); - writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); - writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock); - writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); - writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock); - - writel(CLK_REG_DISABLE, &clk->pll_div2_sel); - - writel(MUX_HPM_SEL_MASK, &clk->src_cpu); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | HPM_SEL_SCLK_MPLL) != val); - - val = arm_clk_ratio->arm2_ratio << 28 - | arm_clk_ratio->apll_ratio << 24 - | arm_clk_ratio->pclk_dbg_ratio << 20 - | arm_clk_ratio->atb_ratio << 16 - | arm_clk_ratio->periph_ratio << 12 - | arm_clk_ratio->acp_ratio << 8 - | arm_clk_ratio->cpud_ratio << 4 - | arm_clk_ratio->arm_ratio; - writel(val, &clk->div_cpu0); - do { - val = readl(&clk->div_stat_cpu0); - } while (0 != val); - - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - do { - val = readl(&clk->div_stat_cpu1); - } while (0 != val); - - /* Set APLL */ - writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, - arm_clk_ratio->apll_sdiv); - writel(val, &clk->apll_con0); - while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) - ; - - /* Set MPLL */ - writel(MPLL_CON1_VAL, &clk->mpll_con1); - val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); - writel(val, &clk->mpll_con0); - while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) - ; - - /* Set BPLL */ - writel(BPLL_CON1_VAL, &clk->bpll_con1); - val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &clk->bpll_con0); - while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) - ; - - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &clk->cpll_con0); - while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) - ; - - /* Set GPLL */ - writel(GPLL_CON1_VAL, &clk->gpll_con1); - val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); - writel(val, &clk->gpll_con0); - while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) - ; - - /* Set EPLL */ - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); - writel(val, &clk->epll_con0); - while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) - ; - - /* Set VPLL */ - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &clk->vpll_con0); - while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) - ; - - writel(CLK_SRC_CORE0_VAL, &clk->src_core0); - writel(CLK_DIV_CORE0_VAL, &clk->div_core0); - while (readl(&clk->div_stat_core0) != 0) - ; - - writel(CLK_DIV_CORE1_VAL, &clk->div_core1); - while (readl(&clk->div_stat_core1) != 0) - ; - - writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); - while (readl(&clk->div_stat_sysrgt) != 0) - ; - - writel(CLK_DIV_ACP_VAL, &clk->div_acp); - while (readl(&clk->div_stat_acp) != 0) - ; - - writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); - while (readl(&clk->div_stat_syslft) != 0) - ; - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(TOP2_VAL, &clk->src_top2); - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); - while (readl(&clk->div_stat_top0)) - ; - - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); - while (readl(&clk->div_stat_top1)) - ; - - writel(CLK_SRC_LEX_VAL, &clk->src_lex); - while (1) { - val = readl(&clk->mux_stat_lex); - if (val == (val | 1)) - break; - } - - writel(CLK_DIV_LEX_VAL, &clk->div_lex); - while (readl(&clk->div_stat_lex)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R1X_VAL, &clk->div_r1x); - while (readl(&clk->div_stat_r1x)) - ; - - writel(CLK_REG_DISABLE, &clk->src_cdrex); - - writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); - while (readl(&clk->div_stat_cdrex)) - ; - - val = readl(&clk->src_cpu); - val |= CLK_SRC_CPU_VAL; - writel(val, &clk->src_cpu); - - val = readl(&clk->src_top2); - val |= CLK_SRC_TOP2_VAL; - writel(val, &clk->src_top2); - - val = readl(&clk->src_core1); - val |= CLK_SRC_CORE1_VAL; - writel(val, &clk->src_core1); - - writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); - while (readl(&clk->div_stat_fsys0)) - ; - - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - - writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); - writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); - writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); - - writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); - writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); - writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); - - /* FIMD1 SRC CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); - - val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET - | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET - | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET - | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; - writel(val, &clk->div_fsys2); -} - -static void exynos5420_system_clock_init(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - struct mem_timings *mem; - struct arm_clk_ratios *arm_clk_ratio; - u32 val; - - mem = clock_get_mem_timings(); - arm_clk_ratio = get_arm_ratios(); - - /* PLL locktime */ - writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); - writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); - writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); - writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); - writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock); - writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); - writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock); - writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); - writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); - writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); - writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock); - - setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); - - writel(0, &clk->src_top6); - - writel(0, &clk->src_cdrex); - writel(SRC_KFC_HPM_SEL, &clk->src_kfc); - writel(HPM_RATIO, &clk->div_cpu1); - writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); - - /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&clk->src_cpu, APLL_FOUT); - - /* Set APLL */ - writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(arm_clk_ratio->apll_mdiv, - arm_clk_ratio->apll_pdiv, - arm_clk_ratio->apll_sdiv); - writel(val, &clk->apll_con0); - while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) - ; - - /* now it is safe to switch to APLL */ - setbits_le32(&clk->src_cpu, APLL_FOUT); - - writel(SRC_KFC_HPM_SEL, &clk->src_kfc); - writel(CLK_DIV_KFC_VAL, &clk->div_kfc0); - - /* switch A7 clock source to OSC clock before changing KPLL */ - clrbits_le32(&clk->src_kfc, KPLL_FOUT); - - /* Set KPLL*/ - writel(KPLL_CON1_VAL, &clk->kpll_con1); - val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv); - writel(val, &clk->kpll_con0); - while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) - ; - - /* now it is safe to switch to KPLL */ - setbits_le32(&clk->src_kfc, KPLL_FOUT); - - /* Set MPLL */ - writel(MPLL_CON1_VAL, &clk->mpll_con1); - val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); - writel(val, &clk->mpll_con0); - while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) - ; - - /* Set DPLL */ - writel(DPLL_CON1_VAL, &clk->dpll_con1); - val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv); - writel(val, &clk->dpll_con0); - while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0) - ; - - /* Set EPLL */ - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); - writel(val, &clk->epll_con0); - while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) - ; - - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &clk->cpll_con0); - while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) - ; - - /* Set IPLL */ - writel(IPLL_CON1_VAL, &clk->ipll_con1); - val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv); - writel(val, &clk->ipll_con0); - while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0) - ; - - /* Set VPLL */ - writel(VPLL_CON1_VAL, &clk->vpll_con1); - val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &clk->vpll_con0); - while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0) - ; - - /* Set BPLL */ - writel(BPLL_CON1_VAL, &clk->bpll_con1); - val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &clk->bpll_con0); - while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0) - ; - - /* Set SPLL */ - writel(SPLL_CON1_VAL, &clk->spll_con1); - val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv); - writel(val, &clk->spll_con0); - while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) - ; - - /* Set RPLL */ - writel(RPLL_CON2_VAL, &clk->rpll_con2); - writel(RPLL_CON1_VAL, &clk->rpll_con1); - val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); - writel(val, &clk->rpll_con0); - while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) - ; - - writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); - writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(CLK_SRC_TOP2_VAL, &clk->src_top2); - writel(CLK_SRC_TOP7_VAL, &clk->src_top7); - - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); - writel(CLK_DIV_TOP2_VAL, &clk->div_top2); - - writel(0, &clk->src_top10); - writel(0, &clk->src_top11); - writel(0, &clk->src_top12); - - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - writel(CLK_SRC_TOP4_VAL, &clk->src_top4); - writel(CLK_SRC_TOP5_VAL, &clk->src_top5); - - /* DISP1 BLK CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10); - writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10); - - /* AUDIO BLK */ - writel(AUDIO0_SEL_EPLL, &clk->src_mau); - writel(DIV_MAU_VAL, &clk->div_mau); - - /* FSYS */ - writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); - writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); - writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); - - writel(CLK_SRC_ISP_VAL, &clk->src_isp); - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); - - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); - writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); - - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); - writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); - writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); - - writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1); - - writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio); - writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio); - writel(CLK_DIV_G2D, &clk->div_g2d); - - writel(CLK_SRC_TOP6_VAL, &clk->src_top6); - writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex); - writel(CLK_SRC_KFC_VAL, &clk->src_kfc); -} - -void system_clock_init(void) -{ - if (proid_is_exynos5420() || proid_is_exynos5800()) - exynos5420_system_clock_init(); - else - exynos5250_system_clock_init(); -} - -void clock_init_dp_clock(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - /* DP clock enable */ - setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); - - /* We run DP at 267 Mhz */ - setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); -} - -/* - * Set clock divisor value for booting from EMMC. - * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. - */ -void emmc_boot_clk_div_set(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int div_mmc; - - div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; - div_mmc |= FSYS1_MMC0_DIV_VAL; - writel(div_mmc, (unsigned int) &clk->div_fsys1); -} diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h deleted file mode 100644 index 5235abb808..0000000000 --- a/arch/arm/cpu/armv7/exynos/common_setup.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Common APIs for EXYNOS based board - * - * Copyright (C) 2013 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/system.h> - -#define DMC_OFFSET 0x10000 - -/* - * Memory initialization - * - * @param reset Reset PHY during initialization. - */ -void mem_ctrl_init(int reset); - - /* System Clock initialization */ -void system_clock_init(void); - -/* - * Init subsystems according to the reset status - * - * @return 0 for a normal boot, non-zero for a resume - */ -int do_lowlevel_init(void); - -void sdelay(unsigned long); - -enum l2_cache_params { - CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0), - CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0), - CACHE_DISABLE_CLEAN_EVICT = (1 << 3), - CACHE_DATA_RAM_SETUP = (1 << 5), - CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6), - CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6), - CACHE_ENABLE_HAZARD_DETECT = (1 << 7), - CACHE_TAG_RAM_SETUP = (1 << 9), - CACHE_ECC_AND_PARITY = (1 << 21), - CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) -}; - - -#ifndef CONFIG_SYS_L2CACHE_OFF -/* - * Configure L2CTLR to get timings that keep us from hanging/crashing. - * - * Must be inline here since low_power_start() is called without a - * stack (!). - */ -static inline void configure_l2_ctlr(void) -{ - uint32_t val; - - mrc_l2_ctlr(val); - - val |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP | - CACHE_TAG_RAM_LATENCY_2_CYCLES | - CACHE_DATA_RAM_LATENCY_2_CYCLES; - - if (proid_is_exynos5420() || proid_is_exynos5800()) { - val |= CACHE_ECC_AND_PARITY | - CACHE_TAG_RAM_LATENCY_3_CYCLES | - CACHE_DATA_RAM_LATENCY_3_CYCLES; - } - - mcr_l2_ctlr(val); -} - -/* - * Configure L2ACTLR. - * - * Must be inline here since low_power_start() is called without a - * stack (!). - */ -static inline void configure_l2_actlr(void) -{ - uint32_t val; - - if (proid_is_exynos5420() || proid_is_exynos5800()) { - mrc_l2_aux_ctlr(val); - val |= CACHE_ENABLE_FORCE_L2_LOGIC | - CACHE_DISABLE_CLEAN_EVICT; - mcr_l2_aux_ctlr(val); - } -} -#endif diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk deleted file mode 100644 index ee0d2dab7b..0000000000 --- a/arch/arm/cpu/armv7/exynos/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -SPL_OBJCFLAGS += -j .machine_param diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c deleted file mode 100644 index 9b6ee69f46..0000000000 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Mem setup common file for different types of DDR present on Exynos boards. - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/spl.h> - -#include "clock_init.h" -#include "common_setup.h" -#include "exynos5_setup.h" - -#define ZQ_INIT_TIMEOUT 10000 - -int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, - uint32_t *phy1_con16, uint32_t *phy0_con17, - uint32_t *phy1_con17) -{ - unsigned long val = 0; - int i; - - /* - * ZQ Calibration: - * Select Driver Strength, - * long calibration for manual calibration - */ - val = PHY_CON16_RESET_VAL; - val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; - val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; - val |= ZQ_CLK_DIV_EN; - writel(val, phy0_con16); - writel(val, phy1_con16); - - /* Disable termination */ - if (mem->zq_mode_noterm) - val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, phy0_con16); - writel(val, phy1_con16); - - /* ZQ_MANUAL_START: Enable */ - val |= ZQ_MANUAL_STR; - writel(val, phy0_con16); - writel(val, phy1_con16); - - /* ZQ_MANUAL_START: Disable */ - val &= ~ZQ_MANUAL_STR; - - /* - * Since we are manaully calibrating the ZQ values, - * we are looping for the ZQ_init to complete. - */ - i = ZQ_INIT_TIMEOUT; - while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { - sdelay(100); - i--; - } - if (!i) - return -1; - writel(val, phy0_con16); - - i = ZQ_INIT_TIMEOUT; - while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { - sdelay(100); - i--; - } - if (!i) - return -1; - writel(val, phy1_con16); - - return 0; -} - -void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) -{ - unsigned long val; - - if (mode == DDR_MODE_DDR3) { - val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, phycontrol0); - } - - /* Update DLL Information: Force DLL Resyncronization */ - val = readl(phycontrol0); - val |= FP_RSYNC; - writel(val, phycontrol0); - - /* Reset Force DLL Resyncronization */ - val = readl(phycontrol0); - val &= ~FP_RSYNC; - writel(val, phycontrol0); -} - -void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd) -{ - int channel, chip; - - for (channel = 0; channel < mem->dmc_channels; channel++) { - unsigned long mask; - - mask = channel << DIRECT_CMD_CHANNEL_SHIFT; - for (chip = 0; chip < mem->chips_to_configure; chip++) { - int i; - - mask |= chip << DIRECT_CMD_CHIP_SHIFT; - - /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, directcmd); - - /* - * TODO(alim.akhtar@samsung.com): Do we need these - * delays? This one and the next were not there for - * DDR3. - */ - sdelay(0x10000); - - /* Sending EMRS/MRS commands */ - for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem->direct_cmd_msr[i] | mask, - directcmd); - sdelay(0x10000); - } - - if (mem->send_zq_init) { - /* Sending ZQINIT command */ - writel(DIRECT_CMD_ZQINIT | mask, - directcmd); - - sdelay(10000); - } - } - } -} - -void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd) -{ - int channel, chip; - - for (channel = 0; channel < mem->dmc_channels; channel++) { - unsigned long mask; - - mask = channel << DIRECT_CMD_CHANNEL_SHIFT; - for (chip = 0; chip < mem->chips_per_channel; chip++) { - mask |= chip << DIRECT_CMD_CHIP_SHIFT; - - /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, directcmd); - sdelay(0x10000); - } - } -} - -void mem_ctrl_init(int reset) -{ - struct spl_machine_param *param = spl_get_machine_params(); - struct mem_timings *mem; - int ret; - - mem = clock_get_mem_timings(); - - /* If there are any other memory variant, add their init call below */ - if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, reset); - if (ret) { - /* will hang if failed to init memory control */ - while (1) - ; - } - } else { - /* will hang if unknow memory type */ - while (1) - ; - } -} diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c deleted file mode 100644 index 7c0b12ae51..0000000000 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ /dev/null @@ -1,866 +0,0 @@ -/* - * DDR3 mem setup file for board based on EXYNOS5 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dmc.h> -#include <asm/arch/power.h> -#include "common_setup.h" -#include "exynos5_setup.h" -#include "clock_init.h" - -#define TIMEOUT_US 10000 -#define NUM_BYTE_LANES 4 -#define DEFAULT_DQS 8 -#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ - || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) - -#ifdef CONFIG_EXYNOS5250 -static void reset_phy_ctrl(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); - writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); -} - -int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) -{ - unsigned int val; - struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; - struct exynos5_dmc *dmc; - int i; - - phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy(); - phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy() - + DMC_OFFSET); - dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl(); - - if (reset) - reset_phy_ctrl(); - - /* Set Impedance Output Driver */ - val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | - (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | - (mem->impedance << CA_CS_DRVR_DS_OFFSET) | - (mem->impedance << CA_ADR_DRVR_DS_OFFSET); - writel(val, &phy0_ctrl->phy_con39); - writel(val, &phy1_ctrl->phy_con39); - - /* Set Read Latency and Burst Length for PHY0 and PHY1 */ - val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | - (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &phy0_ctrl->phy_con42); - writel(val, &phy1_ctrl->phy_con42); - - /* ZQ Calibration */ - if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, - &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) - return SETUP_ERR_ZQ_CALIBRATION_FAILURE; - - /* DQ Signal */ - writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); - writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); - - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), - &dmc->concontrol); - - update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); - - /* DQS Signal */ - writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); - writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); - - writel(mem->phy0_dq, &phy0_ctrl->phy_con6); - writel(mem->phy1_dq, &phy1_ctrl->phy_con6); - - writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); - writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); - - val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); - - /* Start DLL locking */ - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy0_ctrl->phy_con12); - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy1_ctrl->phy_con12); - - update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); - - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &dmc->concontrol); - - /* Memory Channel Inteleaving Size */ - writel(mem->iv_size, &dmc->ivcontrol); - - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(mem->membaseconfig0, &dmc->membaseconfig0); - writel(mem->membaseconfig1, &dmc->membaseconfig1); - - /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &dmc->prechconfig); - - /* Power Down mode Configuration */ - writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | - mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, - &dmc->pwrdnconfig); - - /* TimingRow, TimingData, TimingPower and Timingaref - * values as per Memory AC parameters - */ - writel(mem->timing_ref, &dmc->timingref); - writel(mem->timing_row, &dmc->timingrow); - writel(mem->timing_data, &dmc->timingdata); - writel(mem->timing_power, &dmc->timingpower); - - /* Send PALL command */ - dmc_config_prech(mem, &dmc->directcmd); - - /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, &dmc->directcmd); - - if (mem->gate_leveling_enable) { - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); - - val = PHY_CON2_RESET_VAL; - val |= INIT_DESKEW_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); - - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - val |= BYTE_RDLVL_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); - - val = (mem->ctrl_start_point << - PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | - (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); - - val = PHY_CON2_RESET_VAL; - val |= INIT_DESKEW_EN; - val |= RDLVL_GATE_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); - - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - val |= BYTE_RDLVL_EN; - val |= CTRL_SHGATE; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); - - val = PHY_CON1_RESET_VAL; - val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &phy0_ctrl->phy_con1); - writel(val, &phy1_ctrl->phy_con1); - - writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = TIMEOUT_US; - while ((readl(&dmc->phystatus) & - (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != - (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { - /* - * TODO(waihong): Comment on how long this take to - * timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config); - - writel(0, &phy0_ctrl->phy_con14); - writel(0, &phy1_ctrl->phy_con14); - - val = (mem->ctrl_start_point << - PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | - (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | - (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); - - update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); - } - - /* Send PALL command */ - dmc_config_prech(mem, &dmc->directcmd); - - writel(mem->memcontrol, &dmc->memcontrol); - - /* Set DMC Concontrol and enable auto-refresh counter */ - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); - return 0; -} -#endif - -#ifdef CONFIG_EXYNOS5420 -/** - * RAM address to use in the test. - * - * We'll use 4 words at this address and 4 at this address + 0x80 (Ares - * interleaves channels every 128 bytes). This will allow us to evaluate all of - * the chips in a 1 chip per channel (2GB) system and half the chips in a 2 - * chip per channel (4GB) system. We can't test the 2nd chip since we need to - * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't - * critical because the 1st and 2nd chip have very similar timings (they'd - * better have similar timings, since there's only a single adjustment that is - * shared by both chips). - */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; - -/* Test pattern with which RAM will be tested */ -static const unsigned int test_pattern[] = { - 0x5a5a5a5a, - 0xa5a5a5a5, - 0xf0f0f0f0, - 0x0f0f0f0f, -}; - -/** - * This function is a test vector for sw read leveling, - * it compares the read data with the written data. - * - * @param ch DMC channel number - * @param byte_lane which DQS byte offset, - * possible values are 0,1,2,3 - * @return TRUE if memory was good, FALSE if not. - */ -static bool dmc_valid_window_test_vector(int ch, int byte_lane) -{ - unsigned int read_data; - unsigned int mask; - int i; - - mask = 0xFF << (8 * byte_lane); - - for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { - read_data = readl(test_addr + i * 4 + ch * 0x80); - if ((read_data & mask) != (test_pattern[i] & mask)) - return false; - } - - return true; -} - -/** - * This function returns current read offset value. - * - * @param phy_ctrl pointer to the current phy controller - */ -static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control - *phy_ctrl) -{ - return readl(&phy_ctrl->phy_con4); -} - -/** - * This function performs resync, so that slave DLL is updated. - * - * @param phy_ctrl pointer to the current phy controller - */ -static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) -{ - setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); - clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); -} - -/** - * This function sets read offset value register with 'offset'. - * - * ...we also call call ddr_phy_set_do_resync(). - * - * @param phy_ctrl pointer to the current phy controller - * @param offset offset to read DQS - */ -static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, - unsigned int offset) -{ - writel(offset, &phy_ctrl->phy_con4); - ddr_phy_set_do_resync(phy_ctrl); -} - -/** - * Convert a 2s complement byte to a byte with a sign bit. - * - * NOTE: you shouldn't use normal math on the number returned by this function. - * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted - * to do math and get the average of 10 and -10 (should be 0): - * 0x8a + 0xa = 0x94 (-108) - * 0x94 / 2 = 0xca (-54) - * ...and 0xca = sign bit plus 0x4a, or -74 - * - * Also note that you lose the ability to represent -128 since there are two - * representations of 0. - * - * @param b The byte to convert in two's complement. - * @return The 7-bit value + sign bit. - */ - -unsigned char make_signed_byte(signed char b) -{ - if (b < 0) - return 0x80 | -b; - else - return b; -} - -/** - * Test various shifts starting at 'start' and going to 'end'. - * - * For each byte lane, we'll walk through shift starting at 'start' and going - * to 'end' (inclusive). When we are finally able to read the test pattern - * we'll store the value in the results array. - * - * @param phy_ctrl pointer to the current phy controller - * @param ch channel number - * @param start the start shift. -127 to 127 - * @param end the end shift. -127 to 127 - * @param results we'll store results for each byte lane. - */ - -void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, - int start, int end, int results[NUM_BYTE_LANES]) -{ - int incr = (start < end) ? 1 : -1; - int byte_lane; - - for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { - int shift; - - dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); - results[byte_lane] = DEFAULT_DQS; - - for (shift = start; shift != (end + incr); shift += incr) { - unsigned int byte_offsetr; - unsigned int offsetr; - - byte_offsetr = make_signed_byte(shift); - - offsetr = dmc_get_read_offset_value(phy_ctrl); - offsetr &= ~(0xFF << (8 * byte_lane)); - offsetr |= (byte_offsetr << (8 * byte_lane)); - dmc_set_read_offset_value(phy_ctrl, offsetr); - - if (dmc_valid_window_test_vector(ch, byte_lane)) { - results[byte_lane] = shift; - break; - } - } - } -} - -/** - * This function performs SW read leveling to compensate DQ-DQS skew at - * receiver it first finds the optimal read offset value on each DQS - * then applies the value to PHY. - * - * Read offset value has its min margin and max margin. If read offset - * value exceeds its min or max margin, read data will have corruption. - * To avoid this we are doing sw read leveling. - * - * SW read leveling is: - * 1> Finding offset value's left_limit and right_limit - * 2> and calculate its center value - * 3> finally programs that center value to PHY - * 4> then PHY gets its optimal offset value. - * - * @param phy_ctrl pointer to the current phy controller - * @param ch channel number - * @param coarse_lock_val The coarse lock value read from PHY_CON13. - * (0 - 0x7f) - */ -static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl, - int ch, unsigned int coarse_lock_val) -{ - unsigned int offsetr_cent; - int byte_lane; - int left_limit; - int right_limit; - int left[NUM_BYTE_LANES]; - int right[NUM_BYTE_LANES]; - int i; - - /* Fill the memory with test patterns */ - for (i = 0; i < ARRAY_SIZE(test_pattern); i++) - writel(test_pattern[i], test_addr + i * 4 + ch * 0x80); - - /* Figure out the limits we'll test with; keep -127 < limit < 127 */ - left_limit = DEFAULT_DQS - coarse_lock_val; - right_limit = DEFAULT_DQS + coarse_lock_val; - if (right_limit > 127) - right_limit = 127; - - /* Fill in the location where reads were OK from left and right */ - test_shifts(phy_ctrl, ch, left_limit, right_limit, left); - test_shifts(phy_ctrl, ch, right_limit, left_limit, right); - - /* Make a final value by taking the center between the left and right */ - offsetr_cent = 0; - for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { - int temp_center; - unsigned int vmwc; - - temp_center = (left[byte_lane] + right[byte_lane]) / 2; - vmwc = make_signed_byte(temp_center); - offsetr_cent |= vmwc << (8 * byte_lane); - } - dmc_set_read_offset_value(phy_ctrl, offsetr_cent); -} - -int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - struct exynos5420_power *power = - (struct exynos5420_power *)samsung_get_base_power(); - struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; - struct exynos5420_dmc *drex0, *drex1; - struct exynos5420_tzasc *tzasc0, *tzasc1; - struct exynos5_power *pmu; - uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; - uint32_t lock0_info, lock1_info; - int chip; - int i; - - phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy(); - phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy() - + DMC_OFFSET); - drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl(); - drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl() - + DMC_OFFSET); - tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); - tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() - + DMC_OFFSET); - pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; - - if (CONFIG_NR_DRAM_BANKS > 4) { - /* Need both controllers. */ - mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; - mem->chips_per_channel = 2; - mem->chips_to_configure = 2; - } else { - /* 2GB requires a single controller */ - mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; - } - - /* Enable PAUSE for DREX */ - setbits_le32(&clk->pause, ENABLE_BIT); - - /* Enable BYPASS mode */ - setbits_le32(&clk->bpll_con1, BYPASS_EN); - - writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex); - do { - val = readl(&clk->mux_stat_cdrex); - val &= BPLL_SEL_MASK; - } while (val != FOUTBPLL); - - clrbits_le32(&clk->bpll_con1, BYPASS_EN); - - /* Specify the DDR memory type as DDR3 */ - val = readl(&phy0_ctrl->phy_con0); - val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); - val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &phy0_ctrl->phy_con0); - - val = readl(&phy1_ctrl->phy_con0); - val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); - val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &phy1_ctrl->phy_con0); - - /* Set Read Latency and Burst Length for PHY0 and PHY1 */ - val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | - (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &phy0_ctrl->phy_con42); - writel(val, &phy1_ctrl->phy_con42); - - val = readl(&phy0_ctrl->phy_con26); - val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); - val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &phy0_ctrl->phy_con26); - - val = readl(&phy1_ctrl->phy_con26); - val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); - val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &phy1_ctrl->phy_con26); - - /* - * Set Driver strength for CK, CKE, CS & CA to 0x7 - * Set Driver strength for Data Slice 0~3 to 0x7 - */ - val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | - (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); - val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | - (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); - writel(val, &phy0_ctrl->phy_con39); - writel(val, &phy1_ctrl->phy_con39); - - /* ZQ Calibration */ - if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, - &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) - return SETUP_ERR_ZQ_CALIBRATION_FAILURE; - - clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN); - clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); - - /* DQ Signal */ - val = readl(&phy0_ctrl->phy_con14); - val |= mem->phy0_pulld_dqs; - writel(val, &phy0_ctrl->phy_con14); - val = readl(&phy1_ctrl->phy_con14); - val |= mem->phy1_pulld_dqs; - writel(val, &phy1_ctrl->phy_con14); - - val = MEM_TERM_EN | PHY_TERM_EN; - writel(val, &drex0->phycontrol0); - writel(val, &drex1->phycontrol0); - - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &drex0->concontrol); - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &drex1->concontrol); - - do { - val = readl(&drex0->phystatus); - } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); - do { - val = readl(&drex1->phystatus); - } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); - - clrbits_le32(&drex0->concontrol, DFI_INIT_START); - clrbits_le32(&drex1->concontrol, DFI_INIT_START); - - update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); - update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); - - /* - * Set Base Address: - * 0x2000_0000 ~ 0x5FFF_FFFF - * 0x6000_0000 ~ 0x9FFF_FFFF - */ - /* MEMBASECONFIG0 */ - val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) | - DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); - writel(val, &tzasc0->membaseconfig0); - writel(val, &tzasc1->membaseconfig0); - - /* MEMBASECONFIG1 */ - val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) | - DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); - writel(val, &tzasc0->membaseconfig1); - writel(val, &tzasc1->membaseconfig1); - - /* - * Memory Channel Inteleaving Size - * Ares Channel interleaving = 128 bytes - */ - /* MEMCONFIG0/1 */ - writel(mem->memconfig, &tzasc0->memconfig0); - writel(mem->memconfig, &tzasc1->memconfig0); - writel(mem->memconfig, &tzasc0->memconfig1); - writel(mem->memconfig, &tzasc1->memconfig1); - - /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &drex0->prechconfig0); - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &drex1->prechconfig0); - - /* - * TimingRow, TimingData, TimingPower and Timingaref - * values as per Memory AC parameters - */ - writel(mem->timing_ref, &drex0->timingref); - writel(mem->timing_ref, &drex1->timingref); - writel(mem->timing_row, &drex0->timingrow0); - writel(mem->timing_row, &drex1->timingrow0); - writel(mem->timing_data, &drex0->timingdata0); - writel(mem->timing_data, &drex1->timingdata0); - writel(mem->timing_power, &drex0->timingpower0); - writel(mem->timing_power, &drex1->timingpower0); - - if (reset) { - /* - * Send NOP, MRS and ZQINIT commands - * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory - * corruption as DRAM content is lost after DRAM reset - */ - dmc_config_mrs(mem, &drex0->directcmd); - dmc_config_mrs(mem, &drex1->directcmd); - } - - /* - * Get PHY_CON13 from both phys. Gate CLKM around reading since - * PHY_CON13 is glitchy when CLKM is running. We're paranoid and - * wait until we get a "fine lock", though a coarse lock is probably - * OK (we only use the coarse numbers below). We try to gate the - * clock for as short a time as possible in case SDRAM is somehow - * sensitive. sdelay(10) in the loop is arbitrary to make sure - * there is some time for PHY_CON13 to get updated. In practice - * no delay appears to be needed. - */ - val = readl(&clk->gate_bus_cdrex); - while (true) { - writel(val & ~0x1, &clk->gate_bus_cdrex); - lock0_info = readl(&phy0_ctrl->phy_con13); - writel(val, &clk->gate_bus_cdrex); - - if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) - break; - - sdelay(10); - } - while (true) { - writel(val & ~0x2, &clk->gate_bus_cdrex); - lock1_info = readl(&phy1_ctrl->phy_con13); - writel(val, &clk->gate_bus_cdrex); - - if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) - break; - - sdelay(10); - } - - if (!reset) { - /* - * During Suspend-Resume & S/W-Reset, as soon as PMU releases - * pad retention, CKE goes high. This causes memory contents - * not to be retained during DRAM initialization. Therfore, - * there is a new control register(0x100431e8[28]) which lets us - * release pad retention and retain the memory content until the - * initialization is complete. - */ - writel(PAD_RETENTION_DRAM_COREBLK_VAL, - &power->pad_retention_dram_coreblk_option); - do { - val = readl(&power->pad_retention_dram_status); - } while (val != 0x1); - - /* - * CKE PAD retention disables DRAM self-refresh mode. - * Send auto refresh command for DRAM refresh. - */ - for (i = 0; i < 128; i++) { - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - } - } - - if (mem->gate_leveling_enable) { - writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); - writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); - - setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); - setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); - - val = PHY_CON2_RESET_VAL; - val |= INIT_DESKEW_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); - - val = readl(&phy0_ctrl->phy_con1); - val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &phy0_ctrl->phy_con1); - - val = readl(&phy1_ctrl->phy_con1); - val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &phy1_ctrl->phy_con1); - - n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; - n_lock_r = readl(&phy0_ctrl->phy_con12); - n_lock_r &= ~CTRL_DLL_ON; - n_lock_r |= n_lock_w_phy0; - writel(n_lock_r, &phy0_ctrl->phy_con12); - - n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; - n_lock_r = readl(&phy1_ctrl->phy_con12); - n_lock_r &= ~CTRL_DLL_ON; - n_lock_r |= n_lock_w_phy1; - writel(n_lock_r, &phy1_ctrl->phy_con12); - - val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); - setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); - - setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE); - setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE); - - val = readl(&phy0_ctrl->phy_con1); - val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &phy0_ctrl->phy_con1); - - val = readl(&phy1_ctrl->phy_con1); - val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &phy1_ctrl->phy_con1); - - writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); - i = TIMEOUT_US; - while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != - RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take to - * timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); - - writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); - i = TIMEOUT_US; - while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != - RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take to - * timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config); - - writel(0, &phy0_ctrl->phy_con14); - writel(0, &phy1_ctrl->phy_con14); - - val = (0x3 << DIRECT_CMD_BANK_SHIFT); - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - /* Common Settings for Leveling */ - val = PHY_CON12_RESET_VAL; - writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); - writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12); - - setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN); - setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); - } - - /* - * Do software read leveling - * - * Do this before we turn on auto refresh since the auto refresh can - * be in conflict with the resync operation that's part of setting - * read leveling. - */ - if (!reset) { - /* restore calibrated value after resume */ - dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); - dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); - } else { - software_find_read_offset(phy0_ctrl, 0, - CTRL_LOCK_COARSE(lock0_info)); - software_find_read_offset(phy1_ctrl, 1, - CTRL_LOCK_COARSE(lock1_info)); - /* save calibrated value to restore after resume */ - writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); - writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); - } - - /* Send PALL command */ - dmc_config_prech(mem, &drex0->directcmd); - dmc_config_prech(mem, &drex1->directcmd); - - writel(mem->memcontrol, &drex0->memcontrol); - writel(mem->memcontrol, &drex1->memcontrol); - - /* - * Set DMC Concontrol: Enable auto-refresh counter, provide - * read data fetch cycles and enable DREX auto set powerdown - * for input buffer of I/O in none read memory state. - */ - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &drex0->concontrol); - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &drex1->concontrol); - - /* - * Enable Clock Gating Control for DMC - * this saves around 25 mw dmc power as compared to the power - * consumption without these bits enabled - */ - setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); - setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); - - /* - * As per Exynos5800 UM ver 0.00 section 17.13.2.1 - * CONCONTROL register bit 3 [update_mode], Exynos5800 does not - * support the PHY initiated update. And it is recommended to set - * this field to 1'b1 during initialization - * - * When we apply PHY-initiated mode, DLL lock value is determined - * once at DMC init time and not updated later when we change the MIF - * voltage based on ASV group in kernel. Applying MC-initiated mode - * makes sure that DLL tracing is ON so that silicon is able to - * compensate the voltage variation. - */ - val = readl(&drex0->concontrol); - val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex0->concontrol); - val = readl(&drex1->concontrol); - val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex1->concontrol); - - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c deleted file mode 100644 index ecddc72684..0000000000 --- a/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Memory setup for board based on EXYNOS4210 - * - * Copyright (C) 2013 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/dmc.h> -#include "common_setup.h" -#include "exynos4_setup.h" - -struct mem_timings mem = { - .direct_cmd_msr = { - DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4 - }, - .timingref = TIMINGREF_VAL, - .timingrow = TIMINGROW_VAL, - .timingdata = TIMINGDATA_VAL, - .timingpower = TIMINGPOWER_VAL, - .zqcontrol = ZQ_CONTROL_VAL, - .control0 = CONTROL0_VAL, - .control1 = CONTROL1_VAL, - .control2 = CONTROL2_VAL, - .concontrol = CONCONTROL_VAL, - .prechconfig = PRECHCONFIG, - .memcontrol = MEMCONTROL_VAL, - .memconfig0 = MEMCONFIG0_VAL, - .memconfig1 = MEMCONFIG1_VAL, - .dll_resync = FORCE_DLL_RESYNC, - .dll_on = DLL_CONTROL_ON, -}; -static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) -{ - if (ctrl_no) { - writel((mem.control1 | (1 << mem.dll_resync)), - &dmc->phycontrol1); - writel((mem.control1 | (0 << mem.dll_resync)), - &dmc->phycontrol1); - } else { - writel((mem.control0 | (0 << mem.dll_on)), - &dmc->phycontrol0); - writel((mem.control0 | (1 << mem.dll_on)), - &dmc->phycontrol0); - } -} - -static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) -{ - int i; - unsigned long mask = 0; - - if (chip) - mask = DIRECT_CMD_CHIP1_SHIFT; - - for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem.direct_cmd_msr[i] | mask, - &dmc->directcmd); - } -} - -static void dmc_init(struct exynos4_dmc *dmc) -{ - /* - * DLL Parameter Setting: - * Termination: Enable R/W - * Phase Delay for DQS Cleaning: 180' Shift - */ - writel(mem.control1, &dmc->phycontrol1); - - /* - * ZQ Calibration - * Termination: Disable - * Auto Calibration Start: Enable - */ - writel(mem.zqcontrol, &dmc->phyzqcontrol); - sdelay(0x100000); - - /* - * Update DLL Information: - * Force DLL Resyncronization - */ - phy_control_reset(1, dmc); - phy_control_reset(0, dmc); - - /* Set DLL Parameters */ - writel(mem.control1, &dmc->phycontrol1); - - /* DLL Start */ - writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0); - - writel(mem.control2, &dmc->phycontrol2); - - /* Set Clock Ratio of Bus clock to Memory Clock */ - writel(mem.concontrol, &dmc->concontrol); - - /* - * Memor Burst length: 8 - * Number of chips: 2 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 1 Cycle - */ - writel(mem.memcontrol, &dmc->memcontrol); - - writel(mem.memconfig0, &dmc->memconfig0); - writel(mem.memconfig1, &dmc->memconfig1); - - /* Config Precharge Policy */ - writel(mem.prechconfig, &dmc->prechconfig); - /* - * TimingAref, TimingRow, TimingData, TimingPower Setting: - * Values as per Memory AC Parameters - */ - writel(mem.timingref, &dmc->timingref); - writel(mem.timingrow, &dmc->timingrow); - writel(mem.timingdata, &dmc->timingdata); - writel(mem.timingpower, &dmc->timingpower); - - /* Chip0: NOP Command: Assert and Hold CKE to high level */ - writel(DIRECT_CMD_NOP, &dmc->directcmd); - sdelay(0x100000); - - /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ - dmc_config_mrs(dmc, 0); - sdelay(0x100000); - - /* Chip0: ZQINIT */ - writel(DIRECT_CMD_ZQ, &dmc->directcmd); - sdelay(0x100000); - - writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd); - sdelay(0x100000); - - /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ - dmc_config_mrs(dmc, 1); - sdelay(0x100000); - - /* Chip1: ZQINIT */ - writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd); - sdelay(0x100000); - - phy_control_reset(1, dmc); - sdelay(0x100000); - - /* turn on DREX0, DREX1 */ - writel((mem.concontrol | AREF_EN), &dmc->concontrol); -} - -void mem_ctrl_init(int reset) -{ - struct exynos4_dmc *dmc; - - /* - * Async bridge configuration at CPU_core: - * 1: half_sync - * 0: full_sync - */ - writel(1, ASYNC_CONFIG); -#ifdef CONFIG_ORIGEN - /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ - writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + - APB_SFR_INTERLEAVE_CONF_OFFSET); - /* Update MIU Configuration */ - writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE + - APB_SFR_ARBRITATION_CONF_OFFSET); -#else - writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + - APB_SFR_INTERLEAVE_CONF_OFFSET); - writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET); - writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET); - writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE + - ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); -#ifdef CONFIG_MIU_LINEAR - writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET); - writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET); - writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET); - writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + - ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET); - writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE + - ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); -#endif -#endif - /* DREX0 */ - dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); - dmc_init(dmc); - dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() - + DMC_OFFSET); - dmc_init(dmc); -} diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h deleted file mode 100644 index 9f29d94c10..0000000000 --- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Machine Specific Values for EXYNOS4012 based board - * - * Copyright (C) 2011 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ORIGEN_SETUP_H -#define _ORIGEN_SETUP_H - -#include <config.h> -#include <asm/arch/cpu.h> - -#ifdef CONFIG_CLK_800_330_165 -#define DRAM_CLK_330 -#endif -#ifdef CONFIG_CLK_1000_200_200 -#define DRAM_CLK_200 -#endif -#ifdef CONFIG_CLK_1000_330_165 -#define DRAM_CLK_330 -#endif -#ifdef CONFIG_CLK_1000_400_200 -#define DRAM_CLK_400 -#endif - -/* Bus Configuration Register Address */ -#define ASYNC_CONFIG 0x10010350 - -/* CLK_SRC_CPU */ -#define MUX_HPM_SEL_MOUTAPLL 0x0 -#define MUX_HPM_SEL_SCLKMPLL 0x1 -#define MUX_CORE_SEL_MOUTAPLL 0x0 -#define MUX_CORE_SEL_SCLKMPLL 0x1 -#define MUX_MPLL_SEL_FILPLL 0x0 -#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 -#define MUX_APLL_SEL_FILPLL 0x0 -#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ - | (MUX_CORE_SEL_MOUTAPLL << 16) \ - | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ - | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) - -/* CLK_DIV_CPU0 */ -#define APLL_RATIO 0x0 -#define PCLK_DBG_RATIO 0x1 -#define ATB_RATIO 0x3 -#define PERIPH_RATIO 0x3 -#define COREM1_RATIO 0x7 -#define COREM0_RATIO 0x3 -#define CORE_RATIO 0x0 -#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (COREM1_RATIO << 8) \ - | (COREM0_RATIO << 4) \ - | (CORE_RATIO << 0)) - -/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x0 -#define COPY_RATIO 0x3 -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) - -/* CLK_SRC_DMC */ -#define MUX_PWI_SEL_XXTI 0x0 -#define MUX_PWI_SEL_XUSBXTI 0x1 -#define MUX_PWI_SEL_SCLK_HDMI24M 0x2 -#define MUX_PWI_SEL_SCLK_USBPHY0 0x3 -#define MUX_PWI_SEL_SCLK_USBPHY1 0x4 -#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5 -#define MUX_PWI_SEL_SCLKMPLL 0x6 -#define MUX_PWI_SEL_SCLKEPLL 0x7 -#define MUX_PWI_SEL_SCLKVPLL 0x8 -#define MUX_DPHY_SEL_SCLKMPLL 0x0 -#define MUX_DPHY_SEL_SCLKAPLL 0x1 -#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0 -#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1 -#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \ - | (MUX_DPHY_SEL_SCLKMPLL << 8) \ - | (MUX_DMC_BUS_SEL_SCLKMPLL << 4)) - -/* CLK_DIV_DMC0 */ -#define CORE_TIMERS_RATIO 0x1 -#define COPY2_RATIO 0x3 -#define DMCP_RATIO 0x1 -#define DMCD_RATIO 0x1 -#define DMC_RATIO 0x1 -#define DPHY_RATIO 0x1 -#define ACP_PCLK_RATIO 0x1 -#define ACP_RATIO 0x3 -#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ - | (COPY2_RATIO << 24) \ - | (DMCP_RATIO << 20) \ - | (DMCD_RATIO << 16) \ - | (DMC_RATIO << 12) \ - | (DPHY_RATIO << 8) \ - | (ACP_PCLK_RATIO << 4) \ - | (ACP_RATIO << 0)) - -/* CLK_DIV_DMC1 */ -#define DPM_RATIO 0x1 -#define DVSEM_RATIO 0x1 -#define PWI_RATIO 0x1 -#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ - | (DVSEM_RATIO << 16) \ - | (PWI_RATIO << 8)) - -/* CLK_SRC_TOP0 */ -#define MUX_ONENAND_SEL_ACLK_133 0x0 -#define MUX_ONENAND_SEL_ACLK_160 0x1 -#define MUX_ACLK_133_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_133_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_160_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_160_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_100_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_100_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_200_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_200_SEL_SCLKAPLL 0x1 -#define MUX_VPLL_SEL_FINPLL 0x0 -#define MUX_VPLL_SEL_FOUTVPLL 0x1 -#define MUX_EPLL_SEL_FINPLL 0x0 -#define MUX_EPLL_SEL_FOUTEPLL 0x1 -#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 -#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 -#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \ - | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ - | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ - | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ - | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ - | (MUX_VPLL_SEL_FINPLL << 8) \ - | (MUX_EPLL_SEL_FINPLL << 4)\ - | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) - -/* CLK_SRC_TOP1 */ -#define VPLLSRC_SEL_FINPLL 0x0 -#define VPLLSRC_SEL_SCLKHDMI24M 0x1 -#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL) - -/* CLK_DIV_TOP */ -#define ONENAND_RATIO 0x0 -#define ACLK_133_RATIO 0x5 -#define ACLK_160_RATIO 0x4 -#define ACLK_100_RATIO 0x7 -#define ACLK_200_RATIO 0x3 -#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ - | (ACLK_133_RATIO << 12)\ - | (ACLK_160_RATIO << 8) \ - | (ACLK_100_RATIO << 4) \ - | (ACLK_200_RATIO << 0)) - -/* CLK_SRC_LEFTBUS */ -#define MUX_GDL_SEL_SCLKMPLL 0x0 -#define MUX_GDL_SEL_SCLKAPLL 0x1 -#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL) - -/* CLK_DIV_LEFTBUS */ -#define GPL_RATIO 0x1 -#define GDL_RATIO 0x3 -#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) - -/* CLK_SRC_RIGHTBUS */ -#define MUX_GDR_SEL_SCLKMPLL 0x0 -#define MUX_GDR_SEL_SCLKAPLL 0x1 -#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL) - -/* CLK_DIV_RIGHTBUS */ -#define GPR_RATIO 0x1 -#define GDR_RATIO 0x3 -#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) - -/* CLK_SRS_FSYS: 6 = SCLKMPLL */ -#define SATA_SEL_SCLKMPLL 0 -#define SATA_SEL_SCLKAPLL 1 - -#define MMC_SEL_XXTI 0 -#define MMC_SEL_XUSBXTI 1 -#define MMC_SEL_SCLK_HDMI24M 2 -#define MMC_SEL_SCLK_USBPHY0 3 -#define MMC_SEL_SCLK_USBPHY1 4 -#define MMC_SEL_SCLK_HDMIPHY 5 -#define MMC_SEL_SCLKMPLL 6 -#define MMC_SEL_SCLKEPLL 7 -#define MMC_SEL_SCLKVPLL 8 - -#define MMCC0_SEL MMC_SEL_SCLKMPLL -#define MMCC1_SEL MMC_SEL_SCLKMPLL -#define MMCC2_SEL MMC_SEL_SCLKMPLL -#define MMCC3_SEL MMC_SEL_SCLKMPLL -#define MMCC4_SEL MMC_SEL_SCLKMPLL -#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ - | (MMCC4_SEL << 16) \ - | (MMCC3_SEL << 12) \ - | (MMCC2_SEL << 8) \ - | (MMCC1_SEL << 4) \ - | (MMCC0_SEL << 0)) - -/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ -/* CLK_DIV_FSYS1 */ -#define MMC0_RATIO 0xF -#define MMC0_PRE_RATIO 0x0 -#define MMC1_RATIO 0xF -#define MMC1_PRE_RATIO 0x0 -#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ - | (MMC1_RATIO << 16) \ - | (MMC0_PRE_RATIO << 8) \ - | (MMC0_RATIO << 0)) - -/* CLK_DIV_FSYS2 */ -#define MMC2_RATIO 0xF -#define MMC2_PRE_RATIO 0x0 -#define MMC3_RATIO 0xF -#define MMC3_PRE_RATIO 0x0 -#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ - | (MMC3_RATIO << 16) \ - | (MMC2_PRE_RATIO << 8) \ - | (MMC2_RATIO << 0)) - -/* CLK_DIV_FSYS3 */ -#define MMC4_RATIO 0xF -#define MMC4_PRE_RATIO 0x0 -#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ - | (MMC4_RATIO << 0)) - -/* CLK_SRC_PERIL0 */ -#define UART_SEL_XXTI 0 -#define UART_SEL_XUSBXTI 1 -#define UART_SEL_SCLK_HDMI24M 2 -#define UART_SEL_SCLK_USBPHY0 3 -#define UART_SEL_SCLK_USBPHY1 4 -#define UART_SEL_SCLK_HDMIPHY 5 -#define UART_SEL_SCLKMPLL 6 -#define UART_SEL_SCLKEPLL 7 -#define UART_SEL_SCLKVPLL 8 - -#define UART0_SEL UART_SEL_SCLKMPLL -#define UART1_SEL UART_SEL_SCLKMPLL -#define UART2_SEL UART_SEL_SCLKMPLL -#define UART3_SEL UART_SEL_SCLKMPLL -#define UART4_SEL UART_SEL_SCLKMPLL -#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ - | (UART0_SEL << 0)) - -/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */ -/* CLK_DIV_PERIL0 */ -#define UART0_RATIO 7 -#define UART1_RATIO 7 -#define UART2_RATIO 7 -#define UART3_RATIO 7 -#define UART4_RATIO 7 -#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ - | (UART3_RATIO << 12) \ - | (UART2_RATIO << 8) \ - | (UART1_RATIO << 4) \ - | (UART0_RATIO << 0)) - -/* Clock Source CAM/FIMC */ -/* CLK_SRC_CAM */ -#define CAM0_SEL_XUSBXTI 1 -#define CAM1_SEL_XUSBXTI 1 -#define CSIS0_SEL_XUSBXTI 1 -#define CSIS1_SEL_XUSBXTI 1 - -#define FIMC_SEL_SCLKMPLL 6 -#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL -#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL -#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL -#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL - -#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \ - | (CSIS0_SEL_XUSBXTI << 24) \ - | (CAM1_SEL_XUSBXTI << 20) \ - | (CAM0_SEL_XUSBXTI << 16) \ - | (FIMC3_LCLK_SEL << 12) \ - | (FIMC2_LCLK_SEL << 8) \ - | (FIMC1_LCLK_SEL << 4) \ - | (FIMC0_LCLK_SEL << 0)) - -/* SCLK CAM */ -/* CLK_DIV_CAM */ -#define FIMC0_LCLK_RATIO 4 -#define FIMC1_LCLK_RATIO 4 -#define FIMC2_LCLK_RATIO 4 -#define FIMC3_LCLK_RATIO 4 -#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \ - | (FIMC2_LCLK_RATIO << 8) \ - | (FIMC1_LCLK_RATIO << 4) \ - | (FIMC0_LCLK_RATIO << 0)) - -/* SCLK MFC */ -/* CLK_SRC_MFC */ -#define MFC_SEL_MPLL 0 -#define MOUTMFC_0 0 -#define MFC_SEL MOUTMFC_0 -#define MFC_0_SEL MFC_SEL_MPLL -#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) - - -/* CLK_DIV_MFC */ -#define MFC_RATIO 3 -#define CLK_DIV_MFC_VAL (MFC_RATIO) - -/* SCLK G3D */ -/* CLK_SRC_G3D */ -#define G3D_SEL_MPLL 0 -#define MOUTG3D_0 0 -#define G3D_SEL MOUTG3D_0 -#define G3D_0_SEL G3D_SEL_MPLL -#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL)) - -/* CLK_DIV_G3D */ -#define G3D_RATIO 1 -#define CLK_DIV_G3D_VAL (G3D_RATIO) - -/* SCLK LCD0 */ -/* CLK_SRC_LCD0 */ -#define FIMD_SEL_SCLKMPLL 6 -#define MDNIE0_SEL_XUSBXTI 1 -#define MDNIE_PWM0_SEL_XUSBXTI 1 -#define MIPI0_SEL_XUSBXTI 1 -#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \ - | (MDNIE_PWM0_SEL_XUSBXTI << 8) \ - | (MDNIE0_SEL_XUSBXTI << 4) \ - | (FIMD_SEL_SCLKMPLL << 0)) - -/* CLK_DIV_LCD0 */ -#define FIMD0_RATIO 4 -#define CLK_DIV_LCD0_VAL (FIMD0_RATIO) - -/* Required period to generate a stable clock output */ -/* PLL_LOCK_TIME */ -#define PLL_LOCKTIME 0x1C20 - -/* PLL Values */ -#define DISABLE 0 -#define ENABLE 1 -#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ - | (mdiv << 16) \ - | (pdiv << 8) \ - | (sdiv << 0)) - -/* APLL_CON0 */ -#define APLL_MDIV 0xFA -#define APLL_PDIV 0x6 -#define APLL_SDIV 0x1 -#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) - -/* APLL_CON1 */ -#define APLL_AFC_ENB 0x1 -#define APLL_AFC 0xC -#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) - -/* MPLL_CON0 */ -#define MPLL_MDIV 0xC8 -#define MPLL_PDIV 0x6 -#define MPLL_SDIV 0x1 -#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) - -/* MPLL_CON1 */ -#define MPLL_AFC_ENB 0x0 -#define MPLL_AFC 0x1C -#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) - -/* EPLL_CON0 */ -#define EPLL_MDIV 0x30 -#define EPLL_PDIV 0x3 -#define EPLL_SDIV 0x2 -#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) - -/* EPLL_CON1 */ -#define EPLL_K 0x0 -#define EPLL_CON1_VAL (EPLL_K >> 0) - -/* VPLL_CON0 */ -#define VPLL_MDIV 0x35 -#define VPLL_PDIV 0x3 -#define VPLL_SDIV 0x2 -#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) - -/* VPLL_CON1 */ -#define VPLL_SSCG_EN DISABLE -#define VPLL_SEL_PF_DN_SPREAD 0x0 -#define VPLL_MRR 0x11 -#define VPLL_MFR 0x0 -#define VPLL_K 0x400 -#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ - | (VPLL_SEL_PF_DN_SPREAD << 29) \ - | (VPLL_MRR << 24) \ - | (VPLL_MFR << 16) \ - | (VPLL_K << 0)) - -/* DMC */ -#define DIRECT_CMD_NOP 0x07000000 -#define DIRECT_CMD_ZQ 0x0a000000 -#define DIRECT_CMD_CHIP1_SHIFT (1 << 20) -#define MEM_TIMINGS_MSR_COUNT 4 -#define CTRL_START (1 << 0) -#define CTRL_DLL_ON (1 << 1) -#define AREF_EN (1 << 5) -#define DRV_TYPE (1 << 6) - -struct mem_timings { - unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; - unsigned timingref; - unsigned timingrow; - unsigned timingdata; - unsigned timingpower; - unsigned zqcontrol; - unsigned control0; - unsigned control1; - unsigned control2; - unsigned concontrol; - unsigned prechconfig; - unsigned memcontrol; - unsigned memconfig0; - unsigned memconfig1; - unsigned dll_resync; - unsigned dll_on; -}; - -/* MIU */ -/* MIU Config Register Offsets*/ -#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 -#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 -#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800 -#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808 -#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810 -#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818 -#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820 -#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 -#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830 - -#ifdef CONFIG_ORIGEN -/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ -#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 -#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 -#endif - -#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000 -#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff -#define INTERLEAVE_ADDR_MAP_EN 0x00000001 - -#ifdef CONFIG_MIU_1BIT_INTERLEAVED -/* Interleave_bit0: 0xC*/ -#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c -#endif -#ifdef CONFIG_MIU_2BIT_INTERLEAVED -/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */ -#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c -#endif -#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000 -#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff -#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000 -#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff -/* Enable SME0 and SME1*/ -#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006 - -#define FORCE_DLL_RESYNC 3 -#define DLL_CONTROL_ON 1 - -#define DIRECT_CMD1 0x00020000 -#define DIRECT_CMD2 0x00030000 -#define DIRECT_CMD3 0x00010002 -#define DIRECT_CMD4 0x00000328 - -#define CTRL_ZQ_MODE_NOTERM (0x1 << 0) -#define CTRL_ZQ_START (0x1 << 1) -#define CTRL_ZQ_DIV (0 << 4) -#define CTRL_ZQ_MODE_DDS (0x7 << 8) -#define CTRL_ZQ_MODE_TERM (0x2 << 11) -#define CTRL_ZQ_FORCE_IMPN (0x5 << 14) -#define CTRL_ZQ_FORCE_IMPP (0x6 << 17) -#define CTRL_DCC (0xE38 << 20) -#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\ - | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\ - | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\ - | CTRL_ZQ_FORCE_IMPP | CTRL_DCC) - -#define ASYNC (0 << 0) -#define CLK_RATIO (1 << 1) -#define DIV_PIPE (1 << 3) -#define AWR_ON (1 << 4) -#define AREF_DISABLE (0 << 5) -#define DRV_TYPE_DISABLE (0 << 6) -#define CHIP0_NOT_EMPTY (0 << 8) -#define CHIP1_NOT_EMPTY (0 << 9) -#define DQ_SWAP_DISABLE (0 << 10) -#define QOS_FAST_DISABLE (0 << 11) -#define RD_FETCH (0x3 << 12) -#define TIMEOUT_LEVEL0 (0xFFF << 16) -#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\ - | AREF_DISABLE | DRV_TYPE_DISABLE\ - | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\ - | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\ - | RD_FETCH | TIMEOUT_LEVEL0) - -#define CLK_STOP_DISABLE (0 << 1) -#define DPWRDN_DISABLE (0 << 2) -#define DPWRDN_TYPE (0 << 3) -#define TP_DISABLE (0 << 4) -#define DSREF_DIABLE (0 << 5) -#define ADD_LAT_PALL (1 << 6) -#define MEM_TYPE_DDR3 (0x6 << 8) -#define MEM_WIDTH_32 (0x2 << 12) -#define NUM_CHIP_2 (1 << 16) -#define BL_8 (0x3 << 20) -#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\ - | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\ - | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\ - | NUM_CHIP_2 | BL_8) - - -#define CHIP_BANK_8 (0x3 << 0) -#define CHIP_ROW_14 (0x2 << 4) -#define CHIP_COL_10 (0x3 << 8) -#define CHIP_MAP_INTERLEAVED (1 << 12) -#define CHIP_MASK (0xe0 << 16) -#ifdef CONFIG_MIU_LINEAR -#define CHIP0_BASE (0x40 << 24) -#define CHIP1_BASE (0x60 << 24) -#else -#define CHIP0_BASE (0x20 << 24) -#define CHIP1_BASE (0x40 << 24) -#endif -#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\ - | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE) -#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\ - | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE) - -#define TP_CNT (0xff << 24) -#define PRECHCONFIG TP_CNT - -#define CTRL_OFF (0 << 0) -#define CTRL_DLL_OFF (0 << 1) -#define CTRL_HALF (0 << 2) -#define CTRL_DFDQS (1 << 3) -#define DQS_DELAY (0 << 4) -#define CTRL_START_POINT (0x10 << 8) -#define CTRL_INC (0x10 << 16) -#define CTRL_FORCE (0x71 << 24) -#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\ - | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\ - | CTRL_INC | CTRL_FORCE) - -#define CTRL_SHIFTC (0x6 << 0) -#define CTRL_REF (8 << 4) -#define CTRL_SHGATE (1 << 29) -#define TERM_READ_EN (1 << 30) -#define TERM_WRITE_EN (1 << 31) -#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\ - | TERM_READ_EN | TERM_WRITE_EN) - -#define CONTROL2_VAL 0x00000000 - -#ifdef CONFIG_ORIGEN -#define TIMINGREF_VAL 0x000000BB -#define TIMINGROW_VAL 0x4046654f -#define TIMINGDATA_VAL 0x46400506 -#define TIMINGPOWER_VAL 0x52000A3C -#else -#define TIMINGREF_VAL 0x000000BC -#ifdef DRAM_CLK_330 -#define TIMINGROW_VAL 0x3545548d -#define TIMINGDATA_VAL 0x45430506 -#define TIMINGPOWER_VAL 0x4439033c -#endif -#ifdef DRAM_CLK_400 -#define TIMINGROW_VAL 0x45430506 -#define TIMINGDATA_VAL 0x56500506 -#define TIMINGPOWER_VAL 0x5444033d -#endif -#endif -#endif diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h deleted file mode 100644 index 9073f50f6b..0000000000 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ /dev/null @@ -1,947 +0,0 @@ -/* - * Machine Specific Values for SMDK5250 board based on EXYNOS5 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SMDK5250_SETUP_H -#define _SMDK5250_SETUP_H - -#include <config.h> -#include <asm/arch/dmc.h> - -#define NOT_AVAILABLE 0 -#define DATA_MASK 0xFFFFF - -#define ENABLE_BIT 0x1 -#define DISABLE_BIT 0x0 -#define CA_SWAP_EN (1 << 0) - -/* Set PLL */ -#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) - -/* MEMCONTROL register bit fields */ -#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) -#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) -#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2) -#define DMC_MEMCONTROL_TP_DISABLE (0 << 4) -#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) -#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) -#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) - -#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8) - -#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) - -#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) - -#define DMC_MEMCONTROL_BL_8 (3 << 20) -#define DMC_MEMCONTROL_BL_4 (2 << 20) - -#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) - -#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) - -/* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) -#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) -#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0) - -#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0) -#define DMC_MEMBASECONFIG_VAL(x) ( \ - DMC_MEMBASECONFIGX_CHIP_BASE(x) | \ - DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \ -) - -/* - * As we use channel interleaving, therefore value of the base address - * register must be set as half of the bus base address - * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so - * we need to set half 0x10 to the membaseconfigx registers - * see exynos5420 UM section 17.17.3.21 for more. - */ -#define DMC_CHIP_BASE_0 0x10 -#define DMC_CHIP_BASE_1 0x50 -#define DMC_CHIP_MASK 0x7C0 - -#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) -#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) - -#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF - -#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 -#define DFI_INIT_START (1 << 28) -#define EMPTY (1 << 8) -#define AREF_EN (1 << 5) - -#define DFI_INIT_COMPLETE_CHO (1 << 2) -#define DFI_INIT_COMPLETE_CH1 (1 << 3) - -#define RDLVL_COMPLETE_CHO (1 << 14) -#define RDLVL_COMPLETE_CH1 (1 << 15) - -#define CLK_STOP_EN (1 << 0) -#define DPWRDN_EN (1 << 1) -#define DSREF_EN (1 << 5) - -/* COJCONTROL register bit fields */ -#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) -#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3) -#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) -#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5) -#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) -#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) -#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) -#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) -#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) - -#define DMC_CONCONTROL_VAL 0x1FFF2101 - -#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \ - | DMC_CONCONTROL_AREF_EN_ENABLE \ - | DMC_CONCONTROL_IO_PD_CON_ENABLE - -#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6) - -/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x2 -#define COPY_RATIO 0x0 - -/* CLK_DIV_CPU1 = 0x00000003 */ -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ - | (COPY_RATIO)) - -/* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00000000 - -/* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 - -/* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x00120000 - -/* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 - -/* CLK_DIV_SYSRGT */ -#define CLK_DIV_SYSRGT_VAL 0x00000111 - -/* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 - -/* CLK_DIV_SYSLFT */ -#define CLK_DIV_SYSLFT_VAL 0x00000311 - -#define MUX_APLL_SEL_MASK (1 << 0) -#define MUX_MPLL_SEL_MASK (1 << 8) -#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) -#define MUX_CPLL_SEL_MASK (1 << 8) -#define MUX_EPLL_SEL_MASK (1 << 12) -#define MUX_VPLL_SEL_MASK (1 << 16) -#define MUX_GPLL_SEL_MASK (1 << 28) -#define MUX_BPLL_SEL_MASK (1 << 0) -#define MUX_HPM_SEL_MASK (1 << 20) -#define HPM_SEL_SCLK_MPLL (1 << 21) -#define PLL_LOCKED (1 << 29) -#define APLL_CON0_LOCKED (1 << 29) -#define MPLL_CON0_LOCKED (1 << 29) -#define BPLL_CON0_LOCKED (1 << 29) -#define CPLL_CON0_LOCKED (1 << 29) -#define EPLL_CON0_LOCKED (1 << 29) -#define GPLL_CON0_LOCKED (1 << 29) -#define VPLL_CON0_LOCKED (1 << 29) -#define CLK_REG_DISABLE 0x0 -#define TOP2_VAL 0x0110000 - -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ -#define SPI0_ISP_SEL 6 -#define SPI1_ISP_SEL 6 -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ - | (SPI0_ISP_SEL << 0) - -/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ -#define SPI0_ISP_RATIO 0xf -#define SPI1_ISP_RATIO 0xf -#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ - | (SPI0_ISP_RATIO << 0) - -/* CLK_DIV_FSYS2 */ -#define MMC2_RATIO_MASK 0xf -#define MMC2_RATIO_VAL 0x3 -#define MMC2_RATIO_OFFSET 0 - -#define MMC2_PRE_RATIO_MASK 0xff -#define MMC2_PRE_RATIO_VAL 0x9 -#define MMC2_PRE_RATIO_OFFSET 8 - -#define MMC3_RATIO_MASK 0xf -#define MMC3_RATIO_VAL 0x1 -#define MMC3_RATIO_OFFSET 16 - -#define MMC3_PRE_RATIO_MASK 0xff -#define MMC3_PRE_RATIO_VAL 0x0 -#define MMC3_PRE_RATIO_OFFSET 24 - -/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 - -/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 - -/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 - -/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 - -/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 - -/* CLK_SRC_KFC */ -#define SRC_KFC_HPM_SEL (1 << 15) - -/* CLK_SRC_KFC */ -#define CLK_SRC_KFC_VAL 0x00008001 - -/* CLK_DIV_KFC */ -#define CLK_DIV_KFC_VAL 0x03300110 - -/* CLK_DIV2_RATIO */ -#define CLK_DIV2_RATIO 0x10111150 - -/* CLK_DIV4_RATIO */ -#define CLK_DIV4_RATIO 0x00000003 - -/* CLK_DIV_G2D */ -#define CLK_DIV_G2D 0x00000010 - -/* - * DIV_DISP1_0 - * For DP, divisor should be 2 - */ -#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) - -/* CLK_GATE_IP_DISP1 */ -#define CLK_GATE_DP1_ALLOW (1 << 4) - -/* AUDIO CLK SEL */ -#define AUDIO0_SEL_EPLL (0x6 << 28) -#define AUDIO0_RATIO 0x5 -#define PCM0_RATIO 0x3 -#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) - -/* CLK_SRC_CDREX */ -#define MUX_MCLK_CDR_MSPLL (1 << 4) -#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) -#define BPLL_SEL_MASK 0x7 -#define FOUTBPLL 2 - -#define DDR3PHY_CTRL_PHY_RESET (1 << 0) -#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) - -#define PHY_CON0_RESET_VAL 0x17020a40 -#define P0_CMD_EN (1 << 14) -#define BYTE_RDLVL_EN (1 << 13) -#define CTRL_SHGATE (1 << 8) - -#define PHY_CON1_RESET_VAL 0x09210100 -#define RDLVL_PASS_ADJ_VAL 0x6 -#define RDLVL_PASS_ADJ_OFFSET 16 -#define CTRL_GATEDURADJ_MASK (0xf << 20) -#define READ_LEVELLING_DDR3 0x0100 - -#define PHY_CON2_RESET_VAL 0x00010004 -#define INIT_DESKEW_EN (1 << 6) -#define DLL_DESKEW_EN (1 << 12) -#define RDLVL_GATE_EN (1 << 24) -#define RDLVL_EN (1 << 25) -#define RDLVL_INCR_ADJ (0x1 << 16) - -/* DREX_PAUSE */ -#define DREX_PAUSE_EN (1 << 0) - -#define BYPASS_EN (1 << 22) - -/* MEMMORY VAL */ -#define PHY_CON0_VAL 0x17021A00 - -#define PHY_CON12_RESET_VAL 0x10100070 -#define PHY_CON12_VAL 0x10107F50 -#define CTRL_START (1 << 6) -#define CTRL_DLL_ON (1 << 5) -#define CTRL_LOCK_COARSE_OFFSET 10 -#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) -#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ - CTRL_LOCK_COARSE_OFFSET) -#define CTRL_FORCE_MASK (0x7F << 8) -#define CTRL_FINE_LOCKED 0x7 - -#define CTRL_OFFSETD_RESET_VAL 0x8 -#define CTRL_OFFSETD_VAL 0x7F - -#define CTRL_OFFSETR0 0x7F -#define CTRL_OFFSETR1 0x7F -#define CTRL_OFFSETR2 0x7F -#define CTRL_OFFSETR3 0x7F -#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \ - CTRL_OFFSETR1 << 8 | \ - CTRL_OFFSETR2 << 16 | \ - CTRL_OFFSETR3 << 24) -#define PHY_CON4_RESET_VAL 0x08080808 - -#define CTRL_OFFSETW0 0x7F -#define CTRL_OFFSETW1 0x7F -#define CTRL_OFFSETW2 0x7F -#define CTRL_OFFSETW3 0x7F -#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \ - CTRL_OFFSETW1 << 8 | \ - CTRL_OFFSETW2 << 16 | \ - CTRL_OFFSETW3 << 24) -#define PHY_CON6_RESET_VAL 0x08080808 - -#define PHY_CON14_RESET_VAL 0x001F0000 -#define CTRL_PULLD_DQS 0xF -#define CTRL_PULLD_DQS_OFFSET 0 - -/* ZQ Configurations */ -#define PHY_CON16_RESET_VAL 0x08000304 - -#define ZQ_CLK_EN (1 << 27) -#define ZQ_CLK_DIV_EN (1 << 18) -#define ZQ_MANUAL_STR (1 << 1) -#define ZQ_DONE (1 << 0) -#define ZQ_MODE_DDS_OFFSET 24 - -#define CTRL_RDLVL_GATE_ENABLE 1 -#define CTRL_RDLVL_GATE_DISABLE 0 -#define CTRL_RDLVL_DATA_ENABLE 2 - -/* Direct Command */ -#define DIRECT_CMD_NOP 0x07000000 -#define DIRECT_CMD_PALL 0x01000000 -#define DIRECT_CMD_ZQINIT 0x0a000000 -#define DIRECT_CMD_CHANNEL_SHIFT 28 -#define DIRECT_CMD_CHIP_SHIFT 20 -#define DIRECT_CMD_BANK_SHIFT 16 -#define DIRECT_CMD_REFA (5 << 24) -#define DIRECT_CMD_MRS1 0x71C00 -#define DIRECT_CMD_MRS2 0x10BFC -#define DIRECT_CMD_MRS3 0x0050C -#define DIRECT_CMD_MRS4 0x00868 -#define DIRECT_CMD_MRS5 0x00C04 - -/* Drive Strength */ -#define IMPEDANCE_48_OHM 4 -#define IMPEDANCE_40_OHM 5 -#define IMPEDANCE_34_OHM 6 -#define IMPEDANCE_30_OHM 7 -#define PHY_CON39_VAL_48_OHM 0x09240924 -#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D -#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 -#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF - -#define CTRL_BSTLEN_OFFSET 8 -#define CTRL_RDLAT_OFFSET 0 - -#define CMD_DEFAULT_LPDDR3 0xF -#define CMD_DEFUALT_OFFSET 0 -#define T_WRDATA_EN 0x7 -#define T_WRDATA_EN_DDR3 0x8 -#define T_WRDATA_EN_OFFSET 16 -#define T_WRDATA_EN_MASK 0x1f - -#define PHY_CON31_VAL 0x0C183060 -#define PHY_CON32_VAL 0x60C18306 -#define PHY_CON33_VAL 0x00000030 - -#define PHY_CON31_RESET_VAL 0x0 -#define PHY_CON32_RESET_VAL 0x0 -#define PHY_CON33_RESET_VAL 0x0 - -#define SL_DLL_DYN_CON_EN (1 << 1) -#define FP_RESYNC (1 << 3) -#define CTRL_START (1 << 6) - -#define DMC_AREF_EN (1 << 5) -#define DMC_CONCONTROL_EMPTY (1 << 8) -#define DFI_INIT_START (1 << 28) - -#define DMC_MEMCONTROL_VAL 0x00312700 -#define CLK_STOP_EN (1 << 0) -#define DPWRDN_EN (1 << 1) -#define DSREF_EN (1 << 5) - -#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 -#define MEMBASECONFIG_CHIP_MASK_OFFSET 0 -#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20 -#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40 -#define CHIP_BASE_OFFSET 16 - -#define MEMCONFIG_VAL 0x1323 -#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 -#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF - -#define TIMINGAREF_VAL 0x5d -#define TIMINGROW_VAL 0x345A8692 -#define TIMINGDATA_VAL 0x3630065C -#define TIMINGPOWER_VAL 0x50380336 -#define DFI_INIT_COMPLETE (1 << 3) - -#define BRBRSVCONTROL_VAL 0x00000033 -#define BRBRSVCONFIG_VAL 0x88778877 - -/* Clock Gating Control (CGCONTROL) register */ -#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ -#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ -#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ -#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ -#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ - BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) - -/* DMC PHY Control0 register */ -#define PHY_CONTROL0_RESET_VAL 0x0 -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ - -/* Driver strength for CK, CKE, CS & CA */ -#define IMP_OUTPUT_DRV_40_OHM 0x5 -#define IMP_OUTPUT_DRV_30_OHM 0x7 -#define DA_3_DS_OFFSET 25 -#define DA_2_DS_OFFSET 22 -#define DA_1_DS_OFFSET 19 -#define DA_0_DS_OFFSET 16 -#define CA_CK_DRVR_DS_OFFSET 9 -#define CA_CKE_DRVR_DS_OFFSET 6 -#define CA_CS_DRVR_DS_OFFSET 3 -#define CA_ADR_DRVR_DS_OFFSET 0 - -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 -#define PHY_CON42_CTRL_RDLAT_SHIFT 0 - -/* - * Definitions that differ with SoC's. - * Below is the part defining macros for Exynos5250. - * Else part introduces macros for Exynos5420. - */ -#ifndef CONFIG_EXYNOS5420 - -/* APLL_CON1 */ -#define APLL_CON1_VAL (0x00203800) - -/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) - -/* CPLL_CON1 */ -#define CPLL_CON1_VAL (0x00203800) - -/* DPLL_CON1 */ -#define DPLL_CON1_VAL (NOT_AVAILABLE) - -/* GPLL_CON1 */ -#define GPLL_CON1_VAL (0x00203800) - -/* EPLL_CON1, CON2 */ -#define EPLL_CON1_VAL 0x00000000 -#define EPLL_CON2_VAL 0x00000080 - -/* VPLL_CON1, CON2 */ -#define VPLL_CON1_VAL 0x00000000 -#define VPLL_CON2_VAL 0x00000080 - -/* RPLL_CON1, CON2 */ -#define RPLL_CON1_VAL NOT_AVAILABLE -#define RPLL_CON2_VAL NOT_AVAILABLE - -/* BPLL_CON1 */ -#define BPLL_CON1_VAL 0x00203800 - -/* SPLL_CON1 */ -#define SPLL_CON1_VAL NOT_AVAILABLE - -/* IPLL_CON1 */ -#define IPLL_CON1_VAL NOT_AVAILABLE - -/* KPLL_CON1 */ -#define KPLL_CON1_VAL NOT_AVAILABLE - -/* CLK_SRC_ISP */ -#define CLK_SRC_ISP_VAL NOT_AVAILABLE -#define CLK_DIV_ISP0_VAL 0x31 -#define CLK_DIV_ISP1_VAL 0x0 - -/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 -#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE -#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE - -/* CLK_SRC_CPU */ -/* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 - -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ - | (MUX_CPU_SEL << 16) \ - | (MUX_APLL_SEL)) - -/* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x1 - -/* CLK_DIV_CDREX */ -#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE -#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE - -/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL NOT_AVAILABLE - -#define MCLK_CDREX2_RATIO 0x0 -#define ACLK_EFCON_RATIO 0x1 -#define MCLK_DPHY_RATIO 0x1 -#define MCLK_CDREX_RATIO 0x1 -#define ACLK_C2C_200_RATIO 0x1 -#define C2C_CLK_400_RATIO 0x1 -#define PCLK_CDREX_RATIO 0x1 -#define ACLK_CDREX_RATIO 0x1 - -#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ - | (C2C_CLK_400_RATIO << 6) \ - | (PCLK_CDREX_RATIO << 4) \ - | (ACLK_CDREX_RATIO)) - -/* CLK_SRC_TOP0 */ -#define MUX_ACLK_300_GSCL_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID_SEL 0x0 -#define MUX_ACLK_400_G3D_MID_SEL 0x0 -#define MUX_ACLK_333_SEL 0x0 -#define MUX_ACLK_300_DISP1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID_SEL 0x0 -#define MUX_ACLK_200_SEL 0x0 -#define MUX_ACLK_166_SEL 0x0 -#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ - | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ - | (MUX_ACLK_400_G3D_MID_SEL << 20) \ - | (MUX_ACLK_333_SEL << 16) \ - | (MUX_ACLK_300_DISP1_SEL << 15) \ - | (MUX_ACLK_300_DISP1_MID_SEL << 14) \ - | (MUX_ACLK_200_SEL << 12) \ - | (MUX_ACLK_166_SEL << 8)) - -/* CLK_SRC_TOP1 */ -#define MUX_ACLK_400_G3D_SEL 0x1 -#define MUX_ACLK_400_ISP_SEL 0x0 -#define MUX_ACLK_400_IOP_SEL 0x0 -#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 -#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ - |(MUX_ACLK_400_ISP_SEL << 24) \ - |(MUX_ACLK_400_IOP_SEL << 20) \ - |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ - |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ - |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) - -/* CLK_SRC_TOP2 */ -#define MUX_GPLL_SEL 0x1 -#define MUX_BPLL_USER_SEL 0x0 -#define MUX_MPLL_USER_SEL 0x0 -#define MUX_VPLL_SEL 0x1 -#define MUX_EPLL_SEL 0x1 -#define MUX_CPLL_SEL 0x1 -#define VPLLSRC_SEL 0x0 -#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ - | (MUX_BPLL_USER_SEL << 24) \ - | (MUX_MPLL_USER_SEL << 20) \ - | (MUX_VPLL_SEL << 16) \ - | (MUX_EPLL_SEL << 12) \ - | (MUX_CPLL_SEL << 8) \ - | (VPLLSRC_SEL)) -/* CLK_SRC_TOP3 */ -#define MUX_ACLK_333_SUB_SEL 0x1 -#define MUX_ACLK_400_SUB_SEL 0x1 -#define MUX_ACLK_266_ISP_SUB_SEL 0x1 -#define MUX_ACLK_266_GPS_SUB_SEL 0x0 -#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 -#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 -#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ - | (MUX_ACLK_400_SUB_SEL << 20) \ - | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ - | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ - | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ - | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ - | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ - | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) - -#define CLK_SRC_TOP4_VAL NOT_AVAILABLE -#define CLK_SRC_TOP5_VAL NOT_AVAILABLE -#define CLK_SRC_TOP6_VAL NOT_AVAILABLE -#define CLK_SRC_TOP7_VAL NOT_AVAILABLE - -/* CLK_DIV_TOP0 */ -#define ACLK_300_DISP1_RATIO 0x2 -#define ACLK_400_G3D_RATIO 0x0 -#define ACLK_333_RATIO 0x0 -#define ACLK_266_RATIO 0x2 -#define ACLK_200_RATIO 0x3 -#define ACLK_166_RATIO 0x1 -#define ACLK_133_RATIO 0x1 -#define ACLK_66_RATIO 0x5 - -#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \ - | (ACLK_400_G3D_RATIO << 24) \ - | (ACLK_333_RATIO << 20) \ - | (ACLK_266_RATIO << 16) \ - | (ACLK_200_RATIO << 12) \ - | (ACLK_166_RATIO << 8) \ - | (ACLK_133_RATIO << 4) \ - | (ACLK_66_RATIO)) - -/* CLK_DIV_TOP1 */ -#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 -#define ACLK_66_PRE_RATIO 0x1 -#define ACLK_400_ISP_RATIO 0x1 -#define ACLK_400_IOP_RATIO 0x1 -#define ACLK_300_GSCL_RATIO 0x2 - -#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ - | (ACLK_66_PRE_RATIO << 24) \ - | (ACLK_400_ISP_RATIO << 20) \ - | (ACLK_400_IOP_RATIO << 16) \ - | (ACLK_300_GSCL_RATIO << 12)) - -#define CLK_DIV_TOP2_VAL NOT_AVAILABLE - -/* PLL Lock Value Factor */ -#define PLL_LOCK_FACTOR 250 -#define PLL_X_LOCK_FACTOR 3000 - -/* CLK_SRC_PERIC0 */ -#define PWM_SEL 6 -#define UART3_SEL 6 -#define UART2_SEL 6 -#define UART1_SEL 6 -#define UART0_SEL 6 -/* SRC_CLOCK = SCLK_MPLL */ -#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ - | (UART0_SEL)) - -/* CLK_SRC_PERIC1 */ -/* SRC_CLOCK = SCLK_MPLL */ -#define SPI0_SEL 6 -#define SPI1_SEL 6 -#define SPI2_SEL 6 -#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \ - | (SPI1_SEL << 20) \ - | (SPI0_SEL << 16)) - -/* CLK_DIV_PERIL0 */ -#define UART5_RATIO 7 -#define UART4_RATIO 7 -#define UART3_RATIO 7 -#define UART2_RATIO 7 -#define UART1_RATIO 7 -#define UART0_RATIO 7 - -#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ - | (UART2_RATIO << 8) \ - | (UART1_RATIO << 4) \ - | (UART0_RATIO)) -/* CLK_DIV_PERIC1 */ -#define SPI1_RATIO 0x7 -#define SPI0_RATIO 0xf -#define SPI1_SUB_RATIO 0x0 -#define SPI0_SUB_RATIO 0x0 -#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ - | ((SPI1_RATIO << 16) \ - | (SPI0_SUB_RATIO << 8) \ - | (SPI0_RATIO << 0))) - -/* CLK_DIV_PERIC2 */ -#define SPI2_RATIO 0xf -#define SPI2_SUB_RATIO 0x0 -#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \ - | (SPI2_RATIO << 0)) - -/* CLK_DIV_PERIC3 */ -#define PWM_RATIO 8 -#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) - - -/* CLK_DIV_PERIC4 */ -#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE - -/* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x6 -#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE - -#define APLL_FOUT (1 << 0) -#define KPLL_FOUT NOT_AVAILABLE - -#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE - -#else - -#define CPU_CONFIG_STATUS_OFFSET 0x80 -#define CPU_RST_FLAG_VAL 0xFCBA0D10 -#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 - -/* APLL_CON1 */ -#define APLL_CON1_VAL (0x0020F300) - -/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x0020F300) - - -/* CPLL_CON1 */ -#define CPLL_CON1_VAL 0x0020f300 - -/* DPLL_CON1 */ -#define DPLL_CON1_VAL (0x0020F300) - -/* GPLL_CON1 */ -#define GPLL_CON1_VAL (NOT_AVAILABLE) - - -/* EPLL_CON1, CON2 */ -#define EPLL_CON1_VAL 0x00000000 -#define EPLL_CON2_VAL 0x00000080 - -/* VPLL_CON1, CON2 */ -#define VPLL_CON1_VAL 0x0020f300 -#define VPLL_CON2_VAL NOT_AVAILABLE - -/* RPLL_CON1, CON2 */ -#define RPLL_CON1_VAL 0x00000000 -#define RPLL_CON2_VAL 0x00000080 - -/* BPLL_CON1 */ -#define BPLL_CON1_VAL 0x0020f300 - -/* SPLL_CON1 */ -#define SPLL_CON1_VAL 0x0020f300 - -/* IPLL_CON1 */ -#define IPLL_CON1_VAL 0x00000080 - -/* KPLL_CON1 */ -#define KPLL_CON1_VAL 0x200000 - -/* CLK_SRC_ISP */ -#define CLK_SRC_ISP_VAL 0x33366000 -#define CLK_DIV_ISP0_VAL 0x13131300 -#define CLK_DIV_ISP1_VAL 0xbb110202 - - -/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x33033300 -#define CLK_DIV_FSYS0_VAL 0x0 -#define CLK_DIV_FSYS1_VAL 0x04f13c4f -#define CLK_DIV_FSYS2_VAL 0x041d0000 - -/* CLK_SRC_CPU */ -/* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 1 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 - -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ - | (MUX_CPU_SEL << 16) \ - | (MUX_APLL_SEL)) - -/* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x00000011 - -/* CLK_DIV_CDREX */ -#define CLK_DIV_CDREX0_VAL 0x30010100 -#define CLK_DIV_CDREX1_VAL 0x300 - -#define CLK_DIV_CDREX_VAL 0x17010100 - -/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL 0x01440020 - -/* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12221222 -#define CLK_SRC_TOP1_VAL 0x00100200 -#define CLK_SRC_TOP2_VAL 0x11101000 -#define CLK_SRC_TOP3_VAL 0x11111111 -#define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111101 -#define CLK_SRC_TOP6_VAL 0x11110111 -#define CLK_SRC_TOP7_VAL 0x00022200 - -/* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23712311 -#define CLK_DIV_TOP1_VAL 0x13100B00 -#define CLK_DIV_TOP2_VAL 0x11101100 - -/* PLL Lock Value Factor */ -#define PLL_LOCK_FACTOR 200 -#define PLL_X_LOCK_FACTOR 3000 - -/* CLK_SRC_PERIC0 */ -#define SPDIF_SEL 1 -#define PWM_SEL 3 -#define UART4_SEL 3 -#define UART3_SEL 3 -#define UART2_SEL 3 -#define UART1_SEL 3 -#define UART0_SEL 3 -/* SRC_CLOCK = SCLK_RPLL */ -#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ - | (PWM_SEL << 24) \ - | (UART4_SEL << 20) \ - | (UART3_SEL << 16) \ - | (UART2_SEL << 12) \ - | (UART1_SEL << 8) \ - | (UART0_SEL << 4)) - -/* CLK_SRC_PERIC1 */ -/* SRC_CLOCK = SCLK_EPLL */ -#define SPI0_SEL 6 -#define SPI1_SEL 6 -#define SPI2_SEL 6 -#define AUDIO0_SEL 6 -#define AUDIO1_SEL 6 -#define AUDIO2_SEL 6 -#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \ - | (SPI1_SEL << 24) \ - | (SPI0_SEL << 20) \ - | (AUDIO2_SEL << 16) \ - | (AUDIO2_SEL << 12) \ - | (AUDIO2_SEL << 8)) - -/* CLK_DIV_PERIC0 */ -#define PWM_RATIO 8 -#define UART4_RATIO 9 -#define UART3_RATIO 9 -#define UART2_RATIO 9 -#define UART1_RATIO 9 -#define UART0_RATIO 9 - -#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ - | (UART4_RATIO << 24) \ - | (UART3_RATIO << 20) \ - | (UART2_RATIO << 16) \ - | (UART1_RATIO << 12) \ - | (UART0_RATIO << 8)) -/* CLK_DIV_PERIC1 */ -#define SPI2_RATIO 0x1 -#define SPI1_RATIO 0x1 -#define SPI0_RATIO 0x1 -#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ - | (SPI1_RATIO << 24) \ - | (SPI0_RATIO << 20)) - -/* CLK_DIV_PERIC2 */ -#define PCM2_RATIO 0x3 -#define PCM1_RATIO 0x3 -#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \ - | (PCM1_RATIO << 16)) - -/* CLK_DIV_PERIC3 */ -#define AUDIO2_RATIO 0x5 -#define AUDIO1_RATIO 0x5 -#define AUDIO0_RATIO 0x5 -#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ - | (AUDIO1_RATIO << 24) \ - | (AUDIO0_RATIO << 20)) - -/* CLK_DIV_PERIC4 */ -#define SPI2_PRE_RATIO 0x2 -#define SPI1_PRE_RATIO 0x2 -#define SPI0_PRE_RATIO 0x2 -#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ - | (SPI1_PRE_RATIO << 16) \ - | (SPI0_PRE_RATIO << 8)) - -/* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x10666600 -#define CLK_DIV_DISP1_0_VAL 0x01050211 - -#define APLL_FOUT (1 << 0) -#define KPLL_FOUT (1 << 0) - -#define CLK_DIV_CPERI1_VAL 0x3f3f0000 -#endif - -struct mem_timings; - -/* Errors that we can encourter in low-level setup */ -enum { - SETUP_ERR_OK, - SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1, - SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2, -}; - -/* - * Memory variant specific initialization code for DDR3 - * - * @param mem Memory timings for this memory type. - * @param reset Reset DDR PHY during initialization. - * @return 0 if ok, SETUP_ERR_... if there is a problem - */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset); - -/* Memory variant specific initialization code for LPDDR3 */ -void lpddr3_mem_ctrl_init(void); - -/* - * Configure ZQ I/O interface - * - * @param mem Memory timings for this memory type. - * @param phy0_con16 Register address for dmc_phy0->phy_con16 - * @param phy1_con16 Register address for dmc_phy1->phy_con16 - * @param phy0_con17 Register address for dmc_phy0->phy_con17 - * @param phy1_con17 Register address for dmc_phy1->phy_con17 - * @return 0 if ok, -1 on error - */ -int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, - uint32_t *phy1_con16, uint32_t *phy0_con17, - uint32_t *phy1_con17); -/* - * Send NOP and MRS/EMRS Direct commands - * - * @param mem Memory timings for this memory type. - * @param directcmd Register address for dmc_phy->directcmd - */ -void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd); - -/* - * Send PALL Direct commands - * - * @param mem Memory timings for this memory type. - * @param directcmd Register address for dmc_phy->directcmd - */ -void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd); - -/* - * Reset the DLL. This function is common between DDR3 and LPDDR2. - * However, the reset value is different. So we are passing a flag - * ddr_mode to distinguish between LPDDR2 and DDR3. - * - * @param phycontrol0 Register address for dmc_phy->phycontrol0 - * @param ddr_mode Type of DDR memory - */ -void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode); -#endif diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c deleted file mode 100644 index 3774607848..0000000000 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Lowlevel setup for EXYNOS5 based board - * - * Copyright (C) 2013 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <debug_uart.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dmc.h> -#include <asm/arch/power.h> -#include <asm/arch/tzpc.h> -#include <asm/arch/periph.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/system.h> -#include <asm/armv7.h> -#include "common_setup.h" -#include "exynos5_setup.h" - -/* These are the things we can do during low-level init */ -enum { - DO_WAKEUP = 1 << 0, - DO_CLOCKS = 1 << 1, - DO_MEM_RESET = 1 << 2, - DO_UART = 1 << 3, - DO_POWER = 1 << 4, -}; - -#ifdef CONFIG_EXYNOS5420 -/* - * Power up secondary CPUs. - */ -static void secondary_cpu_start(void) -{ - v7_enable_smp(EXYNOS5420_INFORM_BASE); - svc32_mode_en(); - branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE); -} - -/* - * This is the entry point of hotplug-in and - * cluster switching. - */ -static void low_power_start(void) -{ - uint32_t val, reg_val; - - reg_val = readl(EXYNOS5420_SPARE_BASE); - if (reg_val != CPU_RST_FLAG_VAL) { - writel(0x0, CONFIG_LOWPOWER_FLAG); - branch_bx(0x0); - } - - reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); - if (reg_val != (uint32_t)&low_power_start) { - /* Store jump address as low_power_start if not present */ - writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4); - dsb(); - sev(); - } - - /* Set the CPU to SVC32 mode */ - svc32_mode_en(); - -#ifndef CONFIG_SYS_L2CACHE_OFF - /* Read MIDR for Primary Part Number */ - mrc_midr(val); - val = (val >> 4); - val &= 0xf; - - if (val == 0xf) { - configure_l2_ctlr(); - configure_l2_actlr(); - v7_enable_l2_hazard_detect(); - } -#endif - - /* Invalidate L1 & TLB */ - val = 0x0; - mcr_tlb(val); - mcr_icache(val); - - /* Disable MMU stuff and caches */ - mrc_sctlr(val); - - val &= ~((0x2 << 12) | 0x7); - val |= ((0x1 << 12) | (0x8 << 8) | 0x2); - mcr_sctlr(val); - - /* CPU state is hotplug or reset */ - secondary_cpu_start(); - - /* Core should not enter into WFI here */ - wfi(); -} - -/* - * Pointer to this function is stored in iRam which is used - * for jump and power down of a specific core. - */ -static void power_down_core(void) -{ - uint32_t tmp, core_id, core_config; - - /* Get the unique core id */ - /* - * Multiprocessor Affinity Register - * [11:8] Cluster ID - * [1:0] CPU ID - */ - mrc_mpafr(core_id); - tmp = core_id & 0x3; - core_id = (core_id >> 6) & ~3; - core_id |= tmp; - core_id &= 0x3f; - - /* Set the status of the core to low */ - core_config = (core_id * CPU_CONFIG_STATUS_OFFSET); - core_config += EXYNOS5420_CPU_CONFIG_BASE; - writel(0x0, core_config); - - /* Core enter WFI */ - wfi(); -} - -/* - * Configurations for secondary cores are inapt at this stage. - * Reconfigure secondary cores. Shutdown and change the status - * of all cores except the primary core. - */ -static void secondary_cores_configure(void) -{ - /* Clear secondary boot iRAM base */ - writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C)); - - /* set lowpower flag and address */ - writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); - writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR); - writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); - /* Store jump address for power down */ - writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); - - /* Need all core power down check */ - dsb(); - sev(); -} - -extern void relocate_wait_code(void); -#endif - -int do_lowlevel_init(void) -{ - uint32_t reset_status; - int actions = 0; - - arch_cpu_init(); - -#ifndef CONFIG_SYS_L2CACHE_OFF - /* - * Init L2 cache parameters here for use by boot and resume - * - * These are here instead of in v7_outer_cache_enable() so that the - * L2 cache settings get properly set even at resume time or if we're - * running U-Boot with the cache off. The kernel still needs us to - * set these for it. - */ - configure_l2_ctlr(); - configure_l2_actlr(); - dsb(); - isb(); -#endif - -#ifdef CONFIG_EXYNOS5420 - relocate_wait_code(); - - /* Reconfigure secondary cores */ - secondary_cores_configure(); -#endif - - reset_status = get_reset_status(); - - switch (reset_status) { - case S5P_CHECK_SLEEP: - actions = DO_CLOCKS | DO_WAKEUP; - break; - case S5P_CHECK_DIDLE: - case S5P_CHECK_LPA: - actions = DO_WAKEUP; - break; - default: - /* This is a normal boot (not a wake from sleep) */ - actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER; - } - - if (actions & DO_POWER) - set_ps_hold_ctrl(); - - if (actions & DO_CLOCKS) { - system_clock_init(); -#ifdef CONFIG_DEBUG_UART - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - debug_uart_init(); -#endif - mem_ctrl_init(actions & DO_MEM_RESET); - tzpc_init(); - } - - return actions & DO_WAKEUP; -} diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c deleted file mode 100644 index e97cb376ff..0000000000 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ /dev/null @@ -1,915 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics. - * Abhilash Kesavan <a.kesavan@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fdtdec.h> -#include <asm/gpio.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/sromc.h> - -static void exynos5_uart_config(int peripheral) -{ - int i, start, count; - - switch (peripheral) { - case PERIPH_ID_UART0: - start = EXYNOS5_GPIO_A00; - count = 4; - break; - case PERIPH_ID_UART1: - start = EXYNOS5_GPIO_D00; - count = 4; - break; - case PERIPH_ID_UART2: - start = EXYNOS5_GPIO_A10; - count = 4; - break; - case PERIPH_ID_UART3: - start = EXYNOS5_GPIO_A14; - count = 2; - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return; - } - for (i = start; i < start + count; i++) { - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } -} - -static void exynos5420_uart_config(int peripheral) -{ - int i, start, count; - - switch (peripheral) { - case PERIPH_ID_UART0: - start = EXYNOS5420_GPIO_A00; - count = 4; - break; - case PERIPH_ID_UART1: - start = EXYNOS5420_GPIO_A04; - count = 4; - break; - case PERIPH_ID_UART2: - start = EXYNOS5420_GPIO_A10; - count = 4; - break; - case PERIPH_ID_UART3: - start = EXYNOS5420_GPIO_A14; - count = 2; - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return; - } - - for (i = start; i < start + count; i++) { - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } -} - -static int exynos5_mmc_config(int peripheral, int flags) -{ - int i, start, start_ext, gpio_func = 0; - - switch (peripheral) { - case PERIPH_ID_SDMMC0: - start = EXYNOS5_GPIO_C00; - start_ext = EXYNOS5_GPIO_C10; - gpio_func = S5P_GPIO_FUNC(0x2); - break; - case PERIPH_ID_SDMMC1: - start = EXYNOS5_GPIO_C20; - start_ext = 0; - break; - case PERIPH_ID_SDMMC2: - start = EXYNOS5_GPIO_C30; - start_ext = EXYNOS5_GPIO_C43; - gpio_func = S5P_GPIO_FUNC(0x3); - break; - case PERIPH_ID_SDMMC3: - start = EXYNOS5_GPIO_C40; - start_ext = 0; - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", - peripheral); - return -1; - } - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i <= (start_ext + 3); i++) { - gpio_cfg_pin(i, gpio_func); - gpio_set_pull(i, S5P_GPIO_PULL_UP); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - } - for (i = start; i < (start + 2); i++) { - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - for (i = (start + 3); i <= (start + 6); i++) { - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(i, S5P_GPIO_PULL_UP); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - - return 0; -} - -static int exynos5420_mmc_config(int peripheral, int flags) -{ - int i, start = 0, start_ext = 0; - - switch (peripheral) { - case PERIPH_ID_SDMMC0: - start = EXYNOS5420_GPIO_C00; - start_ext = EXYNOS5420_GPIO_C30; - break; - case PERIPH_ID_SDMMC1: - start = EXYNOS5420_GPIO_C10; - start_ext = EXYNOS5420_GPIO_D14; - break; - case PERIPH_ID_SDMMC2: - start = EXYNOS5420_GPIO_C20; - start_ext = 0; - break; - default: - start = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - - if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", - peripheral); - return -1; - } - - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i <= (start_ext + 3); i++) { - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(i, S5P_GPIO_PULL_UP); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - } - - for (i = start; i < (start + 3); i++) { - /* - * MMC0 is intended to be used for eMMC. The - * card detect pin is used as a VDDEN signal to - * power on the eMMC. The 5420 iROM makes - * this same assumption. - */ - if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { -#ifndef CONFIG_SPL_BUILD - gpio_request(i, "sdmmc0_vdden"); -#endif - gpio_set_value(i, 1); - gpio_cfg_pin(i, S5P_GPIO_OUTPUT); - } else { - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - - for (i = (start + 3); i <= (start + 6); i++) { - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(i, S5P_GPIO_PULL_UP); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - - return 0; -} - -static void exynos5_sromc_config(int flags) -{ - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), - S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - - gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - - gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); - } -} - -static void exynos5_i2c_config(int peripheral, int flags) -{ - int func01, func23; - - /* High-Speed I2C */ - if (flags & PINMUX_FLAG_HS_MODE) { - func01 = 4; - func23 = 4; - } else { - func01 = 2; - func23 = 3; - } - - switch (peripheral) { - case PERIPH_ID_I2C0: - gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01)); - gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01)); - break; - case PERIPH_ID_I2C1: - gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01)); - gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01)); - break; - case PERIPH_ID_I2C2: - gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23)); - gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23)); - break; - case PERIPH_ID_I2C3: - gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23)); - gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23)); - break; - case PERIPH_ID_I2C4: - gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C5: - gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C6: - gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); - break; - case PERIPH_ID_I2C7: - gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); - break; - } -} - -static void exynos5420_i2c_config(int peripheral) -{ - switch (peripheral) { - case PERIPH_ID_I2C0: - gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C1: - gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C2: - gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C3: - gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C4: - gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C5: - gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C6: - gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); - break; - case PERIPH_ID_I2C7: - gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C8: - gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C9: - gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C10: - gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); - break; - } -} - -static void exynos5_i2s_config(int peripheral) -{ - int i; - - switch (peripheral) { - case PERIPH_ID_I2S0: - for (i = 0; i < 5; i++) - gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); - break; - case PERIPH_ID_I2S1: - for (i = 0; i < 5; i++) - gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); - break; - } -} - -void exynos5_spi_config(int peripheral) -{ - int cfg = 0, pin = 0, i; - - switch (peripheral) { - case PERIPH_ID_SPI0: - cfg = S5P_GPIO_FUNC(0x2); - pin = EXYNOS5_GPIO_A20; - break; - case PERIPH_ID_SPI1: - cfg = S5P_GPIO_FUNC(0x2); - pin = EXYNOS5_GPIO_A24; - break; - case PERIPH_ID_SPI2: - cfg = S5P_GPIO_FUNC(0x5); - pin = EXYNOS5_GPIO_B11; - break; - case PERIPH_ID_SPI3: - cfg = S5P_GPIO_FUNC(0x2); - pin = EXYNOS5_GPIO_F10; - break; - case PERIPH_ID_SPI4: - for (i = 0; i < 2; i++) { - gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); - } - break; - } - if (peripheral != PERIPH_ID_SPI4) { - for (i = pin; i < pin + 4; i++) - gpio_cfg_pin(i, cfg); - } -} - -void exynos5420_spi_config(int peripheral) -{ - int cfg, pin, i; - - switch (peripheral) { - case PERIPH_ID_SPI0: - pin = EXYNOS5420_GPIO_A20; - cfg = S5P_GPIO_FUNC(0x2); - break; - case PERIPH_ID_SPI1: - pin = EXYNOS5420_GPIO_A24; - cfg = S5P_GPIO_FUNC(0x2); - break; - case PERIPH_ID_SPI2: - pin = EXYNOS5420_GPIO_B11; - cfg = S5P_GPIO_FUNC(0x5); - break; - case PERIPH_ID_SPI3: - pin = EXYNOS5420_GPIO_F10; - cfg = S5P_GPIO_FUNC(0x2); - break; - case PERIPH_ID_SPI4: - cfg = 0; - pin = 0; - break; - default: - cfg = 0; - pin = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); - return; - } - - if (peripheral != PERIPH_ID_SPI4) { - for (i = pin; i < pin + 4; i++) - gpio_cfg_pin(i, cfg); - } else { - for (i = 0; i < 2; i++) { - gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, - S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, - S5P_GPIO_FUNC(0x4)); - } - } -} - -static int exynos5_pinmux_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - exynos5_uart_config(peripheral); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - return exynos5_mmc_config(peripheral, flags); - case PERIPH_ID_SROMC: - exynos5_sromc_config(flags); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - exynos5_i2c_config(peripheral, flags); - break; - case PERIPH_ID_I2S0: - case PERIPH_ID_I2S1: - exynos5_i2s_config(peripheral); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - exynos5_spi_config(peripheral); - break; - case PERIPH_ID_DPHPD: - /* Set Hotplug detect for DP */ - gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); - - /* - * Hotplug detect should have an external pullup; disable the - * internal pulldown so they don't fight. - */ - gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE); - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - - return 0; -} - -static int exynos5420_pinmux_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - exynos5420_uart_config(peripheral); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - return exynos5420_mmc_config(peripheral, flags); - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - exynos5420_spi_config(peripheral); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - case PERIPH_ID_I2C8: - case PERIPH_ID_I2C9: - case PERIPH_ID_I2C10: - exynos5420_i2c_config(peripheral); - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - - return 0; -} - -static void exynos4_i2c_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_I2C0: - gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C1: - gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C2: - gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C3: - gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C4: - gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C5: - gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C6: - gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); - break; - case PERIPH_ID_I2C7: - gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); - break; - } -} - -static int exynos4_mmc_config(int peripheral, int flags) -{ - int i, start = 0, start_ext = 0; - unsigned int func, ext_func; - - switch (peripheral) { - case PERIPH_ID_SDMMC0: - start = EXYNOS4_GPIO_K00; - start_ext = EXYNOS4_GPIO_K13; - func = S5P_GPIO_FUNC(0x2); - ext_func = S5P_GPIO_FUNC(0x3); - break; - case PERIPH_ID_SDMMC2: - start = EXYNOS4_GPIO_K20; - start_ext = EXYNOS4_GPIO_K33; - func = S5P_GPIO_FUNC(0x2); - ext_func = S5P_GPIO_FUNC(0x3); - break; - case PERIPH_ID_SDMMC4: - start = EXYNOS4_GPIO_K00; - start_ext = EXYNOS4_GPIO_K13; - func = S5P_GPIO_FUNC(0x3); - ext_func = S5P_GPIO_FUNC(0x4); - break; - default: - return -1; - } - for (i = start; i < (start + 7); i++) { - if (i == (start + 2)) - continue; - gpio_cfg_pin(i, func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - /* SDMMC2 do not use 8bit mode at exynos4 */ - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i < (start_ext + 4); i++) { - gpio_cfg_pin(i, ext_func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - } - - return 0; -} - -static void exynos4_uart_config(int peripheral) -{ - int i, start, count; - - switch (peripheral) { - case PERIPH_ID_UART0: - start = EXYNOS4_GPIO_A00; - count = 4; - break; - case PERIPH_ID_UART1: - start = EXYNOS4_GPIO_A04; - count = 4; - break; - case PERIPH_ID_UART2: - start = EXYNOS4_GPIO_A10; - count = 4; - break; - case PERIPH_ID_UART3: - start = EXYNOS4_GPIO_A14; - count = 2; - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return; - } - for (i = start; i < (start + count); i++) { - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } -} - -static void exynos4x12_i2c_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_I2C0: - gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C1: - gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); - break; - case PERIPH_ID_I2C2: - gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C3: - gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C4: - gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C5: - gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); - break; - case PERIPH_ID_I2C6: - gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); - break; - case PERIPH_ID_I2C7: - gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); - break; - } -} - -static int exynos4x12_mmc_config(int peripheral, int flags) -{ - int i, start = 0, start_ext = 0; - unsigned int func, ext_func; - - switch (peripheral) { - case PERIPH_ID_SDMMC0: - start = EXYNOS4X12_GPIO_K00; - start_ext = EXYNOS4X12_GPIO_K13; - func = S5P_GPIO_FUNC(0x2); - ext_func = S5P_GPIO_FUNC(0x3); - break; - case PERIPH_ID_SDMMC2: - start = EXYNOS4X12_GPIO_K20; - start_ext = EXYNOS4X12_GPIO_K33; - func = S5P_GPIO_FUNC(0x2); - ext_func = S5P_GPIO_FUNC(0x3); - break; - case PERIPH_ID_SDMMC4: - start = EXYNOS4X12_GPIO_K00; - start_ext = EXYNOS4X12_GPIO_K13; - func = S5P_GPIO_FUNC(0x3); - ext_func = S5P_GPIO_FUNC(0x4); - break; - default: - return -1; - } - for (i = start; i < (start + 7); i++) { - if (i == (start + 2)) - continue; - gpio_cfg_pin(i, func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i < (start_ext + 4); i++) { - gpio_cfg_pin(i, ext_func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - } - - return 0; -} - -static void exynos4x12_uart_config(int peripheral) -{ - int i, start, count; - - switch (peripheral) { - case PERIPH_ID_UART0: - start = EXYNOS4X12_GPIO_A00; - count = 4; - break; - case PERIPH_ID_UART1: - start = EXYNOS4X12_GPIO_A04; - count = 4; - break; - case PERIPH_ID_UART2: - start = EXYNOS4X12_GPIO_A10; - count = 4; - break; - case PERIPH_ID_UART3: - start = EXYNOS4X12_GPIO_A14; - count = 2; - break; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return; - } - for (i = start; i < (start + count); i++) { - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } -} - -static int exynos4_pinmux_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - exynos4_uart_config(peripheral); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - exynos4_i2c_config(peripheral, flags); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC4: - return exynos4_mmc_config(peripheral, flags); - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC3: - debug("SDMMC device %d not implemented\n", peripheral); - return -1; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - - return 0; -} - -static int exynos4x12_pinmux_config(int peripheral, int flags) -{ - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - exynos4x12_uart_config(peripheral); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - exynos4x12_i2c_config(peripheral, flags); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC4: - return exynos4x12_mmc_config(peripheral, flags); - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC3: - debug("SDMMC device %d not implemented\n", peripheral); - return -1; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - } - - return 0; -} - -int exynos_pinmux_config(int peripheral, int flags) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_pinmux_config(peripheral, flags); - else if (proid_is_exynos5250()) - return exynos5_pinmux_config(peripheral, flags); - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) - return exynos4x12_pinmux_config(peripheral, flags); - else - return exynos4_pinmux_config(peripheral, flags); - } - - debug("pinmux functionality not supported\n"); - - return -1; -} - -#ifdef CONFIG_OF_CONTROL -static int exynos4_pinmux_decode_periph_id(const void *blob, int node) -{ - int err; - u32 cell[3]; - - err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); - if (err) { - debug(" invalid peripheral id\n"); - return PERIPH_ID_NONE; - } - - return cell[1]; -} - -static int exynos5_pinmux_decode_periph_id(const void *blob, int node) -{ - int err; - u32 cell[3]; - - err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); - if (err) - return PERIPH_ID_NONE; - - return cell[1]; -} - -int pinmux_decode_periph_id(const void *blob, int node) -{ - if (cpu_is_exynos5()) - return exynos5_pinmux_decode_periph_id(blob, node); - else if (cpu_is_exynos4()) - return exynos4_pinmux_decode_periph_id(blob, node); - - return PERIPH_ID_NONE; -} -#endif diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c deleted file mode 100644 index 1b12051656..0000000000 --- a/arch/arm/cpu/armv7/exynos/power.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/power.h> - -static void exynos4_mipi_phy_control(unsigned int dev_index, - unsigned int enable) -{ - struct exynos4_power *pmu = - (struct exynos4_power *)samsung_get_base_power(); - unsigned int addr, cfg = 0; - - if (dev_index == 0) - addr = (unsigned int)&pmu->mipi_phy0_control; - else - addr = (unsigned int)&pmu->mipi_phy1_control; - - - cfg = readl(addr); - if (enable) - cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); - else - cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); - - writel(cfg, addr); -} - -void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) -{ - if (cpu_is_exynos4()) - exynos4_mipi_phy_control(dev_index, enable); -} - -void exynos5_set_usbhost_phy_ctrl(unsigned int enable) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - if (enable) { - /* Enabling USBHOST_PHY */ - setbits_le32(&power->usbhost_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - } else { - /* Disabling USBHOST_PHY */ - clrbits_le32(&power->usbhost_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - } -} - -void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) -{ - struct exynos4412_power *power = - (struct exynos4412_power *)samsung_get_base_power(); - - if (enable) { - /* Enabling USBHOST_PHY */ - setbits_le32(&power->usbhost_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - setbits_le32(&power->hsic1_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - setbits_le32(&power->hsic2_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - } else { - /* Disabling USBHOST_PHY */ - clrbits_le32(&power->usbhost_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - clrbits_le32(&power->hsic1_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - clrbits_le32(&power->hsic2_phy_control, - POWER_USB_HOST_PHY_CTRL_EN); - } -} - -void set_usbhost_phy_ctrl(unsigned int enable) -{ - if (cpu_is_exynos5()) - exynos5_set_usbhost_phy_ctrl(enable); - else if (cpu_is_exynos4()) - if (proid_is_exynos4412()) - exynos4412_set_usbhost_phy_ctrl(enable); -} - -static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - if (enable) { - /* Enabling USBDRD_PHY */ - setbits_le32(&power->usbdrd_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - } else { - /* Disabling USBDRD_PHY */ - clrbits_le32(&power->usbdrd_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - } -} - -static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) -{ - struct exynos5420_power *power = - (struct exynos5420_power *)samsung_get_base_power(); - - if (enable) { - /* Enabling USBDEV_PHY */ - setbits_le32(&power->usbdev_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - setbits_le32(&power->usbdev1_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - } else { - /* Disabling USBDEV_PHY */ - clrbits_le32(&power->usbdev_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - clrbits_le32(&power->usbdev1_phy_control, - POWER_USB_DRD_PHY_CTRL_EN); - } -} - -void set_usbdrd_phy_ctrl(unsigned int enable) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - exynos5420_set_usbdev_phy_ctrl(enable); - else - exynos5_set_usbdrd_phy_ctrl(enable); - } -} - -static void exynos5_dp_phy_control(unsigned int enable) -{ - unsigned int cfg; - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - cfg = readl(&power->dptx_phy_control); - if (enable) - cfg |= EXYNOS_DP_PHY_ENABLE; - else - cfg &= ~EXYNOS_DP_PHY_ENABLE; - - writel(cfg, &power->dptx_phy_control); -} - -void set_dp_phy_ctrl(unsigned int enable) -{ - if (cpu_is_exynos5()) - exynos5_dp_phy_control(enable); -} - -static void exynos5_set_ps_hold_ctrl(void) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - /* Set PS-Hold high */ - setbits_le32(&power->ps_hold_control, - EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); -} - -/* - * Set ps_hold data driving value high - * This enables the machine to stay powered on - * after the initial power-on condition goes away - * (e.g. power button). - */ -void set_ps_hold_ctrl(void) -{ - if (cpu_is_exynos5()) - exynos5_set_ps_hold_ctrl(); -} - - -static void exynos5_set_xclkout(void) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - /* use xxti for xclk out */ - clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, - PMU_DEBUG_XXTI); -} - -void set_xclkout(void) -{ - if (cpu_is_exynos5()) - exynos5_set_xclkout(); -} - -/* Enables hardware tripping to power off the system when TMU fails */ -void set_hw_thermal_trip(void) -{ - if (cpu_is_exynos5()) { - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/ - setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); - } -} - -static uint32_t exynos5_get_reset_status(void) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - - return power->inform1; -} - -static uint32_t exynos4_get_reset_status(void) -{ - struct exynos4_power *power = - (struct exynos4_power *)samsung_get_base_power(); - - return power->inform1; -} - -uint32_t get_reset_status(void) -{ - if (cpu_is_exynos5()) - return exynos5_get_reset_status(); - else - return exynos4_get_reset_status(); -} - -static void exynos5_power_exit_wakeup(void) -{ - struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); - typedef void (*resume_func)(void); - - ((resume_func)power->inform0)(); -} - -static void exynos4_power_exit_wakeup(void) -{ - struct exynos4_power *power = - (struct exynos4_power *)samsung_get_base_power(); - typedef void (*resume_func)(void); - - ((resume_func)power->inform0)(); -} - -void power_exit_wakeup(void) -{ - if (cpu_is_exynos5()) - exynos5_power_exit_wakeup(); - else - exynos4_power_exit_wakeup(); -} - -unsigned int get_boot_mode(void) -{ - unsigned int om_pin = samsung_get_base_power(); - - return readl(om_pin) & OM_PIN_MASK; -} diff --git a/arch/arm/cpu/armv7/exynos/sec_boot.S b/arch/arm/cpu/armv7/exynos/sec_boot.S deleted file mode 100644 index dfc3455929..0000000000 --- a/arch/arm/cpu/armv7/exynos/sec_boot.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * Akshay Saraswat <akshay.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <asm/arch/cpu.h> - - .globl relocate_wait_code -relocate_wait_code: - adr r0, code_base @ r0: source address (start) - adr r1, code_end @ r1: source address (end) - ldr r2, =0x02073000 @ r2: target address -1: - ldmia r0!, {r3-r6} - stmia r2!, {r3-r6} - cmp r0, r1 - blt 1b - b code_end - .ltorg -/* - * Secondary core waits here until Primary wake it up. - * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. - * This is a workaround code which is supposed to act as a - * substitute/supplement to the iROM code. - * - * This workaround code is relocated to the address 0x02073000 - * because that comes out to be the last 4KB of the iRAM - * (Base Address - 0x02020000, Limit Address - 0x020740000). - * - * U-boot and kernel are aware of this code and flags by the simple - * fact that we are implementing a workaround in the last 4KB - * of the iRAM and we have already defined these flag and address - * values in both kernel and U-boot for our use. - */ -code_base: - b 1f -/* - * These addresses are being used as flags in u-boot and kernel. - * - * Jump address for resume and flag to check for resume/reset: - * Resume address - 0x2073008 - * Resume flag - 0x207300C - * - * Jump address for cluster switching: - * Switch address - 0x2073018 - * - * Jump address for core hotplug: - * Hotplug address - 0x207301C - * - * Jump address for C2 state (Reserved for future not being used right now): - * C2 address - 0x2073024 - * - * Managed per core status for the active cluster: - * CPU0 state - 0x2073028 - * CPU1 state - 0x207302C - * CPU2 state - 0x2073030 - * CPU3 state - 0x2073034 - * - * Managed per core GIC status for the active cluster: - * CPU0 gic state - 0x2073038 - * CPU1 gic state - 0x207303C - * CPU2 gic state - 0x2073040 - * CPU3 gic state - 0x2073044 - * - * Logic of the code: - * Step-1: Read current CPU status. - * Step-2: If it's a resume then continue, else jump to step 4. - * Step-3: Clear inform1 PMU register and jump to inform0 value. - * Step-4: If it's a switch, C2 or reset, get the hotplug address. - * Step-5: If address is not available, enter WFE. - * Step-6: If address is available, jump to that address. - */ - nop @ for backward compatibility - .word 0x0 @ REG0: RESUME_ADDR - .word 0x0 @ REG1: RESUME_FLAG - .word 0x0 @ REG2 - .word 0x0 @ REG3 -_switch_addr: - .word 0x0 @ REG4: SWITCH_ADDR -_hotplug_addr: - .word 0x0 @ REG5: CPU1_BOOT_REG - .word 0x0 @ REG6 -_c2_addr: - .word 0x0 @ REG7: REG_C2_ADDR -_cpu_state: - .word 0x1 @ CPU0_STATE : RESET - .word 0x2 @ CPU1_STATE : SECONDARY RESET - .word 0x2 @ CPU2_STATE : SECONDARY RESET - .word 0x2 @ CPU3_STATE : SECONDARY RESET -_gic_state: - .word 0x0 @ CPU0 - GICD_IGROUPR0 - .word 0x0 @ CPU1 - GICD_IGROUPR0 - .word 0x0 @ CPU2 - GICD_IGROUPR0 - .word 0x0 @ CPU3 - GICD_IGROUPR0 -1: - adr r0, _cpu_state - mrc p15, 0, r7, c0, c0, 5 @ read MPIDR - and r7, r7, #0xf @ r7 = cpu id -/* Read the current cpu state */ - ldr r10, [r0, r7, lsl #2] -svc_entry: - tst r10, #(1 << 4) - adrne r0, _switch_addr - bne wait_for_addr -/* Clear INFORM1 */ - ldr r0, =(0x10040000 + 0x804) - ldr r1, [r0] - cmp r1, #0x0 - movne r1, #0x0 - strne r1, [r0] -/* Get INFORM0 */ - ldrne r1, =(0x10040000 + 0x800) - ldrne pc, [r1] - tst r10, #(1 << 0) - ldrne pc, =0x23e00000 - adr r0, _hotplug_addr -wait_for_addr: - ldr r1, [r0] - cmp r1, #0x0 - bxne r1 - wfe - b wait_for_addr - .ltorg -code_end: - mov pc, lr diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c deleted file mode 100644 index 0f116b141a..0000000000 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2010 Samsung Electronics. - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/system.h> - -void reset_cpu(ulong addr) -{ - writel(0x1, samsung_get_base_swreset()); -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c deleted file mode 100644 index c7f943eb6a..0000000000 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> - -#include <asm/arch/clock.h> -#include <asm/arch/clk.h> -#include <asm/arch/dmc.h> -#include <asm/arch/periph.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <asm/arch/spl.h> -#include <asm/arch/spi.h> - -#include "common_setup.h" -#include "clock_init.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Index into irom ptr table */ -enum index { - MMC_INDEX, - EMMC44_INDEX, - EMMC44_END_INDEX, - SPI_INDEX, - USB_INDEX, -}; - -/* IROM Function Pointers Table */ -u32 irom_ptr_table[] = { - [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ - [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ - [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer - -EMMC4.4 end boot operation */ - [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ - [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/ - }; - -void *get_irom_func(int index) -{ - return (void *)*(u32 *)irom_ptr_table[index]; -} - -#ifdef CONFIG_USB_BOOTING -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} -#endif - -#ifdef CONFIG_SPI_BOOTING -static void spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) -{ - uint *rxp = (uint *)(dinp + (i * (32 * 1024))); - int rx_lvl, tx_lvl; - uint out_bytes, in_bytes; - - out_bytes = todo; - in_bytes = todo; - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); - - while (in_bytes) { - uint32_t spi_sts; - int temp; - - spi_sts = readl(®s->spi_sts); - rx_lvl = ((spi_sts >> 15) & 0x7f); - tx_lvl = ((spi_sts >> 6) & 0x7f); - while (tx_lvl < 32 && out_bytes) { - temp = 0xffffffff; - writel(temp, ®s->tx_data); - out_bytes -= 4; - tx_lvl += 4; - } - while (rx_lvl >= 4 && in_bytes) { - temp = readl(®s->rx_data); - if (rxp) - *rxp++ = temp; - in_bytes -= 4; - rx_lvl -= 4; - } - } -} - -/* - * Copy uboot from spi flash to RAM - * - * @parma uboot_size size of u-boot to copy - * @param uboot_addr address in u-boot to copy - */ -static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) -{ - int upto, todo; - int i, timeout = 100; - struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; - - set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* set the spi1 GPIO */ - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); - - /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); - /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, ®s->fb_clk); - /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ - - /* clear rx and tx channel if set priveously */ - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - - setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | - SPI_RX_BYTE_SWAP | - SPI_RX_HWORD_SWAP); - - /* do a soft reset */ - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - - /* now set rx and tx channel ON */ - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ - - /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); - - /* waiting for TX done */ - while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) { - if (!timeout) { - debug("SPI TIMEOUT\n"); - break; - } - timeout--; - } - - for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { - todo = min(uboot_size - upto, (unsigned int)(1 << 15)); - spi_rx_tx(regs, todo, (void *)(uboot_addr), - (void *)(SPI_FLASH_UBOOT_POS), i); - } - - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ - - /* - * Let put controller mode to BYTE as - * SPI driver does not support WORD mode yet - */ - clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD); - writel(0, ®s->swap_cfg); - - /* - * Flush spi tx, rx fifos and reset the SPI controller - * and clear rx/tx channel - */ - clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); -} -#endif - -/* -* Copy U-boot from mmc to RAM: -* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains -* Pointer to API (Data transfer from mmc to ram) -*/ -void copy_uboot_to_ram(void) -{ - unsigned int bootmode = BOOT_MODE_OM; - - u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL; - u32 offset = 0, size = 0; -#ifdef CONFIG_SPI_BOOTING - struct spl_machine_param *param = spl_get_machine_params(); -#endif -#ifdef CONFIG_SUPPORT_EMMC_BOOT - u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); - void (*end_bootop_from_emmc)(void); -#endif -#ifdef CONFIG_USB_BOOTING - int is_cr_z_set; - unsigned int sec_boot_check; - - /* - * Note that older hardware (before Exynos5800) does not expect any - * arguments, but it does not hurt to pass them, so a common function - * prototype is used. - */ - u32 (*usb_copy)(u32 num_of_block, u32 *dst); - - /* Read iRAM location to check for secondary USB boot mode */ - sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); - if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) - bootmode = BOOT_MODE_USB; -#endif - - if (bootmode == BOOT_MODE_OM) - bootmode = get_boot_mode(); - - switch (bootmode) { -#ifdef CONFIG_SPI_BOOTING - case BOOT_MODE_SERIAL: - /* Customised function to copy u-boot from SF */ - exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); - break; -#endif - case BOOT_MODE_SD: - offset = BL2_START_OFFSET; - size = BL2_SIZE_BLOC_COUNT; - copy_bl2 = get_irom_func(MMC_INDEX); - break; -#ifdef CONFIG_SUPPORT_EMMC_BOOT - case BOOT_MODE_EMMC: - /* Set the FSYS1 clock divisor value for EMMC boot */ - emmc_boot_clk_div_set(); - - copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX); - end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX); - - copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); - end_bootop_from_emmc(); - break; -#endif -#ifdef CONFIG_USB_BOOTING - case BOOT_MODE_USB: - /* - * iROM needs program flow prediction to be disabled - * before copy from USB device to RAM - */ - is_cr_z_set = config_branch_prediction(0); - usb_copy = get_irom_func(USB_INDEX); - usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); - config_branch_prediction(is_cr_z_set); - break; -#endif - default: - break; - } - - if (copy_bl2) - copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE); -} - -void memzero(void *s, size_t n) -{ - char *ptr = s; - size_t i; - - for (i = 0; i < n; i++) - *ptr++ = '\0'; -} - -/** - * Set up the U-Boot global_data pointer - * - * This sets the address of the global data, and sets up basic values. - * - * @param gdp Value to give to gd - */ -static void setup_global_data(gd_t *gdp) -{ - gd = gdp; - memzero((void *)gd, sizeof(gd_t)); - gd->flags |= GD_FLG_RELOC; - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; -} - -void board_init_f(unsigned long bootflag) -{ - __aligned(8) gd_t local_gd; - __attribute__((noreturn)) void (*uboot)(void); - - setup_global_data(&local_gd); - - if (do_lowlevel_init()) - power_exit_wakeup(); - - copy_uboot_to_ram(); - - /* Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_TEXT_BASE; - (*uboot)(); - /* Never returns Here */ -} - -/* Place Holders */ -void board_init_r(gd_t *id, ulong dest_addr) -{ - /* Function attribute is no-return */ - /* This Function never executes */ - while (1) - ; -} diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c deleted file mode 100644 index ad12445832..0000000000 --- a/arch/arm/cpu/armv7/exynos/system.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/system.h> - -static void exynos5_set_usbhost_mode(unsigned int mode) -{ - struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); - - /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ - if (mode == USB20_PHY_CFG_HOST_LINK_EN) { - setbits_le32(&sysreg->usb20phy_cfg, - USB20_PHY_CFG_HOST_LINK_EN); - } else { - clrbits_le32(&sysreg->usb20phy_cfg, - USB20_PHY_CFG_HOST_LINK_EN); - } -} - -void set_usbhost_mode(unsigned int mode) -{ - if (cpu_is_exynos5()) - exynos5_set_usbhost_mode(mode); -} - -static void exynos4_set_system_display(void) -{ - struct exynos4_sysreg *sysreg = - (struct exynos4_sysreg *)samsung_get_base_sysreg(); - unsigned int cfg = 0; - - /* - * system register path set - * 0: MIE/MDNIE - * 1: FIMD Bypass - */ - cfg = readl(&sysreg->display_ctrl); - cfg |= (1 << 1); - writel(cfg, &sysreg->display_ctrl); -} - -static void exynos5_set_system_display(void) -{ - struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); - unsigned int cfg = 0; - - /* - * system register path set - * 0: MIE/MDNIE - * 1: FIMD Bypass - */ - cfg = readl(&sysreg->disp1blk_cfg); - cfg |= (1 << 15); - writel(cfg, &sysreg->disp1blk_cfg); -} - -void set_system_display_ctrl(void) -{ - if (cpu_is_exynos4()) - exynos4_set_system_display(); - else - exynos5_set_system_display(); -} diff --git a/arch/arm/cpu/armv7/exynos/tzpc.c b/arch/arm/cpu/armv7/exynos/tzpc.c deleted file mode 100644 index 395077cf25..0000000000 --- a/arch/arm/cpu/armv7/exynos/tzpc.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Lowlevel setup for SMDK5250 board based on S5PC520 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/tzpc.h> -#include <asm/io.h> - -/* Setting TZPC[TrustZone Protection Controller] */ -void tzpc_init(void) -{ - struct exynos_tzpc *tzpc; - unsigned int addr, start = 0, end = 0; - - start = samsung_get_base_tzpc(); - - if (cpu_is_exynos5()) - end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); - else if (cpu_is_exynos4()) - end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); - - for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) { - tzpc = (struct exynos_tzpc *)addr; - - if (addr == start) - writel(R0SIZE, &tzpc->r0size); - - writel(DECPROTXSET, &tzpc->decprot0set); - writel(DECPROTXSET, &tzpc->decprot1set); - - if (cpu_is_exynos5() && (addr == end)) - break; - - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); - } -} |
