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-rw-r--r--arch/arm/cpu/armv7/omap4/Kconfig4
-rw-r--r--arch/arm/cpu/armv7/omap4/boot.c45
-rw-r--r--arch/arm/cpu/armv7/omap4/emif.c2
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c15
-rw-r--r--arch/arm/cpu/armv7/omap4/prcm-regs.c1
-rw-r--r--arch/arm/cpu/armv7/omap4/sdram_elpida.c6
6 files changed, 63 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
index df27ea10a2..49adb8ec5b 100644
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ b/arch/arm/cpu/armv7/omap4/Kconfig
@@ -13,6 +13,9 @@ config TARGET_OMAP4_PANDA
config TARGET_OMAP4_SDP4430
bool "TI OMAP4 SDP4430"
+config TARGET_KC1
+ bool "Amazon Kindle Fire (first generation)"
+
endchoice
config SYS_SOC
@@ -21,5 +24,6 @@ config SYS_SOC
source "board/gumstix/duovero/Kconfig"
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
+source "board/amazon/kc1/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/cpu/armv7/omap4/boot.c
index 4b5aa770e7..7f5791e9ed 100644
--- a/arch/arm/cpu/armv7/omap4/boot.c
+++ b/arch/arm/cpu/armv7/omap4/boot.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
#include <spl.h>
static u32 boot_devices[] = {
@@ -58,3 +59,47 @@ u32 omap_sys_boot_device(void)
return boot_devices[sys_boot];
}
+
+int omap_reboot_mode(char *mode, unsigned int length)
+{
+ unsigned int limit;
+ unsigned int i;
+
+ if (length < 2)
+ return -1;
+
+ if (!warm_reset())
+ return -1;
+
+ limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
+ OMAP_REBOOT_REASON_SIZE;
+
+ for (i = 0; i < (limit - 1); i++)
+ mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
+ OMAP_REBOOT_REASON_OFFSET + i));
+
+ mode[i] = '\0';
+
+ return 0;
+}
+
+int omap_reboot_mode_clear(void)
+{
+ writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
+
+ return 0;
+}
+
+int omap_reboot_mode_store(char *mode)
+{
+ unsigned int i;
+
+ for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
+ writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
+ OMAP_REBOOT_REASON_OFFSET + i));
+
+ writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
+ OMAP_REBOOT_REASON_OFFSET + i));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index e89032be75..403c3c6146 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -96,7 +96,7 @@ static const struct lpddr2_ac_timings const*
&timings_jedec_400_mhz
};
-static const struct lpddr2_device_timings jedec_default_timings = {
+const struct lpddr2_device_timings jedec_default_timings = {
.ac_timings = jedec_ac_timings,
.min_tck = &min_tck_jedec
};
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 029533c851..02c06c1577 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -355,6 +355,10 @@ void enable_basic_clocks(void)
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
0
};
@@ -372,10 +376,14 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
- /* Enable optional 48M functional clock for USB PHY */
+ /* Enable optional 48M functional clock for USB PHY */
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+ /* Enable 32 KHz clock for USB PHY */
+ setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
@@ -391,7 +399,6 @@ void enable_basic_uboot_clocks(void)
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbotg_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
- (*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_clksel_usb_60mhz,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
@@ -399,10 +406,6 @@ void enable_basic_uboot_clocks(void)
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
- (*prcm)->cm_l4per_i2c1_clkctrl,
- (*prcm)->cm_l4per_i2c2_clkctrl,
- (*prcm)->cm_l4per_i2c3_clkctrl,
- (*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
0
};
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index a09581e55b..2f0e1e851a 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -129,6 +129,7 @@ struct prcm_regs const omap4_prcm = {
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+ .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 4462c72c7a..78b4f09ce2 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -147,14 +147,14 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
#else
-static const struct lpddr2_device_details elpida_2G_S4_details = {
+const struct lpddr2_device_details elpida_2G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_2Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
-static const struct lpddr2_device_details elpida_4G_S4_details = {
+const struct lpddr2_device_details elpida_4G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_4Gb,
.io_width = LPDDR2_IO_WIDTH_32,
@@ -278,7 +278,7 @@ static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_elpida_400_mhz
};
-static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+const struct lpddr2_device_timings elpida_2G_S4_timings = {
.ac_timings = elpida_ac_timings,
.min_tck = &min_tck_elpida,
};
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