diff options
Diffstat (limited to 'arch/arm/cpu/armv7/omap3')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/board.c | 60 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 |
2 files changed, 21 insertions, 50 deletions
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index dd53b207f8..b064c0cc83 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -244,9 +243,6 @@ void s_init(void) try_unlock_memory(); - /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -419,39 +415,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); } -static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void __weak omap3_set_aux_cr_secure(u32 acr) { - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; + struct emu_hal_params emu_romcode_params; - if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); - } + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); } -static void omap3_setup_aux_cr(void) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); + /* Write ACR - affects secure banked bits */ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); + else + omap3_set_aux_cr_secure(acr); + + /* Write ACR - affects non-secure banked bits - some erratas need it */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } + #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { @@ -461,17 +448,15 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; @@ -483,10 +468,9 @@ static void omap3_invalidate_l2_cache_secure(void) void v7_outer_cache_enable(void) { - /* Set L2EN */ - omap3_update_aux_cr_secure(0x2, 0); /* + * Set L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in setting both banked bits(in fact this is required * by an erratum) @@ -496,10 +480,8 @@ void v7_outer_cache_enable(void) void omap3_outer_cache_disable(void) { - /* Clear L2EN */ - omap3_update_aux_cr_secure(0, 0x2); - /* + * Clear L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in clearing both banked bits(in fact this is required * by an erratum) diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 80cb2639f6..7a691519bb 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -27,17 +27,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif -ENTRY(omap3_gp_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Service ID in R12 - MOV r0, r1 @ Copy parameter to R0 - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(omap3_gp_romcode_call) - /* * Funtion for making PPA HAL API calls in secure devices * Input: |
