diff options
Diffstat (limited to 'arch/arm/cpu/armv7/mx7/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 2ed05ea4f9..c777922e9d 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -11,6 +11,7 @@ #include <asm/arch/sys_proto.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/dma.h> +#include <asm/imx-common/hab.h> #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h> @@ -28,6 +29,13 @@ U_BOOT_DEVICE(imx7_thermal) = { }; #endif +#if defined(CONFIG_SECURE_BOOT) +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { + .bank = 1, + .word = 3, +}; +#endif + /* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING @@ -114,10 +122,19 @@ u32 __weak get_board_rev(void) } #endif +/* enable all periherial can be accessed in nosec mode */ +static void init_csu(void) +{ + int i = 0; + for (i = 0; i < CSU_NUM_REGS; i++) + writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); +} + int arch_cpu_init(void) { init_aips(); + init_csu(); /* Disable PDE bit of WMCR register */ imx_set_wdog_powerdown(false); |
