diff options
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/board.c | 224 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/clock.c | 47 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 90 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 240 |
4 files changed, 380 insertions, 221 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 71309a7f47..ecc26717cd 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -17,22 +17,100 @@ */ #include <common.h> +#include <errno.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> -#include <asm/arch/common_def.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +static const struct gpio_bank gpio_bank_am33xx[4] = { + { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; + +/* MII mode defines */ +#define MII_MODE_ENABLE 0x0 +#define RGMII_MODE_ENABLE 0xA + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static struct am335x_baseboard_id __attribute__((section (".data"))) header; + +static inline int board_is_bone(void) +{ + return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(void) +{ + return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); +} + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, + (uchar *)&header, sizeof(header))) { + puts("Could not read the EEPROM; something " + "fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EINVAL; + } + } + + return 0; +} + /* UART Defines */ #ifdef CONFIG_SPL_BUILD #define UART_RESET (0x1 << 1) @@ -40,21 +118,17 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif -#ifdef CONFIG_SPL_BUILD -/* Initialize timer */ -static void init_timer(void) +/* + * Determine what type of DDR we have. + */ +static short inline board_memory_type(void) { - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); + /* The following boards are known to use DDR3. */ + if (board_is_evm_sk()) + return EMIF_REG_SDRAM_TYPE_DDR3; - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); + return EMIF_REG_SDRAM_TYPE_DDR2; } -#endif /* * early system init of muxing and clocks. @@ -92,22 +166,38 @@ void s_init(void) regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); - /* Initialize the Timer */ - init_timer(); - preloader_console_init(); - config_ddr(); -#endif + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); - /* Enable MMC0 */ - enable_mmc0_pin_mux(); + enable_board_pin_mux(&header); + if (board_is_evm_sk()) { + /* + * EVM SK 1.2A and later use gpio0_7 to enable DDR3. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + } + + config_ddr(board_memory_type()); +#endif } #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + int ret; + + ret = omap_mmc_init(0, 0, 0); + if (ret) + return ret; + + return omap_mmc_init(1, 0, 0); } #endif @@ -116,3 +206,93 @@ void setup_clocks_for_console(void) /* Not yet implemented */ return; } + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = AM335X_CPSW_MDIO_BASE, + .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + debug("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return -1; + } + + if (board_is_bone()) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_MII; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_RGMII; + } + + return cpsw_register(&cpsw_data); +} +#endif diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bbb9c1353f..2b19506a34 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -24,6 +24,7 @@ #define PRCM_MOD_EN 0x2 #define PRCM_FORCE_WAKEUP 0x2 +#define PRCM_FUNCTL 0x0 #define PRCM_EMIF_CLK_ACTIVITY BIT(2) #define PRCM_L3_GCLK_ACTIVITY BIT(4) @@ -38,7 +39,7 @@ #define CLK_MODE_SEL 0x7 #define CLK_MODE_MASK 0xfffffff8 #define CLK_DIV_SEL 0xFFFFFFE0 - +#define CPGMAC0_IDLE 0x30000 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; @@ -70,6 +71,10 @@ static void enable_interface_clocks(void) writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) ; + + writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); + while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) + ; } /* @@ -118,6 +123,36 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) ; + + /* gpio1 module */ + writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); + while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) + ; + + /* gpio2 module */ + writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); + while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) + ; + + /* gpio3 module */ + writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); + while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) + ; + + /* i2c1 */ + writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); + while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) + ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); + while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) + ; + + /* spi0 */ + writel(PRCM_MOD_EN, &cmper->spi0clkctrl); + while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) @@ -216,7 +251,7 @@ static void per_pll_config(void) ; } -static void ddr_pll_config(void) +void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@ -234,7 +269,7 @@ static void ddr_pll_config(void) ; clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N); + clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); writel(clksel, &cmwkup->clkseldpllddr); div_m2 = div_m2 & CLK_DIV_SEL; @@ -255,11 +290,6 @@ void enable_emif_clocks(void) writel(PRCM_MOD_EN, &cmper->emiffwclkctrl); /* Enable EMIF0 Clock */ writel(PRCM_MOD_EN, &cmper->emifclkctrl); - /* Poll for emif_gclk & L3_G clock are active */ - while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) - ; /* Poll if module is functional */ while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN) ; @@ -273,7 +303,6 @@ void pll_init() mpu_pll_config(); core_pll_config(); per_pll_config(); - ddr_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index ed982c11e8..fd9fc4a720 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,13 +17,15 @@ http://www.ti.com/ #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/emif.h> /** * Base address for EMIF instances */ -static struct emif_regs *emif_reg = { - (struct emif_regs *)EMIF4_0_CFG_BASE}; +static struct emif_reg_struct *emif_reg = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE}; /** * Base address for DDR instance @@ -39,109 +41,79 @@ static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; /** - * As a convention, all functions here return 0 on success - * -1 on failure. - */ - -/** * Configure SDRAM */ -int config_sdram(struct sdram_config *cfg) +void config_sdram(const struct emif_regs *regs) { - writel(cfg->sdrcr, &emif_reg->sdrcr); - writel(cfg->sdrcr2, &emif_reg->sdrcr2); - writel(cfg->refresh, &emif_reg->sdrrcr); - writel(cfg->refresh_sh, &emif_reg->sdrrcsr); - - return 0; + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + if (regs->zq_config){ + writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + } + writel(regs->sdram_config, &emif_reg->emif_sdram_config); } /** * Set SDRAM timings */ -int set_sdram_timings(struct sdram_timing *t) +void set_sdram_timings(const struct emif_regs *regs) { - writel(t->time1, &emif_reg->sdrtim1); - writel(t->time1_sh, &emif_reg->sdrtim1sr); - writel(t->time2, &emif_reg->sdrtim2); - writel(t->time2_sh, &emif_reg->sdrtim2sr); - writel(t->time3, &emif_reg->sdrtim3); - writel(t->time3_sh, &emif_reg->sdrtim3sr); - - return 0; + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw); } /** * Configure DDR PHY */ -int config_ddr_phy(struct ddr_phy_control *p) +void config_ddr_phy(const struct emif_regs *regs) { - writel(p->reg, &emif_reg->ddrphycr); - writel(p->reg_sh, &emif_reg->ddrphycsr); - - return 0; + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw); } /** * Configure DDR CMD control registers */ -int config_cmd_ctrl(struct cmd_control *cmd) +void config_cmd_ctrl(const struct cmd_control *cmd) { writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); - writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce); - writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay); writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio); - writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce); - writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay); writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio); - writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce); - writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay); writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); - - return 0; } /** * Configure DDR DATA registers */ -int config_ddr_data(int macrono, struct ddr_data *data) +void config_ddr_data(int macrono, const struct ddr_data *data) { writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); - writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1); - writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0); - writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1); - writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0); - writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1); writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0); - writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1); - writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0); - writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1); - writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0); - writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1); - + writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0); writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); - - return 0; } -int config_io_ctrl(struct ddr_ioctrl *ioctrl) +void config_io_ctrl(unsigned long val) { - writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl); - writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl); - writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl); - writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl); - writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl); - - return 0; + writel(val, &ioctrl_reg->cm0ioctl); + writel(val, &ioctrl_reg->cm1ioctl); + writel(val, &ioctrl_reg->cm2ioctl); + writel(val, &ioctrl_reg->dt0ioctl); + writel(val, &ioctrl_reg->dt1ioctl); } diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 2f4164df82..b2d7c0d956 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -21,15 +21,12 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/hardware.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/emif.h> DECLARE_GLOBAL_DATA_PTR; -struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR; -struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; -struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; - - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -47,58 +44,80 @@ void dram_init_banksize(void) #ifdef CONFIG_SPL_BUILD -static void data_macro_config(int dataMacroNum) -{ - struct ddr_data data; - - data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) - |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)); - data.datardsratio1 = DDR2_RD_DQS>>2; - data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) - |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)); - data.datawdsratio1 = DDR2_WR_DQS>>2; - data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) - |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)); - data.datawiratio1 = DDR2_PHY_WRLVL>>2; - data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) - |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)); - data.datagiratio1 = DDR2_PHY_GATELVL>>2; - data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) - |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)); - data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2; - data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) - |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)); - data.datawrsratio1 = DDR2_PHY_WR_DATA>>2; - data.datadldiff0 = PHY_DLL_LOCK_DIFF; - - config_ddr_data(dataMacroNum, &data); -} - -static void cmd_macro_config(void) -{ - struct cmd_control cmd; - - cmd.cmd0csratio = DDR2_RATIO; - cmd.cmd0csforce = CMD_FORCE; - cmd.cmd0csdelay = CMD_DELAY; - cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd0iclkout = DDR2_INVERT_CLKOUT; - - cmd.cmd1csratio = DDR2_RATIO; - cmd.cmd1csforce = CMD_FORCE; - cmd.cmd1csdelay = CMD_DELAY; - cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd1iclkout = DDR2_INVERT_CLKOUT; - - cmd.cmd2csratio = DDR2_RATIO; - cmd.cmd2csforce = CMD_FORCE; - cmd.cmd2csdelay = CMD_DELAY; - cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd2iclkout = DDR2_INVERT_CLKOUT; - - config_cmd_ctrl(&cmd); - -} +static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; + +static const struct ddr_data ddr2_data = { + .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) + |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), + .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) + |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), + .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) + |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), + .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) + |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), + .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) + |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) + |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + .datauserank0delay = DDR2_PHY_RANK0_DELAY, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = DDR2_RATIO, + .cmd0dldiff = DDR2_DLL_LOCK_DIFF, + .cmd0iclkout = DDR2_INVERT_CLKOUT, + + .cmd1csratio = DDR2_RATIO, + .cmd1dldiff = DDR2_DLL_LOCK_DIFF, + .cmd1iclkout = DDR2_INVERT_CLKOUT, + + .cmd2csratio = DDR2_RATIO, + .cmd2dldiff = DDR2_DLL_LOCK_DIFF, + .cmd2iclkout = DDR2_INVERT_CLKOUT, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = DDR2_EMIF_SDCFG, + .ref_ctrl = DDR2_EMIF_SDREF, + .sdram_tim1 = DDR2_EMIF_TIM1, + .sdram_tim2 = DDR2_EMIF_TIM2, + .sdram_tim3 = DDR2_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, +}; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = DDR3_RD_DQS, + .datawdsratio0 = DDR3_WR_DQS, + .datafwsratio0 = DDR3_PHY_FIFO_WE, + .datawrsratio0 = DDR3_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = DDR3_RATIO, + .cmd0dldiff = DDR3_DLL_LOCK_DIFF, + .cmd0iclkout = DDR3_INVERT_CLKOUT, + + .cmd1csratio = DDR3_RATIO, + .cmd1dldiff = DDR3_DLL_LOCK_DIFF, + .cmd1iclkout = DDR3_INVERT_CLKOUT, + + .cmd2csratio = DDR3_RATIO, + .cmd2dldiff = DDR3_DLL_LOCK_DIFF, + .cmd2iclkout = DDR3_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = DDR3_EMIF_SDCFG, + .ref_ctrl = DDR3_EMIF_SDREF, + .sdram_tim1 = DDR3_EMIF_TIM1, + .sdram_tim2 = DDR3_EMIF_TIM2, + .sdram_tim3 = DDR3_EMIF_TIM3, + .zq_config = DDR3_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, +}; static void config_vtp(void) { @@ -115,87 +134,46 @@ static void config_vtp(void) ; } -static void config_emif_ddr2(void) -{ - int i; - int ret; - struct sdram_config cfg; - struct sdram_timing tmg; - struct ddr_phy_control phyc; - - /*Program EMIF0 CFG Registers*/ - phyc.reg = EMIF_READ_LATENCY; - phyc.reg_sh = EMIF_READ_LATENCY; - phyc.reg2 = EMIF_READ_LATENCY; - - tmg.time1 = EMIF_TIM1; - tmg.time1_sh = EMIF_TIM1; - tmg.time2 = EMIF_TIM2; - tmg.time2_sh = EMIF_TIM2; - tmg.time3 = EMIF_TIM3; - tmg.time3_sh = EMIF_TIM3; - - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - cfg.refresh = 0x00004650; - cfg.refresh_sh = 0x00004650; - - /* Program EMIF instance */ - ret = config_ddr_phy(&phyc); - if (ret < 0) - printf("Couldn't configure phyc\n"); - - ret = config_sdram(&cfg); - if (ret < 0) - printf("Couldn't configure SDRAM\n"); - - ret = set_sdram_timings(&tmg); - if (ret < 0) - printf("Couldn't configure timings\n"); - - /* Delay */ - for (i = 0; i < 5000; i++) - ; - - cfg.refresh = EMIF_SDREF; - cfg.refresh_sh = EMIF_SDREF; - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - - ret = config_sdram(&cfg); - if (ret < 0) - printf("Couldn't configure SDRAM\n"); -} - -void config_ddr(void) +void config_ddr(short ddr_type) { - int data_macro_0 = 0; - int data_macro_1 = 1; - struct ddr_ioctrl ioctrl; + int ddr_pll, ioctrl_val; + const struct emif_regs *emif_regs; + const struct ddr_data *ddr_data; + const struct cmd_control *cmd_ctrl_data; + + if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { + ddr_pll = 266; + cmd_ctrl_data = &ddr2_cmd_ctrl_data; + ddr_data = &ddr2_data; + ioctrl_val = DDR2_IOCTRL_VALUE; + emif_regs = &ddr2_emif_reg_data; + } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) { + ddr_pll = 303; + cmd_ctrl_data = &ddr3_cmd_ctrl_data; + ddr_data = &ddr3_data; + ioctrl_val = DDR3_IOCTRL_VALUE; + emif_regs = &ddr3_emif_reg_data; + } else { + puts("Unknown memory type"); + hang(); + } enable_emif_clocks(); - + ddr_pll_config(ddr_pll); config_vtp(); + config_cmd_ctrl(cmd_ctrl_data); - cmd_macro_config(); - - data_macro_config(data_macro_0); - data_macro_config(data_macro_1); + config_ddr_data(0, ddr_data); + config_ddr_data(1, ddr_data); - writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + config_io_ctrl(ioctrl_val); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - config_io_ctrl(&ioctrl); - - writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl); - writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl); - - config_emif_ddr2(); + /* Program EMIF instance */ + config_ddr_phy(emif_regs); + set_sdram_timings(emif_regs); + config_sdram(emif_regs); } #endif |
