diff options
| -rw-r--r-- | CHANGELOG | 16 | ||||
| -rw-r--r-- | board/icecube/icecube.c | 11 | ||||
| -rw-r--r-- | board/icu862/u-boot.lds | 5 | ||||
| -rw-r--r-- | board/rmu/rmu.c | 19 | ||||
| -rw-r--r-- | cpu/mpc5xxx/cpu.c | 24 | ||||
| -rw-r--r-- | cpu/mpc8xx/start.S | 12 | ||||
| -rw-r--r-- | include/configs/ICU862.h | 2 | ||||
| -rw-r--r-- | include/configs/IceCube.h | 2 | ||||
| -rw-r--r-- | include/configs/rmu.h | 8 | ||||
| -rw-r--r-- | include/mpc5xxx.h | 5 | ||||
| -rw-r--r-- | include/version.h | 2 |
11 files changed, 53 insertions, 53 deletions
@@ -1,5 +1,15 @@ ====================================================================== -Changes for U-Boot 0.4.5: +Changes for U-Boot 0.4.7: +====================================================================== + +* Fix ICU862 environment problem + +* Fix RAM size detection for RMU board + +* Implement "reset" for MGT5100/MPC5200 systems + +====================================================================== +Changes for U-Boot 0.4.6: ====================================================================== * Make Ethernet autonegotiation on INCA-IP work for all clock rates; @@ -14,6 +24,10 @@ Changes for U-Boot 0.4.5: * Patch by Richard Woodruff, 8 Aug 2003: Allow crc32 to be used at address 0x000 (crc32_no_comp, too). +====================================================================== +Changes for U-Boot 0.4.5: +====================================================================== + * Update for TQM board defaults: disable clocks_in_mhz, enable boot count limit diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 396ad2a4f2..f75e675186 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -25,6 +25,7 @@ #include <mpc5xxx.h> #include <pci.h> +#ifndef CFG_RAMBOOT static long int dram_size(long int *base, long int maxsize) { volatile long int *addr; @@ -86,11 +87,14 @@ static void sdram_start (int hi_addr) /* normal operation */ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit; } +#endif long int initdram (int board_type) { - ulong test1, test2, dramsize = 0; + ulong dramsize = 0; #ifndef CFG_RAMBOOT + ulong test1, test2; + /* configure SDRAM start/end */ #if defined(CONFIG_MPC5200) *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ @@ -133,8 +137,11 @@ long int initdram (int board_type) #else #ifdef CONFIG_MGT5100 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); +#else + dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); #endif -#endif +#endif /* CFG_RAMBOOT */ /* return total ram size */ return dramsize; } diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 496c5987ff..84e9cbf2e5 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -136,11 +136,6 @@ SECTIONS *(.bss) *(COMMON) } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/environment.o (.ppcenv) - } _end = . ; PROVIDE (end = .); } diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c index c9925d09a3..331fb9877a 100644 --- a/board/rmu/rmu.c +++ b/board/rmu/rmu.c @@ -96,7 +96,7 @@ long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10 ; + long int size9 ; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); @@ -109,7 +109,7 @@ long int initdram (int board_type) memctl->memc_or1 = CFG_OR1_PRELIM; memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay(200); @@ -122,13 +122,20 @@ long int initdram (int board_type) udelay (1000); - /* Check Bank 0 Memory Size - * try 10 column mode + /* Check Bank 0 Memory Size, + * 9 column mode */ - size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ; + size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ; - return (size10); + /* + * Final mapping: + */ + + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + udelay (1000); + + return (size9); } /* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 7d95d2f9c3..c481d187df 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -54,31 +54,17 @@ int checkcpu (void) int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - ulong msr, addr; - - *(vu_long *)MPC5XXX_CDM_SRESET &= ~(1 << 16); /* Checkstop Reset enable */ - + ulong msr; /* Interrupts and MMU off */ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); + /* Charge the watchdog timer */ + *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0xf; + *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ + return 1; } diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index cdd549fc74..3ebcab46ae 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -76,9 +76,6 @@ GOT_ENTRY(__init_end) GOT_ENTRY(_end) GOT_ENTRY(__bss_start) -#if defined(CONFIG_ICU862) - GOT_ENTRY(environment) -#endif END_GOT /* @@ -617,16 +614,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_ICU862) - /* - * For the FADS - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(_end) -#endif cmplw 0, r3, r4 beq 6f diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index a7a11a6163..fea0fce256 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -196,7 +196,7 @@ #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #endif #else -#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #endif #define CFG_MONITOR_BASE TEXT_BASE #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 6a43441a36..352beae607 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -131,9 +131,7 @@ */ #define CFG_MBAR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 -#ifdef CONFIG_MPC5200 #define CFG_DEFAULT_MBAR 0x80000000 -#endif /* Use SRAM until RAM will be available */ #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM diff --git a/include/configs/rmu.h b/include/configs/rmu.h index 0a94714f7b..7b33c7e1b1 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -291,12 +291,12 @@ * */ #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000E00 -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) /* RPXLITE mem setting */ @@ -321,8 +321,8 @@ * MAMR settings for SDRAM */ -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index b803d03df4..4218b050fc 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -78,6 +78,7 @@ #define MPC5XXX_CDM (CFG_MBAR + 0x0200) #define MPC5XXX_LPB (CFG_MBAR + 0x0300) #define MPC5XXX_ICTL (CFG_MBAR + 0x0500) +#define MPC5XXX_GPT (CFG_MBAR + 0x0600) #define MPC5XXX_GPIO (CFG_MBAR + 0x0b00) #define MPC5XXX_PCI (CFG_MBAR + 0x0d00) #define MPC5XXX_SDMA (CFG_MBAR + 0x1200) @@ -183,6 +184,10 @@ #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) +/* General Purpose Timers registers */ +#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) +#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) + /* Programmable Serial Controller (PSC) status register bits */ #define PSC_SR_CDE 0x0080 #define PSC_SR_RXRDY 0x0100 diff --git a/include/version.h b/include/version.h index 5ba84884c2..d295c2a3c7 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 0.4.6" +#define U_BOOT_VERSION "U-Boot 0.4.7" #endif /* __VERSION_H__ */ |
