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-rw-r--r--.gitignore1
-rw-r--r--MAINTAINERS2
-rw-r--r--Makefile25
-rw-r--r--README17
-rw-r--r--arch/arm/cpu/arm920t/ep93xx/u-boot.lds8
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds7
-rw-r--r--arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds7
-rw-r--r--arch/arm/cpu/armv7/omap-common/u-boot-spl.lds5
-rw-r--r--arch/arm/cpu/ixp/u-boot.lds8
-rw-r--r--arch/arm/cpu/u-boot.lds8
-rw-r--r--arch/arm/imx-common/cmd_bmode.c11
-rw-r--r--arch/arm/include/asm/global_data.h2
-rw-r--r--arch/arm/include/asm/u-boot.h2
-rw-r--r--arch/arm/lib/board.c17
-rw-r--r--arch/avr32/cpu/u-boot.lds8
-rw-r--r--arch/avr32/include/asm/global_data.h2
-rw-r--r--arch/avr32/include/asm/u-boot.h2
-rw-r--r--arch/avr32/lib/board.c4
-rw-r--r--arch/blackfin/cpu/u-boot.lds8
-rw-r--r--arch/blackfin/include/asm/global_data.h2
-rw-r--r--arch/blackfin/include/asm/u-boot.h2
-rw-r--r--arch/blackfin/lib/board.c2
-rw-r--r--arch/m68k/cpu/mcf5227x/cpu_init.c8
-rw-r--r--arch/m68k/cpu/mcf5227x/start.S2
-rw-r--r--arch/m68k/cpu/mcf523x/start.S2
-rw-r--r--arch/m68k/cpu/mcf52x2/start.S2
-rw-r--r--arch/m68k/cpu/mcf532x/start.S2
-rw-r--r--arch/m68k/cpu/mcf5445x/config.mk10
-rw-r--r--arch/m68k/cpu/mcf5445x/cpu.c17
-rw-r--r--arch/m68k/cpu/mcf5445x/cpu_init.c316
-rw-r--r--arch/m68k/cpu/mcf5445x/speed.c89
-rw-r--r--arch/m68k/cpu/mcf5445x/start.S273
-rw-r--r--arch/m68k/cpu/mcf547x_8x/start.S4
-rw-r--r--arch/m68k/include/asm/cache.h11
-rw-r--r--arch/m68k/include/asm/global_data.h2
-rw-r--r--arch/m68k/include/asm/immap.h43
-rw-r--r--arch/m68k/include/asm/immap_5441x.h387
-rw-r--r--arch/m68k/include/asm/m5441x.h887
-rw-r--r--arch/m68k/include/asm/u-boot.h2
-rw-r--r--arch/m68k/lib/board.c7
-rw-r--r--arch/microblaze/cpu/u-boot.lds9
-rw-r--r--arch/microblaze/include/asm/global_data.h2
-rw-r--r--arch/microblaze/include/asm/u-boot.h2
-rw-r--r--arch/mips/cpu/mips32/au1x00/Makefile2
-rw-r--r--arch/mips/cpu/mips32/au1x00/au1x00_ide.c (renamed from board/bmw/m48t59y.h)43
-rw-r--r--arch/mips/cpu/mips32/au1x00/au1x00_serial.c8
-rw-r--r--arch/mips/cpu/mips32/cache.S10
-rw-r--r--arch/mips/cpu/mips32/cpu.c8
-rw-r--r--arch/mips/cpu/mips32/incaip/asc_serial.c10
-rw-r--r--arch/mips/cpu/mips64/Makefile45
-rw-r--r--arch/mips/cpu/mips64/cache.S229
-rw-r--r--arch/mips/cpu/mips64/config.mk40
-rw-r--r--arch/mips/cpu/mips64/cpu.c111
-rw-r--r--arch/mips/cpu/mips64/interrupts.c34
-rw-r--r--arch/mips/cpu/mips64/start.S256
-rw-r--r--arch/mips/cpu/mips64/time.c87
-rw-r--r--arch/mips/cpu/xburst/cpu.c12
-rw-r--r--arch/mips/cpu/xburst/jz_serial.c8
-rw-r--r--arch/mips/cpu/xburst/start.S4
-rw-r--r--arch/mips/include/asm/addrspace.h2
-rw-r--r--arch/mips/include/asm/asm.h2
-rw-r--r--arch/mips/include/asm/cacheops.h82
-rw-r--r--arch/mips/include/asm/global_data.h2
-rw-r--r--arch/mips/include/asm/io.h16
-rw-r--r--arch/mips/include/asm/posix_types.h6
-rw-r--r--arch/mips/include/asm/u-boot.h2
-rw-r--r--arch/mips/lib/board.c4
-rw-r--r--arch/nds32/cpu/n1213/u-boot.lds8
-rw-r--r--arch/nds32/include/asm/global_data.h2
-rw-r--r--arch/nds32/include/asm/u-boot.h2
-rw-r--r--arch/nds32/lib/board.c6
-rw-r--r--arch/nios2/cpu/u-boot.lds10
-rw-r--r--arch/nios2/include/asm/global_data.h2
-rw-r--r--arch/nios2/include/asm/u-boot.h2
-rw-r--r--arch/openrisc/include/asm/global_data.h2
-rw-r--r--arch/openrisc/include/asm/u-boot.h2
-rw-r--r--arch/powerpc/cpu/74xx_7xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc512x/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc5xx/serial.c10
-rw-r--r--arch/powerpc/cpu/mpc5xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds6
-rw-r--r--arch/powerpc/cpu/mpc5xxx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc8220/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc8220/uart.c9
-rw-r--r--arch/powerpc/cpu/mpc824x/cpu_init.c4
-rw-r--r--arch/powerpc/cpu/mpc824x/start.S9
-rw-r--r--arch/powerpc/cpu/mpc824x/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc8260/serial_scc.c9
-rw-r--r--arch/powerpc/cpu/mpc8260/serial_smc.c9
-rw-r--r--arch/powerpc/cpu/mpc8260/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c1
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c3
-rw-r--r--arch/powerpc/cpu/mpc83xx/speed.c27
-rw-r--r--arch/powerpc/cpu/mpc83xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile12
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_ids.c141
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_serdes.c162
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c14
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c42
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c62
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c91
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c34
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c203
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h26
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c70
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h3
-rw-r--r--arch/powerpc/cpu/mpc85xx/liodn.c60
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c155
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.h5
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5040_ids.c127
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5040_serdes.c117
-rw-r--r--arch/powerpc/cpu/mpc85xx/portals.c13
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S219
-rw-r--r--arch/powerpc/cpu/mpc85xx/serial_scc.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c163
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S346
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_ids.c203
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c237
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand.lds7
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds4
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc86xx/fdt.c2
-rw-r--r--arch/powerpc/cpu/mpc86xx/mp.c9
-rw-r--r--arch/powerpc/cpu/mpc86xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c11
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c84
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/interactive.c12
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c16
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c26
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/options.c45
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/util.c22
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fdt.c50
-rw-r--r--arch/powerpc/cpu/mpc8xxx/srio.c216
-rw-r--r--arch/powerpc/cpu/ppc4xx/u-boot.lds8
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h103
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h34
-rw-r--r--arch/powerpc/include/asm/fsl_fman.h17
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h15
-rw-r--r--arch/powerpc/include/asm/fsl_memac.h271
-rw-r--r--arch/powerpc/include/asm/fsl_portals.h5
-rw-r--r--arch/powerpc/include/asm/fsl_serdes.h42
-rw-r--r--arch/powerpc/include/asm/global_data.h4
-rw-r--r--arch/powerpc/include/asm/immap_83xx.h65
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h367
-rw-r--r--arch/powerpc/include/asm/immap_qe.h2
-rw-r--r--arch/powerpc/include/asm/mp.h2
-rw-r--r--arch/powerpc/include/asm/mpc85xx_gpio.h5
-rw-r--r--arch/powerpc/include/asm/processor.h11
-rw-r--r--arch/powerpc/include/asm/u-boot.h2
-rw-r--r--arch/powerpc/lib/Makefile1
-rw-r--r--arch/powerpc/lib/board.c4
-rw-r--r--arch/powerpc/lib/ide.c201
-rw-r--r--arch/powerpc/lib/ide.h31
-rw-r--r--arch/sandbox/cpu/u-boot.lds8
-rw-r--r--arch/sandbox/include/asm/global_data.h2
-rw-r--r--arch/sh/cpu/sh2/u-boot.lds9
-rw-r--r--arch/sh/cpu/sh3/u-boot.lds9
-rw-r--r--arch/sh/cpu/sh4/u-boot.lds9
-rw-r--r--arch/sh/include/asm/global_data.h2
-rw-r--r--arch/sh/include/asm/u-boot.h2
-rw-r--r--arch/sparc/cpu/leon2/serial.c9
-rw-r--r--arch/sparc/cpu/leon3/serial.c9
-rw-r--r--arch/sparc/include/asm/global_data.h2
-rw-r--r--arch/sparc/include/asm/u-boot.h2
-rw-r--r--arch/sparc/lib/board.c4
-rw-r--r--arch/x86/cpu/u-boot.lds7
-rw-r--r--arch/x86/include/asm/global_data.h2
-rw-r--r--board/BuS/eb_cpu5282/u-boot.lds8
-rw-r--r--board/LEOX/elpt860/u-boot.lds8
-rw-r--r--board/Marvell/common/serial.c9
-rw-r--r--board/RPXClassic/u-boot.lds8
-rw-r--r--board/RPXClassic/u-boot.lds.debug8
-rw-r--r--board/RPXlite/u-boot.lds8
-rw-r--r--board/RPXlite/u-boot.lds.debug8
-rw-r--r--board/RPXlite_dw/u-boot.lds8
-rw-r--r--board/RPXlite_dw/u-boot.lds.debug8
-rw-r--r--board/RRvision/u-boot.lds8
-rw-r--r--board/actux1/u-boot.lds8
-rw-r--r--board/actux2/u-boot.lds8
-rw-r--r--board/actux3/u-boot.lds8
-rw-r--r--board/adder/u-boot.lds8
-rw-r--r--board/ait/cam_enc_4xx/u-boot-spl.lds4
-rw-r--r--board/altera/nios2-generic/u-boot.lds10
-rw-r--r--board/amcc/acadia/u-boot-nand.lds6
-rw-r--r--board/amcc/bamboo/u-boot-nand.lds6
-rw-r--r--board/amcc/canyonlands/u-boot-nand.lds6
-rw-r--r--board/amcc/kilauea/u-boot-nand.lds6
-rw-r--r--board/amcc/sequoia/u-boot-nand.lds6
-rw-r--r--board/amcc/sequoia/u-boot-ram.lds6
-rw-r--r--board/astro/mcf5373l/u-boot.lds70
-rw-r--r--board/bmw/README331
-rw-r--r--board/bmw/bmw.c159
-rw-r--r--board/bmw/bmw.h86
-rw-r--r--board/bmw/early_init.S1170
-rw-r--r--board/bmw/flash.c779
-rw-r--r--board/bmw/m48t59y.c324
-rw-r--r--board/bmw/ns16550.c57
-rw-r--r--board/bmw/ns16550.h79
-rw-r--r--board/bmw/serial.c105
-rw-r--r--board/c2mon/u-boot.lds8
-rw-r--r--board/c2mon/u-boot.lds.debug8
-rw-r--r--board/cobra5272/u-boot.lds8
-rw-r--r--board/cogent/serial.c8
-rw-r--r--board/cogent/u-boot.lds8
-rw-r--r--board/cogent/u-boot.lds.debug8
-rw-r--r--board/cpc45/Makefile2
-rw-r--r--board/cpc45/cpc45.c15
-rw-r--r--board/cpc45/ide.c145
-rw-r--r--board/cray/L1/u-boot.lds.debug8
-rw-r--r--board/dave/PPChameleonEVB/u-boot.lds8
-rw-r--r--board/davinci/da8xxevm/u-boot-spl-da850evm.lds6
-rw-r--r--board/davinci/da8xxevm/u-boot-spl-hawk.lds5
-rw-r--r--board/dbau1x00/u-boot.lds7
-rw-r--r--board/dvlhost/u-boot.lds8
-rw-r--r--board/eltec/mhpc/u-boot.lds8
-rw-r--r--board/eltec/mhpc/u-boot.lds.debug8
-rw-r--r--board/emk/top860/u-boot.lds8
-rw-r--r--board/ep88x/u-boot.lds8
-rw-r--r--board/esd/cpci750/ide.c1
-rw-r--r--board/esd/cpci750/serial.c10
-rw-r--r--board/esd/dasa_sim/u-boot.lds8
-rw-r--r--board/esd/pmc440/u-boot-nand.lds6
-rw-r--r--board/esd/tasreg/u-boot.lds8
-rw-r--r--board/esteem192e/u-boot.lds8
-rw-r--r--board/etx094/u-boot.lds8
-rw-r--r--board/evb64260/serial.c9
-rw-r--r--board/evb64260/u-boot.lds8
-rw-r--r--board/fads/u-boot.lds8
-rw-r--r--board/flagadm/u-boot.lds8
-rw-r--r--board/flagadm/u-boot.lds.debug8
-rw-r--r--board/freescale/common/Makefile1
-rw-r--r--board/freescale/common/qixis.c15
-rw-r--r--board/freescale/common/qixis.h8
-rw-r--r--board/freescale/common/vsc3316_3308.c184
-rw-r--r--board/freescale/common/vsc3316_3308.h34
-rw-r--r--board/freescale/m5208evbe/u-boot.lds8
-rw-r--r--board/freescale/m52277evb/u-boot.lds8
-rw-r--r--board/freescale/m5235evb/u-boot.lds8
-rw-r--r--board/freescale/m5249evb/u-boot.lds8
-rw-r--r--board/freescale/m5253demo/u-boot.lds8
-rw-r--r--board/freescale/m5253evbe/u-boot.lds8
-rw-r--r--board/freescale/m5271evb/u-boot.lds8
-rw-r--r--board/freescale/m5272c3/u-boot.lds8
-rw-r--r--board/freescale/m5275evb/u-boot.lds8
-rw-r--r--board/freescale/m5282evb/u-boot.lds11
-rw-r--r--board/freescale/m53017evb/u-boot.lds8
-rw-r--r--board/freescale/m5329evb/u-boot.lds8
-rw-r--r--board/freescale/m5373evb/u-boot.lds8
-rw-r--r--board/freescale/m54418twr/Makefile (renamed from board/bmw/Makefile)17
-rw-r--r--board/freescale/m54418twr/config.mk (renamed from board/bmw/config.mk)13
-rw-r--r--board/freescale/m54418twr/m54418twr.c129
-rw-r--r--board/freescale/m54418twr/u-boot.lds97
-rw-r--r--board/freescale/m54451evb/u-boot.lds8
-rw-r--r--board/freescale/m54455evb/u-boot.lds8
-rw-r--r--board/freescale/m547xevb/u-boot.lds8
-rw-r--r--board/freescale/m548xevb/u-boot.lds8
-rw-r--r--board/freescale/mx31ads/u-boot.lds8
-rw-r--r--board/freescale/t4qds/Makefile (renamed from board/sbc8560/Makefile)18
-rw-r--r--board/freescale/t4qds/ddr.c186
-rw-r--r--board/freescale/t4qds/eth.c495
-rw-r--r--board/freescale/t4qds/law.c47
-rw-r--r--board/freescale/t4qds/pci.c39
-rw-r--r--board/freescale/t4qds/t4240qds_qixis.h56
-rw-r--r--board/freescale/t4qds/t4qds.c395
-rw-r--r--board/freescale/t4qds/t4qds.h37
-rw-r--r--board/freescale/t4qds/tlb.c136
-rw-r--r--board/gaisler/gr_cpci_ax2000/u-boot.lds7
-rw-r--r--board/gaisler/gr_ep2s60/u-boot.lds7
-rw-r--r--board/gaisler/gr_xc3s_1500/u-boot.lds7
-rw-r--r--board/gaisler/grsim/u-boot.lds7
-rw-r--r--board/gaisler/grsim_leon2/u-boot.lds7
-rw-r--r--board/gen860t/u-boot-flashenv.lds7
-rw-r--r--board/gen860t/u-boot.lds8
-rw-r--r--board/genietv/u-boot.lds8
-rw-r--r--board/genietv/u-boot.lds.debug8
-rw-r--r--board/hermes/u-boot.lds8
-rw-r--r--board/hermes/u-boot.lds.debug8
-rw-r--r--board/hymod/u-boot.lds8
-rw-r--r--board/hymod/u-boot.lds.debug8
-rw-r--r--board/icu862/u-boot.lds8
-rw-r--r--board/icu862/u-boot.lds.debug8
-rw-r--r--board/idmr/u-boot.lds8
-rw-r--r--board/incaip/u-boot.lds7
-rw-r--r--board/ip860/u-boot.lds8
-rw-r--r--board/ip860/u-boot.lds.debug8
-rw-r--r--board/ivm/ivm.c46
-rw-r--r--board/ivm/u-boot.lds8
-rw-r--r--board/ivm/u-boot.lds.debug8
-rw-r--r--board/keymile/km83xx/km83xx.c2
-rw-r--r--board/kmc/kzm9g/kzm9g.c7
-rw-r--r--board/korat/u-boot-F7FC.lds6
-rw-r--r--board/kup/kup4k/u-boot.lds8
-rw-r--r--board/kup/kup4k/u-boot.lds.debug8
-rw-r--r--board/kup/kup4x/u-boot.lds8
-rw-r--r--board/kup/kup4x/u-boot.lds.debug8
-rw-r--r--board/lantec/u-boot.lds8
-rw-r--r--board/lantec/u-boot.lds.debug8
-rw-r--r--board/linkstation/ide.c1
-rw-r--r--board/lubbock/lubbock.c9
-rw-r--r--board/lwmon/u-boot.lds8
-rw-r--r--board/lwmon/u-boot.lds.debug8
-rw-r--r--board/manroland/uc100/u-boot.lds8
-rw-r--r--board/matrix_vision/mvsmr/u-boot.lds8
-rw-r--r--board/mbx8xx/u-boot.lds8
-rw-r--r--board/mbx8xx/u-boot.lds.debug8
-rw-r--r--board/micronas/vct/u-boot.lds6
-rw-r--r--board/mousse/u-boot.lds8
-rw-r--r--board/mousse/u-boot.lds.ram3
-rw-r--r--board/mousse/u-boot.lds.rom3
-rw-r--r--board/mpl/pip405/u-boot.lds.debug8
-rw-r--r--board/mvblue/u-boot.lds8
-rw-r--r--board/netphone/u-boot.lds8
-rw-r--r--board/netphone/u-boot.lds.debug8
-rw-r--r--board/netta/u-boot.lds8
-rw-r--r--board/netta/u-boot.lds.debug8
-rw-r--r--board/netta2/u-boot.lds8
-rw-r--r--board/netta2/u-boot.lds.debug8
-rw-r--r--board/netvia/u-boot.lds8
-rw-r--r--board/netvia/u-boot.lds.debug8
-rw-r--r--board/nx823/u-boot.lds8
-rw-r--r--board/nx823/u-boot.lds.debug8
-rw-r--r--board/openrisc/openrisc-generic/u-boot.lds8
-rw-r--r--board/palmtc/palmtc.c9
-rw-r--r--board/pb1x00/u-boot.lds7
-rw-r--r--board/pcippc2/fpga_serial.c7
-rw-r--r--board/pcippc2/fpga_serial.h1
-rw-r--r--board/pcippc2/pcippc2.c3
-rw-r--r--board/pcs440ep/pcs440ep.c57
-rw-r--r--board/prodrive/p3mx/serial.c10
-rw-r--r--board/pxa255_idp/pxa_idp.c9
-rw-r--r--board/qemu-mips/config.mk10
-rw-r--r--board/qemu-mips/u-boot.lds16
-rw-r--r--board/qi/qi_lb60/u-boot.lds8
-rw-r--r--board/quantum/u-boot.lds8
-rw-r--r--board/r360mpi/u-boot.lds8
-rw-r--r--board/rbc823/u-boot.lds8
-rw-r--r--board/renesas/sh7757lcr/u-boot.lds9
-rw-r--r--board/rsdproto/u-boot.lds8
-rw-r--r--board/samsung/smdk5250/smdk5250-uboot-spl.lds5
-rw-r--r--board/samsung/smdk6400/u-boot-nand.lds10
-rw-r--r--board/sandburst/karef/u-boot.lds.debug8
-rw-r--r--board/sandburst/metrobox/u-boot.lds.debug8
-rw-r--r--board/sandpoint/u-boot.lds8
-rw-r--r--board/sbc8560/README57
-rw-r--r--board/sbc8560/ddr.c43
-rw-r--r--board/sbc8560/law.c60
-rw-r--r--board/sbc8560/sbc8560.c369
-rw-r--r--board/sbc8560/tlb.c65
-rw-r--r--board/siemens/IAD210/u-boot.lds8
-rw-r--r--board/sixnet/u-boot.lds8
-rw-r--r--board/snmc/qs850/u-boot.lds8
-rw-r--r--board/snmc/qs860t/u-boot.lds8
-rw-r--r--board/spc1920/u-boot.lds8
-rw-r--r--board/spd8xx/u-boot.lds8
-rw-r--r--board/spd8xx/u-boot.lds.debug8
-rw-r--r--board/stx/stxxtc/u-boot.lds8
-rw-r--r--board/stx/stxxtc/u-boot.lds.debug8
-rw-r--r--board/svm_sc8xx/u-boot.lds8
-rw-r--r--board/ti/omap2420h4/omap2420h4.c2
-rw-r--r--board/tqc/tqm8xx/u-boot.lds8
-rw-r--r--board/trizepsiv/conxs.c9
-rw-r--r--board/v37/u-boot.lds8
-rw-r--r--board/vpac270/u-boot-spl.lds4
-rw-r--r--board/w7o/u-boot.lds.debug8
-rw-r--r--board/westel/amx860/u-boot.lds8
-rw-r--r--board/westel/amx860/u-boot.lds.debug8
-rw-r--r--board/xes/xpedite1000/u-boot.lds.debug8
-rw-r--r--boards.cfg21
-rw-r--r--common/Makefile2
-rw-r--r--common/bouncebuf.c92
-rw-r--r--common/cmd_bdinfo.c26
-rw-r--r--common/cmd_cbfs.c214
-rw-r--r--common/cmd_fdt.c186
-rw-r--r--common/cmd_help.c8
-rw-r--r--common/cmd_i2c.c70
-rw-r--r--common/cmd_ide.c483
-rw-r--r--common/command.c17
-rw-r--r--common/env_common.c97
-rw-r--r--common/env_embedded.c104
-rw-r--r--common/image.c46
-rw-r--r--common/usb.c12
-rw-r--r--common/usb_storage.c24
-rw-r--r--config.mk2
-rw-r--r--disk/part.c54
-rw-r--r--disk/part_dos.c28
-rw-r--r--disk/part_efi.c86
-rw-r--r--disk/part_efi.h13
-rw-r--r--doc/DocBook/Makefile2
-rw-r--r--doc/DocBook/linker_lists.tmpl46
-rw-r--r--doc/DocBook/stdio.tmpl46
-rw-r--r--doc/README.VSC3316-330843
-rw-r--r--doc/README.commands10
-rw-r--r--doc/README.fsl-ddr5
-rw-r--r--doc/README.m54418twr244
-rw-r--r--doc/README.mpc85xx-spin-table26
-rw-r--r--doc/README.t4240qds98
-rw-r--r--drivers/i2c/sh_i2c.c139
-rw-r--r--drivers/input/i8042.c90
-rw-r--r--drivers/input/input.c102
-rw-r--r--drivers/mmc/Makefile2
-rw-r--r--drivers/mmc/dw_mmc.c385
-rw-r--r--drivers/mmc/mmc.c92
-rw-r--r--drivers/mmc/mmc_spi.c4
-rw-r--r--drivers/mmc/mxsmmc.c36
-rw-r--r--drivers/mmc/pxa_mmc.c643
-rw-r--r--drivers/mmc/s5p_sdhci.c3
-rw-r--r--drivers/mmc/sdhci.c12
-rw-r--r--drivers/net/fm/Makefile6
-rw-r--r--drivers/net/fm/eth.c39
-rw-r--r--drivers/net/fm/init.c18
-rw-r--r--drivers/net/fm/memac.c132
-rw-r--r--drivers/net/fm/memac_phy.c150
-rw-r--r--drivers/net/fm/t4240.c128
-rw-r--r--drivers/net/mcfmii.c4
-rw-r--r--drivers/pci/fsl_pci_init.c65
-rw-r--r--drivers/qe/qe.c21
-rw-r--r--drivers/serial/altera_jtag_uart.c8
-rw-r--r--drivers/serial/altera_uart.c9
-rw-r--r--drivers/serial/atmel_usart.c8
-rw-r--r--drivers/serial/lpc32xx_hsuart.c8
-rw-r--r--drivers/serial/mcfuart.c11
-rw-r--r--drivers/serial/ns9750_serial.c15
-rw-r--r--drivers/serial/opencores_yanu.c10
-rw-r--r--drivers/serial/s3c4510b_uart.c6
-rw-r--r--drivers/serial/s3c64xx.c8
-rw-r--r--drivers/serial/serial.c204
-rw-r--r--drivers/serial/serial_clps7111.c9
-rw-r--r--drivers/serial/serial_imx.c9
-rw-r--r--drivers/serial/serial_ixp.c9
-rw-r--r--drivers/serial/serial_ks8695.c9
-rw-r--r--drivers/serial/serial_lpc2292.c9
-rw-r--r--drivers/serial/serial_mxc.c9
-rw-r--r--drivers/serial/serial_netarm.c9
-rw-r--r--drivers/serial/serial_pl01x.c9
-rw-r--r--drivers/serial/serial_s3c44b0.c9
-rw-r--r--drivers/serial/serial_sa1100.c9
-rw-r--r--drivers/serial/serial_sh.c9
-rw-r--r--drivers/spi/fsl_espi.c6
-rw-r--r--drivers/usb/host/ehci-fsl.c22
-rw-r--r--examples/standalone/mips64.lds59
-rw-r--r--examples/standalone/sparc.lds1
-rw-r--r--fs/Makefile1
-rw-r--r--fs/cbfs/Makefile43
-rw-r--r--fs/cbfs/cbfs.c339
-rw-r--r--fs/fat/fat.c20
-rw-r--r--fs/fat/fat_write.c2
-rw-r--r--helper.mk64
-rw-r--r--include/bouncebuf.h87
-rw-r--r--include/cbfs.h181
-rw-r--r--include/command.h28
-rw-r--r--include/config_phylib_all_drivers.h1
-rw-r--r--include/configs/BMW.h302
-rw-r--r--include/configs/CPC45.h1
-rw-r--r--include/configs/ICU862.h1
-rw-r--r--include/configs/IVML24.h2
-rw-r--r--include/configs/IVMS8.h2
-rw-r--r--include/configs/KUP4K.h1
-rw-r--r--include/configs/KUP4X.h1
-rw-r--r--include/configs/M54418TWR.h448
-rw-r--r--include/configs/MBX.h1
-rw-r--r--include/configs/MPC8308RDB.h1
-rw-r--r--include/configs/NETTA.h1
-rw-r--r--include/configs/NSCU.h1
-rw-r--r--include/configs/P3041DS.h4
-rw-r--r--include/configs/P4080DS.h4
-rw-r--r--include/configs/P5020DS.h4
-rw-r--r--include/configs/R360MPI.h1
-rw-r--r--include/configs/RPXClassic.h1
-rw-r--r--include/configs/RPXlite.h1
-rw-r--r--include/configs/RPXlite_DW.h1
-rw-r--r--include/configs/RRvision.h1
-rw-r--r--include/configs/SBC8540.h428
-rw-r--r--include/configs/SPD823TS.h2
-rw-r--r--include/configs/T4240QDS.h35
-rw-r--r--include/configs/TK885D.h1
-rw-r--r--include/configs/TQM823L.h1
-rw-r--r--include/configs/TQM823M.h1
-rw-r--r--include/configs/TQM850L.h1
-rw-r--r--include/configs/TQM850M.h1
-rw-r--r--include/configs/TQM855L.h1
-rw-r--r--include/configs/TQM855M.h1
-rw-r--r--include/configs/TQM860L.h1
-rw-r--r--include/configs/TQM860M.h1
-rw-r--r--include/configs/TQM862L.h1
-rw-r--r--include/configs/TQM862M.h1
-rw-r--r--include/configs/TQM866M.h1
-rw-r--r--include/configs/TQM885D.h1
-rw-r--r--include/configs/apx4devkit.h2
-rw-r--r--include/configs/atc.h1
-rw-r--r--include/configs/c2mon.h1
-rw-r--r--include/configs/coreboot.h3
-rw-r--r--include/configs/corenet_ds.h4
-rw-r--r--include/configs/km/km8309-common.h176
-rw-r--r--include/configs/km/km8321-common.h2
-rw-r--r--include/configs/km/km83xx-common.h6
-rw-r--r--include/configs/kzm9g.h8
-rw-r--r--include/configs/lubbock.h3
-rw-r--r--include/configs/lwmon.h1
-rw-r--r--include/configs/m28evk.h2
-rw-r--r--include/configs/mpc8308_p1m.h1
-rw-r--r--include/configs/mx28evk.h2
-rw-r--r--include/configs/palmtc.h3
-rw-r--r--include/configs/pxa255_idp.h3
-rw-r--r--include/configs/qemu-mips.h55
-rw-r--r--include/configs/qemu-mips64.h175
-rw-r--r--include/configs/quantum.h1
-rw-r--r--include/configs/sbc8560.h459
-rw-r--r--include/configs/suvd3.h19
-rw-r--r--include/configs/svm_sc8xx.h2
-rw-r--r--include/configs/t4qds.h875
-rw-r--r--include/configs/trizepsiv.h3
-rw-r--r--include/configs/uc100.h1
-rw-r--r--include/configs/virtlab2.h1
-rw-r--r--include/dwmmc.h191
-rw-r--r--include/e500.h3
-rw-r--r--include/env_default.h135
-rw-r--r--include/fm_eth.h53
-rw-r--r--include/fsl_mdio.h6
-rw-r--r--include/i8042.h19
-rw-r--r--include/ide.h21
-rw-r--r--include/image.h4
-rw-r--r--include/input.h2
-rw-r--r--include/libfdt.h275
-rw-r--r--include/linker_lists.h148
-rw-r--r--include/mpc83xx.h155
-rw-r--r--include/sdhci.h1
-rw-r--r--include/serial.h2
-rw-r--r--lib/libfdt/Makefile2
-rw-r--r--lib/libfdt/fdt_empty_tree.c84
-rw-r--r--lib/libfdt/fdt_rw.c27
-rw-r--r--nand_spl/board/freescale/mpc8536ds/Makefile9
-rw-r--r--nand_spl/board/freescale/mpc8569mds/Makefile9
-rw-r--r--nand_spl/board/freescale/mpc8572ds/Makefile9
-rw-r--r--nand_spl/board/freescale/mx31pdk/Makefile9
-rw-r--r--nand_spl/board/freescale/mx31pdk/u-boot.lds8
-rw-r--r--nand_spl/board/freescale/p1010rdb/Makefile9
-rw-r--r--nand_spl/board/freescale/p1023rds/Makefile9
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb/Makefile9
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb_pc/Makefile9
-rw-r--r--nand_spl/board/karo/tx25/Makefile9
-rw-r--r--nand_spl/board/karo/tx25/u-boot.lds8
-rw-r--r--nand_spl/board/samsung/smdk6400/u-boot.lds8
-rw-r--r--spl/.gitignore1
-rw-r--r--spl/Makefile8
-rw-r--r--tools/env/fw_env.c130
-rw-r--r--tools/patman/gitutil.py2
-rw-r--r--tools/patman/patchstream.py3
548 files changed, 16352 insertions, 8403 deletions
diff --git a/.gitignore b/.gitignore
index d91e91b1e6..1ac43f2825 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,6 +38,7 @@
/u-boot.sha1
/u-boot.dis
/u-boot.lds
+/u-boot.lst
/u-boot.ubl
/u-boot.ais
/u-boot.dtb
diff --git a/MAINTAINERS b/MAINTAINERS
index c0fff0e40c..1b2da9421a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -214,9 +214,7 @@ Siddarth Gore <gores@marvell.com>
Paul Gortmaker <paul.gortmaker@windriver.com>
sbc8349 MPC8349
- sbc8540 MPC8540
sbc8548 MPC8548
- sbc8560 MPC8560
sbc8641d MPC8641D
Frank Gottschling <fgottschling@eltec.de>
diff --git a/Makefile b/Makefile
index 08eecbbbcd..328347d177 100644
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+ fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
fs/fat/libfat.o \
fs/fdos/libfdos.o \
@@ -533,9 +534,10 @@ GEN_UBOOT = \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
- UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+ UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+ $$UNDEF_LST $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
@@ -568,8 +570,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
-$(obj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
@@ -808,6 +814,7 @@ clean:
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
+ $(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@@ -841,8 +848,10 @@ clobber: tidy
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)u-boot.spr
- @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
- @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+ @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+ @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/README b/README
index df4aed14e4..69da2b86ba 100644
--- a/README
+++ b/README
@@ -363,6 +363,12 @@ The following options need to be configured:
ICache only when Code runs from RAM.
- 85xx CPU Options:
+ CONFIG_SYS_PPC64
+
+ Specifies that the core is a 64-bit PowerPC implementation (implements
+ the "64" category of the Power ISA). This is necessary for ePAPR
+ compliance, among other possible reasons.
+
CONFIG_SYS_FSL_TBCLK_DIV
Defines the core time base clock divider ratio compared to the
@@ -1084,7 +1090,7 @@ The following options need to be configured:
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
- CONFIG_DRIVER_LAN91C96
+ CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
CONFIG_LAN91C96_BASE
@@ -1094,7 +1100,7 @@ The following options need to be configured:
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_DRIVER_SMC91111
+ CONFIG_SMC91111
Support for SMSC's LAN91C111 chip
CONFIG_SMC91111_BASE
@@ -1316,6 +1322,13 @@ The following options need to be configured:
This will also enable the command "fatwrite" enabling the
user to write files to FAT.
+CBFS (Coreboot Filesystem) support
+ CONFIG_CMD_CBFS
+
+ Define this to enable support for reading from a Coreboot
+ filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+ and cbfsload.
+
- Keyboard Support:
CONFIG_ISA_KEYBOARD
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index dc6ba34082..008ae891ca 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -48,9 +48,11 @@ SECTIONS
.got : { *(.got) }
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
__bss_start = .;
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index f8ea38c03d..6dc681a313 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index afd3381e16..f3bd5e7367 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 1d8efb213b..9979c30853 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -47,6 +47,11 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
__image_copy_end = .;
_end = .;
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 7199de4af1..81d954f2de 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -46,9 +46,11 @@ SECTIONS
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c552..227aaff1e6 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -49,9 +49,11 @@ SECTIONS
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c
index 02fe72ed7f..ddc14b099e 100644
--- a/arch/arm/imx-common/cmd_bmode.c
+++ b/arch/arm/imx-common/cmd_bmode.c
@@ -24,6 +24,7 @@
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
+#include <command.h>
static const struct boot_mode *modes[2];
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
int size;
char *dest;
- if (__u_boot_cmd_bmode.usage) {
- free(__u_boot_cmd_bmode.usage);
- __u_boot_cmd_bmode.usage = NULL;
+ cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+ if (entry->usage) {
+ free(entry->usage);
+ entry->usage = NULL;
}
modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
dest = malloc(size);
if (dest) {
create_usage(dest);
- __u_boot_cmd_bmode.usage = dest;
+ entry->usage = dest;
}
}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index f8088fe21a..2b9af93806 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -34,7 +34,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index eac3800729..2ba98bca7d 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -37,7 +37,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 99cb54b8d8..92cad9a6eb 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -57,13 +57,6 @@
#include <miiphy.h>
#endif
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
ulong monitor_flash_len;
@@ -613,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* enable exceptions */
enable_interrupts();
- /* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
- /* XXX: this needs to be moved to board init */
- if (getenv("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- smc_set_mac_addr(enetaddr);
- }
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds
index 0e532f234e..0b16d2a883 100644
--- a/arch/avr32/cpu/u-boot.lds
+++ b/arch/avr32/cpu/u-boot.lds
@@ -47,11 +47,11 @@ SECTIONS
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : {
- KEEP(*(.u_boot_cmd))
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index 7878bb185a..bf661e23be 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -33,7 +33,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 1d2959a2ad..97bbbdef6d 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -23,7 +23,7 @@
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
- unsigned long bi_baudrate;
+ unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 9d3b76e15a..e3287c486b 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -272,8 +272,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds
index 2b8d285e1f..58db838fb0 100644
--- a/arch/blackfin/cpu/u-boot.lds
+++ b/arch/blackfin/cpu/u-boot.lds
@@ -112,11 +112,9 @@ SECTIONS
CONSTRUCTORS
} >ram_data
- .u_boot_cmd :
- {
- ___u_boot_cmd_start = .;
- *(.u_boot_cmd)
- ___u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
} >ram_data
.text_l1 :
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index 290a9e7662..d91e5a40d3 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -41,7 +41,7 @@ typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long board_type;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
index df81183e81..7abd6c2a32 100644
--- a/arch/blackfin/include/asm/u-boot.h
+++ b/arch/blackfin/include/asm/u-boot.h
@@ -29,7 +29,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e47b606e87..9fbbea0d9b 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -78,7 +78,7 @@ static void display_global_data(void)
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-board_type: %lx\n", gd->board_type);
- printf(" |-baudrate: %lu\n", gd->baudrate);
+ printf(" |-baudrate: %u\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index e23b20df91..1928eb384e 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -31,6 +31,7 @@
#include <asm/immap.h>
#include <asm/io.h>
#include <asm/rtc.h>
+#include <linux/compiler.h>
/*
* Breath some life into the CPU...
@@ -41,12 +42,13 @@
*/
void cpu_init_f(void)
{
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- pll_t *pll = (pll_t *)MMAP_PLL;
+ fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_CF_SBF)
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ pll_t *pll = (pll_t *)MMAP_PLL;
+
/* Workaround, must place before fbcs */
out_be32(&pll->psr, 0x12);
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index c5096a80c2..a683778127 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -485,7 +485,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index e6a69ab470..05f17231b2 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -247,7 +247,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index ee17792cb3..f5e55dd965 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -307,7 +307,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index fe98d76474..583ed1d41a 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -261,7 +261,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk
index 61a731eeff..0c48783e4c 100644
--- a/arch/m68k/cpu/mcf5445x/config.mk
+++ b/arch/m68k/cpu/mcf5445x/config.mk
@@ -4,6 +4,8 @@
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
# See file CREDITS for list of people who contributed to this
# project.
#
@@ -24,7 +26,15 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
+PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
+else
PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+endif
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index adfc708c35..b612cdaea1 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -39,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
+ out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
+ udelay(10000);
setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
@@ -74,6 +76,21 @@ int checkcpu(void)
case 0x4f:
id = 54450;
break;
+ case 0x9F:
+ id = 54410;
+ break;
+ case 0xA0:
+ id = 54415;
+ break;
+ case 0xA1:
+ id = 54416;
+ break;
+ case 0xA2:
+ id = 54417;
+ break;
+ case 0xA3:
+ id = 54418;
+ break;
}
if (id) {
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 3f9209ff19..6e947d06f9 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -31,6 +31,7 @@
#include <asm/processor.h>
#include <asm/rtc.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
@@ -38,37 +39,11 @@
#include <asm/fec.h>
#endif
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
{
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
+ fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
- /* FlexBus */
- out_8(&gpio->par_be,
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
- GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
- out_8(&gpio->par_fbctl,
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
- GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
@@ -106,6 +81,145 @@ void cpu_init_f(void)
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+ scm_t *scm = (scm_t *) MMAP_SCM;
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ /* Disable Switch */
+ *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+ /* Disable core watchdog */
+ out_be16(&scm->cwcr, 0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+ GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+ GPIO_PAR_FBCTL_TA_TA);
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+ /* eDMA */
+ out_8(&pm->pmcr0, 17);
+
+ /* INTR0 - INTR2 */
+ out_8(&pm->pmcr0, 18);
+ out_8(&pm->pmcr0, 19);
+ out_8(&pm->pmcr0, 20);
+
+ /* I2C */
+ out_8(&pm->pmcr0, 22);
+ out_8(&pm->pmcr1, 4);
+ out_8(&pm->pmcr1, 7);
+
+ /* DTMR0 - DTMR3*/
+ out_8(&pm->pmcr0, 28);
+ out_8(&pm->pmcr0, 29);
+ out_8(&pm->pmcr0, 30);
+ out_8(&pm->pmcr0, 31);
+
+ /* PIT0 - PIT3 */
+ out_8(&pm->pmcr0, 32);
+ out_8(&pm->pmcr0, 33);
+ out_8(&pm->pmcr0, 34);
+ out_8(&pm->pmcr0, 35);
+
+ /* Edge Port */
+ out_8(&pm->pmcr0, 36);
+ out_8(&pm->pmcr0, 37);
+
+ /* USB OTG */
+ out_8(&pm->pmcr0, 44);
+ /* USB Host */
+ out_8(&pm->pmcr0, 45);
+
+ /* ESDHC */
+ out_8(&pm->pmcr0, 51);
+
+ /* ENET0 - ENET1 */
+ out_8(&pm->pmcr0, 53);
+ out_8(&pm->pmcr0, 54);
+
+ /* NAND */
+ out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+ out_8(&gpio->par_cani2c, 0xF0);
+ /* I2C0 pull up */
+ out_be16(&gpio->pcr_b, 0x003C);
+ /* I2C0 max speed */
+ out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+ /* I2C2 */
+ out_8(&gpio->par_ssi0h, 0xA0);
+ /* I2C2, UART7 */
+ out_8(&gpio->par_ssi0h, 0xA8);
+ /* UART7 */
+ out_8(&gpio->par_ssi0l, 0x2);
+ /* UART8, UART9 */
+ out_8(&gpio->par_cani2c, 0xAA);
+ /* UART4, UART0 */
+ out_8(&gpio->par_uart0, 0xAF);
+ /* UART5, UART1 */
+ out_8(&gpio->par_uart1, 0xAF);
+ /* UART6, UART2 */
+ out_8(&gpio->par_uart2, 0xAF);
+ /* I2C2 pull up */
+ out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+ /* I2C5 */
+ out_8(&gpio->par_uart1, 0x0A);
+ /* I2C5 pull up */
+ out_be16(&gpio->pcr_e, 0x0003);
+ out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+ /* Lowest slew rate for UART0,1,2 */
+ out_8(&gpio->srcr_uart, 0x00);
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+
+ /* FlexBus */
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_FSL_I2C
+ out_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif /* CONFIG_MCF5445x */
+
+ /* FlexBus Chipselect */
+ init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
@@ -115,11 +229,6 @@ void cpu_init_f(void)
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
-#ifdef CONFIG_FSL_I2C
- out_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-
icache_enable();
}
@@ -142,9 +251,95 @@ int cpu_init_r(void)
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+#endif
/* Setup Ports: */
switch (port) {
+#ifdef CONFIG_MCF5441x
+ case 0:
+ /* UART0 */
+ out_8(&pm->pmcr0, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+ break;
+ case 1:
+ /* UART1 */
+ out_8(&pm->pmcr0, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+ break;
+ case 2:
+ /* UART2 */
+ out_8(&pm->pmcr0, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+ break;
+ case 3:
+ /* UART3 */
+ out_8(&pm->pmcr0, 27);
+ clrbits_8(&gpio->par_dspi0,
+ ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+ setbits_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+ break;
+ case 4:
+ /* UART4 */
+ out_8(&pm->pmcr1, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+ break;
+ case 5:
+ /* UART5 */
+ out_8(&pm->pmcr1, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+ break;
+ case 6:
+ /* UART6 */
+ out_8(&pm->pmcr1, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+ break;
+ case 7:
+ /* UART7 */
+ out_8(&pm->pmcr1, 27);
+ clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+ clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+ setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+ setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+ break;
+ case 8:
+ /* UART8 */
+ out_8(&pm->pmcr0, 28);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+ break;
+ case 9:
+ /* UART9 */
+ out_8(&pm->pmcr1, 29);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+ break;
+#endif
+#ifdef CONFIG_MCF5445x
case 0:
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@@ -177,6 +372,7 @@ void uart_port_conf(int port)
GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
+#endif /* CONFIG_MCF5445x */
}
}
@@ -186,6 +382,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
@@ -223,6 +420,21 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
#endif
}
}
+#endif /* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+ if (setclear) {
+ out_8(&gpio->par_fec, 0x03);
+ out_8(&gpio->srcr_fec, 0x0F);
+ clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+ GPIO_PAR_SIMP0H_DAT_GPIO);
+ clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+ GPIO_PDDR_G4_OUTPUT);
+ clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+ } else
+ clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
return 0;
}
#endif
@@ -232,10 +444,24 @@ void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
}
int cfspi_claim_bus(uint bus, uint cs)
@@ -249,6 +475,7 @@ int cfspi_claim_bus(uint bus, uint cs)
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -271,6 +498,20 @@ int cfspi_claim_bus(uint bus, uint cs)
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
+#endif
return 0;
}
@@ -283,6 +524,7 @@ void cfspi_release_bus(uint bus, uint cs)
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -300,5 +542,11 @@ void cfspi_release_bus(uint bus, uint cs)
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ if (cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
}
#endif
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 073b7efafb..55d1c488a3 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -57,8 +57,10 @@ void clock_enter_limp(int lpdiv)
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+#ifdef CONFIG_MCF5445x
/* Apply the divider to the system clock */
clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+#endif
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
@@ -81,19 +83,76 @@ void clock_exit_limp(void)
;
}
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
{
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
+ int temp, vco = 0, bootmod_ccr, pdr;
+
+ bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
+
+ switch (bootmod_ccr) {
+ case 0:
+ out_be32(&pll->pcr, 0x00000013);
+ out_be32(&pll->pdr, 0x00e70c61);
+ clock_exit_limp();
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ }
+
+ /*Change frequency for Modelo SER1 USB host*/
+#ifdef CONFIG_LOW_MCFCLK
+ temp = in_be32(&pll->pcr);
+ temp &= ~0x3f;
+ temp |= 5;
+ out_be32(&pll->pcr, temp);
+
+ temp = in_be32(&pll->pdr);
+ temp &= ~0x001f0000;
+ temp |= 0x00040000;
+ out_be32(&pll->pdr, temp);
+ __asm__("tpf");
+#endif
+ setbits_be16(&ccm->misccr2, 0x02);
+
+ vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
+ CONFIG_SYS_INPUT_CLKSRC;
+ gd->vco_clk = vco;
+
+ gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+
+ pdr = in_be32(&pll->pdr);
+ temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+ gd->cpu_clk = vco / temp; /* cpu clock */
+ gd->flb_clk = vco / temp; /* FlexBus clock */
+ gd->flb_clk >>= 1;
+ if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
+ gd->flb_clk >>= 1;
+
+ temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+ gd->bus_clk = vco / temp; /* bus clock */
+
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco = 0, bPci, temp, fbtemp, pcrvalue;
+ int vco = 0, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
+#ifdef CONFIG_PCI
+ int bPci;
+#endif
#ifdef CONFIG_M54455EVB
u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
@@ -105,14 +164,16 @@ int get_clocks(void)
((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
+#ifdef CONFIG_PCI
bPci = 1;
+#endif
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
-#endif
bPci = 0;
+#endif
}
#ifdef CONFIG_M54455EVB
@@ -215,6 +276,22 @@ int get_clocks(void)
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
+}
+#endif
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+ setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+ setup_5445x_clocks();
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
return (0);
}
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 99060141d8..5fc944d2f3 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -2,6 +2,9 @@
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -21,8 +24,10 @@
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm-offsets.h>
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
@@ -43,8 +48,9 @@
addl #60,%sp; /* space for 15 regs */ \
rte;
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
@@ -55,10 +61,15 @@
* These vectors are to catch any un-intended traps.
*/
_vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
INITSP: .long 0 /* Initial SP */
+#ifdef CONFIG_CF_SBF
INITPC: .long ASM_DRAMINIT /* Initial PC */
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC: .long ASM_DRAMINIT_N /* Initial PC */
+#endif
#else
@@ -95,7 +106,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
/* TRAP #0 - #15 */
vector20_2F:
@@ -138,16 +149,26 @@ vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
- .long 0x00030000 /* image length */
+ .long 0x00040000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.w #0x2700,%sr /* Mask off Interrupt */
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* for assembly stack */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
@@ -180,7 +201,90 @@ asm_dram_init:
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+ /* TC: enable all peripherals,
+ in the future only enable certain peripherals */
+ move.l #0xFC04002D, %a1
+#if defined(CONFIG_CF_SBF)
+ move.b #23, (%a1) /* dspi */
+#endif
+ move.b #46, (%a1) /* DDR */
+
+ /* slew settings */
+ move.l #0xEC094060, %a1
+ move.b #0, (%a1)
+
+ /* use vco instead of cpu*2 clock for ddr clock */
+ move.l #0xEC09001A, %a1
+ move.w #0xE01D, (%a1)
+
+ /* DDR settings */
+ move.l #0xFC0B8180, %a1
+ move.l #0x00000000, (%a1)
+ move.l #0x40000000, (%a1)
+
+ move.l #0xFC0B81AC, %a1
+ move.l #0x01030203, (%a1)
+
+ move.l #0xFC0B8000, %a1
+ move.l #0x01010101, (%a1)+ /* 0x00 */
+ move.l #0x00000101, (%a1)+ /* 0x04 */
+ move.l #0x01010100, (%a1)+ /* 0x08 */
+ move.l #0x01010000, (%a1)+ /* 0x0C */
+ move.l #0x00010101, (%a1)+ /* 0x10 */
+ move.l #0xFC0B8018, %a1
+ move.l #0x00010100, (%a1)+ /* 0x18 */
+ move.l #0x00000001, (%a1)+ /* 0x1C */
+ move.l #0x01000001, (%a1)+ /* 0x20 */
+ move.l #0x00000100, (%a1)+ /* 0x24 */
+ move.l #0x00010001, (%a1)+ /* 0x28 */
+ move.l #0x00000200, (%a1)+ /* 0x2C */
+ move.l #0x01000002, (%a1)+ /* 0x30 */
+ move.l #0x00000000, (%a1)+ /* 0x34 */
+ move.l #0x00000100, (%a1)+ /* 0x38 */
+ move.l #0x02000100, (%a1)+ /* 0x3C */
+ move.l #0x02000407, (%a1)+ /* 0x40 */
+ move.l #0x02030007, (%a1)+ /* 0x44 */
+ move.l #0x02000100, (%a1)+ /* 0x48 */
+ move.l #0x0A030203, (%a1)+ /* 0x4C */
+ move.l #0x00020708, (%a1)+ /* 0x50 */
+ move.l #0x00050008, (%a1)+ /* 0x54 */
+ move.l #0x04030002, (%a1)+ /* 0x58 */
+ move.l #0x00000004, (%a1)+ /* 0x5C */
+ move.l #0x020A0000, (%a1)+ /* 0x60 */
+ move.l #0x0C00000E, (%a1)+ /* 0x64 */
+ move.l #0x00002004, (%a1)+ /* 0x68 */
+ move.l #0x00000000, (%a1)+ /* 0x6C */
+ move.l #0x00100010, (%a1)+ /* 0x70 */
+ move.l #0x00100010, (%a1)+ /* 0x74 */
+ move.l #0x00000000, (%a1)+ /* 0x78 */
+ move.l #0x07990000, (%a1)+ /* 0x7C */
+ move.l #0xFC0B80A0, %a1
+ move.l #0x00000000, (%a1)+ /* 0xA0 */
+ move.l #0x00C80064, (%a1)+ /* 0xA4 */
+ move.l #0x44520002, (%a1)+ /* 0xA8 */
+ move.l #0x00C80023, (%a1)+ /* 0xAC */
+ move.l #0xFC0B80B4, %a1
+ move.l #0x0000C350, (%a1) /* 0xB4 */
+ move.l #0xFC0B80E0, %a1
+ move.l #0x04000000, (%a1)+ /* 0xE0 */
+ move.l #0x03000304, (%a1)+ /* 0xE4 */
+ move.l #0x40040000, (%a1)+ /* 0xE8 */
+ move.l #0xC0004004, (%a1)+ /* 0xEC */
+ move.l #0x0642C000, (%a1)+ /* 0xF0 */
+ move.l #0x00000642, (%a1)+ /* 0xF4 */
+ move.l #0xFC0B8024, %a1
+ tpf
+ move.l #0x01000100, (%a1) /* 0x24 */
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
/* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
@@ -203,7 +307,9 @@ dramsz_loop:
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
-
+#ifdef CONFIG_SYS_NAND_BOOT
+ beq asm_nand_chk_status
+#endif
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
@@ -275,7 +381,9 @@ dramsz_loop:
move.l #2000, %d1
jsr asm_delay
+#endif /* CONFIG_MCF5445x */
+#ifdef CONFIG_CF_SBF
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -286,15 +394,28 @@ dramsz_loop:
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+ move.l #0xEC09404E, %a1
+ move.l #0xEC09404F, %a2
+ move.b #0xFF, (%a1)
+ move.b #0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
-
+#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+ move.l #0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
move.l #0x3E000011, (%a0)
+#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
@@ -379,19 +500,148 @@ asm_dspi_rd_status:
move.b (%a3), %d1
rts
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* copy 4 boot pages to dram as soon as possible */
+ /* each page is 996 bytes (1056 total with 60 ECC bytes */
+ move.l #0x00000000, %a1 /* src */
+ move.l #TEXT_BASE, %a2 /* dst */
+ move.l #0x3E0, %d0 /* sz in long */
+
+asm_boot_nand_copy:
+ move.l (%a1)+, (%a2)+
+ subq.l #1, %d0
+ bne asm_boot_nand_copy
+
+ /* jump to memory and execute */
+ move.l #(asm_nand_init), %a0
+ jmp (%a0)
+
+asm_nand_init:
+ /* exit nand boot-mode */
+ move.l #0xFC0FFF30, %a1
+ or.l #0x00000040, %d1
+ move.l %d1, (%a1)
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CACR_STATUS), %a1 /* CACR */
+ move.l #(ICACHE_STATUS), %a2 /* icache */
+ move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+ move.l %d0, (%a3)
+
+ /* invalidate and disable cache */
+ move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
+ /* Must disable global address */
+ move.l #0xFC008000, %a1
+ move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #0xFC008008, %a1
+ move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #0xFC008004, %a1
+ move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+
+ /* NAND port configuration */
+ move.l #0xEC094048, %a1
+ move.b #0xFD, (%a1)+
+ move.b #0x5F, (%a1)+
+ move.b #0x04, (%a1)+
+
+ /* reset nand */
+ move.l #0xFC0FFF38, %a1 /* isr */
+ move.l #0x000e0000, (%a1)
+ move.l #0xFC0FFF08, %a2
+ move.l #0x00000000, (%a2)+ /* car */
+ move.l #0x11000000, (%a2)+ /* rar */
+ move.l #0x00000000, (%a2)+ /* rpt */
+ move.l #0x00000000, (%a2)+ /* rai */
+ move.l #0xFC0FFF2c, %a2 /* cfg */
+ move.l #0x00000000, (%a2)+ /* secsz */
+ move.l #0x000e0681, (%a2)+
+ move.l #0xFC0FFF04, %a2 /* cmd2 */
+ move.l #0xFF404001, (%a2)
+ move.l #0x000e0000, (%a1)
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+
+ /* setup nand */
+ move.l #0xFC0FFF00, %a1
+ move.l #0x30700000, (%a1)+ /* cmd1 */
+ move.l #0x007EF000, (%a1)+ /* cmd2 */
+
+ move.l #0xFC0FFF2C, %a1
+ move.l #0x00000841, (%a1)+ /* secsz */
+ move.l #0x000e0681, (%a1)+ /* cfg */
+
+ move.l #100, %d4 /* 100 pages ~200KB */
+ move.l #4, %d2 /* start at 4 */
+ move.l #0xFC0FFF04, %a0 /* cmd2 */
+ move.l #0xFC0FFF0C, %a1 /* rar */
+ move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
+
+asm_nand_read:
+ move.l #0x11000000, %d0 /* rar */
+ or.l %d2, %d0
+ move.l %d0, (%a1)
+ add.l #1, %d2
+
+ move.l (%a0), %d0 /* cmd2 */
+ or.l #1, %d0
+ move.l %d0, (%a0)
+
+ move.l #0x200, %d1
+ jsr asm_delay
+
+asm_nand_chk_status:
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ and.l #0x40000000, %d0
+ tst.l %d0
+ beq asm_nand_chk_status
+
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ or.l #0x000E0000, %d0
+ move.l %d0, (%a4)
+
+ move.l #0x200, %d3
+ move.l #0xFC0FC000, %a3 /* buf 1 */
+asm_nand_copy:
+ move.l (%a3)+, (%a2)+
+ subq.l #1, %d3
+ bgt asm_nand_copy
+
+ subq.l #1, %d4
+ bgt asm_nand_read
+
+ /* jump to memory and execute */
+ move.l #(TEXT_BASE + 0x400), %a0
+ jmp (%a0)
+
+#endif /* CONFIG_SYS_NAND_BOOT */
asm_delay:
nop
subq.l #1, %d1
bne asm_delay
rts
-#endif /* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
.text
. = 0x400
.globl _start
_start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
@@ -418,12 +668,15 @@ _start:
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
+#else
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+#endif
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#endif
move.l #__got_start, %a5 /* put relocation table address to a5 */
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index ec65cae3d8..d99747b7fa 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -164,8 +164,8 @@ _start:
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ jbsr cpu_init_f /* run low-level CPU init code (from flash) */
+ jbsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 5c9bb30835..f9e2d15f43 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -1,7 +1,7 @@
/*
* ColdFire cache
*
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -37,10 +37,9 @@
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
-#if defined(CONFIG_MCF5441x)
+#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
-#endif
/* ***** CACR ***** */
/* V2 Core */
@@ -87,7 +86,7 @@
#endif /* CONFIG_CF_V3 */
/* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_CACR_DEC (1 << 31)
#define CF_CACR_DW (1 << 30)
@@ -113,7 +112,7 @@
#define CF_CACR_IDSP (1 << 7)
#define CF_CACR_EUSP (1 << 5)
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
#define CF_CACR_IVO (1 << 20)
#define CF_CACR_SPA (1 << 14)
#else
@@ -148,7 +147,7 @@
#endif /* CONFIG_CF_V2 */
/* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_ACR_AMM (1 << 10)
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index cd55b83c52..0cdb11cf99 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -34,7 +34,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index e83ce08d57..2aab463a90 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -1,7 +1,7 @@
/*
* ColdFire Internal Memory Map and Defines
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -318,6 +318,47 @@
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
+ ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI MMAP_DSPI0
+#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (6)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE (6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS (128)
+
+#endif /* CONFIG_M54418 */
+
#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h
new file mode 100644
index 0000000000..300f4d2868
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5441x.h
@@ -0,0 +1,387 @@
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_CAN0 0xFC020000
+#define MMAP_CAN1 0xFC024000
+#define MMAP_I2C1 0xFC038000
+#define MMAP_DSPI1 0xFC03C000
+#define MMAP_SCM 0xFC040000
+#define MMAP_PM 0xFC04002C
+#define MMAP_EDMA 0xFC044000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_INTC2 0xFC050000
+#define MMAP_IACK 0xFC054000
+#define MMAP_I2C0 0xFC058000
+#define MMAP_DSPI0 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_UART3 0xFC06C000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_EPORT0 0xFC090000
+#define MMAP_ADC 0xFC094000
+#define MMAP_DAC0 0xFC098000
+#define MMAP_DAC1 0xFC09C000
+#define MMAP_RRTC 0xFC0A8000
+#define MMAP_SIM 0xFC0AC000
+#define MMAP_USBOTG 0xFC0B0000
+#define MMAP_USBEHCI 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI0 0xFC0BC000
+#define MMAP_PLL 0xFC0C0000
+#define MMAP_RNG 0xFC0C4000
+#define MMAP_SSI1 0xFC0C8000
+#define MMAP_ESDHC 0xFC0CC000
+#define MMAP_FEC0 0xFC0D4000
+#define MMAP_FEC1 0xFC0D8000
+#define MMAP_L2_SW0 0xFC0DC000
+#define MMAP_L2_SW1 0xFC0E0000
+
+#define MMAP_NFC_RAM 0xFC0FC000
+#define MMAP_NFC 0xFC0FF000
+
+#define MMAP_1WIRE 0xEC008000
+#define MMAP_I2C2 0xEC010000
+#define MMAP_I2C3 0xEC014000
+#define MMAP_I2C4 0xEC018000
+#define MMAP_I2C5 0xEC01C000
+#define MMAP_DSPI2 0xEC038000
+#define MMAP_DSPI3 0xEC03C000
+#define MMAP_UART4 0xEC060000
+#define MMAP_UART5 0xEC064000
+#define MMAP_UART6 0xEC068000
+#define MMAP_UART7 0xEC06C000
+#define MMAP_UART8 0xEC070000
+#define MMAP_UART9 0xEC074000
+#define MMAP_RCM 0xEC090000
+#define MMAP_CCM 0xEC090000
+#define MMAP_GPIO 0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+ u8 resv0[0x18];
+ u16 sbfsr; /* Serial Boot Facility Status */
+ u8 resv1[0x6];
+ u16 sbfcr; /* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+ u8 ccm_resv0[0x4]; /* 0x00 */
+ u16 ccr; /* 0x04 Chip Configuration */
+ u8 resv1[0x2]; /* 0x06 */
+ u16 rcon; /* 0x08 Reset Configuration */
+ u16 cir; /* 0x0A Chip Identification */
+ u8 resv2[0x2]; /* 0x0C */
+ u16 misccr; /* 0x0E Miscellaneous Control */
+ u16 cdrh; /* 0x10 Clock Divider */
+ u16 cdrl; /* 0x12 Clock Divider */
+ u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
+ u16 uhcsr; /* 0x16 */
+ u16 misccr3; /* 0x18 */
+ u16 misccr2; /* 0x1A */
+ u16 adctsr; /* 0x1C */
+ u16 dactsr; /* 0x1E */
+ u16 sbfsr; /* 0x20 */
+ u16 sbfcr; /* 0x22 */
+ u32 fnacr; /* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+ u8 podr_a; /* 0x00 */
+ u8 podr_b; /* 0x01 */
+ u8 podr_c; /* 0x02 */
+ u8 podr_d; /* 0x03 */
+ u8 podr_e; /* 0x04 */
+ u8 podr_f; /* 0x05 */
+ u8 podr_g; /* 0x06 */
+ u8 podr_h; /* 0x07 */
+ u8 podr_i; /* 0x08 */
+ u8 podr_j; /* 0x09 */
+ u8 podr_k; /* 0x0A */
+ u8 rsvd0; /* 0x0B */
+
+ u8 pddr_a; /* 0x0C */
+ u8 pddr_b; /* 0x0D */
+ u8 pddr_c; /* 0x0E */
+ u8 pddr_d; /* 0x0F */
+ u8 pddr_e; /* 0x10 */
+ u8 pddr_f; /* 0x11 */
+ u8 pddr_g; /* 0x12 */
+ u8 pddr_h; /* 0x13 */
+ u8 pddr_i; /* 0x14 */
+ u8 pddr_j; /* 0x15 */
+ u8 pddr_k; /* 0x16 */
+ u8 rsvd1; /* 0x17 */
+
+ u8 ppdsdr_a; /* 0x18 */
+ u8 ppdsdr_b; /* 0x19 */
+ u8 ppdsdr_c; /* 0x1A */
+ u8 ppdsdr_d; /* 0x1B */
+ u8 ppdsdr_e; /* 0x1C */
+ u8 ppdsdr_f; /* 0x1D */
+ u8 ppdsdr_g; /* 0x1E */
+ u8 ppdsdr_h; /* 0x1F */
+ u8 ppdsdr_i; /* 0x20 */
+ u8 ppdsdr_j; /* 0x21 */
+ u8 ppdsdr_k; /* 0x22 */
+ u8 rsvd2; /* 0x23 */
+
+ u8 pclrr_a; /* 0x24 */
+ u8 pclrr_b; /* 0x25 */
+ u8 pclrr_c; /* 0x26 */
+ u8 pclrr_d; /* 0x27 */
+ u8 pclrr_e; /* 0x28 */
+ u8 pclrr_f; /* 0x29 */
+ u8 pclrr_g; /* 0x2A */
+ u8 pclrr_h; /* 0x2B */
+ u8 pclrr_i; /* 0x2C */
+ u8 pclrr_j; /* 0x2D */
+ u8 pclrr_k; /* 0x2E */
+ u8 rsvd3; /* 0x2F */
+
+ u16 pcr_a; /* 0x30 */
+ u16 pcr_b; /* 0x32 */
+ u16 pcr_c; /* 0x34 */
+ u16 pcr_d; /* 0x36 */
+ u16 pcr_e; /* 0x38 */
+ u16 pcr_f; /* 0x3A */
+ u16 pcr_g; /* 0x3C */
+ u16 pcr_h; /* 0x3E */
+ u16 pcr_i; /* 0x40 */
+ u16 pcr_j; /* 0x42 */
+ u16 pcr_k; /* 0x44 */
+ u16 rsvd4; /* 0x46 */
+
+ u8 par_fbctl; /* 0x48 */
+ u8 par_be; /* 0x49 */
+ u8 par_cs; /* 0x4A */
+ u8 par_cani2c; /* 0x4B */
+ u8 par_irqh; /* 0x4C */
+ u8 par_irql; /* 0x4D */
+ u8 par_dspi0; /* 0x4E */
+ u8 par_dspiow; /* 0x4F */
+ u8 par_timer; /* 0x50 */
+ u8 par_uart2; /* 0x51 */
+ u8 par_uart1; /* 0x52 */
+ u8 par_uart0; /* 0x53 */
+ u8 par_sdhch; /* 0x54 */
+ u8 par_sdhcl; /* 0x55 */
+ u8 par_simp0h; /* 0x56 */
+ u8 par_simp1h; /* 0x57 */
+ u8 par_ssi0h; /* 0x58 */
+ u8 par_ssi0l; /* 0x59 */
+ u8 par_dbg1h; /* 0x5A */
+ u8 par_dbg0h; /* 0x5B */
+ u8 par_dbgl; /* 0x5C */
+ u8 rsvd5; /* 0x5D */
+ u8 par_fec; /* 0x5E */
+ u8 rsvd6; /* 0x5F */
+
+ u8 mscr_sdram; /* 0x60 */
+ u8 rsvd7[3]; /* 0x61-0x63 */
+
+ u8 srcr_fb1; /* 0x64 */
+ u8 srcr_fb2; /* 0x65 */
+ u8 srcr_fb3; /* 0x66 */
+ u8 srcr_fb4; /* 0x67 */
+ u8 srcr_dspiow; /* 0x68 */
+ u8 srcr_cani2c; /* 0x69 */
+ u8 srcr_irq; /* 0x6A */
+ u8 srcr_timer; /* 0x6B */
+ u8 srcr_uart; /* 0x6C */
+ u8 srcr_fec; /* 0x6D */
+ u8 srcr_sdhc; /* 0x6E */
+ u8 srcr_simp0; /* 0x6F */
+ u8 srcr_ssi0; /* 0x70 */
+ u8 rsvd8[3]; /* 0x71-0x73 */
+
+ u16 urts_pol; /* 0x74 */
+ u16 ucts_pol; /* 0x76 */
+ u16 utxd_wom; /* 0x78 */
+ u32 urxd_wom; /* 0x7c */
+
+ u32 hcr1; /* 0x80 */
+ u32 hcr0; /* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+ u32 cr00; /* 0x00 */
+ u32 cr01; /* 0x04 */
+ u32 cr02; /* 0x08 */
+ u32 cr03; /* 0x0C */
+ u32 cr04; /* 0x10 */
+ u32 cr05; /* 0x14 */
+ u32 cr06; /* 0x18 */
+ u32 cr07; /* 0x1C */
+
+ u32 cr08; /* 0x20 */
+ u32 cr09; /* 0x24 */
+ u32 cr10; /* 0x28 */
+ u32 cr11; /* 0x2C */
+ u32 cr12; /* 0x30 */
+ u32 cr13; /* 0x34 */
+ u32 cr14; /* 0x38 */
+ u32 cr15; /* 0x3C */
+
+ u32 cr16; /* 0x40 */
+ u32 cr17; /* 0x44 */
+ u32 cr18; /* 0x48 */
+ u32 cr19; /* 0x4C */
+ u32 cr20; /* 0x50 */
+ u32 cr21; /* 0x54 */
+ u32 cr22; /* 0x58 */
+ u32 cr23; /* 0x5C */
+
+ u32 cr24; /* 0x60 */
+ u32 cr25; /* 0x64 */
+ u32 cr26; /* 0x68 */
+ u32 cr27; /* 0x6C */
+ u32 cr28; /* 0x70 */
+ u32 cr29; /* 0x74 */
+ u32 cr30; /* 0x78 */
+ u32 cr31; /* 0x7C */
+
+ u32 cr32; /* 0x80 */
+ u32 cr33; /* 0x84 */
+ u32 cr34; /* 0x88 */
+ u32 cr35; /* 0x8C */
+ u32 cr36; /* 0x90 */
+ u32 cr37; /* 0x94 */
+ u32 cr38; /* 0x98 */
+ u32 cr39; /* 0x9C */
+
+ u32 cr40; /* 0xA0 */
+ u32 cr41; /* 0xA4 */
+ u32 cr42; /* 0xA8 */
+ u32 cr43; /* 0xAC */
+ u32 cr44; /* 0xB0 */
+ u32 cr45; /* 0xB4 */
+ u32 cr46; /* 0xB8 */
+ u32 cr47; /* 0xBC */
+ u32 cr48; /* 0xC0 */
+ u32 cr49; /* 0xC4 */
+ u32 cr50; /* 0xC8 */
+ u32 cr51; /* 0xCC */
+ u32 cr52; /* 0xD0 */
+ u32 cr53; /* 0xD4 */
+ u32 cr54; /* 0xD8 */
+ u32 cr55; /* 0xDC */
+ u32 cr56; /* 0xE0 */
+ u32 cr57; /* 0xE4 */
+ u32 cr58; /* 0xE8 */
+ u32 cr59; /* 0xEC */
+ u32 cr60; /* 0xF0 */
+ u32 cr61; /* 0xF4 */
+ u32 cr62; /* 0xF8 */
+ u32 cr63; /* 0xFC */
+
+ u32 rsvd3[32]; /* 0xF4-0x1A8 */
+
+ u32 rcrcr; /* 0x180 */
+ u32 swrcr; /* 0x184 */
+ u32 rcr; /* 0x188 */
+ u32 msovr; /* 0x18C */
+ u32 rcrdbg; /* 0x190 */
+ u32 sl0adj; /* 0x194 */
+ u32 sl1adj; /* 0x198 */
+ u32 sl2adj; /* 0x19C */
+ u32 sl3adj; /* 0x1A0 */
+ u32 sl4adj; /* 0x1A4 */
+ u32 flight_tm; /* 0x1A8 */
+ u32 padcr; /* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+ u32 pcr; /* Control */
+ u32 pdr; /* Divider */
+ u32 psr; /* Status */
+} pll_t;
+
+typedef struct scm {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u32 rsvd5; /* 0x20 - 0x23 */
+ u32 bcr; /* 0x24 */
+ u8 rsvd6[72]; /* 0x28 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm_t;
+
+typedef struct pm {
+ u8 pmsr0; /* */
+ u8 pmcr0;
+ u8 pmsr1;
+ u8 pmcr1;
+ u32 pmhr0;
+ u32 pmlr0;
+ u32 pmhr1;
+ u32 pmlr1;
+} pm_t;
+
+#endif /* __IMMAP_5441X__ */
diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h
new file mode 100644
index 0000000000..f5c82d4b56
--- /dev/null
+++ b/arch/m68k/include/asm/m5441x.h
@@ -0,0 +1,887 @@
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_UART3 (29)
+#define INT0_LO_I2C0 (30)
+#define INT0_LO_DSPI0 (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_MACNET0_TXF (36)
+#define INT0_HI_MACNET0_TXB (37)
+#define INT0_HI_MACNET0_UN (38)
+#define INT0_HI_MACNET0_RL (39)
+#define INT0_HI_MACNET0_RXF (40)
+#define INT0_HI_MACNET0_RXB (41)
+#define INT0_HI_MACNET0_MII (42)
+#define INT0_HI_MACNET0_LC (43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA (45)
+#define INT0_HI_MACNET0_EBERR (46)
+#define INT0_HI_MACNET0_BABT (47)
+#define INT0_HI_MACNET0_BABR (48)
+#define INT0_HI_MACNET1_TXF (49)
+#define INT0_HI_MACNET1_TXB (50)
+#define INT0_HI_MACNET1_UN (51)
+#define INT0_HI_MACNET1_RL (52)
+#define INT0_HI_MACNET1_RXF (53)
+#define INT0_HI_MACNET1_RXB (54)
+#define INT0_HI_MACNET1_MII (55)
+#define INT0_HI_MACNET1_LC (56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA (58)
+#define INT0_HI_MACNET1_EBERR (59)
+#define INT0_HI_MACNET1_BABT (60)
+#define INT0_HI_MACNET1_BABR (61)
+#define INT0_HI_SCMIR (62)
+#define INT0_HI_OW (63)
+
+#define INT1_LO_CAN0_IFG (0)
+#define INT1_LO_CAN0_BOFF (1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN (3)
+#define INT1_LO_CAN1_IFG (4)
+#define INT1_LO_CAN1_BOFF (5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN (7)
+#define INT1_LO_EDMA_16 (8)
+#define INT1_LO_EDMA_17 (9)
+#define INT1_LO_EDMA_18 (10)
+#define INT1_LO_EDMA_19 (11)
+#define INT1_LO_EDMA_20 (12)
+#define INT1_LO_EDMA_21 (13)
+#define INT1_LO_EDMA_22 (14)
+#define INT1_LO_EDMA_23 (15)
+#define INT1_LO_EDMA_24 (16)
+#define INT1_LO_EDMA_25 (17)
+#define INT1_LO_EDMA_26 (18)
+#define INT1_LO_EDMA_27 (19)
+#define INT1_LO_EDMA_28 (20)
+#define INT1_LO_EDMA_29 (21)
+#define INT1_LO_EDMA_30 (22)
+#define INT1_LO_EDMA_31 (23)
+#define INT1_LO_EDMA_32 (24)
+#define INT1_LO_EDMA_33 (25)
+#define INT1_LO_EDMA_34 (26)
+#define INT1_LO_EDMA_35 (27)
+#define INT1_LO_EDMA_36 (28)
+#define INT1_LO_EDMA_37 (29)
+#define INT1_LO_EDMA_38 (30)
+#define INT1_LO_EDMA_39 (31)
+#define INT1_LO_EDMA_40 (32)
+#define INT1_HI_EDMA_41 (33)
+#define INT1_HI_EDMA_42 (34)
+#define INT1_HI_EDMA_43 (35)
+#define INT1_HI_EDMA_44 (36)
+#define INT1_HI_EDMA_45 (37)
+#define INT1_HI_EDMA_46 (38)
+#define INT1_HI_EDMA_47 (39)
+#define INT1_HI_EDMA_48 (40)
+#define INT1_HI_EDMA_49 (41)
+#define INT1_HI_EDMA_50 (42)
+#define INT1_HI_EDMA_51 (43)
+#define INT1_HI_EDMA_52 (44)
+#define INT1_HI_EDMA_53 (45)
+#define INT1_HI_EDMA_54 (46)
+#define INT1_HI_EDMA_55 (47)
+#define INT1_HI_UART4 (48)
+#define INT1_HI_UART5 (49)
+#define INT1_HI_UART6 (50)
+#define INT1_HI_UART7 (51)
+#define INT1_HI_UART8 (52)
+#define INT1_HI_UART9 (53)
+#define INT1_HI_DSPI1 (54)
+#define INT1_HI_DSPI2 (55)
+#define INT1_HI_DSPI3 (56)
+#define INT1_HI_I2C1 (57)
+#define INT1_HI_I2C2 (58)
+#define INT1_HI_I2C3 (59)
+#define INT1_HI_I2C4 (60)
+#define INT1_HI_I2C5 (61)
+
+#define INT2_LO_EDMA56_63 (0)
+#define INT2_LO_PWM_SM0SR_CF (1)
+#define INT2_LO_PWM_SM1SR_CF (2)
+#define INT2_LO_PWM_SM2SR_CF (3)
+#define INT2_LO_PWM_SM3SR_CF (4)
+#define INT2_LO_PWM_SM0SR_RF (5)
+#define INT2_LO_PWM_SM1SR_RF (6)
+#define INT2_LO_PWM_SM2SR_RF (7)
+#define INT2_LO_PWM_SM3SR_RF (8)
+#define INT2_LO_PWM_FSR (9)
+#define INT2_LO_PWM_SMSR_REF (10)
+#define INT2_LO_PLL_SR_LOCF (11)
+#define INT2_LO_PLL_SR_LOLF (12)
+#define INT2_LO_PIT0_PIF (13)
+#define INT2_LO_PIT1_PIF (14)
+#define INT2_LO_PIT2_PIF (15)
+#define INT2_LO_PIT3_PIF (16)
+#define INT2_LO_USBOTG_USBSTS (17)
+#define INT2_LO_USBH_USBSTS (18)
+/* not used 19-20 */
+#define INT2_LO_SSI0 (21)
+#define INT2_LO_SSI1 (22)
+#define INT2_LO_NFC (23)
+/* not used 24-25 */
+#define INT2_LO_RTC (26)
+#define INT2_LO_CCM_UOCSR (27)
+#define INT2_LO_RNG_EI (28)
+#define INT2_LO_SIM1_DATA (29)
+#define INT2_LO_SIM1 (30)
+#define INT2_LO_SDHC (31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR (38)
+#define INT2_HI_L2SW_RXB (39)
+#define INT2_HI_L2SW_RXF (40)
+#define INT2_HI_L2SW_TXB (41)
+#define INT2_HI_L2SW_TXF (42)
+#define INT2_HI_L2SW_QM (43)
+#define INT2_HI_L2SW_OD0 (44)
+#define INT2_HI_L2SW_OD1 (45)
+#define INT2_HI_L2SW_OD2 (46)
+#define INT2_HI_L2SW_LRN (47)
+#define INT2_HI_MACNET0_TS (48)
+#define INT2_HI_MACNET0_WAKE (49)
+#define INT2_HI_MACNET0_PLR (50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS (51)
+#define INT2_HI_MACNET1_WAKE (52)
+#define INT2_HI_MACNET1_PLR (53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
+#define SBF_SBFCR_FR (0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST (0x80)
+#define RCM_RCR_FRCRSTOUT (0x40)
+
+#define RCM_RSR_SOFT (0x20)
+#define RCM_RSR_LOC (0x10)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_LOL (0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD (0xC000)
+#define CCM_CCR_PLLMULT (0x0FC0)
+#define CCM_CCR_BOOTPS (0x0030)
+#define CCM_CCR_BOOTPS_32 (0x0000)
+#define CCM_CCR_BOOTPS_16 (0x0020)
+#define CCM_CCR_BOOTPS_8 (0x0010)
+#define CCM_CCR_BOOTPS_ (0x0000)
+#define CCM_CCR_ALESEL (0x0008)
+#define CCM_CCR_OSCMOD (0x0004)
+#define CCM_CCR_PLLMOD (0x0002)
+#define CCM_CCR_BOOTMEM (0x0001)
+
+#define CCM_CIR_PIN_MASK (0xFFC0)
+#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN_MCF54410 (0x9F<<6)
+#define CCM_CIR_PIN_MCF54415 (0xA0<<6)
+#define CCM_CIR_PIN_MCF54416 (0xA1<<6)
+#define CCM_CIR_PIN_MCF54417 (0xA2<<6)
+#define CCM_CIR_PIN_MCF54418 (0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_BME (0x0800)
+#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536 (0)
+#define CCM_MISCCR_BMT_32768 (1)
+#define CCM_MISCCR_BMT_16384 (2)
+#define CCM_MISCCR_BMT_8192 (3)
+#define CCM_MISCCR_BMT_4096 (4)
+#define CCM_MISCCR_BMT_2048 (5)
+#define CCM_MISCCR_BMT_1024 (6)
+#define CCM_MISCCR_BMT_512 (7)
+#define CCM_MISCCR_SDHCSRC (0x0040)
+#define CCM_MISCCR_SSI1SRC (0x0020)
+#define CCM_MISCCR_SSI0SRC (0x0010)
+#define CCM_MISCCR_USBHOC (0x0008)
+#define CCM_MISCCR_USBOOC (0x0004)
+#define CCM_MISCCR_USBPUE (0x0002)
+#define CCM_MISCCR_USBSRC (0x0001)
+
+#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK (0x00FF)
+#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK (0xFF00)
+#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK (0xFF0F)
+#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+#define CCM_UHCSR_DRV_VBUS (0x0010)
+#define CCM_UHCSR_PWRFLT (0x0008)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UOMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+#define CCM_MISCCR3_TMR_ENET (0x1000)
+#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII (0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC (0x0600)
+#define CCM_MISCCR3_ENETCLK_USB (0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP (0x8000)
+#define CCM_MISCCR2_DDR2CLK (0x4000)
+#define CCM_MISCCR2_RGPIO_HALF (0x2000)
+#define CCM_MISCCR2_SWTSCR (0x1000)
+#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
+#define CCM_MISCCR2_DCCBYP (0x0080)
+#define CCM_MISCCR2_DAC1SEL (0x0040)
+#define CCM_MISCCR2_DAC0SEL (0x0020)
+#define CCM_MISCCR2_ADCEN (0x0010)
+#define CCM_MISCCR2_ADC7SEL (0x0008)
+#define CCM_MISCCR2_ADC3SEL (0x0004)
+#define CCM_MISCCR2_FBHALF (0x0002)
+#define CCM_MISCCR2_ULPI (0x0001)
+
+#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
+#define CCM_FNACR_MCC(x) ((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK (0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK (0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_FBCLK (0x08)
+#define GPIO_PAR_FBCTL_RW (0x04)
+#define GPIO_PAR_FBCTL_TA(x) ((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TA_TA (0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
+
+#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define GPIO_PAR_BE_BE3_CS3 (0x80)
+#define GPIO_PAR_BE_BE3_FB_A1 (0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
+#define GPIO_PAR_BE_BE3_GPIO (0x00)
+#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_BE2 (0x30)
+#define GPIO_PAR_BE_BE2_CS2 (0x20)
+#define GPIO_PAR_BE_BE2_FB_A0 (0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
+#define GPIO_PAR_BE_BE2_GPIO (0x00)
+#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK (0xF3)
+#define GPIO_PAR_BE_BE1_BE1 (0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
+#define GPIO_PAR_BE_BE1_GPIO (0x00)
+#define GPIO_PAR_BE_BS0(x) ((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK (0xFC)
+#define GPIO_PAR_BE_BE0_BE0 (0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
+#define GPIO_PAR_BE_BE0_GPIO (0x00)
+
+#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK (0x3F)
+#define GPIO_PAR_CS_CS5_CS5 (0xC0)
+#define GPIO_PAR_CS_CS5_DACK1 (0x80)
+#define GPIO_PAR_CS_CS5_GPIO (0x00)
+#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK (0xCF)
+#define GPIO_PAR_CS_CS4_CS4 (0x30)
+#define GPIO_PAR_CS_CS4_DREQ1 (0x20)
+#define GPIO_PAR_CS_CS4_GPIO (0x00)
+#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK (0xF3)
+#define GPIO_PAR_CS_CS1_CS1 (0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE (0x04)
+#define GPIO_PAR_CS_CS1_GPIO (0x00)
+#define GPIO_PAR_CS_CS0_CS0 (0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
+
+#define GPIO_PAR_IRQH_IRQ7 (0x10)
+#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
+#define GPIO_PAR_IRQH_IRQ1 (0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
+#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS (0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS (0x80)
+#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
+#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
+#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
+#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
+#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK (0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST (0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD (0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD (0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK (0xF3)
+#define GPIO_PAR_SSI0H_FS_FS (0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO (0x00)
+#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3 (0x40)
+#define GPIO_PAR_DEBUGH1_DAT2 (0x10)
+#define GPIO_PAR_DEBUGH1_DAT1 (0x04)
+#define GPIO_PAR_DEBUGH1_DAT0 (0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3 (0x40)
+#define GPIO_PAR_DEBUGH0_PST2 (0x10)
+#define GPIO_PAR_DEBUGH0_PST1 (0x04)
+#define GPIO_PAR_DEBUGH0_PST0 (0x01)
+
+#define GPIO_PODR_G4_VAL (0x01 << 4)
+#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
+#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST (0x01)
+
+#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK (0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO (0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0 (0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
+#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK (0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK (0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK (0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK (0xF3)
+#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK (0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
+
+#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK (0xCF)
+#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK (0xF3)
+#define GPIO_SRCR_UART_U0(x) ((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK (0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
+#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
+
+#define GPIO_PCR_URTS_U2 (0x0004)
+#define GPIO_PCR_URTS_U1 (0x0002)
+#define GPIO_PCR_URTS_U0 (0x0001)
+
+#define GPIO_PCR_UCTS_U2 (0x0004)
+#define GPIO_PCR_UCTS_U1 (0x0002)
+#define GPIO_PCR_UCTS_U0 (0x0001)
+
+#define GPIO_UTXD_WOM_U9 (0x0200)
+#define GPIO_UTXD_WOM_U8 (0x0100)
+#define GPIO_UTXD_WOM_U7 (0x0080)
+#define GPIO_UTXD_WOM_U6 (0x0040)
+#define GPIO_UTXD_WOM_U5 (0x0020)
+#define GPIO_UTXD_WOM_U4 (0x0010)
+#define GPIO_UTXD_WOM_U3 (0x0008)
+#define GPIO_UTXD_WOM_U2 (0x0004)
+#define GPIO_UTXD_WOM_U1 (0x0002)
+#define GPIO_UTXD_WOM_U0 (0x0001)
+
+#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x) ((x)&3)
+#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x) ((x)&7)
+#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3 (0x00000400)
+#define GPIO_HCR0_PK0 (0x00000200)
+#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
+#define GPIO_HCR0_PE7 (0x00000020)
+#define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ (0x00040000)
+#define PLL_CR_LOCRE (0x00020000)
+#define PLL_CR_LOCEN (0x00010000)
+#define PLL_CR_LOLIRQ (0x00004000)
+#define PLL_CR_LOLRE (0x00002000)
+#define PLL_CR_LOLEN (0x00001000)
+#define PLL_CR_REFDIV(x) (((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x) ((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS (0x3F)
+
+#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS (0x03E00000)
+#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS (0x001F0000)
+#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS (0x00007C00)
+#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS (0x000003E0)
+#define PLL_DR_OUTDIV1(x) ((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS (0x0000001F)
+
+#define PLL_SR_LOCF (0x00000200)
+#define PLL_SR_LOC (0x00000100)
+#define PLL_SR_LOLF (0x00000040)
+#define PLL_SR_LOCKS (0x00000020)
+#define PLL_SR_LOCK (0x00000010)
+#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
+#define PLL_SR_MODE(x) ((x)&7)
+#define PLL_SR_MODE_MASK (0xFFFFFFF8)
+
+#endif /* __MCF5441X__ */
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 973c9ee098..8c7c554a46 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -58,7 +58,7 @@ typedef struct bd_info {
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index 67c9a1382e..02d73fda61 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -29,6 +29,7 @@
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
+#include <linux/compiler.h>
#include <asm/immap.h>
@@ -387,7 +388,7 @@ board_init_f (ulong bootflag)
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- char *s;
+ char *s __maybe_unused;
bd_t *bd;
#ifndef CONFIG_ENV_IS_NOWHERE
@@ -415,8 +416,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index d033a2835b..4297b93443 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -50,12 +50,9 @@ SECTIONS
__data_end = .;
}
- .u_boot_cmd ALIGN(0x4):
- {
- . = .;
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
.bss ALIGN(0x4):
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index de3b8dbe92..2111c7cba2 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -35,7 +35,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
index a0b1dbf9e6..8d00658564 100644
--- a/arch/microblaze/include/asm/u-boot.h
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -40,7 +40,7 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile
index dc58475f68..b9f895df5b 100644
--- a/arch/mips/cpu/mips32/au1x00/Makefile
+++ b/arch/mips/cpu/mips32/au1x00/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/bmw/m48t59y.h b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
index 717300d957..932cdfb9bb 100644
--- a/board/bmw/m48t59y.h
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
@@ -1,13 +1,7 @@
/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
+ * (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,33 +19,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-#ifndef __M48_T59_Y_H
-#define __M48_T59_Y_H
-
-/*
- * M48 T59Y -Timekeeping Battery backed SRAM.
- */
-
-int m48_tod_init(void);
-
-int m48_tod_set(int year,
- int month,
- int day,
- int hour,
- int minute,
- int second);
-
-int m48_tod_get(int *year,
- int *month,
- int *day,
- int *hour,
- int *minute,
- int *second);
-
-int m48_tod_get_second(void);
-
-void m48_watchdog_arm(int usec);
+#include <common.h>
+#include <ide.h>
-#endif /*!__M48_T59_Y_H */
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ ide_input_data(dev, sect_buf, words);
+}
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
index 0beac98fde..3e85b90cde 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
@@ -103,12 +103,6 @@ static void au1x00_serial_putc(const char c)
*uart_tx = (u32)c;
}
-static void au1x00_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static int au1x00_serial_getc(void)
{
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
@@ -137,7 +131,7 @@ static struct serial_device au1x00_serial_drv = {
.stop = NULL,
.setbrg = au1x00_serial_setbrg,
.putc = au1x00_serial_putc,
- .puts = au1x00_serial_puts,
+ .puts = default_serial_puts,
.getc = au1x00_serial_getc,
.tstc = au1x00_serial_tstc,
};
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8be8c..64dfad0263 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_op Fill t0
+2: cache_op FILL t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b612..50bb248bd0 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c
index 08949f4fb0..6f0e4f2520 100644
--- a/arch/mips/cpu/mips32/incaip/asc_serial.c
+++ b/arch/mips/cpu/mips32/incaip/asc_serial.c
@@ -236,14 +236,6 @@ static void asc_serial_putc(const char c)
}
}
-static void asc_serial_puts(const char *s)
-{
- while (*s)
- {
- serial_putc (*s++);
- }
-}
-
static int asc_serial_getc(void)
{
ulong symbol_mask;
@@ -292,7 +284,7 @@ static struct serial_device asc_serial_drv = {
.stop = NULL,
.setbrg = asc_serial_setbrg,
.putc = asc_serial_putc,
- .puts = asc_serial_puts,
+ .puts = default_serial_puts,
.getc = asc_serial_getc,
.tstc = asc_serial_tstc,
};
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
new file mode 100644
index 0000000000..be38664844
--- /dev/null
+++ b/arch/mips/cpu/mips64/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS-y = cpu.o interrupts.o time.o cache.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
new file mode 100644
index 0000000000..036f035d96
--- /dev/null
+++ b/arch/mips/cpu/mips64/cache.S
@@ -0,0 +1,229 @@
+/*
+ * Cache-handling routined for MIPS CPUs
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x10000
+
+#define INDEX_BASE CKSEG0
+
+ .macro cache_op op addr
+ .set push
+ .set noreorder
+ .set mips3
+ cache \op, 0(\addr)
+ .set pop
+ .endm
+
+ .macro f_fill64 dst, offset, val
+ LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+ LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+ .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear tag to invalidate */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* fill once, so data field parity is correct */
+ PTR_LI t0, INDEX_BASE
+2: cache_op FILL t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* invalidate again - prudent but not strictly neccessary */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* load from each line (in cached space) */
+ PTR_LI t0, INDEX_BASE
+2: LONG_L zero, 0(t0)
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+ move RA, ra
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
+
+ li v0, MIPS_MAX_CACHE_SIZE
+
+ /*
+ * Now clear that much memory starting from zero.
+ */
+ PTR_LI a0, CKSEG1
+ PTR_ADDU a1, a0, v0
+2: PTR_ADDIU a0, 64
+ f_fill64 a0, -64, zero
+ bne a0, a1, 2b
+
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
+
+ /*
+ * Assume bottom of RAM will generate good parity for the cache.
+ */
+
+ /*
+ * Initialize the I-cache first,
+ */
+ move a1, t2
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
+
+ /*
+ * then initialize D-cache.
+ */
+ move a1, t3
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
+
+ jr RA
+ END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+ mfc0 t0, CP0_CONFIG
+ li t1, CONF_CM_UNCACHED
+ andi t0, t0, CONF_CM_CMASK
+ move v0, zero
+ beq t0, t1, 2f
+ li v0, 1
+2: jr ra
+ END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+ mfc0 t0, CP0_CONFIG
+ li t1, -8
+ and t0, t0, t1
+ ori t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_enable)
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
new file mode 100644
index 0000000000..ebc1ceb83b
--- /dev/null
+++ b/arch/mips/cpu/mips64/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf64btsmip
+else
+PLATFORM_LDFLAGS += -m elf64ltsmip
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 0000000000..2a38d0c8d0
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr) \
+ __asm__ __volatile__( \
+ " .set push\n" \
+ " .set noreorder\n" \
+ " .set mips64\n" \
+ " cache %0, %1\n" \
+ " .set pop\n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+ fprintf(stderr, "*** reset failed ***\n");
+
+ while (1)
+ /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_INVALIDATE_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 0000000000..e4e9aae0ca
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644
index 0000000000..4112de7026
--- /dev/null
+++ b/arch/mips/cpu/mips64/start.S
@@ -0,0 +1,256 @@
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ dli t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches... */
+ dla t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ dli t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ dli t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ dli t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 0000000000..51542808dd
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY \
+ (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa47c..cc190dfe56 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
__asm__ __volatile__("sync");
diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c
index 3199007757..a147657350 100644
--- a/arch/mips/cpu/xburst/jz_serial.c
+++ b/arch/mips/cpu/xburst/jz_serial.c
@@ -109,19 +109,13 @@ static int jz_serial_getc(void)
return readb(&uart->rbr_thr_dllr);
}
-static void jz_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static struct serial_device jz_serial_drv = {
.name = "jz_serial",
.start = jz_serial_init,
.stop = NULL,
.setbrg = jz_serial_setbrg,
.putc = jz_serial_putc,
- .puts = jz_serial_puts,
+ .puts = default_serial_puts,
.getc = jz_serial_getc,
.tstc = jz_serial_tstc,
};
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104d10..3a8280cb0a 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
- cache Index_Writeback_Inv_D, 0(t0)
+ cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
@@ -106,7 +106,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
- cache Index_Invalidate_I, 0(t0)
+ cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3a1e6d615f..b768bb5081 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcfbb3..933ccb1b78 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol = value
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else
#define R10KCBARRIER(addr)
#endif
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 70bcad7694..6464250d84 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,54 +14,54 @@
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
+#define INDEX_INVALIDATE_I 0x00
+#define INDEX_WRITEBACK_INV_D 0x01
+#define INDEX_LOAD_TAG_I 0x04
+#define INDEX_LOAD_TAG_D 0x05
+#define INDEX_STORE_TAG_I 0x08
+#define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
+#define HIT_INVALIDATE_I 0x00
#else
-#define Hit_Invalidate_I 0x10
+#define HIT_INVALIDATE_I 0x10
#endif
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
+#define HIT_INVALIDATE_D 0x11
+#define HIT_WRITEBACK_INV_D 0x15
/*
* R4000-specific cacheops
*/
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
+#define CREATE_DIRTY_EXCL_D 0x0d
+#define FILL 0x14
+#define HIT_WRITEBACK_I 0x18
+#define HIT_WRITEBACK_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
+#define INDEX_INVALIDATE_SI 0x02
+#define INDEX_WRITEBACK_INV_SD 0x03
+#define INDEX_LOAD_TAG_SI 0x06
+#define INDEX_LOAD_TAG_SD 0x07
+#define INDEX_STORE_TAG_SI 0x0A
+#define INDEX_STORE_TAG_SD 0x0B
+#define CREATE_DIRTY_EXCL_SD 0x0f
+#define HIT_INVALIDATE_SI 0x12
+#define HIT_INVALIDATE_SD 0x13
+#define HIT_WRITEBACK_INV_SD 0x17
+#define HIT_WRITEBACK_SD 0x1b
+#define HIT_SET_VIRTUAL_SI 0x1e
+#define HIT_SET_VIRTUAL_SD 0x1f
/*
* R5000-specific cacheops
*/
-#define R5K_Page_Invalidate_S 0x17
+#define R5K_PAGE_INVALIDATE_S 0x17
/*
* RM7000-specific cacheops
*/
-#define Page_Invalidate_T 0x16
+#define PAGE_INVALIDATE_T 0x16
/*
* R10000-specific cacheops
@@ -69,17 +69,17 @@
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
+#define INDEX_WRITEBACK_INV_S 0x03
+#define INDEX_LOAD_TAG_S 0x07
+#define INDEX_STORE_TAG_S 0x0B
+#define HIT_INVALIDATE_S 0x13
+#define CACHE_BARRIER 0x14
+#define HIT_WRITEBACK_INV_S 0x17
+#define INDEX_LOAD_DATA_I 0x18
+#define INDEX_LOAD_DATA_D 0x19
+#define INDEX_LOAD_DATA_S 0x1b
+#define INDEX_STORE_DATA_I 0x1c
+#define INDEX_STORE_DATA_D 0x1d
+#define INDEX_STORE_DATA_S 0x1f
#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 6e2cdc72cf..a735a8a2c7 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -48,7 +48,7 @@ typedef struct global_data {
unsigned long tbl;
unsigned long lastinc;
#endif
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012ae60..80eab75e15 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 879aae210b..4deac5207a 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
+#if _MIPS_SZLONG != 64
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 590649aa3e..5fa4a6a730 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -32,7 +32,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index b14b33efcd..7ddd77832c 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -266,8 +266,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
index 190342062a..cef19c51ee 100644
--- a/arch/nds32/cpu/n1213/u-boot.lds
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -52,9 +52,11 @@ SECTIONS
}
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
index 94bd4c2722..b1feb2c0d0 100644
--- a/arch/nds32/include/asm/global_data.h
+++ b/arch/nds32/include/asm/global_data.h
@@ -44,7 +44,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
index b533fea7c5..7b8d8e48fb 100644
--- a/arch/nds32/include/asm/u-boot.h
+++ b/arch/nds32/include/asm/u-boot.h
@@ -39,7 +39,7 @@
#include <environment.h>
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 89900fea43..91395cabf3 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -320,8 +320,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
serial_initialize();
@@ -396,7 +396,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds
index 4856bd368d..d0eb80de0e 100644
--- a/arch/nios2/cpu/u-boot.lds
+++ b/arch/nios2/cpu/u-boot.lds
@@ -45,13 +45,11 @@ SECTIONS
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index 3b0d9e6294..413b485b61 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -26,7 +26,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h
index 315ef8bedb..e591237634 100644
--- a/arch/nios2/include/asm/u-boot.h
+++ b/arch/nios2/include/asm/u-boot.h
@@ -39,7 +39,7 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h
index 6a0c0cc547..96f3f1cdbb 100644
--- a/arch/openrisc/include/asm/global_data.h
+++ b/arch/openrisc/include/asm/global_data.h
@@ -35,7 +35,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h
index 76b813273f..f2f31d3bb4 100644
--- a/arch/openrisc/include/asm/u-boot.h
+++ b/arch/openrisc/include/asm/u-boot.h
@@ -32,7 +32,7 @@
#define _U_BOOT_H_
typedef struct bd_info {
- unsigned long bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
index 24823cd20f..ecee439579 100644
--- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds
+++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
@@ -62,9 +62,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
index 7a4d9270df..7faefba555 100644
--- a/arch/powerpc/cpu/mpc512x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc512x/u-boot.lds
@@ -57,9 +57,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc5xx/serial.c b/arch/powerpc/cpu/mpc5xx/serial.c
index 6ef8be8fac..732856a5c5 100644
--- a/arch/powerpc/cpu/mpc5xx/serial.c
+++ b/arch/powerpc/cpu/mpc5xx/serial.c
@@ -161,21 +161,13 @@ static void mpc5xx_serial_setbrg(void)
#endif
}
-static void mpc5xx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s);
- ++s;
- }
-}
-
static struct serial_device mpc5xx_serial_drv = {
.name = "mpc5xx_serial",
.start = mpc5xx_serial_init,
.stop = NULL,
.setbrg = mpc5xx_serial_setbrg,
.putc = mpc5xx_serial_putc,
- .puts = mpc5xx_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc5xx_serial_getc,
.tstc = mpc5xx_serial_tstc,
};
diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds
index e02b213d28..c91e146d26 100644
--- a/arch/powerpc/cpu/mpc5xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
index 0c6c54e10a..ac7844dcf4 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
@@ -66,10 +66,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
index 5dcaec1820..1f46eadb5d 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
@@ -60,9 +60,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds
index 39bb42e1c9..c1479544f9 100644
--- a/arch/powerpc/cpu/mpc8220/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8220/u-boot.lds
@@ -59,9 +59,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc8220/uart.c b/arch/powerpc/cpu/mpc8220/uart.c
index 25d4472ea0..772528f82c 100644
--- a/arch/powerpc/cpu/mpc8220/uart.c
+++ b/arch/powerpc/cpu/mpc8220/uart.c
@@ -84,13 +84,6 @@ static void mpc8220_serial_putc(const char c)
psc->xmitbuf[0] = c;
}
-static void mpc8220_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8220_serial_getc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
@@ -132,7 +125,7 @@ static struct serial_device mpc8220_serial_drv = {
.stop = NULL,
.setbrg = mpc8220_serial_setbrg,
.putc = mpc8220_serial_putc,
- .puts = mpc8220_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8220_serial_getc,
.tstc = mpc8220_serial_tstc,
};
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c
index 395f7767d1..cfc665d95c 100644
--- a/arch/powerpc/cpu/mpc824x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc824x/cpu_init.c
@@ -63,7 +63,7 @@ void
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
+#if !defined(CONFIG_MOUSSE)
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
@@ -321,7 +321,7 @@ cpu_init_f (void)
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
__asm__ __volatile__("eieio");
-#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
+#endif /* !CONFIG_MOUSSE */
}
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index 70db73e156..076df70a9f 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -113,9 +113,6 @@ _start:
in_flash:
-#if defined(CONFIG_BMW)
- bl early_init_f /* Must be ASM: no stack yet! */
-#endif
/*
* Setup BATs - cannot be done in C since we don't have a stack yet
*/
@@ -126,7 +123,7 @@ in_flash:
mfmsr r3
ori r3, r3, (MSR_IR | MSR_DR)
mtmsr r3
-#if !defined(CONFIG_BMW)
+
/* Enable and invalidate data cache.
*/
mfspr r3, HID0
@@ -158,7 +155,7 @@ in_flash:
ori r3, r3, 0x0080
sync
mtspr 1011, r3
-#endif /* !CONFIG_BMW */
+
/*
* Thisk the stack pointer *somewhere* sensible. Doesnt
* matter much where as we'll move it when we relocate
@@ -498,7 +495,6 @@ relocate_code:
bdnz 3b
4:
-#if !defined(CONFIG_BMW)
/* Unlock the data cache and invalidate locked area */
xor r0, r0, r0
mtspr 1011, r0
@@ -510,7 +506,6 @@ relocate_code:
dcbi r0, r4
addi r4, r4, 32
bdnz 41b
-#endif
/*
* Now flush the cache: note that we must start from a cache aligned
diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds
index b30ce76e02..a7130125c7 100644
--- a/arch/powerpc/cpu/mpc824x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc824x/u-boot.lds
@@ -60,9 +60,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc8260/serial_scc.c b/arch/powerpc/cpu/mpc8260/serial_scc.c
index ab7755824a..ab2a2b29cb 100644
--- a/arch/powerpc/cpu/mpc8260/serial_scc.c
+++ b/arch/powerpc/cpu/mpc8260/serial_scc.c
@@ -217,13 +217,6 @@ static void mpc8260_scc_serial_putc(const char c)
tbdf->cbd_sc |= BD_SC_READY;
}
-static void mpc8260_scc_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8260_scc_serial_getc(void)
{
volatile cbd_t *rbdf;
@@ -267,7 +260,7 @@ static struct serial_device mpc8260_scc_serial_drv = {
.stop = NULL,
.setbrg = mpc8260_scc_serial_setbrg,
.putc = mpc8260_scc_serial_putc,
- .puts = mpc8260_scc_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8260_scc_serial_getc,
.tstc = mpc8260_scc_serial_tstc,
};
diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c
index 7edde9a492..feba1f63d2 100644
--- a/arch/powerpc/cpu/mpc8260/serial_smc.c
+++ b/arch/powerpc/cpu/mpc8260/serial_smc.c
@@ -216,13 +216,6 @@ static void mpc8260_smc_serial_putc(const char c)
rtx->txbd.cbd_sc |= BD_SC_READY;
}
-static void mpc8260_smc_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8260_smc_serial_getc(void)
{
volatile smc_uart_t *up;
@@ -270,7 +263,7 @@ static struct serial_device mpc8260_smc_serial_drv = {
.stop = NULL,
.setbrg = mpc8260_smc_serial_setbrg,
.putc = mpc8260_smc_serial_putc,
- .puts = mpc8260_smc_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8260_smc_serial_getc,
.tstc = mpc8260_smc_serial_tstc,
};
diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds
index 60b71ecd70..42385fcc19 100644
--- a/arch/powerpc/cpu/mpc8260/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8260/u-boot.lds
@@ -59,9 +59,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 663510987d..e64b0c3411 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -56,6 +56,7 @@ int checkcpu(void)
u32 partid;
} cpu_type_list [] = {
CPU_TYPE_ENTRY(8308),
+ CPU_TYPE_ENTRY(8309),
CPU_TYPE_ENTRY(8311),
CPU_TYPE_ENTRY(8313),
CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 76afba5dd2..20d06003e5 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -268,6 +268,9 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
+#ifdef CONFIG_SYS_GPR1
+ __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f78099d2fe..fb0f7aad6d 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -105,6 +105,8 @@ int get_clocks(void)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
u32 usbmph_clk;
@@ -120,14 +122,16 @@ int get_clocks(void)
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#if !defined(CONFIG_MPC8309)
u32 enc_clk;
+#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
#if defined(CONFIG_MPC8360)
u32 mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
u32 qepmf;
u32 qepdf;
u32 qe_clk;
@@ -185,7 +189,10 @@ int get_clocks(void)
/* unkown SCCR_TSEC1CM value */
return -2;
}
+#endif
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
@@ -260,6 +267,7 @@ int get_clocks(void)
return -6;
}
#endif
+#if !defined(CONFIG_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@@ -277,6 +285,7 @@ int get_clocks(void)
/* unkown SCCR_ENCCM value */
return -7;
}
+#endif
#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -329,6 +338,8 @@ int get_clocks(void)
i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+ i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -444,7 +455,7 @@ int get_clocks(void)
return -13;
}
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -457,6 +468,8 @@ int get_clocks(void)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
gd->usbmph_clk = usbmph_clk;
@@ -472,14 +485,16 @@ int get_clocks(void)
#if !defined(CONFIG_MPC832x)
gd->i2c2_clk = i2c2_clk;
#endif
+#if !defined(CONFIG_MPC8309)
gd->enc_clk = enc_clk;
+#endif
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
gd->mem_sec_clk = mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
@@ -523,7 +538,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
printf("Clock configuration:\n");
printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
@@ -533,7 +548,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_MPC8360)
printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
+#if !defined(CONFIG_MPC8309)
printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832x)
printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
@@ -549,6 +566,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+ printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 2f4b9ad557..d699def9dd 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -58,9 +58,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c88d7..78c412d9f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,9 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,10 +83,14 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
@@ -110,6 +117,9 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
new file mode 100644
index 0000000000..7d33731a7b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 0),
+ SET_QP_INFO(10, 36, 1, 0),
+ SET_QP_INFO(11, 37, 1, 1),
+ SET_QP_INFO(12, 38, 1, 1),
+ SET_QP_INFO(13, 39, 1, 2),
+ SET_QP_INFO(14, 40, 1, 2),
+ SET_QP_INFO(15, 41, 1, 3),
+ SET_QP_INFO(16, 42, 1, 3),
+ SET_QP_INFO(17, 43, 1, 0),
+ SET_QP_INFO(18, 44, 1, 0),
+ SET_QP_INFO(19, 45, 1, 1),
+ SET_QP_INFO(20, 46, 1, 1),
+ SET_QP_INFO(21, 47, 1, 2),
+ SET_QP_INFO(22, 48, 1, 2),
+ SET_QP_INFO(23, 49, 1, 3),
+ SET_QP_INFO(24, 50, 1, 3),
+ SET_QP_INFO(25, 51, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+ SET_SRIO_LIODN_1(1, 307),
+ SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+
+ SET_DMA_LIODN(1, 147),
+ SET_DMA_LIODN(2, 227),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+ /* Set RMan block 0-3 liodn offset */
+ SET_RMAN_LIODN(0, 678),
+ SET_RMAN_LIODN(1, 679),
+ SET_RMAN_LIODN(2, 680),
+ SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
new file mode 100644
index 0000000000..9990202f42
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+ u8 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x30, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x32, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x33, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x34, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ AURORA, AURORA,
+ SRIO1, SRIO1}},
+ {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2, AURORA, AURORA,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2, AURORA, AURORA,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0x9A, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e8989bdf45..2be192d578 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -76,11 +76,15 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
puts("Work-around for Erratum ESDHC111 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+ puts("Work-around for Erratum A004468 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
puts("Work-around for Erratum ESDHC135 enabled\n");
#endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
- puts("Work-around for Erratum ESDHC136 enabled\n");
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
+ if (SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum ESDHC13 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
puts("Work-around for Erratum ESDHC-A001 enabled\n");
@@ -127,6 +131,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ puts("Work-around for Erratum SRIO-A004034 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+ puts("Work-around for Erratum A004934 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5ddb29435c..db232e64f8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -60,20 +60,32 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+ defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
- u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
- >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+ /*
+ * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+ * mode. Previous platform use ddr ratio to do the same. This
+ * information is only for display here.
+ */
#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ u32 ddr_sync = 0; /* only async mode is supported */
+#else
u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_FSL_CORENET */
+
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
@@ -127,6 +139,11 @@ int checkcpu (void)
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+ if (nr_cores > CONFIG_MAX_CPUS) {
+ panic("\nUnexpected number of cores: %d, max is %d\n",
+ nr_cores, CONFIG_MAX_CPUS);
+ }
+
get_sys_info(&sysinfo);
puts("Clock Configuration:");
@@ -181,6 +198,10 @@ int checkcpu (void)
}
#endif
+#if defined(CONFIG_FSL_IFC)
+ printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+#endif
+
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
@@ -196,6 +217,10 @@ int checkcpu (void)
}
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+#endif
+
#ifdef CONFIG_SYS_DPAA_PME
printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif
@@ -270,10 +295,7 @@ reset_85xx_watchdog(void)
/*
* Clear TSR(WIS) bit by writing 1
*/
- unsigned long val;
- val = mfspr(SPRN_TSR);
- val |= TSR_WIS;
- mtspr(SPRN_TSR, val);
+ mtspr(SPRN_TSR, TSR_WIS);
}
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index afb56719da..736293c41d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -295,6 +295,43 @@ static void __fsl_serdes__init(void)
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int enable_cluster_l2(void)
+{
+ int i = 0;
+ u32 cluster;
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_cluster_l2 __iomem *l2cache;
+
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ if (cluster & TP_CLUSTER_EOC)
+ return 0;
+
+ /* The first cache has already been set up, so skip it */
+ i++;
+
+ /* Look through the remaining clusters, and set up their caches */
+ do {
+ l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+
+ /* set stash ID to (cluster) * 2 + 32 + 1 */
+ clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+ printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+ out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+ while ((in_be32(&l2cache->l2csr0) &
+ (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+ ;
+ out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ i++;
+ } while (!(cluster & TP_CLUSTER_EOC));
+
+ return 0;
+}
+#endif
+
/*
* Initialize L2 as cache.
*
@@ -306,7 +343,12 @@ int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
+#endif
+#ifdef CONFIG_L2_CACHE
+ ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
@@ -356,7 +398,6 @@ int cpu_init_r(void)
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint ver;
u32 l2siz_field;
@@ -467,6 +508,11 @@ int cpu_init_r(void)
}
skip_l2:
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+ if (l2cache->l2csr0 & L2CSR0_L2E)
+ printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+ enable_cluster_l2();
#else
puts("disabled\n");
#endif
@@ -478,7 +524,7 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
char *s = getenv("bootmaster");
if (s) {
if (!strcmp(s, "SRIO1")) {
@@ -497,11 +543,13 @@ skip_l2:
setup_mp();
#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
- void *p;
- p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
- setbits_be32(p, 1 << (31 - 14));
+ if (SVR_MAJ(svr) < 3) {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 1 << (31 - 14));
+ }
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ca4ed62645..f118dd5daf 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -18,12 +18,14 @@
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
- unsigned int i;
+ unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ int timeout_save;
volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
- u32 total_gb_size_per_controller;
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
@@ -52,8 +54,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
return;
}
- out_be32(&ddr->eor, regs->ddr_eor);
-
+ if (regs->ddr_eor)
+ out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -121,6 +123,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+ if (regs->ddr_wrlvl_cntl_2)
+ out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
@@ -134,6 +141,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+ out_be32(&ddr->debug[28], 0x00003000);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
@@ -270,9 +280,48 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
+ total_gb_size_per_controller *= 3;
+ else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ timeout_save = timeout;
+#endif
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
- while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
/* continue this workaround */
@@ -330,23 +379,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
while (in_be32(&ddr->debug[1]) & 0x400)
udelay(10000); /* throttle polling rate */
- /* 7. Wait for 400ms/GB */
- total_gb_size_per_controller = 0;
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i == csn) {
- total_gb_size_per_controller +=
- ((csn_bnds_backup & 0xFFFF) >> 6)
- - (csn_bnds_backup >> 22) + 1;
- } else {
- total_gb_size_per_controller +=
- ((regs->cs[i].bnds & 0xFFFF) >> 6)
- - (regs->cs[i].bnds >> 22) + 1;
- }
- }
- if (in_be32(&ddr->sdram_cfg) & 0x80000)
- total_gb_size_per_controller <<= 1;
- debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
- udelay(total_gb_size_per_controller * 400000);
+ /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
+ debug("Wait for %d * 10ms\n", timeout_save);
+ udelay(timeout_save * 10000);
/* 8. Set sdram_cfg_2[dinit] if options requires */
setbits_be32(&ddr->sdram_cfg_2,
@@ -354,8 +389,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
/* 9. Poll until dinit is cleared */
- while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
- udelay(10000);
+ timeout = timeout_save;
+ debug("Need to wait up to %d * 10ms\n", timeout);
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
/* 10. Clear EEBACR[3] */
clrbits_be32(&ecm->eebacr, 10000000);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index a0a9b4c5ae..ab0933076d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -47,8 +47,8 @@ extern void ft_srio_setup(void *blob);
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
int off;
- ulong spin_tbl_addr = get_spin_phys_addr();
- u32 bootpg = determine_mp_bootpg();
+ phys_addr_t spin_tbl_addr = get_spin_phys_addr();
+ u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
@@ -97,7 +97,16 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
if ((u64)bootpg < memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
if (off < 0)
- printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+ printf("Failed to reserve memory for bootpg: %s\n",
+ fdt_strerror(off));
+ }
+ /* Reserve spin table page */
+ if (spin_tbl_addr < memory_limit) {
+ off = fdt_add_mem_rsv(blob,
+ (spin_tbl_addr & ~0xffful), 4096);
+ if (off < 0)
+ printf("Failed to reserve memory for spin table: %s\n",
+ fdt_strerror(off));
}
}
#endif
@@ -220,12 +229,19 @@ static inline void ft_fixup_l2cache(void *blob)
/* we dont bother w/L3 since no platform of this type has one */
}
-#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
+ defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
static inline void ft_fixup_l2cache(void *blob)
{
int off, l2_off, l3_off = -1;
u32 *ph;
+#ifdef CONFIG_BACKSIDE_L2_CACHE
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+#else
+ struct ccsr_cluster_l2 *l2cache =
+ (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
+#endif
u32 size, line_size, num_ways, num_sets;
int has_l2 = 1;
@@ -257,7 +273,12 @@ static inline void ft_fixup_l2cache(void *blob)
if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ /* Only initialize every eighth thread */
+ if (reg && !((*reg) % 8))
+#else
if (reg)
+#endif
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
#endif
@@ -390,6 +411,11 @@ static void ft_fixup_dpaa_clks(void *blob)
#endif
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ do_fixup_by_compat_u32(blob, "fsl,qman",
+ "clock-frequency", sysinfo.freqQMAN, 1);
+#endif
+
#ifdef CONFIG_SYS_DPAA_PME
do_fixup_by_compat_u32(blob, "fsl,pme",
"clock-frequency", sysinfo.freqPME, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
new file mode 100644
index 0000000000..01dcdf6bc1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include <asm/errno.h>
+#include "fsl_corenet2_serdes.h"
+
+static u64 serdes1_prtcl_map;
+static u64 serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+static u64 serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+static u64 serdes4_prtcl_map;
+#endif
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+ [NONE] = "NA",
+ [PCIE1] = "PCIE1",
+ [PCIE2] = "PCIE2",
+ [PCIE3] = "PCIE3",
+ [PCIE4] = "PCIE4",
+ [SATA1] = "SATA1",
+ [SATA2] = "SATA2",
+ [SRIO1] = "SRIO1",
+ [SRIO2] = "SRIO2",
+ [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+ [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+ [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+ [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+ [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+ [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
+ [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+ [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+ [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+ [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [XAUI_FM1] = "XAUI_FM1",
+ [XAUI_FM2] = "XAUI_FM2",
+ [AURORA] = "DEBUG",
+ [CPRI1] = "CPRI1",
+ [CPRI2] = "CPRI2",
+ [CPRI3] = "CPRI3",
+ [CPRI4] = "CPRI4",
+ [CPRI5] = "CPRI5",
+ [CPRI6] = "CPRI6",
+ [CPRI7] = "CPRI7",
+ [CPRI8] = "CPRI8",
+ [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
+ [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
+ [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
+ [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
+ [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
+ [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
+ [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
+ [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
+ [QSGMII_FM1_A] = "QSGMII_FM1_A",
+ [QSGMII_FM1_B] = "QSGMII_FM1_B",
+ [QSGMII_FM2_A] = "QSGMII_FM2_A",
+ [QSGMII_FM2_B] = "QSGMII_FM2_B",
+ [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
+ [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
+ [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
+ [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
+ [INTERLAKEN] = "INTERLAKEN",
+};
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ u64 ret = 0;
+
+ ret |= (1ULL << device) & serdes1_prtcl_map;
+ ret |= (1ULL << device) & serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ ret |= (1ULL << device) & serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ ret |= (1ULL << device) & serdes4_prtcl_map;
+#endif
+
+ return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 cfg = in_be32(&gur->rcwsr[4]);
+ int i;
+
+ switch (sd) {
+ case FSL_SRDS_1:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ break;
+ case FSL_SRDS_2:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ break;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ case FSL_SRDS_3:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+ break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ case FSL_SRDS_4:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+ break;
+#endif
+ default:
+ printf("invalid SerDes%d\n", sd);
+ break;
+ }
+ /* Is serdes enabled at all? */
+ if (unlikely(cfg == 0))
+ return -ENODEV;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(sd, cfg, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u64 serdes_prtcl_map = 0;
+ u32 cfg;
+ int lane;
+
+ cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+ /* Is serdes enabled at all? */
+ if (!cfg) {
+ printf("SERDES%d is not enabled\n", sd + 1);
+ return 0;
+ }
+
+ cfg >>= sd_prctl_shift;
+ printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+ serdes_prtcl_map |= (1ULL << lane_prtcl);
+ }
+
+ return serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+
+ serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+ serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+#endif
+
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
new file mode 100644
index 0000000000..2258f41888
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET2_SERDES_H
+#define __FSL_CORENET2_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#endif /* __FSL_CORENET2_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060369..e6b1b1b7ee 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+ * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+ * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
+ * to decide whether a protocol is supported on a given lane, so SATA
+ * will be identified as not supported, and therefore not initialized.
+ * So for protocols which use SATA on bank4, we add SATA support in
+ * serdes_prtcl_map.
+ */
+ switch (cfg) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ case 0x5:
+ case 0x6:
+ case 0x7:
+ serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
+ break;
+ default:
+ srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+
+ /* We don't need bank 4, so power it down */
+ setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
+ }
+#endif
+
soc_serdes_init();
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -617,6 +655,38 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+ /*
+ * To avoid the situation that resulted in the P4080 erratum
+ * SERDES-8, a given SerDes bank will use the PLLs from the previous
+ * bank if one of the PLL frequencies is a multiple of the other. For
+ * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+ * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
+ * that, in this situation, lane synchronization is not initiated. So
+ * when we detect a bank with a "borrowed" PLL, we have to manually
+ * initiate lane synchronization.
+ */
+ for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
+ /* Determine the first lane for this bank */
+ unsigned int lane;
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++)
+ if (lanes[lane].bank == bank)
+ break;
+ idx = lanes[lane].idx;
+
+ /*
+ * Check if the PLL for the bank is borrowed. The UOTHL
+ * bit of the first lane will tell us that.
+ */
+ if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
+ /* Manually start lane synchronization */
+ setbits_be32(&srds_regs->bank[bank].pllcr0,
+ SRDS_PLLCR0_PVCOCNT_EN);
+ }
+ }
+#endif
+
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
index f261351c8a..3c551e9b4c 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -22,9 +22,6 @@
#ifndef __FSL_CORENET_SERDES_H
#define __FSL_CORENET_SERDES_H
-#define SRDS_MAX_LANES 18
-#define SRDS_MAX_BANK 3
-
enum srds_bank {
FSL_SRDS_BANK_1 = 0,
FSL_SRDS_BANK_2 = 1,
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 11881c9489..2e533672f3 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -40,6 +40,7 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
return liodn_bases[dpaa_dev].num_ids;
}
+#ifdef CONFIG_SYS_SRIO
static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
{
int i;
@@ -54,6 +55,7 @@ static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
}
}
}
+#endif
static void set_liodn(struct liodn_id_table *tbl, int size)
{
@@ -181,8 +183,10 @@ void set_liodns(void)
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
+#ifdef CONFIG_SYS_SRIO
/* setup SRIO port liodns */
set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
+#endif
/* setup SEC block liodn bases & offsets if we have one */
if (IS_E_PROCESSOR(get_svr())) {
@@ -219,6 +223,7 @@ void set_liodns(void)
#endif
}
+#ifdef CONFIG_SYS_SRIO
static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
{
int i, srio_off;
@@ -247,6 +252,57 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
}
}
}
+#endif
+
+#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CONFIG_SYS_PCI_EP_LIODN_START 256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+ int off, pci_idx = 0, pci_cnt = 0, i, rc;
+ const uint32_t *base_liodn;
+ uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+ /*
+ * Count the number of pci nodes.
+ * It's needed later when the interleaved liodn offsets are generated.
+ */
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ while (off != -FDT_ERR_NOTFOUND) {
+ pci_cnt++;
+ off = fdt_node_offset_by_compatible(fdt, off, compat);
+ }
+
+ for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ off != -FDT_ERR_NOTFOUND;
+ off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+ base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+ if (!base_liodn) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Could not get liodn of node %s: %s\n",
+ path, fdt_strerror(rc));
+ continue;
+ }
+ for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+ i * pci_cnt + pci_idx - *base_liodn;
+ rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+ liodn_offs, sizeof(liodn_offs));
+ if (rc) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Unable to set fsl,liodn-offset-list for "
+ "node %s: %s\n", path, fdt_strerror(rc));
+ continue;
+ }
+ pci_idx++;
+ }
+}
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
{
@@ -277,7 +333,9 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
void fdt_fixup_liodn(void *blob)
{
+#ifdef CONFIG_SYS_SRIO
fdt_fixup_srio_liodn(blob, srio_liodn_tbl);
+#endif
fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -295,4 +353,6 @@ void fdt_fixup_liodn(void *blob)
#ifdef CONFIG_SYS_DPAA_RMAN
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
+
+ fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
}
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index ffc2a9ad65..e1197ac9e5 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -27,9 +27,13 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
+u32 fsl_ddr_get_intl3r(void);
+
+extern u32 __spin_table[];
u32 get_my_id()
{
@@ -76,17 +80,16 @@ int cpu_status(int nr)
return 0;
if (nr == id) {
- table = (u32 *)get_spin_virt_addr();
+ table = (u32 *)&__spin_table;
printf("table base @ 0x%p\n", table);
} else {
- table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+ table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
printf("Running on cpu %d\n", id);
printf("\n");
printf("table @ 0x%p\n", table);
printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
- printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
- printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
+ printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
}
return 0;
@@ -149,12 +152,11 @@ static u8 boot_entry_map[4] = {
0,
BOOT_ENTRY_PIR,
BOOT_ENTRY_R3_LOWER,
- BOOT_ENTRY_R6_LOWER,
};
int cpu_release(int nr, int argc, char * const argv[])
{
- u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+ u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
if (hold_cores_in_reset(1))
@@ -172,8 +174,8 @@ int cpu_release(int nr, int argc, char * const argv[])
boot_addr = simple_strtoull(argv[0], NULL, 16);
- /* handle pir, r3, r6 */
- for (i = 1; i < 4; i++) {
+ /* handle pir, r3 */
+ for (i = 1; i < 3; i++) {
if (argv[i][0] != '-') {
u8 entry = boot_entry_map[i];
val = simple_strtoul(argv[i], NULL, 16);
@@ -191,38 +193,80 @@ int cpu_release(int nr, int argc, char * const argv[])
return 0;
}
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
{
- /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
- if ((u64)gd->ram_size > 0xfffff000)
- return (0xfffff000);
+ u32 bootpg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+ u32 svr = get_svr();
+ u32 granule_size, check;
+ struct law_entry e;
+#endif
- return (gd->ram_size - 4096);
-}
-ulong get_spin_phys_addr(void)
-{
- extern ulong __secondary_start_page;
- extern ulong __spin_table;
+ /* use last 4K of mapped memory */
+ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+ CONFIG_SYS_SDRAM_BASE - 4096;
+ if (pagesize)
+ *pagesize = 4096;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+/*
+ * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
+ * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
+ * the way boot page chosen in u-boot avoids hitting this erratum. So only
+ * thw workaround for 3-way interleaving is needed.
+ *
+ * To make sure boot page translation works with 3-Way DDR interleaving
+ * enforce a check for the following constrains
+ * 8K granule size requires BRSIZE=8K and
+ * bootpg >> log2(BRSIZE) %3 == 1
+ * 4K and 1K granule size requires BRSIZE=4K and
+ * bootpg >> log2(BRSIZE) %3 == 0
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
+ e = find_law(bootpg);
+ switch (e.trgt_id) {
+ case LAW_TRGT_IF_DDR_INTLV_123:
+ granule_size = fsl_ddr_get_intl3r() & 0x1f;
+ if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
+ if (pagesize)
+ *pagesize = 8192;
+ bootpg &= 0xffffe000; /* align to 8KB */
+ check = bootpg >> 13;
+ while ((check % 3) != 1)
+ check--;
+ bootpg = check << 13;
+ debug("Boot page (8K) at 0x%08x\n", bootpg);
+ break;
+ } else {
+ bootpg &= 0xfffff000; /* align to 4KB */
+ check = bootpg >> 12;
+ while ((check % 3) != 0)
+ check--;
+ bootpg = check << 12;
+ debug("Boot page (4K) at 0x%08x\n", bootpg);
+ }
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
- return (determine_mp_bootpg() +
- (ulong)&__spin_table - (ulong)&__secondary_start_page);
+ return bootpg;
}
-ulong get_spin_virt_addr(void)
+phys_addr_t get_spin_phys_addr(void)
{
- extern ulong __secondary_start_page;
- extern ulong __spin_table;
-
- return (CONFIG_BPTR_VIRT_ADDR +
- (ulong)&__spin_table - (ulong)&__secondary_start_page);
+ return virt_to_phys(&__spin_table);
}
#ifdef CONFIG_FSL_CORENET
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
{
- u32 cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_virt_addr();
+ u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
+ u32 *table = (u32 *)&__spin_table;
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
@@ -241,7 +285,11 @@ static void plat_mp_up(unsigned long bootpg)
out_be32(&ccm->bstrl, bootpg);
e = find_law(bootpg);
- out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
+ /* pagesize is only 4K or 8K */
+ if (pagesize == 8192)
+ brsize = LAW_SIZE_8K;
+ out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
+ debug("BRSIZE is 0x%x\n", brsize);
/* readback to sync write */
in_be32(&ccm->bstrar);
@@ -294,10 +342,10 @@ static void plat_mp_up(unsigned long bootpg)
#endif
}
#else
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
{
u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_virt_addr();
+ u32 *table = (u32 *)&__spin_table;
volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -374,27 +422,52 @@ static void plat_mp_up(unsigned long bootpg)
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
lmb_reserve(lmb, bootpg, 4096);
}
void setup_mp(void)
{
- extern ulong __secondary_start_page;
- extern ulong __bootpg_addr;
- ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg = determine_mp_bootpg();
+ extern u32 __secondary_start_page;
+ extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
+
+ int i;
+ ulong fixup = (u32)&__secondary_start_page;
+ u32 bootpg, bootpg_map, pagesize;
+
+ bootpg = determine_mp_bootpg(&pagesize);
+
+ /*
+ * pagesize is only 4K or 8K
+ * we only use the last 4K of boot page
+ * bootpg_map saves the address for the boot page
+ * 8K is used for the workaround of 3-way DDR interleaving
+ */
+
+ bootpg_map = bootpg;
+
+ if (pagesize == 8192)
+ bootpg += 4096; /* use 2nd half */
/* Some OSes expect secondary cores to be held in reset */
if (hold_cores_in_reset(0))
return;
- /* Store the bootpg's SDRAM address for use by secondary CPU cores */
- __bootpg_addr = bootpg;
+ /*
+ * Store the bootpg's cache-able half address for use by secondary
+ * CPU cores to continue to boot
+ */
+ __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
+
+ /* Store spin table's physical address for use by secondary cores */
+ __spin_table_addr = (u32)get_spin_phys_addr();
+
+ /* flush bootpg it before copying invalidate any staled cacheline */
+ flush_cache(bootpg, 4096);
/* look for the tlb covering the reset page, there better be one */
- int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
/* we found a match */
if (i != -1) {
@@ -407,7 +480,7 @@ void setup_mp(void)
memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
- plat_mp_up(bootpg);
+ plat_mp_up(bootpg_map, pagesize);
} else {
puts("WARNING: No reset page TLB. "
"Skipping secondary core setup\n");
diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h
index 87bac37152..ad9950bcf5 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.h
+++ b/arch/powerpc/cpu/mpc85xx/mp.h
@@ -3,8 +3,7 @@
#include <asm/mp.h>
-ulong get_spin_phys_addr(void);
-ulong get_spin_virt_addr(void);
+phys_addr_t get_spin_phys_addr(void);
u32 get_my_id(void);
int hold_cores_in_reset(int verbose);
@@ -16,7 +15,7 @@ int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_PIR 5
#define BOOT_ENTRY_R6_UPPER 6
#define BOOT_ENTRY_R6_LOWER 7
-#define NUM_BOOT_ENTRY 8
+#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */
#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
new file mode 100644
index 0000000000..878ee3e73e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 6, 1),
+ SET_QP_INFO(13, 14, 7, 2),
+ SET_QP_INFO(15, 16, 8, 3),
+ SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+#endif
+
+ SET_SDHC_LIODN(1, 64),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 93),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 94),
+
+ SET_SATA_LIODN(1, 95),
+ SET_SATA_LIODN(2, 96),
+
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
+
+ SET_DMA_LIODN(1, 193),
+ SET_DMA_LIODN(2, 194),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 6),
+ SET_FMAN_RX_1G_LIODN(1, 1, 7),
+ SET_FMAN_RX_1G_LIODN(1, 2, 8),
+ SET_FMAN_RX_1G_LIODN(1, 3, 9),
+ SET_FMAN_RX_1G_LIODN(1, 4, 10),
+ SET_FMAN_RX_10G_LIODN(1, 0, 11),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(2, 0, 12),
+ SET_FMAN_RX_1G_LIODN(2, 1, 13),
+ SET_FMAN_RX_1G_LIODN(2, 2, 14),
+ SET_FMAN_RX_1G_LIODN(2, 3, 15),
+ SET_FMAN_RX_1G_LIODN(2, 4, 16),
+ SET_FMAN_RX_10G_LIODN(2, 0, 17),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+ SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+ SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+ SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 89),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 90),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 91),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 92),
+ SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
+ SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
+ SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
+ SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
+#endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
new file mode 100644
index 0000000000..890b88e4e3
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+/*
+ * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
+ * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in
+ * this table. This works because most of the SerDes code is for errata
+ * work-arounds, and there are no P5040 errata that effect bank 4.
+ */
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
+ [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ /* SATA1, SATA2 */ },
+ [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ /* SATA1, SATA2 */ },
+ [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
+ /* NONE, NONE */ },
+ [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
+ [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
+ [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, /* NONE, NONE */ },
+ [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
+ /* NONE, NONE */ },
+ [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, /* NONE, NONE */ },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 6199633541..b59ef69f1f 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -182,14 +182,18 @@ void fdt_fixup_qportals(void *blob)
{
int off, err;
unsigned int maj, min;
+ unsigned int ip_cfg;
u32 rev_1 = in_be32(&qman->ip_rev_1);
+ u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
int compat_len;
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
+ ip_cfg = rev_2 & 0xff;
- compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1;
+ compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
@@ -267,14 +271,19 @@ void fdt_fixup_bportals(void *blob)
{
int off, err;
unsigned int maj, min;
+ unsigned int ip_cfg;
u32 rev_1 = in_be32(&bman->ip_rev_1);
+ u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];
int compat_len;
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
- compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1;
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 22e73e0661..4ba44a9028 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -150,29 +150,33 @@ __secondary_start_page:
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
/* get our PIR to figure out our table entry */
- lis r3,toreset(__spin_table)@h
- ori r3,r3,toreset(__spin_table)@l
+ lis r3,toreset(__spin_table_addr)@h
+ ori r3,r3,toreset(__spin_table_addr)@l
+ lwz r3,0(r3)
- /* r10 has the base address for the entry */
+ /*
+ * r10 has the base address for the entry.
+ * we cannot access it yet before setting up a new TLB
+ */
mfspr r0,SPRN_PIR
#if defined(CONFIG_E6500)
/*
* PIR definition for E6500
* 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID, 2’b00 - SoC 1
+ * 8-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
- * 20-24 CLUSTER_ID 5’b00000 - CCM 1
+ * 20-24 CLUSTER_ID 5'b00000 - CCM 1
* all others - reserved
- * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
- * 2’b01 - cluster 2
- * 2’b10 - cluster 3
- * 2’b11 - cluster 4
- * 27-28 CORE_ID 2’b00 - core 0
- * 2’b01 - core 1
- * 2’b10 - core 2
- * 2’b11 - core 3
- * 29-31 THREAD_ID 3’b000 - thread 0
- * 3’b001 - thread 1
+ * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
+ * 2'b01 - cluster 2
+ * 2'b10 - cluster 3
+ * 2'b11 - cluster 4
+ * 27-28 CORE_ID 2'b00 - core 0
+ * 2'b01 - core 1
+ * 2'b10 - core 2
+ * 2'b11 - core 3
+ * 29-31 THREAD_ID 3'b000 - thread 0
+ * 3'b001 - thread 1
*/
rlwinm r4,r0,29,25,31
#elif defined(CONFIG_E500MC)
@@ -180,16 +184,9 @@ __secondary_start_page:
#else
mr r4,r0
#endif
- slwi r8,r4,5
+ slwi r8,r4,6 /* spin table is padded to 64 byte */
add r10,r3,r8
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
- /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
- slwi r8,r4,1
- addi r8,r8,32
- mtspr L1CSR2,r8
-#endif
-
#ifdef CONFIG_E6500
mfspr r0,SPRN_PIR
/*
@@ -209,6 +206,13 @@ __secondary_start_page:
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_CACHE_STASHING
+ /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+ slwi r8,r4,1
+ addi r8,r8,32
+ mtspr L1CSR2,r8
+#endif
+
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
@@ -277,73 +281,111 @@ __secondary_start_page:
beq 2b
#endif
3:
-
-#define EPAPR_MAGIC (0x45504150)
-#define ENTRY_ADDR_UPPER 0
-#define ENTRY_ADDR_LOWER 4
-#define ENTRY_R3_UPPER 8
-#define ENTRY_R3_LOWER 12
-#define ENTRY_RESV 16
-#define ENTRY_PIR 20
-#define ENTRY_R6_UPPER 24
-#define ENTRY_R6_LOWER 28
-#define ENTRY_SIZE 32
-
- /* setup the entry */
- li r3,0
- li r8,1
- stw r4,ENTRY_PIR(r10)
- stw r3,ENTRY_ADDR_UPPER(r10)
- stw r8,ENTRY_ADDR_LOWER(r10)
- stw r3,ENTRY_R3_UPPER(r10)
- stw r4,ENTRY_R3_LOWER(r10)
- stw r3,ENTRY_R6_UPPER(r10)
- stw r3,ENTRY_R6_LOWER(r10)
-
- /* load r13 with the address of the 'bootpg' in SDRAM */
- lis r13,toreset(__bootpg_addr)@h
- ori r13,r13,toreset(__bootpg_addr)@l
+ /* setup mapping for the spin table, WIMGE=0b00100 */
+ lis r13,toreset(__spin_table_addr)@h
+ ori r13,r13,toreset(__spin_table_addr)@l
lwz r13,0(r13)
+ /* mask by 4K */
+ rlwinm r13,r13,0,0,19
- /* setup mapping for AS = 1, and jump there */
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
- oris r11,r13,(MAS2_I|MAS2_G)@h
- ori r11,r13,(MAS2_I|MAS2_G)@l
+ oris r11,r13,(MAS2_M|MAS2_G)@h
+ ori r11,r13,(MAS2_M|MAS2_G)@l
mtspr SPRN_MAS2,r11
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
mtspr SPRN_MAS3,r11
+ li r11,0
+ mtspr SPRN_MAS7,r11
tlbwe
- bl 1f
-1: mflr r11
/*
- * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
- * this mask to fixup the cpu spin table and the address that we want
- * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
- * bootpg is at 0x7ffff000 in SDRAM.
+ * __bootpg_addr has the address of __second_half_boot_page
+ * jump there in AS=1 space with cache enabled
*/
- ori r13,r13,0xfff
- and r11, r11, r13
- and r10, r10, r13
-
- addi r11,r11,(2f-1b)
+ lis r13,toreset(__bootpg_addr)@h
+ ori r13,r13,toreset(__bootpg_addr)@l
+ lwz r11,0(r13)
+ mtspr SPRN_SRR0,r11
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
-
- mtspr SPRN_SRR0,r11
mtspr SPRN_SRR1,r12
rfi
+ /*
+ * Allocate some space for the SDRAM address of the bootpg.
+ * This variable has to be in the boot page so that it can
+ * be accessed by secondary cores when they come out of reset.
+ */
+ .align L1_CACHE_SHIFT
+ .globl __bootpg_addr
+__bootpg_addr:
+ .long 0
+
+ .global __spin_table_addr
+__spin_table_addr:
+ .long 0
+
+ /*
+ * This variable is set by cpu_init_r() after parsing hwconfig
+ * to enable workaround for erratum NMG_CPU_A011.
+ */
+ .align L1_CACHE_SHIFT
+ .global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+ .long 1
+
+ /* Fill in the empty space. The actual reset vector is
+ * the last word of the page */
+__secondary_start_code_end:
+ .space 4092 - (__secondary_start_code_end - __secondary_start_page)
+__secondary_reset_vector:
+ b __secondary_start_page
+
+
+/* this is a separated page for the spin table and cacheable boot code */
+ .align L1_CACHE_SHIFT
+ .global __second_half_boot_page
+__second_half_boot_page:
+#define EPAPR_MAGIC 0x45504150
+#define ENTRY_ADDR_UPPER 0
+#define ENTRY_ADDR_LOWER 4
+#define ENTRY_R3_UPPER 8
+#define ENTRY_R3_LOWER 12
+#define ENTRY_RESV 16
+#define ENTRY_PIR 20
+#define ENTRY_SIZE 64
+ /*
+ * setup the entry
+ * r10 has the base address of the spin table.
+ * spin table is defined as
+ * struct {
+ * uint64_t entry_addr;
+ * uint64_t r3;
+ * uint32_t rsvd1;
+ * uint32_t pir;
+ * };
+ * we pad this struct to 64 bytes so each entry is in its own cacheline
+ */
+ li r3,0
+ li r8,1
+ mfspr r4,SPRN_PIR
+ stw r3,ENTRY_ADDR_UPPER(r10)
+ stw r3,ENTRY_R3_UPPER(r10)
+ stw r4,ENTRY_R3_LOWER(r10)
+ stw r3,ENTRY_RESV(r10)
+ stw r4,ENTRY_PIR(r10)
+ msync
+ stw r8,ENTRY_ADDR_LOWER(r10)
+
/* spin waiting for addr */
-2:
- lwz r4,ENTRY_ADDR_LOWER(r10)
+3: lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
- bne 2b
+ bne 3b
isync
/* setup IVORs to match fixed offsets */
@@ -362,11 +404,20 @@ __secondary_start_page:
/* mask by ~64M to setup our tlb we will jump to */
rlwinm r12,r4,0,0,5
- /* setup r3, r4, r5, r6, r7, r8, r9 */
+ /*
+ * setup r3, r4, r5, r6, r7, r8, r9
+ * r3 contains the value to put in the r3 register at secondary cpu
+ * entry. The high 32-bits are ignored on 32-bit chip implementations.
+ * 64-bit chip implementations however shall load all 64-bits
+ */
+#ifdef CONFIG_SYS_PPC64
+ ld r3,ENTRY_R3_UPPER(r10)
+#else
lwz r3,ENTRY_R3_LOWER(r10)
+#endif
li r4,0
li r5,0
- lwz r6,ENTRY_R6_LOWER(r10)
+ li r6,0
lis r7,(64*1024*1024)@h
li r8,0
li r9,0
@@ -404,32 +455,10 @@ __secondary_start_page:
mtspr SPRN_SRR1,r13
rfi
- /*
- * Allocate some space for the SDRAM address of the bootpg.
- * This variable has to be in the boot page so that it can
- * be accessed by secondary cores when they come out of reset.
- */
- .globl __bootpg_addr
-__bootpg_addr:
- .long 0
- .align L1_CACHE_SHIFT
+ .align 6
.globl __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*ENTRY_SIZE
-
- /*
- * This variable is set by cpu_init_r() after parsing hwconfig
- * to enable workaround for erratum NMG_CPU_A011.
- */
- .align L1_CACHE_SHIFT
- .global enable_cpu_a011_workaround
-enable_cpu_a011_workaround:
- .long 1
-
- /* Fill in the empty space. The actual reset vector is
- * the last word of the page */
-__secondary_start_code_end:
- .space 4092 - (__secondary_start_code_end - __secondary_start_page)
-__secondary_reset_vector:
- b __secondary_start_page
+__spin_table_end:
+ .space 4096 - (__spin_table_end - __spin_table)
diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c
index fe9af55c7a..6345362d88 100644
--- a/arch/powerpc/cpu/mpc85xx/serial_scc.c
+++ b/arch/powerpc/cpu/mpc85xx/serial_scc.c
@@ -220,13 +220,6 @@ static void mpc85xx_serial_putc(const char c)
tbdf->cbd_sc |= BD_SC_READY;
}
-static void mpc85xx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc85xx_serial_getc(void)
{
volatile cbd_t *rbdf;
@@ -268,7 +261,7 @@ static struct serial_device mpc85xx_serial_drv = {
.stop = NULL,
.setbrg = mpc85xx_serial_setbrg,
.putc = mpc85xx_serial_putc,
- .puts = mpc85xx_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc85xx_serial_getc,
.tstc = mpc85xx_serial_tstc,
};
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index abfeb268d4..801ee078c0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -39,6 +39,10 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
@@ -72,16 +76,22 @@ void get_sys_info (sys_info_t * sysInfo)
[13] = 2, /* CC4 PPL / 2 */
[14] = 4, /* CC4 PPL / 4 */
};
- uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
- uint ratio[4];
+ uint i, freqCC_PLL[6], rcw_tmp;
+ uint ratio[6];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
sysInfo->freqDDRBus = sysclk;
+#endif
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+ & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
if (mem_pll_rat > 2)
sysInfo->freqDDRBus *= mem_pll_rat;
else
@@ -91,27 +101,151 @@ void get_sys_info (sys_info_t * sysInfo)
ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
- for (i = 0; i < 4; i++) {
+ ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
+ ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
+ for (i = 0; i < 6; i++) {
if (ratio[i] > 4)
freqCC_PLL[i] = sysclk * ratio[i];
else
freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
}
- rcw_tmp = in_be32(&gur->rcwsr[3]);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ /*
+ * Each cluster has up to 4 cores, sharing the same PLL selection.
+ * The cluster assignment is fixed per SoC. There is no way identify the
+ * assignment so far, presuming the "first configuration" which is to
+ * fill the lower cluster group first before moving up to next group.
+ * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
+ * and core 4~7 on cluster 2
+ * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
+ * and core 12~15 on cluster 4 if existing
+ */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+ & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+ if (cplx_pll > 3)
+ printf("Unsupported architecture configuration"
+ " in function %s\n", __func__);
+ cplx_pll += (cpu / 8) * 3;
sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
+#define PME_CLK_SEL 0xe0000000
+#define PME_CLK_SHIFT 29
+#define FM1_CLK_SEL 0x1c000000
+#define FM1_CLK_SHIFT 26
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+ switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqPME = freqCC_PLL[0];
+ break;
+ case 2:
+ sysInfo->freqPME = freqCC_PLL[0] / 2;
+ break;
+ case 3:
+ sysInfo->freqPME = freqCC_PLL[0] / 3;
+ break;
+ case 4:
+ sysInfo->freqPME = freqCC_PLL[0] / 4;
+ break;
+ case 6:
+ sysInfo->freqPME = freqCC_PLL[1] / 2;
+ break;
+ case 7:
+ sysInfo->freqPME = freqCC_PLL[1] / 3;
+ break;
+ default:
+ printf("Error: Unknown PME clock select!\n");
+ case 0:
+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqFMan[0] = freqCC_PLL[3];
+ break;
+ case 2:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+ break;
+ case 3:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+ break;
+ case 4:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+ break;
+ case 6:
+ sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+ break;
+ case 7:
+ sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan1 clock select!\n");
+ case 0:
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#if (CONFIG_SYS_NUM_FMAN) == 2
+#define FM2_CLK_SEL 0x00000038
+#define FM2_CLK_SHIFT 3
+ rcw_tmp = in_be32(&gur->rcwsr[15]);
+ switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqFMan[1] = freqCC_PLL[4];
+ break;
+ case 2:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+ break;
+ case 3:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+ break;
+ case 4:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+ break;
+ case 6:
+ sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+ break;
+ case 7:
+ sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan2 clock select!\n");
+ case 0:
+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#endif /* CONFIG_SYS_NUM_FMAN == 2 */
+#endif /* CONFIG_SYS_DPAA_FMAN */
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+ sysInfo->freqProcessor[cpu] =
+ freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+ }
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
#define FM2_CLK_SEL 0x20000000
#define HWA_ASYNC_DIV 0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL 1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL 2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL 2
#else
@@ -151,11 +285,10 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#endif
-#else
- uint plat_ratio,e500_ratio,half_freqSystemBus;
-#if defined(CONFIG_FSL_LBC)
- uint lcrr_div;
-#endif
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else /* CONFIG_FSL_CORENET */
+ uint plat_ratio, e500_ratio, half_freqSystemBus;
int i;
#ifdef CONFIG_QE
__maybe_unused u32 qe_ratio;
@@ -202,6 +335,7 @@ void get_sys_info (sys_info_t * sysInfo)
#endif /* CONFIG_FSL_CORENET */
#if defined(CONFIG_FSL_LBC)
+ uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -228,6 +362,13 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqLocalBus = lcrr_div;
}
#endif
+
+#if defined(CONFIG_FSL_IFC)
+ ccr = in_be32(&ifc_regs->ifc_ccr);
+ ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9e04257d2c..ac17f9d3ca 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -169,7 +169,7 @@ l2_disabled:
*
*/
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
li r2,(32 + 0)
mtspr L1CSR2,r2
@@ -211,6 +211,77 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
+ .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
+ lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+ mtspr MAS0, \scratch
+ lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+ mtspr MAS3, \scratch
+ lis \scratch, \phy_high@h
+ ori \scratch, \scratch, \phy_high@l
+ mtspr MAS7, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
+ lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+ mtspr MAS0, \scratch
+ lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+ mtspr MAS3, \scratch
+ lis \scratch, \phy_high@h
+ ori \scratch, \scratch, \phy_high@l
+ mtspr MAS7, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro delete_tlb1_entry esel scratch
+ lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+ mtspr MAS0, \scratch
+ li \scratch, 0
+ mtspr MAS1, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro delete_tlb0_entry esel epn wimg scratch
+ lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+ mtspr MAS0, \scratch
+ li \scratch, 0
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
@@ -220,61 +291,35 @@ l2_disabled:
* in AS1.
*/
- lis r6,FSL_BOOKE_MAS0(1,
- CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(1,
- CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
-
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
- (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
- (MAS2_I|MAS2_G))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_4M, \
+ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
- /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
- lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
- (MAS2_I))@l
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_256K, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I, \
+ CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- tlbwe
- isync
#endif
/*
@@ -392,27 +437,11 @@ l2_disabled:
*/
/* create a temp mapping TLB0[0] for LBCR */
- lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
-
- lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
-
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
+ CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
+ 0, r6
/* Set LBCR register */
lis r4,CONFIG_SYS_LBCR_ADDR@h
@@ -551,49 +580,22 @@ create_ccsr_new_tlb:
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
- lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
- lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
- ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
- lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
- ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
- ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
- mtspr MAS7, r7
-#endif
- mtspr MAS0, r0
- mtspr MAS1, r1
- mtspr MAS2, r2
- mtspr MAS3, r3
- isync
- msync
- tlbwe
-
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
/*
* Create a TLB for the current location of CCSR. Register R9 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
- lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
- lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
- ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- li r7, 0 /* The default CCSR address is always a 32-bit number */
- mtspr MAS7, r7
-#endif
- mtspr MAS0, r0
- /* MAS1 is the same as above */
- mtspr MAS2, r2
- mtspr MAS3, r3
- isync
- msync
- tlbwe
+ create_tlb0_entry 1, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
+ 0, r3 /* The default CCSR address is always a 32-bit number */
+
/*
* We have a TLB for what we think is the current (old) CCSR. Let's
@@ -743,29 +745,46 @@ write_new_ccsrbar:
/* Delete the temporary TLBs */
delete_temp_tlbs:
- lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
- li r1, 0
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
- mtspr MAS0, r0
- mtspr MAS1, r1
- mtspr MAS2, r2
- isync
- msync
- tlbwe
+ delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+ delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
- lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
- mtspr MAS0, r0
- mtspr MAS2, r2
- isync
- msync
- tlbwe
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+create_ccsr_l2_tlb:
+ /*
+ * Create a TLB for the MMR location of CCSR
+ * to access L2CSR0 register
+ */
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+
+enable_l2_cluster_l2:
+ /* enable L2 cache */
+ lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
+ ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+ li r4, 33 /* stash id */
+ stw r4, 4(r3)
+ lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
+ ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
+ sync
+ stw r4, 0(r3) /* invalidate L2 */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ bne 1b
+ lis r4, L2CSR0_L2E@h
+ sync
+ stw r4, 0(r3) /* eanble L2 */
+delete_ccsr_l2_tlb:
+ delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
@@ -1019,83 +1038,50 @@ create_init_ram_area:
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS=1 to the 4M boot window */
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_4M, \
+ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
-
- /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
- lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS = 1 for Flash mapping
* created by PBL for ISBC code
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
* image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
-
/* create a temp mapping in AS=1 to the stack */
- lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
-
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
-
#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
- li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
- mtspr MAS7,r10
+ create_tlb1_entry 14, \
+ 1, BOOKE_PAGESZ_16K, \
+ CONFIG_SYS_INIT_RAM_ADDR, 0, \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+
#else
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 14, \
+ 1, BOOKE_PAGESZ_16K, \
+ CONFIG_SYS_INIT_RAM_ADDR, 0, \
+ CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
-
lis r6,MSR_IS|MSR_DS|MSR_DE@h
ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
lis r7,switch_as@h
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
new file mode 100644
index 0000000000..a8f16b1cd6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 4),
+ SET_QP_INFO(10, 36, 1, 4),
+ SET_QP_INFO(11, 37, 1, 5),
+ SET_QP_INFO(12, 38, 1, 5),
+ SET_QP_INFO(13, 39, 1, 6),
+ SET_QP_INFO(14, 40, 1, 6),
+ SET_QP_INFO(15, 41, 1, 7),
+ SET_QP_INFO(16, 42, 1, 7),
+ SET_QP_INFO(17, 43, 1, 8),
+ SET_QP_INFO(18, 44, 1, 8),
+ SET_QP_INFO(19, 45, 1, 9),
+ SET_QP_INFO(20, 46, 1, 9),
+ SET_QP_INFO(21, 47, 1, 10),
+ SET_QP_INFO(22, 48, 1, 10),
+ SET_QP_INFO(23, 49, 1, 11),
+ SET_QP_INFO(24, 50, 1, 11),
+ SET_QP_INFO(65, 89, 1, 0),
+ SET_QP_INFO(66, 90, 1, 0),
+ SET_QP_INFO(67, 91, 1, 1),
+ SET_QP_INFO(68, 92, 1, 1),
+ SET_QP_INFO(69, 93, 1, 2),
+ SET_QP_INFO(70, 94, 1, 2),
+ SET_QP_INFO(71, 95, 1, 3),
+ SET_QP_INFO(72, 96, 1, 3),
+ SET_QP_INFO(73, 97, 1, 4),
+ SET_QP_INFO(74, 98, 1, 4),
+ SET_QP_INFO(75, 99, 1, 5),
+ SET_QP_INFO(76, 100, 1, 5),
+ SET_QP_INFO(77, 101, 1, 6),
+ SET_QP_INFO(78, 102, 1, 6),
+ SET_QP_INFO(79, 103, 1, 7),
+ SET_QP_INFO(80, 104, 1, 7),
+ SET_QP_INFO(81, 105, 1, 8),
+ SET_QP_INFO(82, 106, 1, 8),
+ SET_QP_INFO(83, 107, 1, 9),
+ SET_QP_INFO(84, 108, 1, 9),
+ SET_QP_INFO(85, 109, 1, 10),
+ SET_QP_INFO(86, 110, 1, 10),
+ SET_QP_INFO(87, 111, 1, 11),
+ SET_QP_INFO(88, 112, 1, 11),
+ SET_QP_INFO(25, 51, 1, 0),
+ SET_QP_INFO(26, 52, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+ SET_SRIO_LIODN_1(1, 307),
+ SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+ SET_SATA_LIODN(1, 555),
+ SET_SATA_LIODN(2, 556),
+
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+ SET_DMA_LIODN(1, 147),
+ SET_DMA_LIODN(2, 227),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+ SET_PMAN_LIODN(1, 513),
+ SET_PMAN_LIODN(2, 514),
+ SET_PMAN_LIODN(3, 515),
+#endif
+
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(2, 0, 88),
+ SET_FMAN_RX_1G_LIODN(2, 1, 89),
+ SET_FMAN_RX_1G_LIODN(2, 2, 90),
+ SET_FMAN_RX_1G_LIODN(2, 3, 91),
+ SET_FMAN_RX_1G_LIODN(2, 4, 92),
+ SET_FMAN_RX_1G_LIODN(2, 5, 93),
+ SET_FMAN_RX_10G_LIODN(2, 0, 94),
+ SET_FMAN_RX_10G_LIODN(2, 1, 95),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+ /* Set RMan block 0-3 liodn offset */
+ SET_RMAN_LIODN(0, 678),
+ SET_RMAN_LIODN(1, 679),
+ SET_RMAN_LIODN(2, 680),
+ SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+ [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
+#endif
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
new file mode 100644
index 0000000000..102defa560
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10, XAUI_FM2_MAC10,
+ XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
+ {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {38, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {}
+};
+static struct serdes_config serdes3_cfg_tbl[] = {
+ /* SerDes 3 */
+ {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+ {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+ {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+ {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2}},
+ {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2}},
+ {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {}
+};
+static struct serdes_config serdes4_cfg_tbl[] = {
+ /* SerDes 4 */
+ {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+ {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+ {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
+ {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+ {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
+ {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+ serdes3_cfg_tbl,
+ serdes4_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a607e..a548dec9a7 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -249,7 +249,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
- unsigned int wimge = 0;
+ unsigned int wimge = MAS2_M;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam;
u64 size, memsize = (u64)memsize_in_meg << 20;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index 8ba9399169..f7c4a22d29 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -70,9 +70,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 668158f702..46dbaed1e0 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -53,6 +53,10 @@ SECTIONS
}
_edata = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index efe34b774d..4a40a1f51b 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -77,9 +77,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 61f5110b7d..2f955fe930 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_MP
int off;
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
index 30c99ebc56..de705f0ae8 100644
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ b/arch/powerpc/cpu/mpc86xx/mp.c
@@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[])
return 1;
}
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
{
+ if (pagesize)
+ *pagesize = 4096;
+
/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
if ((u64)gd->ram_size > 0xfffff000)
return (0xfff00000);
@@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void)
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
/* tell u-boot we stole a page */
lmb_reserve(lmb, bootpg, 4096);
@@ -115,7 +118,7 @@ void setup_mp(void)
{
extern ulong __secondary_start_page;
ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
u32 bootpg_va;
if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
index 121e529876..8bfadf28dc 100644
--- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds
@@ -64,9 +64,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 78a8f926b3..2c487cac20 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -73,6 +73,17 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
+ CPU_TYPE_ENTRY(P5021, P5021, 2),
+ CPU_TYPE_ENTRY(P5040, P5040, 4),
+ CPU_TYPE_ENTRY(T4240, T4240, 0),
+ CPU_TYPE_ENTRY(T4120, T4120, 0),
+ CPU_TYPE_ENTRY(B4860, B4860, 0),
+ CPU_TYPE_ENTRY(G4860, G4860, 0),
+ CPU_TYPE_ENTRY(G4060, G4060, 0),
+ CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(G4440, G4440, 0),
+ CPU_TYPE_ENTRY(B4420, B4420, 0),
+ CPU_TYPE_ENTRY(B4220, B4220, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
#elif defined(CONFIG_MPC86xx)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2592873c9f..5928eb8806 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -229,6 +229,26 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
#if !defined(CONFIG_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+ if (dimm_params[0].n_ranks == 4)
+ return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+ if ((dimm_params[0].n_ranks == 2) &&
+ (dimm_params[1].n_ranks == 2))
+ return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (dimm_params[0].n_ranks == 4)
+ return 1;
+#endif
+#endif
+ return 0;
+}
+
/*
* DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
*
@@ -236,7 +256,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
* dreams up non-zero default values to be backwards compatible.
*/
static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts)
+ const memctl_options_t *popts,
+ const dimm_params_t *dimm_params)
{
unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
@@ -266,7 +287,18 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4;
/* set the turnaround time */
- trwt_mclk = 1;
+
+ /*
+ * for single quad-rank DIMM and two dual-rank DIMMs
+ * to avoid ODT overlap
+ */
+ if (avoid_odt_overlap(dimm_params)) {
+ twwt_mclk = 2;
+ trrt_mclk = 1;
+ }
+ /* for faster clock, need more time for data setup */
+ trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
twrt_mclk = 1;
@@ -451,8 +483,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
| ((caslat_ctrl & 0xF) << 16)
| ((refrec_ctrl & 0xF) << 12)
| ((wrrec_mclk & 0x0F) << 8)
- | ((acttoact_mclk & 0x07) << 4)
- | ((wrtord_mclk & 0x07) << 0)
+ | ((acttoact_mclk & 0x0F) << 4)
+ | ((wrtord_mclk & 0x0F) << 0)
);
debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
}
@@ -659,6 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
unsigned int dqs_cfg; /* DQS configuration */
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
+ unsigned int slow = 0; /* DDR will be run less than 1250 */
unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
unsigned int ap_en; /* Address Parity Enable */
unsigned int d_init; /* DRAM data initialization */
@@ -692,6 +725,10 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
obc_cfg = 0;
#endif
+#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
+ slow = get_ddr_freq(0) < 1249000000;
+#endif
+
if (popts->registered_dimm_en) {
rcw_en = 1;
ap_en = popts->ap_en;
@@ -720,6 +757,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((dqs_cfg & 0x3) << 26)
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
+ | ((slow & 1) << 11)
| (qd_en << 9)
| (unq_mrs_en << 8)
| ((obc_cfg & 0x1) << 6)
@@ -1347,6 +1385,11 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
| ((wrlvl_start & 0x1F) << 0)
);
debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
+ ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
+ debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
+ ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
+ debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
+
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
@@ -1370,6 +1413,12 @@ static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
}
+static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+ ddr->ddr_cdr2 = popts->ddr_cdr2;
+ debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
+}
+
unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
@@ -1466,7 +1515,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
break;
}
sa = common_dimm->base_address;
- ea = common_dimm->total_mem - 1;
+ ea = sa + common_dimm->total_mem - 1;
} else if (!popts->memctl_interleaving) {
/*
* If memory interleaving between controllers is NOT
@@ -1480,7 +1529,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
sa = common_dimm->base_address;
- ea = common_dimm->total_mem - 1;
+ ea = sa + common_dimm->total_mem - 1;
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
if ((i >= 2) && (dimm_number == 0)) {
@@ -1537,17 +1586,19 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
sa >>= 24;
ea >>= 24;
- ddr->cs[i].bnds = (0
- | ((sa & 0xFFF) << 16) /* starting address MSB */
- | ((ea & 0xFFF) << 0) /* ending address MSB */
- );
+ if (cs_en) {
+ ddr->cs[i].bnds = (0
+ | ((sa & 0xFFF) << 16)/* starting address MSB */
+ | ((ea & 0xFFF) << 0) /* ending address MSB */
+ );
+ } else {
+ debug("FSLDDR: setting bnds to 0 for inactive CS\n");
+ ddr->cs[i].bnds = 0;
+ }
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
- if (cs_en) {
- set_csn_config(dimm_number, i, ddr, popts, dimm_params);
- set_csn_config_2(i, ddr);
- } else
- debug("CS%d is disabled.\n", i);
+ set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+ set_csn_config_2(i, ddr);
}
/*
@@ -1560,7 +1611,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1)
- set_timing_cfg_0(ddr, popts);
+ set_timing_cfg_0(ddr, popts, dimm_params);
#endif
set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
@@ -1569,6 +1620,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
cas_latency, additive_latency);
set_ddr_cdr1(ddr, popts);
+ set_ddr_cdr2(ddr, popts);
set_ddr_sdram_cfg(ddr, popts, common_dimm);
ip_rev = fsl_ddr_get_version();
if (ip_rev > 0x40400)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index f59d1051bf..cb71f94ba1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -452,6 +452,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS(ddr_cdr1),
+ CTRL_OPTIONS(ddr_cdr2),
CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
CTRL_OPTIONS(tFAW_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
@@ -518,6 +520,8 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(timing_cfg_5),
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
+ CFG_REGS(ddr_wrlvl_cntl_2),
+ CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
@@ -525,6 +529,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
CFG_REGS(ddr_cdr2),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
+ CFG_REGS(ddr_eor),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -584,6 +589,8 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(timing_cfg_5),
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
+ CFG_REGS(ddr_wrlvl_cntl_2),
+ CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
@@ -593,7 +600,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
CFG_REGS(err_int_en),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_sdram_rcw_2),
-
+ CFG_REGS(ddr_eor),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -689,6 +696,8 @@ static void print_memctl_options(const memctl_options_t *popts)
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS_HEX(ddr_cdr1),
+ CTRL_OPTIONS_HEX(ddr_cdr2),
CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
CTRL_OPTIONS(tFAW_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
@@ -1597,6 +1606,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
* doesn't return
*/
do_reset(NULL, 0, 0, NULL);
+ printf("Reset didn't work\n");
}
if (strcmp(argv[0], "recompute") == 0) {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 03a784cd47..6a1f4e4e38 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -76,7 +76,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
unsigned int
compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
- unsigned int number_of_dimms)
+ const unsigned int number_of_dimms)
{
unsigned int i, j;
@@ -126,13 +126,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
temp1++;
continue;
}
+
+ /*
+ * check if quad-rank DIMM is plugged if
+ * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+ * Only the board with proper design is capable
+ */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[i].n_ranks == 4 && \
CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
printf("Found Quad-rank DIMM, not able to support.");
temp1++;
continue;
}
-
+#endif
/*
* Find minimum tCKmax_ps to find fastest slow speed,
* i.e., this is the slowest the whole system can go.
@@ -236,11 +243,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
if (outpdimm->all_DIMMs_registered)
for (j = 0; j < 16; j++) {
outpdimm->rcw[j] = dimm_params[0].rcw[j];
- for (i = 1; i < number_of_dimms; i++)
+ for (i = 1; i < number_of_dimms; i++) {
+ if (!dimm_params[i].n_ranks)
+ continue;
if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
temp1 = 1;
break;
}
+ }
}
if (temp1 != 0)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index b47268c20e..d6b73c7af1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -77,7 +77,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
sizeof(generic_spd_eeprom_t));
if (ret) {
- printf("DDR: failed to read SPD from address %u\n", i2c_address);
+ if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+ SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+ SPD_EEPROM_ADDRESS1
+#endif
+ ) {
+ printf("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ } else {
+ debug("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ }
memset(spd, 0, sizeof(generic_spd_eeprom_t));
}
}
@@ -526,6 +538,17 @@ phys_size_t fsl_ddr_sdram(void)
#endif
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+ /* setup 3-way interleaving before enabling DDRC */
+ switch (info.memctl_opts[0].memctl_interleaving_mode) {
+ case FSL_DDR_3WAY_1KB_INTERLEAVING:
+ case FSL_DDR_3WAY_4KB_INTERLEAVING:
+ case FSL_DDR_3WAY_8KB_INTERLEAVING:
+ fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
+ break;
+ default:
+ break;
+ }
+
/* Program configuration registers. */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
debug("Programming controller %u\n", i);
@@ -561,7 +584,6 @@ phys_size_t fsl_ddr_sdram(void)
case FSL_DDR_3WAY_8KB_INTERLEAVING:
law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
if (i == 0) {
- fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 13e4825274..2f13b8fd93 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -474,6 +474,34 @@ static const struct dynamic_odt odt_unknown[4] = {
}
};
#endif
+
+/*
+ * Automatically seleect bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
+{
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+ if (pdimm[0].n_ranks == 4)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+ else if (pdimm[0].n_ranks == 2)
+ return FSL_DDR_CS0_CS1;
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (pdimm[0].n_ranks == 4)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+#endif
+ if (pdimm[0].n_ranks == 2) {
+ if (pdimm[1].n_ranks == 2)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+ else
+ return FSL_DDR_CS0_CS1;
+ }
+#endif
+ return 0;
+}
+
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
@@ -510,6 +538,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
}
} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ case 4:
+ pdodt = single_Q;
+ if (pdimm[1].n_ranks)
+ printf("Error: Quad- and Dual-rank DIMMs "
+ "cannot be used together\n");
+ break;
+#endif
case 2:
switch (pdimm[1].n_ranks) {
case 2:
@@ -900,6 +936,9 @@ done:
else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
"cs0_cs1_cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "auto", buf))
+ popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
else
printf("hwconfig has unrecognized parameter for bank_intlv.\n");
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
@@ -912,6 +951,10 @@ done:
"interleaving disabled!\n", ctrl_num);
}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (pdimm[0].n_ranks == 4)
+ break;
+#endif
if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for "
@@ -1063,7 +1106,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
- if (j != k) {
+ if (j && (j != k)) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
pinfo->memctl_opts[i].memctl_interleaving = 0;
printf("Not all controllers have compatible "
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 664ad09298..940ffff773 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size)
#endif
}
+u32 fsl_ddr_get_intl3r(void)
+{
+ u32 val = 0;
+#ifdef CONFIG_E6500
+ u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+ val = *mcintl3r;
+#endif
+ return val;
+}
+
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC83xx)
@@ -140,6 +150,18 @@ void board_add_ram_info(int use_default)
uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
int cas_lat;
+#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+ if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+ sdram_cfg = in_be32(&ddr->sdram_cfg);
+ }
+#endif
+#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+ if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+ sdram_cfg = in_be32(&ddr->sdram_cfg);
+ }
+#endif
puts(" (DDR");
switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
SDRAM_CFG_SDRAM_TYPE_SHIFT) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 32ab050962..68db8e2448 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -139,6 +139,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
const char *phys[] = { "ulpi", "utmi" };
const char *mode = NULL;
const char *phy_type = NULL;
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
char usb1_defined = 0;
int usb_mode_off = -1;
int usb_phy_off = -1;
@@ -156,6 +158,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
break;
}
}
+
for (j = 0; j < ARRAY_SIZE(phys); j++) {
if (hwconfig_subarg_cmp(str, "phy_type",
phys[j])) {
@@ -163,31 +166,46 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
break;
}
}
- if (mode_idx >= 0) {
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- modes[mode_idx], NULL, usb_mode_off);
- if (usb_mode_off < 0)
- return;
- }
- if (phy_idx >= 0) {
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, phys[phy_idx], usb_phy_off);
- if (usb_phy_off < 0)
- return;
- }
+
+ dr_mode_type = modes[mode_idx];
+ dr_phy_type = phys[phy_idx];
+
+ /* use usb_dr_mode and usb_phy_type if
+ usb1_defined = 0; these variables are to
+ be deprecated */
if (!strcmp(str, "usb1"))
usb1_defined = 1;
- if (mode_idx < 0 && phy_idx < 0)
+
+ if (mode_idx < 0 && phy_idx < 0) {
printf("WARNING: invalid phy or mode\n");
+ return;
+ }
}
+
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ dr_mode_type, NULL, usb_mode_off);
+
+ if (usb_mode_off < 0)
+ return;
+
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, dr_phy_type, usb_phy_off);
+
+ if (usb_phy_off < 0)
+ return;
}
+
if (!usb1_defined) {
int usb_off = -1;
mode = getenv("usb_dr_mode");
phy_type = getenv("usb_phy_type");
- if (!mode && !phy_type)
- return;
- fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
+ if (mode || phy_type) {
+ printf("WARNING: usb_dr_mode and usb_phy_type "
+ "are to be deprecated soon. Use "
+ "hwconfig to set these values instead!!\n");
+ fdt_fixup_usb_mode_phy_type(blob, mode,
+ phy_type, usb_off);
+ }
}
}
#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0cb65b32e4..6e6f7dcc3f 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -22,7 +22,9 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
+#include <asm/errno.h>
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -31,10 +33,16 @@
#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
#define SRIO_LCSBA1CSR 0x60000000
+#endif
#if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
@@ -52,16 +60,206 @@
#error "No defines for DEVDISR_SRIO"
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+/*
+ * Erratum A-004034
+ * Affects: SRIO
+ * Description: During port initialization, the SRIO port performs
+ * lane synchronization (detecting valid symbols on a lane) and
+ * lane alignment (coordinating multiple lanes to receive valid data
+ * across lanes). Internal errors in lane synchronization and lane
+ * alignment may cause failure to achieve link initialization at
+ * the configured port width.
+ * An SRIO port configured as a 4x port may see one of these scenarios:
+ * 1. One or more lanes fails to achieve lane synchronization. Depending
+ * on which lanes fail, this may result in downtraining from 4x to 1x
+ * on lane 0, 4x to 1x on lane R (redundant lane).
+ * 2. The link may fail to achieve lane alignment as a 4x, even though
+ * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
+ * An SRIO port configured as a 1x port may fail to complete port
+ * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
+ * Impact: SRIO port may downtrain to 1x, or may fail to complete
+ * link initialization. Once a port completes link initialization
+ * successfully, it will operate normally.
+ */
+static int srio_erratum_a004034(u8 port)
+{
+ serdes_corenet_t *srds_regs;
+ u32 conf_lane;
+ u32 init_lane;
+ int idx, first, last;
+ u32 i;
+ unsigned long long end_tick;
+ struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
+ >> (12 - port * 4)) & 0x3;
+ init_lane = (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr) >> 27) & 0x7;
+
+ /*
+ * Start a counter set to ~2 ms after the SERDES reset is
+ * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
+ * corresponding to the SERDES bank/PLL for the SRIO port).
+ */
+ if (in_be32((void *)&srds_regs->bank[0].rstctl)
+ & SRDS_RSTCTL_RSTDONE) {
+ /*
+ * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
+ * PO=1 or the counter expires. If the counter expires, the
+ * port has failed initialization: go to recover steps. If PO=1
+ * and the desired port width is 1x, go to normal steps. If
+ * PO = 1 and the desired port width is 4x, go to recover steps.
+ */
+ end_tick = usec2ticks(2000) + get_ticks();
+ do {
+ if (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pescsr) & 0x2) {
+ if (conf_lane == 0x1)
+ goto host_ok;
+ else {
+ if (init_lane == 0x2)
+ goto host_ok;
+ else
+ break;
+ }
+ }
+ } while (end_tick > get_ticks());
+
+ /* recover at most 3 times */
+ for (i = 0; i < 3; i++) {
+ /* Set SRIO PnCCSR[PD]=1 */
+ setbits_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr,
+ 0x800000);
+ /*
+ * Set SRIO PnPCR[OBDEN] on the host to
+ * enable the discarding of any pending packets.
+ */
+ setbits_be32((void *)&srio_regs->impl.port[port].pcr,
+ 0x04);
+ /* Wait 50 us */
+ udelay(50);
+ /* Run sync command */
+ isync();
+
+ if (port)
+ first = serdes_get_first_lane(SRIO2);
+ else
+ first = serdes_get_first_lane(SRIO1);
+ if (unlikely(first < 0))
+ return -ENODEV;
+ if (conf_lane == 0x1)
+ last = first;
+ else
+ last = first + 3;
+ /*
+ * Set SERDES BnGCRm0[RRST]=0 for each SRIO
+ * bank n and lane m.
+ */
+ for (idx = first; idx <= last; idx++)
+ clrbits_be32(&srds_regs->lane[idx].gcr0,
+ SRDS_GCR0_RRST);
+ /*
+ * Read SERDES BnGCRm0 for each SRIO
+ * bank n and lane m
+ */
+ for (idx = first; idx <= last; idx++)
+ in_be32(&srds_regs->lane[idx].gcr0);
+ /* Run sync command */
+ isync();
+ /* Wait >= 100 ns */
+ udelay(1);
+ /*
+ * Set SERDES BnGCRm0[RRST]=1 for each SRIO
+ * bank n and lane m.
+ */
+ for (idx = first; idx <= last; idx++)
+ setbits_be32(&srds_regs->lane[idx].gcr0,
+ SRDS_GCR0_RRST);
+ /*
+ * Read SERDES BnGCRm0 for each SRIO
+ * bank n and lane m
+ */
+ for (idx = first; idx <= last; idx++)
+ in_be32(&srds_regs->lane[idx].gcr0);
+ /* Run sync command */
+ isync();
+ /* Wait >= 300 ns */
+ udelay(1);
+
+ /* Write 1 to clear all bits in SRIO PnSLCSR */
+ out_be32((void *)&srio_regs->impl.port[port].slcsr,
+ 0xffffffff);
+ /* Clear SRIO PnPCR[OBDEN] on the host */
+ clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
+ 0x04);
+ /* Set SRIO PnCCSR[PD]=0 */
+ clrbits_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr,
+ 0x800000);
+ /* Wait >= 24 ms */
+ udelay(24000);
+ /* Poll the state of the port again */
+ init_lane =
+ (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr) >> 27) & 0x7;
+ if (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pescsr) & 0x2) {
+ if (conf_lane == 0x1)
+ goto host_ok;
+ else {
+ if (init_lane == 0x2)
+ goto host_ok;
+ }
+ }
+ if (i == 2)
+ return -ENODEV;
+ }
+ } else
+ return -ENODEV;
+
+host_ok:
+ /* Poll PnESCSR[OES] on the host until it is clear */
+ end_tick = usec2ticks(1000000) + get_ticks();
+ do {
+ if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
+ & 0x10000)) {
+ out_be32(((void *)&srio_regs->lp_serial
+ .port[port].pescsr), 0xffffffff);
+ out_be32(((void *)&srio_regs->phys_err
+ .port[port].edcsr), 0);
+ out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
+ return 0;
+ }
+ } while (end_tick > get_ticks());
+
+ return -ENODEV;
+}
+#endif
+
void srio_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
int srio1_used = 0, srio2_used = 0;
+ u32 *devdisr;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ devdisr = &gur->devdisr3;
+#else
+ devdisr = &gur->devdisr;
+#endif
if (is_serdes_configured(SRIO1)) {
set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
LAW_TRGT_IF_RIO_1);
srio1_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ if (srio_erratum_a004034(0) < 0)
+ printf("SRIO1: enabled but port error\n");
+ else
+#endif
printf("SRIO1: enabled\n");
} else {
printf("SRIO1: disabled\n");
@@ -73,7 +271,13 @@ void srio_init(void)
law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
LAW_TRGT_IF_RIO_2);
srio2_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ if (srio_erratum_a004034(1) < 0)
+ printf("SRIO2: enabled but port error\n");
+ else
+#endif
printf("SRIO2: enabled\n");
+
} else {
printf("SRIO2: disabled\n");
}
@@ -82,20 +286,20 @@ void srio_init(void)
#ifdef CONFIG_FSL_CORENET
/* On FSL_CORENET devices we can disable individual ports */
if (!srio1_used)
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+ setbits_be32(devdisr, _DEVDISR_SRIO1);
if (!srio2_used)
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+ setbits_be32(devdisr, _DEVDISR_SRIO2);
#endif
/* neither port is used - disable everything */
if (!srio1_used && !srio2_used) {
- setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
- setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
- setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+ setbits_be32(devdisr, _DEVDISR_SRIO1);
+ setbits_be32(devdisr, _DEVDISR_SRIO2);
+ setbits_be32(devdisr, _DEVDISR_RMU);
}
}
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index 2466b79594..a96ddd5577 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -78,9 +78,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index aa27741a92..03baaee1b7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -27,6 +27,8 @@
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
#endif
+#define FSL_DDR_VER_4_7 47
+
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
@@ -311,6 +313,7 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -331,6 +334,7 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -338,8 +342,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -360,6 +366,7 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -367,8 +374,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -389,7 +398,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -398,6 +407,7 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -406,8 +416,11 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -426,12 +439,43 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_DTSEC 5
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_ERRATUM_A004699
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1
@@ -445,6 +489,63 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 12
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
+#define CONFIG_SYS_NUM_FM2_10GEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
+#elif defined(CONFIG_PPC_B4860)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
#else
#error Processor type not defined for this platform
#endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index e271342f08..640d3297d6 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
+#define SDRAM_CS_CONFIG_EN 0x80000000
+
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
@@ -96,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_SHIFT 19
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_16_BE 0x00100000
#define SDRAM_CFG_8_BE 0x00040000
@@ -145,6 +148,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_ODT_SHIFT 17
+#define DDR_CDR1_ODT_MASK 0x6
+#define DDR_CDR2_ODT_MASK 0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_120ohm 0x1
+#define DDR_CDR_ODT_180ohm 0x2
+#define DDR_CDR_ODT_75ohm 0x3
+#define DDR_CDR_ODT_110ohm 0x4
+#define DDR_CDR_ODT_60hm 0x5
+#define DDR_CDR_ODT_70ohm 0x6
+#define DDR_CDR_ODT_47ohm 0x7
+#else
+#define DDR_CDR_ODT_75ohm 0x0
+#define DDR_CDR_ODT_55ohm 0x1
+#define DDR_CDR_ODT_60ohm 0x2
+#define DDR_CDR_ODT_50ohm 0x3
+#define DDR_CDR_ODT_150ohm 0x4
+#define DDR_CDR_ODT_43ohm 0x5
+#define DDR_CDR_ODT_120ohm 0x6
+#endif
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
@@ -177,6 +205,8 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int timing_cfg_5;
unsigned int ddr_zq_cntl;
unsigned int ddr_wrlvl_cntl;
+ unsigned int ddr_wrlvl_cntl_2;
+ unsigned int ddr_wrlvl_cntl_3;
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
@@ -262,6 +292,8 @@ typedef struct memctl_options_s {
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
+ unsigned int wrlvl_ctl_2;
+ unsigned int wrlvl_ctl_3;
unsigned int half_strength_driver_enable;
unsigned int twoT_en;
@@ -288,6 +320,7 @@ typedef struct memctl_options_s {
unsigned int rcw_2;
/* control register 1 */
unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
unsigned int trwt_override;
unsigned int trwt; /* read-to-write turnaround */
@@ -298,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void);
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
+u32 fsl_ddr_get_intl3r(void);
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
index 2c0c9bc2f2..299daca132 100644
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -423,6 +423,14 @@ typedef struct fm_10gec_mdio {
u8 res[4*1024];
} fm_10gec_mdio_t;
+typedef struct fm_memac {
+ u8 res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+ u8 res[4*1024];
+} fm_memac_mdio_t;
+
typedef struct fm_1588 {
u8 res[4*1024];
} fm_1588_t;
@@ -446,6 +454,14 @@ typedef struct ccsr_fman {
u8 res1[8*1024];
fm_soft_parser_t fm_soft_parser;
u8 res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+ struct {
+ fm_memac_t fm_memac;
+ fm_memac_mdio_t fm_memac_mdio;
+ } memac[10];
+ u8 res4[32*1024];
+ fm_memac_mdio_t fm_dedicated_mdio[2];
+#else
struct {
fm_dtsec_t fm_dtesc;
fm_mdio_t fm_mdio;
@@ -455,6 +471,7 @@ typedef struct ccsr_fman {
fm_10gec_mdio_t fm_10gec_mdio;
} mac_10g[1];
u8 res4[48*1024];
+#endif
fm_1588_t fm_1588;
u8 res5[4*1024];
} ccsr_fman_t;
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b80da..d759de975e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
@@ -118,6 +123,12 @@ extern void fdt_fixup_liodn(void *blob);
CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define SET_PMAN_LIODN(num, liodn) \
+ SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+ offsetof(struct ccsr_pman, ppa1) + \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
@@ -184,11 +195,13 @@ extern void fdt_fixup_liodn(void *blob);
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
extern struct liodn_id_table rman_liodn_tbl[];
extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
-extern int srio_liodn_tbl_sz;
extern int rman_liodn_tbl_sz;
#endif
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h
new file mode 100644
index 0000000000..d6b60e65bc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MEMAC_H__
+#define __MEMAC_H__
+
+#include <phy.h>
+
+struct memac {
+ /* memac general control and status registers */
+ u32 res_0[2];
+ u32 command_config; /* Control and configuration register */
+ u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
+ u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
+ u32 maxfrm; /* Maximum frame length register */
+ u32 res_18[5];
+ u32 hashtable_ctrl; /* Hash table control register */
+ u32 res_30[4];
+ u32 ievent; /* Interrupt event register */
+ u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
+ u32 res_48;
+ u32 imask; /* interrupt mask register */
+ u32 res_50;
+ u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
+ u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
+ u32 rx_pause_status; /* Receive pause status register */
+ u32 res_78[2];
+ u32 mac_addr[14]; /* MAC address */
+ u32 lpwake_timer; /* EEE low power wakeup timer register */
+ u32 sleep_timer; /* Transmit EEE Low Power Timer register */
+ u32 res_c0[8];
+ u32 statn_config; /* Statistics configuration register */
+ u32 res_e4[7];
+
+ /* memac statistics counter registers */
+ u32 rx_eoct_l; /* Rx ethernet octests lower */
+ u32 rx_eoct_u; /* Rx ethernet octests upper */
+ u32 rx_oct_l; /* Rx octests lower */
+ u32 rx_oct_u; /* Rx octests upper */
+ u32 rx_align_err_l; /* Rx alignment error lower */
+ u32 rx_align_err_u; /* Rx alignment error upper */
+ u32 rx_pause_frame_l; /* Rx valid pause frame upper */
+ u32 rx_pause_frame_u; /* Rx valid pause frame upper */
+ u32 rx_frame_l; /* Rx frame counter lower */
+ u32 rx_frame_u; /* Rx frame counter upper */
+ u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+ u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+ u32 rx_vlan_l; /* Rx VLAN frame lower */
+ u32 rx_vlan_u; /* Rx VLAN frame upper */
+ u32 rx_err_l; /* Rx frame error lower */
+ u32 rx_err_u; /* Rx frame error upper */
+ u32 rx_uni_l; /* Rx unicast frame lower */
+ u32 rx_uni_u; /* Rx unicast frame upper */
+ u32 rx_multi_l; /* Rx multicast frame lower */
+ u32 rx_multi_u; /* Rx multicast frame upper */
+ u32 rx_brd_l; /* Rx broadcast frame lower */
+ u32 rx_brd_u; /* Rx broadcast frame upper */
+ u32 rx_drop_l; /* Rx dropped packets lower */
+ u32 rx_drop_u; /* Rx dropped packets upper */
+ u32 rx_pkt_l; /* Rx packets lower */
+ u32 rx_pkt_u; /* Rx packets upper */
+ u32 rx_undsz_l; /* Rx undersized packet lower */
+ u32 rx_undsz_u; /* Rx undersized packet upper */
+ u32 rx_64_l; /* Rx 64 oct packet lower */
+ u32 rx_64_u; /* Rx 64 oct packet upper */
+ u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
+ u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
+ u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
+ u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
+ u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
+ u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
+ u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
+ u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
+ u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
+ u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
+ u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
+ u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
+ u32 rx_oversz_l; /* Rx oversized packet lower */
+ u32 rx_oversz_u; /* Rx oversized packet upper */
+ u32 rx_jabber_l; /* Rx Jabber packet lower */
+ u32 rx_jabber_u; /* Rx Jabber packet upper */
+ u32 rx_frag_l; /* Rx Fragment packet lower */
+ u32 rx_frag_u; /* Rx Fragment packet upper */
+ u32 rx_cnp_l; /* Rx control packet lower */
+ u32 rx_cnp_u; /* Rx control packet upper */
+ u32 rx_drntp_l; /* Rx dripped not truncated packet lower */
+ u32 rx_drntp_u; /* Rx dripped not truncated packet upper */
+ u32 res_1d0[0xc];
+
+ u32 tx_eoct_l; /* Tx ethernet octests lower */
+ u32 tx_eoct_u; /* Tx ethernet octests upper */
+ u32 tx_oct_l; /* Tx octests lower */
+ u32 tx_oct_u; /* Tx octests upper */
+ u32 res_210[0x2];
+ u32 tx_pause_frame_l; /* Tx valid pause frame lower */
+ u32 tx_pause_frame_u; /* Tx valid pause frame upper */
+ u32 tx_frame_l; /* Tx frame counter lower */
+ u32 tx_frame_u; /* Tx frame counter upper */
+ u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */
+ u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */
+ u32 tx_vlan_l; /* Tx VLAN frame lower */
+ u32 tx_vlan_u; /* Tx VLAN frame upper */
+ u32 tx_frame_err_l; /* Tx frame error lower */
+ u32 tx_frame_err_u; /* Tx frame error upper */
+ u32 tx_uni_l; /* Tx unicast frame lower */
+ u32 tx_uni_u; /* Tx unicast frame upper */
+ u32 tx_multi_l; /* Tx multicast frame lower */
+ u32 tx_multi_u; /* Tx multicast frame upper */
+ u32 tx_brd_l; /* Tx broadcast frame lower */
+ u32 tx_brd_u; /* Tx broadcast frame upper */
+ u32 res_258[0x2];
+ u32 tx_pkt_l; /* Tx packets lower */
+ u32 tx_pkt_u; /* Tx packets upper */
+ u32 tx_undsz_l; /* Tx undersized packet lower */
+ u32 tx_undsz_u; /* Tx undersized packet upper */
+ u32 tx_64_l; /* Tx 64 oct packet lower */
+ u32 tx_64_u; /* Tx 64 oct packet upper */
+ u32 tx_127_l; /* Tx 65 to 127 oct packet lower */
+ u32 tx_127_u; /* Tx 65 to 127 oct packet upper */
+ u32 tx_255_l; /* Tx 128 to 255 oct packet lower */
+ u32 tx_255_u; /* Tx 128 to 255 oct packet upper */
+ u32 tx_511_l; /* Tx 256 to 511 oct packet lower */
+ u32 tx_511_u; /* Tx 256 to 511 oct packet upper */
+ u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */
+ u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */
+ u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */
+ u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */
+ u32 tx_1519_l; /* Tx 1519 to max oct packet lower */
+ u32 tx_1519_u; /* Tx 1519 to max oct packet upper */
+ u32 res_2a8[0x6];
+ u32 tx_cnp_l; /* Tx control packet lower */
+ u32 tx_cnp_u; /* Tx control packet upper */
+ u32 res_2c8[0xe];
+
+ /* Line interface control register */
+ u32 if_mode; /* interface mode control */
+ u32 if_status; /* interface status */
+ u32 res_308[0xe];
+
+ /* HiGig/2 Register */
+ u32 hg_config; /* HiGig2 control and configuration */
+ u32 res_344[0x3];
+ u32 hg_pause_quanta; /* HiGig2 pause quanta */
+ u32 res_354[0x3];
+ u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */
+ u32 res_364[0x3];
+ u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */
+ u32 hg_fifos_status; /* HiGig2 fifos status */
+ u32 rhm; /* Rx HiGig2 message counter register */
+ u32 thm;/* Tx HiGig2 message counter register */
+ u32 res_380[0x320];
+};
+
+/* COMMAND_CONFIG - command and configuration register */
+#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
+#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
+#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL 0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT 0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT 0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER 0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL 0xffffffff
+
+/* IF_MODE - Interface Mode Register */
+#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
+#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
+#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
+#define IF_MODE_RG 0x00000004 /* 1- RGMII */
+#define IF_MODE_RM 0x00000008 /* 1- RGMII */
+
+#define IF_DEFAULT (IF_GMII)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET 0x8000
+#define PHY_SGMII_CR_RESET_AN 0x0200
+#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN 0x0002
+#define PHY_SGMII_IF_MODE_SGMII 0x0001
+
+struct memac_mdio_controller {
+ u32 res0[0xc];
+ u32 mdio_stat; /* MDIO configuration and status */
+ u32 mdio_ctl; /* MDIO control */
+ u32 mdio_data; /* MDIO data */
+ u32 mdio_addr; /* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY (1 << 0)
+#define MDIO_STAT_RD_ER (1 << 1)
+#define MDIO_STAT_PRE (1 << 5)
+#define MDIO_STAT_ENC (1 << 6)
+#define MDIO_STAT_HOLD_15_CLK (7 << 2)
+
+#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS (1 << 10)
+#define MDIO_CTL_SCAN_EN (1 << 11)
+#define MDIO_CTL_POST_INC (1 << 14)
+#define MDIO_CTL_READ (1 << 15)
+
+#define MDIO_DATA(x) (x & 0xffff)
+#define MDIO_DATA_BSY (1 << 31)
+
+struct fsl_enet_mac;
+
+void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
+ int max_rx_len);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index 5644044eb8..b75f5b975a 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -32,15 +32,16 @@ enum fsl_dpaa_dev {
FSL_HW_PORTAL_FMAN2,
#endif
#endif
-#ifdef CONFIG_SYS_DPAA_PME
FSL_HW_PORTAL_PME,
-#endif
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
FSL_HW_PORTAL_RAID_ENGINE,
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
FSL_HW_PORTAL_RMAN,
#endif
+#ifdef CONFIG_SYS_DPAA_DCE
+ FSL_HW_PORTAL_DCE,
+#endif
};
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 22525f1156..6cd7379c8f 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -37,11 +37,17 @@ enum srds_prtcl {
SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
SGMII_FM2_DTSEC1,
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
SGMII_FM2_DTSEC5,
+ SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC10,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
@@ -49,13 +55,49 @@ enum srds_prtcl {
XAUI_FM1,
XAUI_FM2,
AURORA,
+ CPRI1,
+ CPRI2,
+ CPRI3,
+ CPRI4,
+ CPRI5,
+ CPRI6,
+ CPRI7,
+ CPRI8,
+ XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10,
+ XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10,
+ HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10,
+ HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10,
+ QSGMII_FM1_A, /* A indicates MACs 1-4 */
+ QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
+ QSGMII_FM2_A,
+ QSGMII_FM2_B,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ XFI_FM2_MAC9,
+ XFI_FM2_MAC10,
+ INTERLAKEN,
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+ FSL_SRDS_3 = 2,
+ FSL_SRDS_4 = 3,
};
int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+#else
int serdes_get_first_lane(enum srds_prtcl device);
+#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
void serdes_reset_rx(enum srds_prtcl device);
#endif
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 5a5877fc2c..cb3a80bb2b 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -38,7 +38,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8xx)
@@ -63,6 +63,8 @@ typedef struct global_data {
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ u32 usbdr_clk;
#endif
#if defined (CONFIG_MPC834x)
u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2ba502ad11..679832cd6c 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,12 +73,19 @@ typedef struct sysconf83xx {
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
-#ifdef CONFIG_MPC8308
- u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
+#if defined(CONFIG_MPC830x)
+ u32 sdhccr; /* eSDHC Control Registers for MPC830x */
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
+#if defined(CONFIG_MPC8309)
+ u32 can_dbg_ctrl;
+ u32 res9a;
+ u32 gpr1;
+ u8 res9b[0xAC];
+#else
u8 res9[0xB8];
+#endif
} sysconf83xx_t;
/*
@@ -708,7 +715,11 @@ typedef struct serdes83xx {
* On Chip ROM
*/
typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+ u8 mem[0x8000];
+#else
u8 mem[0x10000];
+#endif
} rom83xx_t;
/*
@@ -972,6 +983,56 @@ typedef struct immap {
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res1[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x200];
+ duart83xx_t duart1[2]; /* DUART */
+ u8 res4[0x500];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res5[0x1000];
+ u8 spi[0x100];
+ u8 res6[0xf00];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
+ u8 res7[0x80];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
+ u8 res8[0x13A00];
+ u8 can1[0x1000]; /* Flexcan 1 */
+ u8 can2[0x1000]; /* Flexcan 2 */
+ u8 res9[0x5000];
+ usb83xx_t usb;
+ u8 res10[0x5000];
+ u8 can3[0x1000]; /* Flexcan 3 */
+ u8 can4[0x1000]; /* Flexcan 4 */
+ u8 res11[0x1000];
+ u8 dma1[0x2000]; /* DMA */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res12[0xC1000];
+ rom83xx_t rom; /* On Chip ROM */
+ u8 res13[0x8000];
+ u8 qe[0x100000]; /* QE block */
+ u8 res14[0xE00000];/* Added for 8309 */
+} immap_t;
#endif
#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7dde..969f726c36 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
u32 cfg_addr; /* PCIX Configuration Addr */
u32 cfg_data; /* PCIX Configuration Data */
u32 int_ack; /* PCIX IRQ Acknowledge */
- u8 res1[3060];
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[3004];
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
@@ -1687,6 +1689,77 @@ typedef struct ccsr_gur {
u32 alt_pmuxcr; /* Alt function signal multiplex control */
u8 res6[12];
u32 devdisr; /* Device disable control */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ u32 devdisr5; /* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL 0x80000000
+#define FSL_CORENET_DEVDISR_PMAN 0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00800000
+#define FSL_CORENET_DEVDISR_DMA2 0x00400000
+#define FSL_CORENET_DEVDISR_USB1 0x00080000
+#define FSL_CORENET_DEVDISR_USB2 0x00040000
+#define FSL_CORENET_DEVDISR_SATA1 0x00008000
+#define FSL_CORENET_DEVDISR_SATA2 0x00004000
+#define FSL_CORENET_DEVDISR_PME 0x00000800
+#define FSL_CORENET_DEVDISR_SEC 0x00000200
+#define FSL_CORENET_DEVDISR_RMU 0x00000080
+#define FSL_CORENET_DEVDISR_DCE 0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
+#define FSL_CORENET_DEVDISR2_FM1 0x00000080
+#define FSL_CORENET_DEVDISR2_FM2 0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
+#define FSL_CORENET_DEVDISR3_LA1 0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
+#define FSL_CORENET_DEVDISR5_IFC 0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
+#define FSL_CORENET_DEVDISR5_DBG 0x00200000
+#define FSL_CORENET_DEVDISR5_NAL 0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
+#define FSL_CORENET_NUM_DEVDISR 5
+#else
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
@@ -1712,7 +1785,6 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR_I2C2 0x00000010
#define FSL_CORENET_DEVDISR_DUART1 0x00000002
#define FSL_CORENET_DEVDISR_DUART2 0x00000001
- u32 devdisr2; /* Device disable control 2 */
#define FSL_CORENET_DEVDISR2_PME 0x80000000
#define FSL_CORENET_DEVDISR2_SEC 0x40000000
#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
@@ -1731,8 +1803,8 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
- u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
+#endif
u8 res8[12];
u32 coredisru; /* uppper portion for support of 64 cores */
u32 coredisrl; /* lower portion for support of 64 cores */
@@ -1755,13 +1827,47 @@ typedef struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#elif defined(CONFIG_PPC_B4860)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
@@ -1784,6 +1890,24 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
#endif
+#if defined(CONFIG_PPC_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
+#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
+#endif
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
+#endif
u8 res18[192];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res19[240];
@@ -1880,34 +2004,38 @@ typedef struct ccsr_gur {
#define rmuliodnr rio1maintliodnr
typedef struct ccsr_clk {
- u32 clkc0csr; /* Core 0 Clock control/status */
+ u32 clkc0csr; /* 0x000 Core 0 Clock control/status */
u8 res1[0x1c];
- u32 clkc1csr; /* Core 1 Clock control/status */
+ u32 clkc1csr; /* 0x020 Core 1 Clock control/status */
u8 res2[0x1c];
- u32 clkc2csr; /* Core 2 Clock control/status */
+ u32 clkc2csr; /* 0x040 Core 2 Clock control/status */
u8 res3[0x1c];
- u32 clkc3csr; /* Core 3 Clock control/status */
+ u32 clkc3csr; /* 0x060 Core 3 Clock control/status */
u8 res4[0x1c];
- u32 clkc4csr; /* Core 4 Clock control/status */
+ u32 clkc4csr; /* 0x080 Core 4 Clock control/status */
u8 res5[0x1c];
- u32 clkc5csr; /* Core 5 Clock control/status */
+ u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */
u8 res6[0x1c];
- u32 clkc6csr; /* Core 6 Clock control/status */
+ u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */
u8 res7[0x1c];
- u32 clkc7csr; /* Core 7 Clock control/status */
+ u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */
u8 res8[0x71c];
- u32 pllc1gsr; /* Cluster PLL 1 General Status */
+ u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
u8 res10[0x1c];
- u32 pllc2gsr; /* Cluster PLL 2 General Status */
+ u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
u8 res11[0x1c];
- u32 pllc3gsr; /* Cluster PLL 3 General Status */
+ u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
u8 res12[0x1c];
- u32 pllc4gsr; /* Cluster PLL 4 General Status */
- u8 res13[0x39c];
- u32 pllpgsr; /* Platform PLL General Status */
+ u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
+ u8 res13[0x1c];
+ u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
u8 res14[0x1c];
- u32 plldgsr; /* DDR PLL General Status */
- u8 res15[0x3dc];
+ u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
+ u8 res15[0x35c];
+ u32 pllpgsr; /* 0xc00 Platform PLL General Status */
+ u8 res16[0x1c];
+ u32 plldgsr; /* 0xc20 DDR PLL General Status */
+ u8 res17[0x3dc];
} ccsr_clk_t;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
@@ -2384,6 +2512,78 @@ typedef struct ccsr_gur {
#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#define SRDS_MAX_LANES 8
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SWRST 0x10000000
+#define SRDS_RSTCTL_SDPD 0x00000020
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF 0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res_0c; /* 0x00c */
+ u32 pllcr3;
+ u32 pllcr4;
+ u8 res_18[0x20-0x18];
+ } bank[2];
+ u8 res_40[0x90-0x40];
+ u32 srdstcalcr; /* 0x90 TX Calibration Control */
+ u8 res_94[0xa0-0x94];
+ u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
+ u8 res_a4[0xb0-0xa4];
+ u32 srdsgr0; /* 0xb0 General Register 0 */
+ u8 res_b4[0xe0-0xb4];
+ u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
+ u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
+ u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
+ u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
+ u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
+ u8 res_f4[0x100-0xf4];
+ struct {
+ u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u8 res_104[0x120-0x104];
+ } srdslnpssr[8];
+ u8 res_200[0x800-0x200];
+ struct {
+ u32 gcr0; /* 0x800 General Control Register 0 */
+ u32 gcr1; /* 0x804 General Control Register 1 */
+ u32 gcr2; /* 0x808 General Control Register 2 */
+ u32 res_80c;
+ u32 recr0; /* 0x810 Receive Equalization Control */
+ u32 res_814;
+ u32 tecr0; /* 0x818 Transmit Equalization Control */
+ u32 res_81c;
+ u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+ u8 res_824[0x840-0x824];
+ } lane[8]; /* Lane A, B, C, D, E, F, G, H */
+ u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES 18
+#define SRDS_MAX_BANK 3
typedef struct serdes_corenet {
struct {
u32 rstctl; /* Reset Control Register */
@@ -2392,11 +2592,13 @@ typedef struct serdes_corenet {
#define SRDS_RSTCTL_RSTERR 0x20000000
#define SRDS_RSTCTL_SDPD 0x00000020
u32 pllcr0; /* PLL Control Register 0 */
-#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
@@ -2421,6 +2623,7 @@ typedef struct serdes_corenet {
u32 gcr0; /* General Control Register 0 */
#define SRDS_GCR0_RRST 0x00400000
#define SRDS_GCR0_1STLANE 0x00010000
+#define SRDS_GCR0_UOTHL 0x00100000
u32 gcr1; /* General Control Register 1 */
#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
@@ -2440,6 +2643,7 @@ typedef struct serdes_corenet {
} lane[24];
u32 res6[384];
} serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
enum {
FSL_SRDS_B1_LANE_A = 0,
@@ -2482,8 +2686,8 @@ typedef struct ccsr_sec {
struct {
u32 ms; /* DECO LIODN Register, MS */
u32 ls; /* DECO LIODN Register, LS */
- } decoliodnr[5];
- u8 res4[0x58];
+ } decoliodnr[8];
+ u8 res4[0x40];
u32 dar; /* DECO Avail Register */
u32 drr; /* DECO Reset Register */
u8 res5[0xe78];
@@ -2523,13 +2727,16 @@ typedef struct ccsr_sec {
#endif
typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ u8 res0[0x200];
+#else
struct {
u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
u32 res;
u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
} qcsp[32];
-
+#endif
/* Not actually reserved, but irrelevant to u-boot */
u8 res[0xbf8 - 0x200];
u32 ip_rev_1;
@@ -2554,6 +2761,14 @@ typedef struct ccsr_qman {
u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
u8 res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
+ } qcsp[50];
+#endif
} ccsr_qman_t;
typedef struct ccsr_bman {
@@ -2617,14 +2832,48 @@ struct ccsr_rman {
};
#endif
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+ u8 res_00[0x40];
+ u32 poes1; /* PMAN Operation Error Status Register 1 */
+ u32 poes2; /* PMAN Operation Error Status Register 2 */
+ u32 poeah; /* PMAN Operation Error Address High */
+ u32 poeal; /* PMAN Operation Error Address Low */
+ u8 res_50[0x50];
+ u32 pr1; /* PMAN Revision Register 1 */
+ u32 pr2; /* PMAN Revision Register 2 */
+ u8 res_a8[0x8];
+ u32 pcap; /* PMAN Capabilities Register */
+ u8 res_b4[0xc];
+ u32 pc1; /* PMAN Control Register 1 */
+ u32 pc2; /* PMAN Control Register 2 */
+ u32 pc3; /* PMAN Control Register 3 */
+ u32 pc4; /* PMAN Control Register 4 */
+ u32 pc5; /* PMAN Control Register 5 */
+ u32 pc6; /* PMAN Control Register 6 */
+ u8 res_d8[0x8];
+ u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
+ u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
+ u8 res_e8[0x8];
+ u32 pics; /* PMAN Interrupt Control and Status */
+ u8 res_f4[0xf0c];
+};
+#endif
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#endif
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
@@ -2635,10 +2884,17 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
+#else
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#endif
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
@@ -2657,7 +2913,9 @@ struct ccsr_rman {
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
@@ -2665,7 +2923,10 @@ struct ccsr_rman {
#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
@@ -2775,6 +3036,8 @@ struct ccsr_rman {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
@@ -2808,4 +3071,62 @@ struct ccsr_rman {
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+ u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
+ u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
+ u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
+ u8 res_0c[500];/* 0x00c - 0x1ff */
+ u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
+ u8 res_204[4];
+ u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
+ u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
+ u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
+ u8 res_214[4];
+ u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
+ u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
+ u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
+ u8 res_224[4];
+ u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
+ u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
+ u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
+ u8 res_234[4];
+ u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
+ u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
+ u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
+ u8 res244[4];
+ u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
+ u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
+ u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
+ u8 res_254[4];
+ u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
+ u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
+ u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
+ u8 res_264[4];
+ u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
+ u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
+ u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
+ u8 res274[4];
+ u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
+ u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
+ u8 res_280[0xb80]; /* 0x280 - 0xdff */
+ u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
+ u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
+ u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+ u8 res_e0c[20]; /* 0xe0c - 0x01f */
+ u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+ u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+ u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
+ u8 res_e2c[20]; /* 0xe2c - 0xe3f */
+ u32 l2errdet; /* 0xe40 L2 cache error detect */
+ u32 l2errdis; /* 0xe44 L2 cache error disable */
+ u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
+ u32 l2errattr; /* 0xe4c L2 cache error attribute */
+ u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
+ u32 l2erraddr; /* 0xe54 L2 cache error address */
+ u32 l2errctl; /* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 9be9dca1f7..f0b989a3b0 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -20,7 +20,7 @@
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index fe490bac05..9188ede3f5 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -25,7 +25,7 @@
void setup_mp(void);
void cpu_mp_lmb_reserve(struct lmb *lmb);
-u32 determine_mp_bootpg(void);
+u32 determine_mp_bootpg(unsigned int *pagesize);
int is_core_disabled(int nr);
#ifdef CONFIG_E6500
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 5a608a5d0f..2aed5148ef 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -98,7 +98,10 @@ static inline int gpio_direction_input(unsigned gpio)
static inline int gpio_direction_output(unsigned gpio, int value)
{
- mpc85xx_gpio_set_low(1U << gpio);
+ if (value)
+ mpc85xx_gpio_set_high(1U << gpio);
+ else
+ mpc85xx_gpio_set_low(1U << gpio);
return 0;
}
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 36695e2fb6..7aa3231ad4 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1095,6 +1095,17 @@
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
+#define SVR_P5021 0X820500
+#define SVR_P5040 0x820400
+#define SVR_T4240 0x824000
+#define SVR_T4120 0x824001
+#define SVR_B4860 0X868000
+#define SVR_G4860 0x868001
+#define SVR_G4060 0x868003
+#define SVR_B4440 0x868100
+#define SVR_G4440 0x868101
+#define SVR_B4420 0x868102
+#define SVR_B4220 0x868103
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index b2fa2b574b..7229a98eaa 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -81,7 +81,7 @@ typedef struct bd_info {
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 965f9ea4a5..808021c42e 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -50,6 +50,7 @@ COBJS-y += cache.o
COBJS-y += extable.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
COBJS-y += time.o
# Workaround for local bus unaligned access problems
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index b860141efd..ebf400851a 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -440,8 +440,8 @@ void board_init_f(ulong bootflag)
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
*/
- if (addr > determine_mp_bootpg()) {
- addr = determine_mp_bootpg();
+ if (addr > determine_mp_bootpg(NULL)) {
+ addr = determine_mp_bootpg(NULL);
debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
diff --git a/arch/powerpc/lib/ide.c b/arch/powerpc/lib/ide.c
new file mode 100644
index 0000000000..139a94a5c1
--- /dev/null
+++ b/arch/powerpc/lib/ide.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Code taken from cmd_ide.c */
+#include <common.h>
+#include <ata.h>
+#include "ide.h"
+
+#ifdef CONFIG_IDE_8xx_DIRECT
+#include <mpc8xx.h>
+#include <pcmcia.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
+ * 70 165 30 PIO-Mode 0, [ns]
+ * 4 9 2 [Cycles]
+ * 50 125 20 PIO-Mode 1, [ns]
+ * 3 7 2 [Cycles]
+ * 30 100 15 PIO-Mode 2, [ns]
+ * 2 6 1 [Cycles]
+ * 30 80 10 PIO-Mode 3, [ns]
+ * 2 5 1 [Cycles]
+ * 25 70 10 PIO-Mode 4, [ns]
+ * 2 4 1 [Cycles]
+ */
+
+static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = {
+ /* Setup Length Hold */
+ { 70, 165, 30 }, /* PIO-Mode 0, [ns] */
+ { 50, 125, 20 }, /* PIO-Mode 1, [ns] */
+ { 30, 101, 15 }, /* PIO-Mode 2, [ns] */
+ { 30, 80, 10 }, /* PIO-Mode 3, [ns] */
+ { 25, 70, 10 }, /* PIO-Mode 4, [ns] */
+};
+
+static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1];
+
+#ifndef CONFIG_SYS_PIO_MODE
+#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */
+#endif
+static int pio_mode = CONFIG_SYS_PIO_MODE;
+
+/* Make clock cycles and always round up */
+
+#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U)
+
+static void set_pcmcia_timing(int pmode)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+ ulong timings;
+
+ debug("Set timing for PIO Mode %d\n", pmode);
+
+ timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
+ | PCMCIA_SST(pio_config_clk[pmode].t_setup)
+ | PCMCIA_SL(pio_config_clk[pmode].t_length);
+
+ /*
+ * IDE 0
+ */
+ pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
+#if (CONFIG_SYS_PCMCIA_POR0 != 0)
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings;
+#else
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0;
+#endif
+ debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
+
+ pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
+#if (CONFIG_SYS_PCMCIA_POR1 != 0)
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings;
+#else
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1;
+#endif
+ debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
+
+ pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
+#if (CONFIG_SYS_PCMCIA_POR2 != 0)
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings;
+#else
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2;
+#endif
+ debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
+
+ pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
+#if (CONFIG_SYS_PCMCIA_POR3 != 0)
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings;
+#else
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3;
+#endif
+ debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
+
+ /*
+ * IDE 1
+ */
+ pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
+#if (CONFIG_SYS_PCMCIA_POR4 != 0)
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings;
+#else
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4;
+#endif
+ debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
+
+ pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
+#if (CONFIG_SYS_PCMCIA_POR5 != 0)
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings;
+#else
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5;
+#endif
+ debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
+
+ pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
+#if (CONFIG_SYS_PCMCIA_POR6 != 0)
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings;
+#else
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6;
+#endif
+ debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
+
+ pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
+#if (CONFIG_SYS_PCMCIA_POR7 != 0)
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings;
+#else
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7;
+#endif
+ debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
+
+}
+
+int ide_preinit(void)
+{
+ int i;
+ /* Initialize PIO timing tables */
+ for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
+ pio_config_clk[i].t_setup =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
+ pio_config_clk[i].t_length =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk);
+ pio_config_clk[i].t_hold =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
+ debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk"
+ " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
+ pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
+ pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
+ pio_config_clk[i].t_hold);
+ }
+
+ return 0;
+}
+
+int ide_init_postreset(void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+
+ /* PCMCIA / IDE initialization for common mem space */
+ pcmp->pcmc_pgcrb = 0;
+
+ /* start in PIO mode 0 - most relaxed timings */
+ pio_mode = 0;
+ set_pcmcia_timing(pio_mode);
+ return 0;
+}
+#endif /* CONFIG_IDE_8xx_DIRECT */
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int ide_preinit(void)
+{
+ ide_devices_found = 0;
+ /* initialize the PCMCIA IDE adapter card */
+ pcmcia_on();
+ if (!ide_devices_found)
+ return 1;
+ udelay(1000000);/* 1 s */
+ return 0;
+}
+#endif
diff --git a/arch/powerpc/lib/ide.h b/arch/powerpc/lib/ide.h
new file mode 100644
index 0000000000..9e80702916
--- /dev/null
+++ b/arch/powerpc/lib/ide.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MPC8XX_IDE_H_
+#define _MPC8XX_IDE_H_ 1
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int pcmcia_on(void);
+extern int ide_devices_found;
+#endif
+#endif
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 99601387cb..1b781ebf6a 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -24,9 +24,11 @@
SECTIONS
{
- __u_boot_cmd_start = .;
- _u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__u_boot_sandbox_option_start = .;
_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index 581fd2f2a0..78a751d96f 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -36,7 +36,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds
index b86a82297f..17f8091ea4 100644
--- a/arch/sh/cpu/sh2/u-boot.lds
+++ b/arch/sh/cpu/sh2/u-boot.lds
@@ -72,13 +72,10 @@ SECTIONS
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds
index 9bf8503640..c8319610c2 100644
--- a/arch/sh/cpu/sh3/u-boot.lds
+++ b/arch/sh/cpu/sh3/u-boot.lds
@@ -78,13 +78,10 @@ SECTIONS
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds
index d9c70bce09..0ecafcf5d9 100644
--- a/arch/sh/cpu/sh4/u-boot.lds
+++ b/arch/sh/cpu/sh4/u-boot.lds
@@ -75,13 +75,10 @@ SECTIONS
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h
index 6e534ad614..9a2c19376d 100644
--- a/arch/sh/include/asm/global_data.h
+++ b/arch/sh/include/asm/global_data.h
@@ -31,7 +31,7 @@ typedef struct global_data
{
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index 6c04daf3bc..2c9c4634d8 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -33,7 +33,7 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c
index 16fffb621d..40d5b01d27 100644
--- a/arch/sparc/cpu/leon2/serial.c
+++ b/arch/sparc/cpu/leon2/serial.c
@@ -105,13 +105,6 @@ static void leon2_serial_putc(const char c)
leon2_serial_putc_raw(c);
}
-static void leon2_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
static int leon2_serial_getc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
@@ -172,7 +165,7 @@ static struct serial_device leon2_serial_drv = {
.stop = NULL,
.setbrg = leon2_serial_setbrg,
.putc = leon2_serial_putc,
- .puts = leon2_serial_puts,
+ .puts = default_serial_puts,
.getc = leon2_serial_getc,
.tstc = leon2_serial_tstc,
};
diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c
index c4f3ee83c3..838d4514ee 100644
--- a/arch/sparc/cpu/leon3/serial.c
+++ b/arch/sparc/cpu/leon3/serial.c
@@ -99,13 +99,6 @@ static void leon3_serial_putc(const char c)
leon3_serial_putc_raw(c);
}
-static void leon3_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
static int leon3_serial_getc(void)
{
if (!leon3_apbuart)
@@ -146,7 +139,7 @@ static struct serial_device leon3_serial_drv = {
.stop = NULL,
.setbrg = leon3_serial_setbrg,
.putc = leon3_serial_putc,
- .puts = leon3_serial_puts,
+ .puts = default_serial_puts,
.getc = leon3_serial_getc,
.tstc = leon3_serial_tstc,
};
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
index 93d3cc02eb..aa63b35cab 100644
--- a/arch/sparc/include/asm/global_data.h
+++ b/arch/sparc/include/asm/global_data.h
@@ -40,7 +40,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h
index 8d011185a0..04c05d4ffe 100644
--- a/arch/sparc/include/asm/u-boot.h
+++ b/arch/sparc/include/asm/u-boot.h
@@ -54,7 +54,7 @@ typedef struct bd_info {
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index ff0e0f2fd0..32d025a342 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -246,8 +246,8 @@ void board_init_f(ulong bootflag)
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index fe28030d84..a1ecefafc6 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -33,10 +33,11 @@ SECTIONS
.text : { *(.text*); }
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 6d29c0b9a3..bce999f41c 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -38,7 +38,7 @@ typedef struct global_data {
unsigned long gd_addr; /* Location of Global Data */
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds
index 4ba1964f7e..0c92d31f61 100644
--- a/board/BuS/eb_cpu5282/u-boot.lds
+++ b/board/BuS/eb_cpu5282/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index 5aaf6b309d..2bb876d689 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -86,9 +86,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 1327c62a75..4a780c3746 100644
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -139,20 +139,13 @@ static void marvell_serial_setbrg(void)
#endif /* CONFIG_MPSC */
-static void marvell_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device marvell_serial_drv = {
.name = "marvell_serial",
.start = marvell_serial_init,
.stop = NULL,
.setbrg = marvell_serial_setbrg,
.putc = marvell_serial_putc,
- .puts = marvell_serial_puts,
+ .puts = default_serial_puts,
.getc = marvell_serial_getc,
.tstc = marvell_serial_tstc,
};
diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds
index d0b60cf7c1..18f962cfa5 100644
--- a/board/RPXClassic/u-boot.lds
+++ b/board/RPXClassic/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug
index 99c48f28d4..dc8c4e958f 100644
--- a/board/RPXClassic/u-boot.lds.debug
+++ b/board/RPXClassic/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds
index d0b60cf7c1..18f962cfa5 100644
--- a/board/RPXlite/u-boot.lds
+++ b/board/RPXlite/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug
index 99c48f28d4..dc8c4e958f 100644
--- a/board/RPXlite/u-boot.lds.debug
+++ b/board/RPXlite/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds
index d0b60cf7c1..18f962cfa5 100644
--- a/board/RPXlite_dw/u-boot.lds
+++ b/board/RPXlite_dw/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug
index 4491edd944..b43a1e4281 100644
--- a/board/RPXlite_dw/u-boot.lds.debug
+++ b/board/RPXlite_dw/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds
index 838537375b..748e5113ef 100644
--- a/board/RRvision/u-boot.lds
+++ b/board/RRvision/u-boot.lds
@@ -71,9 +71,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index 63fd356097..c41eed0e6f 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -54,11 +54,11 @@ SECTIONS
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 9885d06b8e..84099840b5 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -54,11 +54,11 @@ SECTIONS
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 4a1c75aecc..a3bd02b0d2 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -54,11 +54,11 @@ SECTIONS
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
index a7627699e7..73e2f3f9cf 100644
--- a/board/adder/u-boot.lds
+++ b/board/adder/u-boot.lds
@@ -62,9 +62,11 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 52c986e8a9..656b2fbf89 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -48,6 +48,10 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+ . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
index 88ced629ec..289386b35c 100644
--- a/board/altera/nios2-generic/u-boot.lds
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -46,13 +46,11 @@ SECTIONS
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds
index ab67de2f76..beba978f83 100644
--- a/board/amcc/acadia/u-boot-nand.lds
+++ b/board/amcc/acadia/u-boot-nand.lds
@@ -72,10 +72,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds
index 3ad87095a1..2dd00d7f42 100644
--- a/board/amcc/bamboo/u-boot-nand.lds
+++ b/board/amcc/bamboo/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index 76f89f188d..8ac5116296 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds
index ab67de2f76..beba978f83 100644
--- a/board/amcc/kilauea/u-boot-nand.lds
+++ b/board/amcc/kilauea/u-boot-nand.lds
@@ -72,10 +72,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
index 07ae8b1291..18266efd09 100644
--- a/board/amcc/sequoia/u-boot-nand.lds
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds
index 423400ac66..6b02784926 100644
--- a/board/amcc/sequoia/u-boot-ram.lds
+++ b/board/amcc/sequoia/u-boot-ram.lds
@@ -64,10 +64,10 @@ SECTIONS
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds
index a1d8e0f6dc..bc40fd649d 100644
--- a/board/astro/mcf5373l/u-boot.lds
+++ b/board/astro/mcf5373l/u-boot.lds
@@ -22,51 +22,18 @@
*/
OUTPUT_ARCH(m68k)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/m68k/cpu/mcf532x/start.o (.text)
- arch/m68k/lib/traps.o (.text)
- arch/m68k/lib/interrupts.o (.text)
- common/dlmalloc.o (.text)
- lib/zlib.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text*)
- *(.text)
-/* *(.fixup)*/
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
@@ -74,9 +41,6 @@ SECTIONS
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@@ -86,33 +50,30 @@ SECTIONS
.reloc :
{
__got_start = .;
- *(.got)
+ KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
@@ -130,9 +91,8 @@ SECTIONS
.bss :
{
_sbss = .;
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
diff --git a/board/bmw/README b/board/bmw/README
deleted file mode 100644
index 1fbef79e64..0000000000
--- a/board/bmw/README
+++ /dev/null
@@ -1,331 +0,0 @@
-Broadcom 95xx BMW CPCI Platform
-
-Overview
-=========
-BMW is an MPC8245 system controller featuring:
-* 3U CPCI Form Factor
-* BCM5703 Gigabit Ethernet
-* M48T59Y NVRAM
-* 16MB DOC
-* DIP Socket for Socketed DOC up to 1GB
-* 64MB SDRAM
-* LCD Display
-* Configurable Jumper options for 66,85, and 100Mhz memory bus
-
-
-BMW System Address Map
-======================
-BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
-(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
-onboard the processor module are listed briefly below:
-
-0x00000000 - 0x40000000 - 64MB SDRAM SIMM
- (Unregistered PC-100 SDRAM DIMM Module)
-
-0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
- TSOP 16MB (MD2211-D16-V3)
-
-0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
- DIP32 (Socketed 16MB - 1GB ) *
- NOTE: this is not populated on all systems.
-
-0x7c000000 - 0x7c000000 - Reset Register
- (Write 0 to reset)
-
-0x7c000001 - 0x7c000001 - System LED
- (Clear Bit 7 to turn on, set to shut off)
-
-0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
- (Clear bit 7 to reset, set to assert IRQ3)
-
-0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
- (Clear bit 7 to make R/W, set to make R/O)
-
-0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
- 5x7 Dot Matrix Alphanumeric Display
- (Each byte sets the appropriate character)
-
-0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- NVRAM Memory Region
-
-0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- Realtime Clock Registers
-
-0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
- (AMD AM29F040, ST 29W040B)
-
-0xFFF00100 - System Reset Vector
-
-
-IO/MMU (BAT) Configuration
-======================
-The following Block-Address-Translation (BAT) configuration
-is recommended to access all I/O devices.
-
-#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-
-Interrupt Mappings
-======================
-BMW uses MPC8245 discrete mode interrupts. With the following
-hardwired mappings:
-
-BCM5701 10/100/1000 Ethernet IRQ1
-CompactPCI Interrupt A IRQ2
-RTC/Watchdog Interrupt IRQ3
-Internal NS16552 UART IRQ4
-
-
-Jumper Settings
-======================
-
-BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
-A jumper (X) is a 0 bit.
-
-Hence 66= 10110
- 85= 11000
- 100= 10000
-
-Jumper Settings for various Speeds
-=======================
-J1 J2 J3 J4 J5
- X X 66Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X 85Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X X 100Mhz
-=======================
-
-Obviously, 100Mhz memory bus is recommended for optimum performance.
-
-
-U-Boot
-===============
-Broadcom BMW board is supported under config_BWM option.
-Supported features:
-
-- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
-- BCM570x TFTP file transfer support
-- LCD Display Support
-- DOC Support - (underway)
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-=>printenv
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-hostname=switch-2
-bootcmd=tftp 100000 vmlinux.img;bootm
-gateway=10.16.64.1
-ethaddr=00:00:10:18:10:10
-nfsroot=172.16.40.111:/boot/root-fs
-filesize=5ec8c
-netmask=255.255.240.0
-ipaddr=172.16.40.114
-serverip=172.16.40.111
-root=/dev/nfs
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 315/8172 bytes
-=>boot
-
-
-DevTools
-========
-ELDK
- DENX Embedded Linux Development Kit
-
-ROM Emulator
- Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
- Grammar Engine PL32E 32Pin PLCC Emulation cables
- Grammar Engine 3VA8CON (3Volt adapter with Short cables)
- Grammar Engine FPNET PromICE Ethernet Adapters
-
-ICE
- WRS/EST VisionICE-II (PPC8240)
-
-
-=>reset
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-
-Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
-BCM570x PCI Memory base address @0x80100000
-eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
-eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
-eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
-eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
-ARP broadcast 1
-TFTP from server 172.16.40.111; our IP address is 172.16.40.114
-Filename 'vmlinux.img'.
-Load address: 0x100000
-Loading: #################################################################
- ####################################T #############################
- ######################
-done
-Bytes transferred = 777199 (bdbef hex)
-
-eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
-## Booting image at 00100000 ...
- Image Name: vmlinux.bin.gz
- Created: 2002-08-06 6:30:13 UTC
- Image Type: PowerPC Linux Kernel Image (gzip compressed)
- Data Size: 777135 Bytes = 758 kB = 0 MB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
- Uncompressing Kernel Image ... OK
-Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
-CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
-U-Boot Environment: 0xc01b08f0
-IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
-cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
-NOTICE: mounting root file system via NFS
-IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
-On node 0 totalpages: 16384
-zone(0): 16384 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
-root_dev_setup:/dev/nfs or 00:ff
-time_init: decrementer frequency = 16.501145 MHz
-Calibrating delay loop... 175.71 BogoMIPS
-Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
-Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
-Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
-Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
-Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
-devfs: devfs_debug: 0x0
-devfs: boot_options: 0x1
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-pty: 256 Unix98 ptys configured
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-Testing ttyS0 (0xf7f51500, 0xf7f51500)...
-Testing ttyS1 (0xfc004600, 0xfc004600)...
-ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
-ttyS01 at 0xfc004600 (irq = 25) is a 16550A
-Real Time Clock Driver v1.10e
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: loaded (max 8 devices)
-TFFS 5.1.1 Flash disk driver for DiskOnChip
-Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
-DOC device(s) found: 1
-fl_init: registered device at major: 100
-fl_geninit: registered device at major: 100
-Partition check:
- fla: p1
-partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
-partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
-partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
-eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
-eth0: Broadcom BCM5701 Integrated Copper transceiver found
-eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
-bond0 registered without MII link monitoring, in bonding mode.
-rtc: unable to get misc minor
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 4096 bind 4096)
-bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
-IP-Config: Gateway not on directly connected network.
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
-All bugs added by David S. Miller <davem@redhat.com>
-Looking up port of RPC 100003/2 on 172.16.40.111
-Looking up port of RPC 100005/1 on 172.16.40.111
-VFS: Mounted root (nfs filesystem).
-Mounted devfs on /dev
-Freeing unused kernel memory: 100k init
-INIT: version 2.78 booting
-Mounting local filesystems...
-not mounted anything
-Setting up symlinks in /dev...done.
-Setting up extra devices in /dev...done.
-Starting devfsd...Started device management daemon for /dev
-INIT: Entering runlevel: 2
-Starting internet superserver: inetd.
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-switch-2 login: root
-Password:
-PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
-Last login: Thu Nov 25 11:51:14 1920 on console
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-login[49]: ROOT LOGIN on `console'
-
-root@switch-2:~# cat /proc/cpuinfo
-cpu : 82xx
-revision : 16.20 (pvr 8081 1014)
-bogomips : 175.71
-vendor : Broadcom
-machine : BMW/MPC8245
-root@switch-2:~#
diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c
deleted file mode 100644
index 5ba6c09d1c..0000000000
--- a/board/bmw/bmw.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2002
- * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <net.h>
-#include <timestamp.h>
-#include <dtt.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <linux/mtd/doc2000.h>
-
-#include "bmw.h"
-#include "m48t59y.h"
-#include <pci.h>
-
-
-int checkboard(void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
- printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
- /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */
- printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- return 64*1024*1024;
-}
-
-
-void
-get_tod(void)
-{
- int year, month, day, hour, minute, second;
-
- m48_tod_get(&year,
- &month,
- &day,
- &hour,
- &minute,
- &second);
-
- printf(" Current date/time: %d/%d/%d %d:%d:%d \n",
- month, day, year, hour, minute, second);
-
-}
-
-/*
- * EPIC, PCI, and I/O devices.
- * Initialize Mousse Platform, probe for PCI devices,
- * Query configuration parameters if not set.
- */
-int misc_init_f (void)
-{
-#if 0
- m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
- printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n",
- TOD_NVRAM_SIZE);
- get_tod();
-#endif
-
- sys_led_msg("BOOT");
- return 0;
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-struct pci_controller hose;
-
-void pci_init_board (void)
-{
- pci_mpc824x_init(&hose);
- /* pci_dev_init(0); */
-}
-
-/*
- * Write characters to LCD display.
- * Note that the bytes for the first character is the last address.
- */
-void
-sys_led_msg(char* msg)
-{
- LED_REG(0) = msg[3];
- LED_REG(1) = msg[2];
- LED_REG(2) = msg[1];
- LED_REG(3) = msg[0];
-}
-
-#ifdef CONFIG_CMD_DOC
-/*
- * Map onboard TSOP-16MB DOC FLASH chip.
- */
-void doc_init (void)
-{
- doc_probe(DOC_BASE_ADDR);
-}
-#endif
-
-#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR)
-
-/* Read from NVRAM */
-void*
-nvram_read(void *dest, const long src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- return dest;
-}
-
-/* Write to NVRAM */
-void
-nvram_write(long dest, const void *src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- SYS_TOD_UNPROTECT();
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- SYS_TOD_PROTECT();
-}
diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h
deleted file mode 100644
index dd97569303..0000000000
--- a/board/bmw/bmw.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BMW/MPC8245 Board definitions.
- * For more info, see http://www.vooha.com/
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * James Dougherty (jfd@broadcom.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BMW_H
-#define __BMW_H
-
-/* System addresses */
-
-#define PCI_SPECIAL_BASE 0xfe000000
-#define PCI_SPECIAL_SIZE 0x01000000
-
-#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */
-#define EUMBSIZE 0x00100000 /* Size of EUMB region */
-
-/* Extended ROM space devices */
-#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */
-#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */
-#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */
-#define PLD_REG_BASE XROM_BASE_ADDR
-#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000)
-#define TOD_BASE (XROM_BASE_ADDR | 0x4000)
-#define LED_REG(x) (*(volatile unsigned char *) \
- (LED_REG_BASE + (x)))
-#define XROM_DEV_SIZE 0x00006000
-
-#define ENET_DEV_BASE 0x80000000
-
-#define PLD_REG(off) (*(volatile unsigned char *)\
- (PLD_REG_BASE + (off)))
-
-#define PLD_REVID_B1 0x7f /* Fix me */
-#define PLD_REVID_B2 0x01 /* Fix me */
-
-#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
-#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
-#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
-#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
-#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
-#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
-#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
-#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
-
-#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
-#define TOD_NVRAM_BASE TOD_BASE
-#define TOD_NVRAM_SIZE 0x1ff0
-#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
-#define RTC(r) (TOD_BASE + r)
-
-/* Onboard BCM570x device */
-#define PCI_ENET_IOADDR 0x80000000
-#define PCI_ENET_MEMADDR 0x80000000
-
-
-#ifndef __ASSEMBLY__
-/* C Function prototypes */
-void sys_led_msg(char* msg);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __BMW_H */
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
deleted file mode 100644
index 63c29d500f..0000000000
--- a/board/bmw/early_init.S
+++ /dev/null
@@ -1,1170 +0,0 @@
-#include <ppc_asm.tmpl>
-#include <mpc824x.h>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
-
-
-/*
- * Initialize the MMU using BAT entries and hardwired TLB
- * This obviates the need for any code in cpu_init_f which
- * configures the BAT registers.
-*/
-#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
- .global iommu_setup
- /* Initialize IO/MMU mappings via BAT method Ch. 7,
- * PPC Programming Reference
- */
-iommu_setup:
-
-/* initialize the BAT registers (SPRs 528 - 543 */
-#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */
-#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */
-#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */
-#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */
-#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */
-#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */
-#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */
-#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */
-#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */
-#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */
-#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */
-#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */
-#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */
-#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */
-#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */
-#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */
-
-
-/* PowerPC processors do not necessarily initialize the BAT
- registers on power-up or reset. So they are in an unknown
- state. Before programming the BATs for the first time, all
- BAT registers MUST have their Vs and Vp bits cleared in the
- upper BAT half in order to avoid possibly having 2 BATs
- valid and mapping the same memory region.
-
- The reason for this is that, even with address translation
- disabled, multiple BAT hits for an address are treated as
- programming errors and can cause unpredictable results.
-
- It is up to the software to make sure it never has 2 IBAT
- mappings or 2 DBAT mappings that are valid for the same
- addresses. It is not necessary to perform this code
- sequence every time the BATs are programmed, only when
- there is a possibility that there may be overlapping BAT
- entries.
-
- When programming the BATs in non-reset scenarios, even if
- you are sure that your new mapping will not temporarily
- create overlapping regions, it is still a wise idea to
- invalidate a BAT entry by setting its upper BAT register to
- all 0's before programming it. This will avoid having a
- BAT marked valid that is in an unknown or transient state
-*/
-
- addis r5,0,0x0000
- mtibat0u(r5)
- mtibat0l(r5)
- mtibat1u(r5)
- mtibat1l(r5)
- mtibat2u(r5)
- mtibat2l(r5)
- mtibat3u(r5)
- mtibat3l(r5)
- mtdbat0u(r5)
- mtdbat0l(r5)
- mtdbat1u(r5)
- mtdbat1l(r5)
- mtdbat2u(r5)
- mtdbat2l(r5)
- mtdbat3u(r5)
- mtdbat3l(r5)
- isync
-
-/*
- * Set up I/D BAT0
- */
- lis r4, CONFIG_SYS_DBAT0L@h
- ori r4, r4, CONFIG_SYS_DBAT0L@l
- lis r3, CONFIG_SYS_DBAT0U@h
- ori r3, r3, CONFIG_SYS_DBAT0U@l
-
- mtdbat0l(r4)
- isync
- mtdbat0u(r3)
- isync
- sync
-
- lis r4, CONFIG_SYS_IBAT0L@h
- ori r4, r4, CONFIG_SYS_IBAT0L@l
- lis r3, CONFIG_SYS_IBAT0U@h
- ori r3, r3, CONFIG_SYS_IBAT0U@l
-
- isync
- mtibat0l(r4)
- isync
- mtibat0u(r3)
- isync
-
-/*
- * Set up I/D BAT1
- */
- lis r4, CONFIG_SYS_IBAT1L@h
- ori r4, r4, CONFIG_SYS_IBAT1L@l
- lis r3, CONFIG_SYS_IBAT1U@h
- ori r3, r3, CONFIG_SYS_IBAT1U@l
-
- isync
- mtibat1l(r4)
- isync
- mtibat1u(r3)
- isync
- mtdbat1l(r4)
- isync
- mtdbat1u(r3)
- isync
- sync
-
-/*
- * Set up I/D BAT2
- */
- lis r4, CONFIG_SYS_IBAT2L@h
- ori r4, r4, CONFIG_SYS_IBAT2L@l
- lis r3, CONFIG_SYS_IBAT2U@h
- ori r3, r3, CONFIG_SYS_IBAT2U@l
-
- isync
- mtibat2l(r4)
- isync
- mtibat2u(r3)
- isync
- mtdbat2l(r4)
- isync
- mtdbat2u(r3)
- isync
- sync
-
-/*
- * Setup I/D BAT3
- */
- lis r4, CONFIG_SYS_IBAT3L@h
- ori r4, r4, CONFIG_SYS_IBAT3L@l
- lis r3, CONFIG_SYS_IBAT3U@h
- ori r3, r3, CONFIG_SYS_IBAT3U@l
-
- isync
- mtibat3l(r4)
- isync
- mtibat3u(r3)
- isync
- mtdbat3l(r4)
- isync
- mtdbat3u(r3)
- isync
- sync
-
-
-/*
- * Invalidate all 64 TLB's
- */
- lis r3, 0
- mtctr r3
- lis r5, 4
-
-tlblp:
- tlbie r3
- sync
- addi r3, r3, 0x1000
- cmplw r3, r5
- blt tlblp
-
- sync
-
-/*
- * Enable Data Translation
- */
- lis r4, MEMORY_MGMT_MSR_BITS@h
- ori r4, r4, MEMORY_MGMT_MSR_BITS@l
- mfmsr r3
- or r3, r4, r3
- mtmsr r3
- isync
- sync
-
- blr
-
-
-#ifdef USE_V2_INIT
-/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
-/* Macro for hiadjust and lo */
-#define HIADJ(arg) arg@ha
-#define HI(arg) arg@h
-#define LO(arg) arg@l
-
-#undef LOADPTR
-#define LOADPTR(reg,const32) \
- addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
-
-.globl early_init_f
-
-early_init_f:
-/* MPC8245/BMW CPCI System Init
- * Jimmy Blair, Broadcom Corp, 2002.
- */
- mflr r11
- /* Zero-out registers */
-
- addis r0,r0,0
- mtspr SPRG0,r0
- mtspr SPRG1,r0
- mtspr SPRG2,r0
- mtspr SPRG3,r0
-
- /* Set MPU/MSR to a known state. Turn on FP */
-
- LOADPTR (r3, MSR_FP)
- sync
- mtmsr r3
- isync
-
- /* Init the floating point control/status register */
-
- mtfsfi 7,0x0
- mtfsfi 6,0x0
- mtfsfi 5,0x0
- mtfsfi 4,0x0
- mtfsfi 3,0x0
- mtfsfi 2,0x0
- mtfsfi 1,0x0
- mtfsfi 0,0x0
- isync
-
- /* Set MPU/MSR to a known state. Turn off FP */
-
-#if 1 /* Turn off floating point (remove to keep FP on) */
- andi. r3, r3, 0
- sync
- mtmsr r3
- isync
-#endif
-
- /* Init the Segment registers */
-
- andi. r3, r3, 0
- isync
- mtsr 0,r3
- isync
- mtsr 1,r3
- isync
- mtsr 2,r3
- isync
- mtsr 3,r3
- isync
- mtsr 4,r3
- isync
- mtsr 5,r3
- isync
- mtsr 6,r3
- isync
- mtsr 7,r3
- isync
- mtsr 8,r3
- isync
- mtsr 9,r3
- isync
- mtsr 10,r3
- isync
- mtsr 11,r3
- isync
- mtsr 12,r3
- isync
- mtsr 13,r3
- isync
- mtsr 14,r3
- isync
- mtsr 15,r3
- isync
-
- /* Turn off data and instruction cache control bits */
-
- mfspr r3, HID0
- isync
- rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- isync
-
- /* Get cpu type */
-
- mfspr r28, PVR
- rlwinm r28, r28, 16, 16, 31
-
- /* invalidate the MPU's data/instruction caches */
-
- lis r3, 0x0
- cmpli 0, 0, r28, CPU_TYPE_603
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603E
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603P
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_604R
- bne cpuNot604R
-
-cpuIs604R:
- lis r3, 0x0
- mtspr HID0, r3 /* disable the caches */
- isync
- ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */
-
-cpuNot604R:
- ori r3, r3, (HID0_ICFI |HID0_DCI)
-
-cpuIs603:
- ori r3, r3, (HID0_ICE | HID0_DCE)
- or r4, r4, r3 /* set bits */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- andc r4, r4, r3 /* clear bits */
- isync
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604R
- beq cpuIs604
- mtspr HID0, r4
- isync
-
-#ifdef USER_I_CACHE_ENABLE
- b instCacheOn603
-#else
- b cacheEnableDone
-#endif
-
-cpuIs604:
- LOADPTR (r5, 0x1000) /* loop count, 0x1000 */
- mtspr CTR, r5
-loopDelay:
- nop
- bdnz loopDelay
- isync
- mtspr HID0, r4
- isync
-
- /* turn the Instruction cache ON for faster FLASH ROM boots */
-
-#ifdef USER_I_CACHE_ENABLE
-
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- isync /* Synchronize for ICE enable */
- b writeReg4
-instCacheOn603:
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
-
- /*
- * The setting of the instruction cache enable (ICE) bit must be
- * preceded by an isync instruction to prevent the cache from being
- * enabled or disabled while an instruction access is in progress.
- */
- isync
-writeReg4:
- mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cacheEnableDone
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cacheEnableDone
-
- mtspr HID0, r3 /* using 2 consec instructions */
- /* PPC603 recommendation */
-#endif
-cacheEnableDone:
-
- /* Detect map A or B */
-
- addis r5,r0, HI(CHRP_REG_ADDR)
- addis r6,r0, HI(CHRP_REG_DATA)
- LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */
- LOADPTR (r8, BMC_BASE)
-
- stwbrx r8,0,(r5)
- lwbrx r3,0,(r6) /* Store read value to r3 */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* It's not an 8240, is it an 8245? */
-
- LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* Save the PCI controller type in r7 */
- mr r7, r3
-
- LOADPTR (r5, PREP_REG_ADDR)
- LOADPTR (r6, PREP_REG_DATA)
-
-X4_KAHLUA_START:
- /* MPC8245 changes begin here */
- LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */
- stwbrx r3,0,r5
- li r4, 6 /* Command register value */
- sthbrx r4, 0, r6
-
- LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */
- stwbrx r3,0,r5
- li r4, -1 /* Write-to-clear all bits */
- li r3, 2 /* PCI_STATUS is at +2 offset */
- sthbrx r4, r3, r6
-
- /*-------PROC_INT1_ADR */
-
- LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xff141b98)
- stwbrx r4,0,r6
-
- /*-------PROC_INT2_ADR */
-
- LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */
- stwbrx r3,0,r5
- lis r4, 0x2000 /* Flush PCI config writes */
- stwbrx r4,0,r6
-
- LOADPTR (r9, KAHLUA2_ID)
- cmpl 0, 0, r7, r9
- bne L1not8245
-
- /* MIOCR1 -- turn on bit for DLL delay */
-
- LOADPTR (r3, MIOCR1_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x04
- stb r4, MIOCR1_SHIFT(r6)
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
-
- LOADPTR (r3, MIOCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x10
- stb r4, MIOCR2_SHIFT(r6)
-
- /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
-
- LOADPTR (r3, PMCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x20
- stb r4, PMCR2_SHIFT(r6)
-
- /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
-
- LOADPTR (r3, EUMBBAR)
- stwbrx r3,0,r5
- LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
- stwbrx r4,0,r6
-
-L1not8245:
-
- /* Toggle the DLL reset bit in AMBOR */
-
- LOADPTR (r3, AMBOR)
- stwbrx r3,0,r5
- lbz r4, 0(r6)
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
- sync
-
- ori r4, r4, 0x20 /* Set DLL_RESET */
- stb r4, 0(r6)
- sync
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
-
-
- /* Enable RCS2, use supplied timings */
- LOADPTR (r3, ERCR1)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x80408000)
- stwbrx r4,0,r6
-
- /* Disable RCS3 parameters */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- /* RCS3 at 0x70000000, 64KBytes */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000004)
- stwbrx r4,0,r6
-
- /*-------MCCR1 */
-
-#ifdef INCLUDE_ECC
-#define MC_ECC 1
-#else /* INCLUDE_ECC */
-#define MC_ECC 0
-#endif /* INCLUDE_ECC */
-
-#define MC1_ROMNAL 8 /* 0-15 */
-#define MC1_ROMFAL 11 /* 0-31 */
-#define MC1_DBUS_SIZE 0 /* 0-3, read only */
-#define MC1_BURST 0 /* 0-1 */
-#define MC1_MEMGO 0 /* 0-1 */
-#define MC1_SREN 1 /* 0-1 */
-#define MC1_RAM_TYPE 0 /* 0-1 */
-#define MC1_PCKEN MC_ECC /* 0-1 */
-#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
- MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
- MC1_MEMGO << 19 | MC1_SREN << 18 | \
- MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
- li r3, MC1_BANKBITS
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne BankBitsAdd
- cmpli 0, 0, r3, 0x5555
- beq K2BankBitsHack /* On 8245, 5555 ==> 0 */
-BankBitsAdd:
- ori r4, r3, 0
-K2BankBitsHack:
- stwbrx r4, 0, r6
-
- /*------- MCCR2 */
-
-#define MC2_TS_WAIT_TIMER 0 /* 0-7 */
-#define MC2_ASRISE 8 /* 0-15 */
-#define MC2_ASFALL 4 /* 0-15 */
-#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */
-#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */
-#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */
-#define MC2_ECC_EN 0 /* 0-1 */
-#define MC2_EDO 0 /* 0-1 */
-/*
-* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
-* May need to be decreased for 100 MHz
-*/
-#define MC2_REFINT 0x3a5 /* 0-0x3fff */
-#define MC2_RSV_PG 0 /* 0-1 */
-#define MC2_RMW_PAR MC_ECC /* 0-1 */
-
- LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
- MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
- MC2_WRITE_PARITY_CHK_EN << 19 | \
- MC2_INLRD_PARECC_CHK_EN << 18 | \
- MC2_ECC_EN << 17 | MC2_EDO << 16 | \
- MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xfffcffff)
- and r4, r4, r3
-notK2:
- stwbrx r4,0,r6
-
- /*------- MCCR3 */
-
-#define MC_BSTOPRE 0x079 /* 0-0x7ff */
-
-#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf)
-#define MC3_REFREC 8 /* 0-15 */
-#define MC3_RDLAT (4+MC_ECC) /* 0-15 */
-#define MC3_CPX 0 /* 0-1 */
-#define MC3_RAS6P 0 /* 0-15 */
-#define MC3_CAS5 0 /* 0-7 */
-#define MC3_CP4 0 /* 0-7 */
-#define MC3_CAS3 0 /* 0-7 */
-#define MC3_RCD2 0 /* 0-7 */
-#define MC3_RP1 0 /* 0-7 */
-
- LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
- MC3_RDLAT << 20 | MC3_CPX << 19 | \
- MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
- MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2b
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xff000000)
- and r4, r4, r3
-notK2b:
- stwbrx r4,0,r6
-
- /*------- MCCR4 */
-
-#define MC4_PRETOACT 3 /* 0-15 */
-#define MC4_ACTOPRE 5 /* 0-15 */
-#define MC4_WMODE 0 /* 0-1 */
-#define MC4_INLINE MC_ECC /* 0-1 */
-#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */
-#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3)
-#define MC4_REGDIMM 0 /* 0-1 */
-#define MC4_SDMODE_CAS 2 /* 0-7 */
-#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */
-#define MC4_SDMODE_WRAP 0 /* 0-1 */
-#define MC4_SDMODE_BURST 2 /* 0-7 */
-#define MC4_ACTORW 3 /* 0-15 */
-#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf)
-
- LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
- MC4_WMODE << 23 | MC4_INLINE << 22 | \
- MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
- MC4_DBUS_RCS1 << 17 | \
- MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
- MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
- MC4_ACTORW << 4 | MC4_BSTOPRE_L)
- cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */
- bne notK2c
- /* Turn on Kahlua2 extended ROM space */
- LOADPTR (r3, 0x00200000)
- or r4, r4, r3
-notK2c:
- stwbrx r4,0,r6
-
-#ifdef INCLUDE_ECC
- /*------- MEM_ERREN1 */
-
- LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */
- stwbrx r3,0,r5
- lwbrx r4,0,r6
- ori r4,r4,4 /* Set MEM_PERR_EN */
- stwbrx r4,0,r6
-#endif /* INCLUDE_ECC */
-
- /*------- MSAR/MEAR */
-
- LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- /*-------ODCR */
-
- LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */
- stwbrx r3,0,r5
-
- li r4, 0x7f
- stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */
-
- /*-------MBEN */
-
- LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */
- stwbrx r3,0,r5
- li r4, 0x01 /* Enable bank 0 */
- stb r4, 0(r6) /* MBEN is at +0 offset */
-
-#if 0 /* Jimmy: I think page made is broken */
- /*-------PGMAX */
-
- LOADPTR (r3, MPM_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x32
- stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */
-#endif
-
- /* Wait before initializing other registers */
-
- lis r4,0x0001
- mtctr r4
-
-KahluaX4wait200us:
- bdnz KahluaX4wait200us
-
- /* Set MEMGO bit */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */
- stwbrx r3,0,r5
- lwbrx r4,0,r6 /* old MCCR1 */
- oris r4,r4,0x0008 /* MEMGO=1 */
- stwbrx r4, 0, r6
-
- /* Wait again */
-
- addis r4,r0,0x0002
- ori r4,r4,0xffff
-
- mtctr r4
-
-KahluaX4wait8ref:
- bdnz KahluaX4wait8ref
-
- sync
- eieio
- mtlr r11
- blr
-
-#else /* USE_V2_INIT */
-
-
-/* U-Boot works, but memory will not run reliably for all address ranges.
- * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
- * initialized correctly. Could work if debugged.
- */
-/* PCI Support routines */
-
- .globl __pci_config_read_32
-__pci_config_read_32:
- lis r4, 0xfec0
- stwbrx r3, r0, r4
- sync
- lis r4, 0xfee0
- lwbrx r3, 0, r4
- blr
- .globl __pci_config_read_16
-__pci_config_read_16:
- lis r4, 0xfec0
- andi. r5, r3, 2
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lhbrx r3, r0, r4
- blr
- .globl __pci_config_read_8
-__pci_config_read_8:
- lis r4, 0xfec0
- andi. r5, r3, 3
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lbz r3, 0(4)
- blr
- .globl __pci_config_write_32
-__pci_config_write_32:
- lis r5, 0xfec0
- stwbrx r3, r0, r5
- sync
- lis r5, 0xfee0
- stwbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_16
-__pci_config_write_16:
- lis r5, 0xfec0
- andi. r6, r3, 2
- stwbrx r3, r0, 5
- sync
- oris r5, r6, 0xfee0
- sthbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_8
-__pci_config_write_8:
- lis r5, 0xfec0
- andi. r6, r3, 3
- stwbrx r3, r0, r5
- sync
- oris r5, r6, 0xfee0
- stb r4, 0(r5)
- sync
- blr
- .globl in_8
-in_8:
- oris r3, r3, 0xfe00
- lbz r3,0(r3)
- blr
- .globl in_16
-in_16:
- oris r3, r3, 0xfe00
- lhbrx r3, 0, r3
- blr
- .globl in_16_ne
-in_16_ne:
- oris r3, r3, 0xfe00
- lhzx r3, 0, r3
- blr
- .globl in_32
-in_32:
- oris r3, r3, 0xfe00
- lwbrx r3, 0, r3
- blr
- .globl out_8
-out_8:
- oris r3, r3, 0xfe00
- stb r4, 0(r3)
- eieio
- blr
- .globl out_16
-out_16:
- oris r3, r3, 0xfe00
- sthbrx r4, 0, r3
- eieio
- blr
- .globl out_16_ne
-out_16_ne:
- oris r3, r3, 0xfe00
- sth r4, 0(r3)
- eieio
- blr
- .globl out_32
-out_32:
- oris r3, r3, 0xfe00
- stwbrx r4, 0, r3
- eieio
- blr
- .globl read_8
-read_8:
- lbz r3,0(r3)
- blr
- .globl read_16
-read_16:
- lhbrx r3, 0, r3
- blr
- .globl read_32
-read_32:
- lwbrx r3, 0, r3
- blr
- .globl read_32_ne
-read_32_ne:
- lwz r3, 0(r3)
- blr
- .globl write_8
-write_8:
- stb r4, 0(r3)
- eieio
- blr
- .globl write_16
-write_16:
- sthbrx r4, 0, r3
- eieio
- blr
- .globl write_32
-write_32:
- stwbrx r4, 0, r3
- eieio
- blr
- .globl write_32_ne
-write_32_ne:
- stw r4, 0(r3)
- eieio
- blr
-
-
-.globl early_init_f
-
-early_init_f:
- mflr r11
- lis r10, 0x8000
-
- /* PCI Latency Timer */
- li r4, 0x0d
- ori r3, r10, PLTR@l
- bl __pci_config_write_8
-
- /* Cache Line Size */
- li r4, 0x08
- ori r3, r10, PCLSR@l
- bl __pci_config_write_8
-
- /* PCI Cmd */
- li r4, 6
- ori r3, r10, PCICR@l
- bl __pci_config_write_16
-
-#if 1
- /* PCI Stat */
- ori r3, r10, PCISR@l
- bl __pci_config_read_16
- ori r4, r4, 0xffff
- ori r3, r10, PCISR@l
- bl __pci_config_write_16
-#endif
-
- /* PICR1 */
- lis r4, 0xff14
- ori r4, r4, 0x1b98
- ori r3, r10, PICR1@l
- bl __pci_config_write_32
-
-
- /* PICR2 */
- lis r4, 0x0404
- ori r4, r4, 0x0004
- ori r3, r10, PICR2@l
- bl __pci_config_write_32
-
- /* MIOCR1 */
- li r4, 0x04
- ori r3, r10, MIOCR1@l
- bl __pci_config_write_8
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
- li r4, 0x10
- ori r3, r10, MIOCR2@l
- bl __pci_config_write_8
-
- /* EUMBBAR */
- lis r4, 0xfc00
- ori r3, r10, EUMBBAR@l
- bl __pci_config_write_32
-
- /* AMBOR */
-
- /* Even if Address Map B is not being used (though it should),
- * the memory DLL needs to be cleared/set/cleared before using memory.
- */
-
- ori r3, r10, AMBOR@l
- bl __pci_config_read_8 /* get Current bits */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- ori r4, r4, 0x0020
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Set DLL_RESET */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- /* ERCR1 */
- lis r4, 0x8040 /* Enable RCS2, use supplied timings */
- ori r4, r4, 0x8000
- ori r3, r10, ERCR1@l
- bl __pci_config_write_32
-
- /* ERCR2 */
- lis r4, 0x0000 /* Disable RCS3 parms */
- ori r4, r4, 0x0000
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* ERCR3 */
- lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */
- ori r4, r4, 0x0004
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* Preserve memgo bit */
- /* MCCR1 */
-
-/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */
- lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */
-/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */
-/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */
-/* oris r4, r4, 0x0004 / Self-refresh enable */
-
-/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */
-/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */
-/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */
- ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */
-
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* MCCR2 */
-
- lis r4,0x0000
-/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */
- oris r4,r4,0x1000 /* ASRISE = 8 clocks */
- oris r4,r4,0x0080 /* ASFALL = 8 clocks */
-/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */
-/* oris r4,r4,0x0008 / Write parity check */
-/* oris r4,r4,0x0004 / SDRAM inline reads */
-
-
-/* Select a refresh rate; it needs to match the bus speed; if too */
-/* slow, data may be lost; if too fast, performance is lost. We */
-/* use the fastest value so we run at all speeds. */
-/* Refresh = (15600ns/busclk) - (213 (see UM)). */
-
-/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */
-/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */
-/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */
-/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */
- ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */
-/* ori r4,r4,0x0002 / Reserve a page */
-/* ori r4,r4,0x0001 / RWM parity */
-
- ori r3, r10, MCCR2@l
- bl __pci_config_write_32
-
-
- /* MCCR3 */
- lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */
- oris r4,r4,0x0500 /* REFREC = 8 clocks */
- ori r3, r10, MCCR3@l
- bl __pci_config_write_32
-
- /* MCCR4 */ /* Turn on registered buffer mode */
- lis r4, 0x2000 /* PRETOACT = 3 clocks */
- oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */
-/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */
-/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */
- oris r4,r4,0x0020 /* EXTROM enabled */
- oris r4,r4,0x0010 /* Registered buffers */
-/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */
- oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */
-
-/* ori r4,r4,0x8000 / Registered DIMMs */
- ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */
-/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */
-/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */
- ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */
- ori r4,r4,0x0030 /* ACTORW = 3 clocks */
- ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */
-
- ori r3, r10, MCCR4@l
- bl __pci_config_write_32
-
- /* MSAR1 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR1@l
- bl __pci_config_write_32
-
- /* MSAR2 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR2@l
- bl __pci_config_write_32
-
- /* MESAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMSAR1@l
- bl __pci_config_write_32
-
- /* MESAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMSAR2@l
- bl __pci_config_write_32
-
- /* MEAR1 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR1@l
- bl __pci_config_write_32
-
- /* MEAR2 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR2@l
- bl __pci_config_write_32
-
- /* MEEAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMEAR1@l
- bl __pci_config_write_32
-
- /* MEEAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMEAR2@l
- bl __pci_config_write_32
-
- /* ODCR */
- li r4, 0x7f
- ori r3, r10, ODCR@l
- bl __pci_config_write_8
-
- /* MBER */
- li r4, 0x01
- ori r3, r10, MBER@l
- bl __pci_config_write_8
-
- /* Page CTR aka PGMAX */
- li r4, 0x32
- ori r3, r10, 0x70
- bl __pci_config_write_8
-
-#if 0
- /* CLK Drive */
- ori r4, r10, 0xfc01 /* Top bit will be ignored */
- ori r3, r10, 0x74
- bl __pci_config_write_16
-#endif
-
- /* delay */
- lis r7, 1
- mtctr r7
-label1: bdnz label1
-
- /* Set memgo bit */
- /* MCCR1 */
- ori r3, r10, MCCR1@l
- bl __pci_config_read_32
- lis r7, 0x0008
- or r4, r3, r7
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* delay again */
- lis r7, 1
- mtctr r7
-label2: bdnz label2
-#if 0
-/* DEBUG: Infinite loop, write then read */
-loop:
- lis r7, 0xffff
- mtctr r7
- li r3, 0x5004
- lis r4, 0xa0a0
- ori r4, r4, 0x5050
- bl write_32_ne
- li r3, 0x5004
- bl read_32_ne
- bdnz loop
-#endif
- mtlr r11
- blr
-#endif
diff --git a/board/bmw/flash.c b/board/bmw/flash.c
deleted file mode 100644
index 57ffe0890f..0000000000
--- a/board/bmw/flash.c
+++ /dev/null
@@ -1,779 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info);
-#endif /* 0 */
-
-/*flash command address offsets*/
-
-#if 0
-#define ADDR0 (0x555)
-#define ADDR1 (0x2AA)
-#define ADDR3 (0x001)
-#else
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-#endif
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-#if 0
-static int byte_parity_odd (unsigned char x) __attribute__ ((const));
-#endif /* 0 */
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
- __attribute__ ((const));
-
-typedef struct {
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-#if 0
-static int byte_parity_odd (unsigned char x)
-{
- x ^= x >> 4;
- x ^= x >> 2;
- x ^= x >> 1;
- return (x & 0x1) != 0;
-}
-#endif /* 0 */
-
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for (p = &chip_map[0];
- p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if (p->extval == chip) {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for (p = &mfct_map[0];
- p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if (p->extval == mfct) {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-
-unsigned long flash_init (void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
-
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE *const flash =
- (FLASH_WORD_SIZE *) base_address;
-#if 0
- volatile FLASH_WORD_SIZE *addr2;
-#endif
-#if 0
- /* write autoselect sequence */
- flash[0x5555] = 0xaa;
- flash[0x2aaa] = 0x55;
- flash[0x5555] = 0x90;
-#else
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
-#endif
- __asm__ __volatile__ ("sync");
-
-#if 0
- pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
-#else
- pflinfo->flash_id =
- flash_id (flash[0x0], flash[0x2 + 14 * i]);
-#endif
-
- switch (pflinfo->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for (j = 0; j < 8; j++) {
- pflinfo->start[j] =
- base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for (j = 1; j < 16; j++) {
- pflinfo->start[j + 3] =
- base_address + 0x00010000 * j;
- }
-#if 0
- /* check for protected sectors */
- for (j = 0; j < pflinfo->sector_count; j++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE
- *) (pflinfo->start[j]);
- if (pflinfo->flash_id & FLASH_MAN_SST)
- pflinfo->protect[j] = 0;
- else
- pflinfo->protect[j] = addr2[2] & 1;
- }
-#endif
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__ ("sync");
- }
-
- return flash_info[0].size + flash_info[1].size;
-}
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size)
- && erased; flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-#if 0
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- printf ("flash_get_size: \n");
- /* Write auto select command: read Manufacturer ID */
- eieio ();
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT: