diff options
46 files changed, 3013 insertions, 1632 deletions
@@ -2534,18 +2534,32 @@ to save the current settings. - CONFIG_ENV_SIZE: These two #defines specify the offset and size of the environment - area within the first NAND device. + area within the first NAND device. CONFIG_ENV_OFFSET must be + aligned to an erase block boundary. - - CONFIG_ENV_OFFSET_REDUND + - CONFIG_ENV_OFFSET_REDUND (optional): This setting describes a second storage area of CONFIG_ENV_SIZE - size used to hold a redundant copy of the environment data, - so that there is a valid backup copy in case there is a - power failure during a "saveenv" operation. - - Note: CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND must be aligned - to a block boundary, and CONFIG_ENV_SIZE must be a multiple of - the NAND devices block size. + size used to hold a redundant copy of the environment data, so + that there is a valid backup copy in case there is a power failure + during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + aligned to an erase block boundary. + + - CONFIG_ENV_RANGE (optional): + + Specifies the length of the region in which the environment + can be written. This should be a multiple of the NAND device's + block size. Specifying a range with more erase blocks than + are needed to hold CONFIG_ENV_SIZE allows bad blocks within + the range to be avoided. + + - CONFIG_ENV_OFFSET_OOB (optional): + + Enables support for dynamically retrieving the offset of the + environment from block zero's out-of-band data. The + "nand env.oob" command can be used to record this offset. + Currently, CONFIG_ENV_OFFSET_REDUND is not supported when + using CONFIG_ENV_OFFSET_OOB. - CONFIG_NAND_ENV_DST diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h index 35a1585d17..76493a138a 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/include/asm/arch-davinci/emac_defs.h @@ -367,7 +367,6 @@ typedef struct { int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); -void davinci_eth_set_mac_addr(const u_int8_t *addr); typedef struct { diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 5f2dfd08ac..22bd2c9b0e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -409,15 +409,6 @@ void start_armboot (void) enable_interrupts (); /* Perform network card initialisation if necessary */ -#ifdef CONFIG_DRIVER_TI_EMAC - /* XXX: this needs to be moved to board init */ -extern void davinci_eth_set_mac_addr (const u_int8_t *addr); - if (getenv ("ethaddr")) { - uchar enetaddr[6]; - eth_getenv_enetaddr("ethaddr", enetaddr); - davinci_eth_set_mac_addr(enetaddr); - } -#endif #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ @@ -821,16 +812,6 @@ void board_init_r (gd_t *id, ulong dest_addr) enable_interrupts (); /* Perform network card initialisation if necessary */ -#ifdef CONFIG_DRIVER_TI_EMAC - /* XXX: this needs to be moved to board init */ -extern void davinci_eth_set_mac_addr (const u_int8_t *addr); - if (getenv ("ethaddr")) { - uchar enetaddr[6]; - eth_getenv_enetaddr("ethaddr", enetaddr); - davinci_eth_set_mac_addr(enetaddr); - } -#endif - #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ if (getenv ("ethaddr")) { diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 2e9a08dc54..7f6043413e 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -32,6 +32,22 @@ _start: mts rmsr, r0 /* disable cache */ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ + + /* Find-out if u-boot is running on BIG/LITTLE endian platform + * There are some steps which is necessary to keep in mind: + * 1. Setup offset value to r6 + * 2. Store word offset value to address 0x0 + * 3. Load just byte from address 0x0 + * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest + * value that's why is on address 0x0 + * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3 + */ + addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ + swi r6, r0, 0 + lbui r10, r0, 0 + swi r6, r0, 0x40 + swi r10, r0, 0x50 + /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */ swi r6, r0, 0x0 /* reset address */ @@ -75,26 +91,52 @@ _start: /* user_vector_exception */ addik r6, r0, _exception_handler sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0xa - shi r6, r0, 0xe + /* + * BIG ENDIAN memory map for user exception + * 0x8: 0xB000XXXX + * 0xC: 0xB808XXXX + * + * then it is necessary to count address for storing the most significant + * 16bits from _exception_handler address and copy it to + * 0xa address. Big endian use offset in r10=0 that's why is it just + * 0xa address. The same is done for the least significant 16 bits + * for 0xe address. + * + * LITTLE ENDIAN memory map for user exception + * 0x8: 0xXXXX00B0 + * 0xC: 0xXXXX08B8 + * + * Offset is for little endian setup to 0x2. rsubi instruction decrease + * address value to ensure that points to proper place which is + * 0x8 for the most significant 16 bits and + * 0xC for the least significant 16 bits + */ + lhu r7, r1, r10 + rsubi r8, r10, 0xa + sh r7, r0, r8 + rsubi r8, r10, 0xe + sh r6, r0, r8 #endif #ifdef CONFIG_SYS_INTC_0 /* interrupt_handler */ addik r6, r0, _interrupt_handler sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0x12 - shi r6, r0, 0x16 + lhu r7, r1, r10 + rsubi r8, r10, 0x12 + sh r7, r0, r8 + rsubi r8, r10, 0x16 + sh r6, r0, r8 #endif /* hardware exception */ addik r6, r0, _hw_exception_handler sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0x22 - shi r6, r0, 0x26 + lhu r7, r1, r10 + rsubi r8, r10, 0x22 + sh r7, r0, r8 + rsubi r8, r10, 0x26 + sh r6, r0, r8 /* enable instruction and data cache */ mfs r12, rmsr diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h index a4a75b7a6d..b2757a41f8 100644 --- a/arch/microblaze/include/asm/byteorder.h +++ b/arch/microblaze/include/asm/byteorder.h @@ -50,6 +50,10 @@ static __inline__ __u16 ___arch__swab16 (__u16 half_word) #endif /* __GNUC__ */ +#ifdef __MICROBLAZEEL__ +#include <linux/byteorder/little_endian.h> +#else #include <linux/byteorder/big_endian.h> +#endif #endif /* __MICROBLAZE_BYTEORDER_H__ */ diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 3ff5c17d24..0ce040e9ef 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -31,6 +31,7 @@ #include <version.h> #include <watchdog.h> #include <stdio_dev.h> +#include <net.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +43,7 @@ extern int gpio_init (void); #ifdef CONFIG_SYS_INTC_0 extern int interrupts_init (void); #endif + #if defined(CONFIG_CMD_NET) extern int eth_init (bd_t * bis); #endif @@ -165,8 +167,14 @@ void board_init (void) #if defined(CONFIG_CMD_NET) /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - eth_init (bd); + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + + printf("Net: "); + eth_initialize(gd->bd); + + uchar enetaddr[6]; + eth_getenv_enetaddr("ethaddr", enetaddr); + printf("MAC: %pM\n", enetaddr); #endif /* main_loop */ diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 86a875eeaa..b60a46e96d 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -85,45 +85,22 @@ err: return 0; } -/* If there is a MAC address in the environment, and if it is not identical to - * the MAC address in the EEPROM, then a warning is printed and the MAC address - * from the environment is used. - * +/* * If there is no MAC address in the environment, then it will be initialized * (silently) from the value in the EEPROM. */ -void dv_configure_mac_address(uint8_t *rom_enetaddr) +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) { - int i; - u_int8_t env_enetaddr[6]; - char *tmp = getenv("ethaddr"); - char *end; - - /* Read Ethernet MAC address from the U-Boot environment. - * If it is not defined, env_enetaddr[] will be cleared. */ - for (i = 0; i < 6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - /* Check if EEPROM and U-Boot environment MAC addresses match. */ - if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && - memcmp(env_enetaddr, rom_enetaddr, 6) != 0) { - printf("Warning: MAC addresses don't match:\n"); - printf(" EEPROM MAC address: %pM\n", rom_enetaddr); - printf(" \"ethaddr\" value: %pM\n", env_enetaddr) ; - debug("### Using MAC address from environment\n"); - } - if (!tmp) { - char ethaddr[20]; + uint8_t env_enetaddr[6]; + eth_getenv_enetaddr_by_index(0, env_enetaddr); + if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { /* There is no MAC address in the environment, so we initialize * it from the value in the EEPROM. */ - sprintf(ethaddr, "%pM", rom_enetaddr) ; - debug("### Setting environment from EEPROM MAC address = \"%s\"\n", - ethaddr); - setenv("ethaddr", ethaddr); + debug("### Setting environment from EEPROM MAC address = " + "\"%pM\"\n", + env_enetaddr); + eth_setenv_enetaddr("ethaddr", rom_enetaddr); } } diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index 329c369763..a6ac3b9a56 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -46,7 +46,7 @@ struct pinmux_resource { } int dvevm_read_mac_address(uint8_t *buf); -void dv_configure_mac_address(uint8_t *rom_enetaddr); +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 6baa8603f1..8a9f9884d6 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -196,19 +196,17 @@ int board_eth_init(bd_t *bis) { u_int8_t mac_addr[6]; u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; + struct eth_device *dev; /* Read Ethernet MAC address from EEPROM */ if (dvevm_read_mac_address(mac_addr)) /* set address env if not already set */ - dv_configure_mac_address(mac_addr); + davinci_sync_env_enetaddr(mac_addr); /* read the address back from env */ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) return -1; - /* provide the resulting addr to the driver */ - davinci_eth_set_mac_addr(mac_addr); - /* enable the Ethernet switch in the 3 port PHY */ if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, switch_start_cmd, sizeof(switch_start_cmd))) { @@ -222,6 +220,12 @@ int board_eth_init(bd_t *bis) return -1; } + dev = eth_get_dev(); + + /* provide the resulting addr to the driver */ + memcpy(dev->enetaddr, mac_addr, 6); + dev->write_hwaddr(dev); + return 0; } #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 290eb99749..85dbe2a9c3 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -68,7 +68,7 @@ int board_eth_init(bd_t *bis) /* Read Ethernet MAC address from EEPROM */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); davinci_emac_initialize(); diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 98937a9620..073c21a8cc 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -71,7 +71,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); i2c_read(0x39, 0x00, 1, &video_mode, 1); diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index c24b9e188c..657cf2b0d9 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -141,7 +141,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (sffsdr_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); return(0); } diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index 817970aeaa..1dc42c4087 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -70,7 +70,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); return(0); } diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 838f1315b3..744384c1d3 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -27,6 +27,7 @@ #include <common.h> #include <config.h> +#include <netdev.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -66,3 +67,15 @@ int fsl_init2 (void) { return 0; } #endif + +int board_eth_init(bd_t *bis) +{ + /* + * This board either has PCI NICs or uses the CPU's TSECs + * pci_eth_init() will return 0 if no NICs found, so in that case + * returning -1 will force cpu_eth_init() to be called. + */ +#ifdef CONFIG_XILINX_EMACLITE + return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR); +#endif +} diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index ceec5a9751..5481c885d3 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -15,6 +15,9 @@ * Parsing routines are based on driver/mtd/cmdline.c from the linux 2.4 * kernel tree. * + * (C) Copyright 2008 + * Harald Welte, OpenMoko, Inc., Harald Welte <laforge@openmoko.org> + * * $Id: cmdlinepart.c,v 1.17 2004/11/26 11:18:47 lavinen Exp $ * Copyright 2002 SYSGO Real-Time Solutions GmbH * @@ -286,6 +289,29 @@ static void current_save(void) index_partitions(); } + +/** + * Produce a mtd_info given a type and num. + * + * @param type mtd type + * @param num mtd number + * @param mtd a pointer to an mtd_info instance (output) + * @return 0 if device is valid, 1 otherwise + */ +static int get_mtd_info(u8 type, u8 num, struct mtd_info **mtd) +{ + char mtd_dev[16]; + + sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(type), num); + *mtd = get_mtd_device_nm(mtd_dev); + if (IS_ERR(*mtd)) { + printf("Device %s not found!\n", mtd_dev); + return 1; + } + + return 0; +} + /** * Performs sanity check for supplied flash partition. * Table of existing MTD flash devices is searched and partition device @@ -297,17 +323,12 @@ static void current_save(void) */ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part) { - struct mtd_info *mtd; - char mtd_dev[16]; + struct mtd_info *mtd = NULL; int i, j; ulong start; - sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(id->type), id->num); - mtd = get_mtd_device_nm(mtd_dev); - if (IS_ERR(mtd)) { - printf("Partition %s not found on device %s!\n", part->name, mtd_dev); + if (get_mtd_info(id->type, id->num, &mtd)) return 1; - } part->sector_size = mtd->erasesize; @@ -684,20 +705,17 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i /** * Check device number to be within valid range for given device type. * - * @param dev device to validate + * @param type mtd type + * @param num mtd number + * @param size a pointer to the size of the mtd device (output) * @return 0 if device is valid, 1 otherwise */ int mtd_device_validate(u8 type, u8 num, u32 *size) { - struct mtd_info *mtd; - char mtd_dev[16]; + struct mtd_info *mtd = NULL; - sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(type), num); - mtd = get_mtd_device_nm(mtd_dev); - if (IS_ERR(mtd)) { - printf("Device %s not found!\n", mtd_dev); + if (get_mtd_info(type, num, &mtd)) return 1; - } *size = mtd->size; @@ -1200,38 +1218,93 @@ static int generate_mtdparts_save(char *buf, u32 buflen) return ret; } +#if defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) /** - * Format and print out a partition list for each device from global device - * list. + * Get the net size (w/o bad blocks) of the given partition. + * + * @param mtd the mtd info + * @param part the partition + * @return the calculated net size of this partition */ -static void list_partitions(void) +static uint64_t net_part_size(struct mtd_info *mtd, struct part_info *part) +{ + uint64_t i, net_size = 0; + + if (!mtd->block_isbad) + return part->size; + + for (i = 0; i < part->size; i += mtd->erasesize) { + if (!mtd->block_isbad(mtd, part->offset + i)) + net_size += mtd->erasesize; + } + + return net_size; +} +#endif + +static void print_partition_table(void) { struct list_head *dentry, *pentry; struct part_info *part; struct mtd_device *dev; int part_num; - debug("\n---list_partitions---\n"); list_for_each(dentry, &devices) { dev = list_entry(dentry, struct mtd_device, link); + /* list partitions for given device */ + part_num = 0; +#if defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) + struct mtd_info *mtd; + + if (get_mtd_info(dev->id->type, dev->id->num, &mtd)) + return; + + printf("\ndevice %s%d <%s>, # parts = %d\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num, + dev->id->mtd_id, dev->num_parts); + printf(" #: name\t\tsize\t\tnet size\toffset\t\tmask_flags\n"); + + list_for_each(pentry, &dev->parts) { + u32 net_size; + char *size_note; + + part = list_entry(pentry, struct part_info, link); + net_size = net_part_size(mtd, part); + size_note = part->size == net_size ? " " : " (!)"; + printf("%2d: %-20s0x%08x\t0x%08x%s\t0x%08x\t%d\n", + part_num, part->name, part->size, + net_size, size_note, part->offset, + part->mask_flags); +#else /* !defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */ printf("\ndevice %s%d <%s>, # parts = %d\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, dev->id->mtd_id, dev->num_parts); printf(" #: name\t\tsize\t\toffset\t\tmask_flags\n"); - /* list partitions for given device */ - part_num = 0; list_for_each(pentry, &dev->parts) { part = list_entry(pentry, struct part_info, link); printf("%2d: %-20s0x%08x\t0x%08x\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); - +#endif /* defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */ part_num++; } } + if (list_empty(&devices)) printf("no partitions defined\n"); +} + +/** + * Format and print out a partition list for each device from global device + * list. + */ +static void list_partitions(void) +{ + struct part_info *part; + + debug("\n---list_partitions---\n"); + print_partition_table(); /* current_mtd_dev is not NULL only when we have non empty device list */ if (current_mtd_dev) { @@ -1355,6 +1428,101 @@ static int delete_partition(const char *id) return 1; } +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) +/** + * Increase the size of the given partition so that it's net size is at least + * as large as the size member and such that the next partition would start on a + * good block if it were adjacent to this partition. + * + * @param mtd the mtd device + * @param part the partition + * @param next_offset pointer to the offset of the next partition after this + * partition's size has been modified (output) + */ +static void spread_partition(struct mtd_info *mtd, struct part_info *part, + uint64_t *next_offset) +{ + uint64_t net_size, padding_size = 0; + int truncated; + + mtd_get_len_incl_bad(mtd, part->offset, part->size, &net_size, + &truncated); + + /* + * Absorb bad blocks immediately following this + * partition also into the partition, such that + * the next partition starts with a good block. + */ + if (!truncated) { + mtd_get_len_incl_bad(mtd, part->offset + net_size, + mtd->erasesize, &padding_size, &truncated); + if (truncated) + padding_size = 0; + else + padding_size -= mtd->erasesize; + } + + if (truncated) { + printf("truncated partition %s to %lld bytes\n", part->name, + (uint64_t) net_size + padding_size); + } + + part->size = net_size + padding_size; + *next_offset = part->offset + part->size; +} + +/** + * Adjust all of the partition sizes, such that all partitions are at least + * as big as their mtdparts environment variable sizes and they each start + * on a good block. + * + * @return 0 on success, 1 otherwise + */ +static int spread_partitions(void) +{ + struct list_head *dentry, *pentry; + struct mtd_device *dev; + struct part_info *part; + struct mtd_info *mtd; + int part_num; + uint64_t cur_offs; + + list_for_each(dentry, &devices) { + dev = list_entry(dentry, struct mtd_device, link); + + if (get_mtd_info(dev->id->type, dev->id->num, &mtd)) + return 1; + + part_num = 0; + cur_offs = 0; + list_for_each(pentry, &dev->parts) { + part = list_entry(pentry, struct part_info, link); + + debug("spread_partitions: device = %s%d, partition %d =" + " (%s) 0x%08x@0x%08x\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num, + part_num, part->name, part->size, + part->offset); + + if (cur_offs > part->offset) + part->offset = cur_offs; + + spread_partition(mtd, part, &cur_offs); + + part_num++; + } + } + + index_partitions(); + + if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { + printf("generated mtdparts too long, reseting to null\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_CMD_MTDPARTS_SPREAD */ + /** * Accept character string describing mtd partitions and call device_parse() * for each entry. Add created devices to the global devices list. @@ -1782,9 +1950,13 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } /* mtdparts add <mtd-dev> <size>[@<offset>] <name> [ro] */ - if (((argc == 5) || (argc == 6)) && (strcmp(argv[1], "add") == 0)) { + if (((argc == 5) || (argc == 6)) && (strncmp(argv[1], "add", 3) == 0)) { #define PART_ADD_DESC_MAXLEN 64 char tmpbuf[PART_ADD_DESC_MAXLEN]; +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) + struct mtd_info *mtd; + uint64_t next_offset; +#endif u8 type, num, len; struct mtd_device *dev; struct mtd_device *dev_tmp; @@ -1819,15 +1991,25 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) debug("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, dev->id->mtd_id); - if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) { + p = list_entry(dev->parts.next, struct part_info, link); + +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) + if (get_mtd_info(dev->id->type, dev->id->num, &mtd)) + return 1; + + if (!strcmp(&argv[1][3], ".spread")) { + spread_partition(mtd, p, &next_offset); + debug("increased %s to %d bytes\n", p->name, p->size); + } +#endif + + dev_tmp = device_find(dev->id->type, dev->id->num); + if (dev_tmp == NULL) { device_add(dev); - } else { + } else if (part_add(dev_tmp, p) != 0) { /* merge new partition with existing ones*/ - p = list_entry(dev->parts.next, struct part_info, link); - if (part_add(dev_tmp, p) != 0) { - device_del(dev); - return 1; - } + device_del(dev); + return 1; } if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { @@ -1845,6 +2027,11 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return delete_partition(argv[2]); } +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) + if ((argc == 2) && (strcmp(argv[1], "spread") == 0)) + return spread_partitions(); +#endif /* CONFIG_CMD_MTDPARTS_SPREAD */ + return cmd_usage(cmdtp); } @@ -1867,8 +2054,20 @@ U_BOOT_CMD( " - delete partition (e.g. part-id = nand0,1)\n" "mtdparts add <mtd-dev> <size>[@<offset>] [<name>] [ro]\n" " - add partition\n" +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) + "mtdparts add.spread <mtd-dev> <size>[@<offset>] [<name>] [ro]\n" + " - add partition, padding size by skipping bad blocks\n" +#endif "mtdparts default\n" - " - reset partition table to defaults\n\n" + " - reset partition table to defaults\n" +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) + "mtdparts spread\n" + " - adjust the sizes of the partitions so they are\n" + " at least as big as the mtdparts variable specifies\n" + " and they each start on a good block\n\n" +#else + "\n" +#endif /* CONFIG_CMD_MTDPARTS_SPREAD */ "-----\n\n" "this command uses three environment variables:\n\n" "'partition' - keeps current partition identifier\n\n" diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 3f1d077ff7..8a812379a6 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -10,6 +10,13 @@ * (C) Copyright 2006-2007 OpenMoko, Inc. * Added 16-bit nand support * (C) 2004 Texas Instruments + * + * Copyright 2010 Freescale Semiconductor + * The portions of this file whose copyright is held by Freescale and which + * are not considered a derived work of GPL v2-only code may be distributed + * and/or modified under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. */ #include <common.h> @@ -30,10 +37,16 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); #endif -static int nand_dump(nand_info_t *nand, ulong off, int only_oob) +static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) { int i; u_char *datbuf, *oobbuf, *p; + static loff_t last; + + if (repeat) + off = last + nand->writesize; + + last = off; datbuf = malloc(nand->writesize + nand->oobsize); oobbuf = malloc(nand->oobsize); @@ -85,74 +98,132 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob) /* ------------------------------------------------------------------------- */ -static inline int str2long(char *p, ulong *num) +static int set_dev(int dev) +{ + if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[dev].name) { + puts("No such device\n"); + return -1; + } + + if (nand_curr_device == dev) + return 0; + + printf("Device %d: %s", dev, nand_info[dev].name); + puts("... is now current device\n"); + nand_curr_device = dev; + +#ifdef CONFIG_SYS_NAND_SELECT_DEVICE + board_nand_select_device(nand_info[dev].priv, dev); +#endif + + return 0; +} + +static inline int str2off(const char *p, loff_t *num) +{ + char *endptr; + + *num = simple_strtoull(p, &endptr, 16); + return *p != '\0' && *endptr == '\0'; +} + +static inline int str2long(const char *p, ulong *num) { char *endptr; *num = simple_strtoul(p, &endptr, 16); - return (*p != '\0' && *endptr == '\0') ? 1 : 0; + return *p != '\0' && *endptr == '\0'; } -static int -arg_off_size(int argc, char * const argv[], nand_info_t *nand, ulong *off, size_t *size) +static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size) { - int idx = nand_curr_device; -#if defined(CONFIG_CMD_MTDPARTS) +#ifdef CONFIG_CMD_MTDPARTS struct mtd_device *dev; struct part_info *part; u8 pnum; + int ret; - if (argc >= 1 && !(str2long(argv[0], off))) { - if ((mtdparts_init() == 0) && - (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) { - if (dev->id->type != MTD_DEV_TYPE_NAND) { - puts("not a NAND device\n"); - return -1; - } - *off = part->offset; - if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { - printf("'%s' is not a number\n", argv[1]); - return -1; - } - if (*size > part->size) - *size = part->size; - } else { - *size = part->size; - } - idx = dev->id->num; - *nand = nand_info[idx]; - goto out; - } + ret = mtdparts_init(); + if (ret) + return ret; + + ret = find_dev_and_part(partname, &dev, &pnum, &part); + if (ret) + return ret; + + if (dev->id->type != MTD_DEV_TYPE_NAND) { + puts("not a NAND device\n"); + return -1; } + + *off = part->offset; + *size = part->size; + *idx = dev->id->num; + + ret = set_dev(*idx); + if (ret) + return ret; + + return 0; +#else + puts("offset is not a number\n"); + return -1; #endif +} - if (argc >= 1) { - if (!(str2long(argv[0], off))) { - printf("'%s' is not a number\n", argv[0]); - return -1; - } - } else { +static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize) +{ + if (!str2off(arg, off)) + return get_part(arg, idx, off, maxsize); + + if (*off >= nand_info[*idx].size) { + puts("Offset exceeds device limit\n"); + return -1; + } + + *maxsize = nand_info[*idx].size - *off; + return 0; +} + +static int arg_off_size(int argc, char *const argv[], int *idx, + loff_t *off, loff_t *size) +{ + int ret; + loff_t maxsize; + + if (argc == 0) { *off = 0; + *size = nand_info[*idx].size; + goto print; } - if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { - printf("'%s' is not a number\n", argv[1]); - return -1; - } - } else { - *size = nand->size - *off; + ret = arg_off(argv[0], idx, off, &maxsize); + if (ret) + return ret; + + if (argc == 1) { + *size = maxsize; + goto print; } -#if defined(CONFIG_CMD_MTDPARTS) -out: -#endif - printf("device %d ", idx); - if (*size == nand->size) + if (!str2off(argv[1], size)) { + printf("'%s' is not a number\n", argv[1]); + return -1; + } + + if (*size > maxsize) { + puts("Size exceeds partition or device limit\n"); + return -1; + } + +print: + printf("device %d ", *idx); + if (*size == nand_info[*idx].size) puts("whole chip\n"); else - printf("offset 0x%lx, size 0x%zx\n", *off, *size); + printf("offset 0x%llx, size 0x%llx\n", + (unsigned long long)*off, (unsigned long long)*size); return 0; } @@ -200,14 +271,20 @@ static void do_nand_status(nand_info_t *nand) #ifdef CONFIG_ENV_OFFSET_OOB unsigned long nand_env_oob_offset; -int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand, - int argc, char * const argv[]) +int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) { int ret; uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; - + nand_info_t *nand = &nand_info[0]; char *cmd = argv[1]; + if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) { + puts("no devices available\n"); + return 1; + } + + set_dev(0); + if (!strcmp(cmd, "get")) { ret = get_nand_env_oob(nand, &nand_env_oob_offset); if (ret) @@ -215,16 +292,21 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand, printf("0x%08lx\n", nand_env_oob_offset); } else if (!strcmp(cmd, "set")) { - ulong addr; - size_t dummy_size; + loff_t addr; + loff_t maxsize; struct mtd_oob_ops ops; + int idx = 0; if (argc < 3) goto usage; - if (arg_off_size(argc - 2, argv + 2, nand, &addr, - &dummy_size) < 0) { - printf("Offset or partition name expected\n"); + if (arg_off(argv[2], &idx, &addr, &maxsize)) { + puts("Offset or partition name expected\n"); + return 1; + } + + if (idx != 0) { + puts("Partition not on first NAND device\n"); return 1; } @@ -264,8 +346,8 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand, if (addr != nand_env_oob_offset) { printf("Verification of env offset in OOB failed: " - "0x%08lx expected but got 0x%08lx\n", - addr, nand_env_oob_offset); + "0x%08llx expected but got 0x%08lx\n", + (unsigned long long)addr, nand_env_oob_offset); return 1; } } else { @@ -293,9 +375,9 @@ static void nand_print_info(int idx) int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - int i, dev, ret = 0; - ulong addr, off; - size_t size; + int i, ret = 0; + ulong addr; + loff_t off, size; char *cmd, *s; nand_info_t *nand; #ifdef CONFIG_SYS_NAND_QUIET @@ -304,6 +386,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) int quiet = 0; #endif const char *quiet_str = getenv("quiet"); + int dev = nand_curr_device; + int repeat = flag & CMD_FLAG_REPEAT; /* at least two arguments please */ if (argc < 2) @@ -314,6 +398,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) cmd = argv[1]; + /* Only "dump" is repeatable. */ + if (repeat && strcmp(cmd, "dump")) + return 0; + if (strcmp(cmd, "info") == 0) { putc('\n'); @@ -325,68 +413,45 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } if (strcmp(cmd, "device") == 0) { - if (argc < 3) { putc('\n'); - if ((nand_curr_device < 0) || - (nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE)) + if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE) puts("no devices available\n"); else - nand_print_info(nand_curr_device); + nand_print_info(dev); return 0; } - dev = (int)simple_strtoul(argv[2], NULL, 10); - if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev].name) { - puts("No such device\n"); - return 1; - } - printf("Device %d: %s", dev, nand_info[dev].name); - puts("... is now current device\n"); - nand_curr_device = dev; -#ifdef CONFIG_SYS_NAND_SELECT_DEVICE - /* - * Select the chip in the board/cpu specific driver - */ - board_nand_select_device(nand_info[dev].priv, dev); -#endif + dev = (int)simple_strtoul(argv[2], NULL, 10); + set_dev(dev); return 0; } - if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && - strncmp(cmd, "dump", 4) != 0 && - strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && - strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && - strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 -#ifdef CONFIG_ENV_OFFSET_OOB - && strcmp(cmd, "env.oob") != 0 -#endif - ) - goto usage; - #ifdef CONFIG_ENV_OFFSET_OOB /* this command operates only on the first nand device */ - if (strcmp(cmd, "env.oob") == 0) { - return do_nand_env_oob(cmdtp, &nand_info[0], - argc - 1, argv + 1); - } + if (strcmp(cmd, "env.oob") == 0) + return do_nand_env_oob(cmdtp, argc - 1, argv + 1); #endif - /* the following commands operate on the current device */ - if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[nand_curr_device].name) { + /* The following commands operate on the current device, unless + * overridden by a partition specifier. Note that if somehow the + * current device is invalid, it will have to be changed to a valid + * one before these commands can run, even if a partition specifier + * for another device is to be used. + */ + if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[dev].name) { puts("\nno devices available\n"); return 1; } - nand = &nand_info[nand_curr_device]; + nand = &nand_info[dev]; if (strcmp(cmd, "bad") == 0) { - printf("\nDevice %d bad blocks:\n", nand_curr_device); + printf("\nDevice %d bad blocks:\n", dev); for (off = 0; off < nand->size; off += nand->erasesize) if (nand_block_isbad(nand, off)) - printf(" %08lx\n", off); + printf(" %08llx\n", (unsigned long long)off); return 0; } @@ -395,23 +460,52 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) * 0 1 2 3 4 * nand erase [clean] [off size] */ - if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) { + if (strncmp(cmd, "erase", 5) == 0 || strncmp(cmd, "scrub", 5) == 0) { nand_erase_options_t opts; /* "clean" at index 2 means request to write cleanmarker */ int clean = argc > 2 && !strcmp("clean", argv[2]); int o = clean ? 3 : 2; - int scrub = !strcmp(cmd, "scrub"); + int scrub = !strncmp(cmd, "scrub", 5); + int part = 0; + int chip = 0; + int spread = 0; + int args = 2; + + if (cmd[5] != 0) { + if (!strcmp(&cmd[5], ".spread")) { + spread = 1; + } else if (!strcmp(&cmd[5], ".part")) { + part = 1; + args = 1; + } else if (!strcmp(&cmd[5], ".chip")) { + chip = 1; + args = 0; + } else { + goto usage; + } + } + + /* + * Don't allow missing arguments to cause full chip/partition + * erases -- easy to do accidentally, e.g. with a misspelled + * variable name. + */ + if (argc != o + args) + goto usage; - printf("\nNAND %s: ", scrub ? "scrub" : "erase"); + printf("\nNAND %s: ", cmd); /* skip first two or three arguments, look for offset and size */ - if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0) + if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0) return 1; + nand = &nand_info[dev]; + memset(&opts, 0, sizeof(opts)); opts.offset = off; opts.length = size; opts.jffs2 = clean; opts.quiet = quiet; + opts.spread = spread; if (scrub) { puts("Warning: " @@ -449,19 +543,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) if (argc < 3) goto usage; - s = strchr(cmd, '.'); off = (int)simple_strtoul(argv[2], NULL, 16); - - if (s != NULL && strcmp(s, ".oob") == 0) - ret = nand_dump(nand, off, 1); - else - ret = nand_dump(nand, off, 0); + ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat); return ret == 0 ? 1 : 0; - } if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + size_t rwsize; int read; if (argc < 4) @@ -471,23 +560,26 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: ", read ? "read" : "write"); - if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0) + if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0) return 1; + nand = &nand_info[dev]; + rwsize = size; + s = strchr(cmd, '.'); if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) - ret = nand_read_skip_bad(nand, off, &size, + ret = nand_read_skip_bad(nand, off, &rwsize, (u_char *)addr); else - ret = nand_write_skip_bad(nand, off, &size, + ret = nand_write_skip_bad(nand, off, &rwsize, (u_char *)addr); } else if (!strcmp(s, ".oob")) { /* out-of-band data */ mtd_oob_ops_t ops = { .oobbuf = (u8 *)addr, - .ooblen = size, + .ooblen = rwsize, .mode = MTD_OOB_RAW }; @@ -500,7 +592,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } - printf(" %zu bytes %s: %s\n", size, + printf(" %zu bytes %s: %s\n", rwsize, read ? "read" : "written", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; @@ -564,7 +656,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) return 1; - if (!nand_unlock(nand, off, size)) { + if (!nand_unlock(&nand_info[dev], off, size)) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " @@ -588,11 +680,16 @@ U_BOOT_CMD( "nand write - addr off|partition size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" - "nand erase [clean] [off size] - erase 'size' bytes from\n" - " offset 'off' (entire device if not specified)\n" + "nand erase[.spread] [clean] [off [size]] - erase 'size' bytes " + "from offset 'off'\n" + " With '.spread', erase enough for given file size, otherwise,\n" + " 'size' includes skipped bad blocks.\n" + "nand erase.part [clean] partition - erase entire mtd partition'\n" + "nand erase.chip [clean] - erase entire chip'\n" "nand bad - show bad blocks\n" "nand dump[.oob] off - dump page\n" - "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" + "nand scrub off size | scrub.part partition | scrub.chip\n" + " really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)" #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK diff --git a/common/cmd_net.c b/common/cmd_net.c index 3ffb9df1de..44d17db19c 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -54,6 +54,7 @@ U_BOOT_CMD( "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#ifdef CONFIG_CMD_RARP int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return netboot_common (RARP, cmdtp, argc, argv); @@ -64,6 +65,7 @@ U_BOOT_CMD( "boot image via network using RARP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#endif #if defined(CONFIG_CMD_DHCP) int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 6eb52ed50c..a195ddab35 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -142,3 +142,47 @@ void put_mtd_device(struct mtd_info *mtd) c = --mtd->usecount; BUG_ON(c < 0); } + +#if defined(CONFIG_CMD_MTDPARTS_SPREAD) +/** + * mtd_get_len_incl_bad + * + * Check if length including bad blocks fits into device. + * + * @param mtd an MTD device + * @param offset offset in flash + * @param length image length + * @return image length including bad blocks in *len_incl_bad and whether or not + * the length returned was truncated in *truncated + */ +void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, + const uint64_t length, uint64_t *len_incl_bad, + int *truncated) +{ + *truncated = 0; + *len_incl_bad = 0; + + if (!mtd->block_isbad) { + *len_incl_bad = length; + return; + } + + uint64_t len_excl_bad = 0; + uint64_t block_len; + + while (len_excl_bad < length) { + if (offset >= mtd->size) { + *truncated = 1; + return; + } + + block_len = mtd->erasesize - (offset & (mtd->erasesize - 1)); + + if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1))) + len_excl_bad += block_len; + + *len_incl_bad += block_len; + offset += block_len; + } +} +#endif /* defined(CONFIG_CMD_MTDPARTS_SPREAD) */ diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index e2e43eaec4..f647e43668 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -230,18 +230,6 @@ static void part_sync(struct mtd_info *mtd) part->master->sync(part->master); } -static int part_suspend(struct mtd_info *mtd) -{ - struct mtd_part *part = PART(mtd); - return part->master->suspend(part->master); -} - -static void part_resume(struct mtd_info *mtd) -{ - struct mtd_part *part = PART(mtd); - part->master->resume(part->master); -} - static int part_block_isbad(struct mtd_info *mtd, loff_t ofs) { struct mtd_part *part = PART(mtd); @@ -339,10 +327,6 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, slave->mtd.get_fact_prot_info = part_get_fact_prot_info; if (master->sync) slave->mtd.sync = part_sync; - if (!partno && master->suspend && master->resume) { - slave->mtd.suspend = part_suspend; - slave->mtd.resume = part_resume; - } if (master->lock) slave->mtd.lock = part_lock; if (master->unlock) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 7d178468ad..21cc5a3940 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -32,30 +32,6 @@ * */ -/* XXX U-BOOT XXX */ -#if 0 -#include <linux/module.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/sched.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/compatmac.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/leds.h> -#include <asm/io.h> - -#ifdef CONFIG_MTD_PARTITIONS -#include <linux/mtd/partitions.h> -#endif - -#endif - #include <common.h> #define ENOTSUPP 524 /* Operation is not supported */ @@ -75,10 +51,6 @@ #include <asm/io.h> #include <asm/errno.h> -#ifdef CONFIG_JFFS2_NAND -#include <jffs2/jffs2.h> -#endif - /* * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting * a flash. NAND flash is initialized prior to interrupts so standard timers @@ -143,44 +115,17 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, static int nand_wait(struct mtd_info *mtd, struct nand_chip *this); -/* - * For devices which display every fart in the system on a separate LED. Is - * compiled away when LED support is disabled. - */ -/* XXX U-BOOT XXX */ -#if 0 -DEFINE_LED_TRIGGER(nand_led_trigger); -#endif - /** * nand_release_device - [GENERIC] release chip * @mtd: MTD device structure * * Deselect, release chip lock and wake up anyone waiting on the device */ -/* XXX U-BOOT XXX */ -#if 0 -static void nand_release_device(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - - /* De-select the NAND device */ - chip->select_chip(mtd, -1); - - /* Release the controller and the chip */ - spin_lock(&chip->controller->lock); - chip->controller->active = NULL; - chip->state = FL_READY; - wake_up(&chip->controller->wq); - spin_unlock(&chip->controller->lock); -} -#else static void nand_release_device (struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; this->select_chip(mtd, -1); /* De-select the NAND device */ } -#endif /** * nand_read_byte - [DEFAULT] read one byte from the chip @@ -490,24 +435,6 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, * Wait for the ready pin, after a command * The timeout is catched later. */ -/* XXX U-BOOT XXX */ -#if 0 -void nand_wait_ready(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - unsigned long timeo = jiffies + 2; - - led_trigger_event(nand_led_trigger, LED_FULL); - /* wait until command is processed or timeout occures */ - do { - if (chip->dev_ready(mtd)) - break; - touch_softlockup_watchdog(); - } while (time_before(jiffies, timeo)); - led_trigger_event(nand_led_trigger, LED_OFF); -} -EXPORT_SYMBOL_GPL(nand_wait_ready); -#else void nand_wait_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -522,7 +449,6 @@ void nand_wait_ready(struct mtd_info *mtd) break; } } -#endif /** * nand_command - [DEFAULT] Send command to NAND device @@ -759,45 +685,11 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, * * Get the device and lock it for exclusive access */ -/* XXX U-BOOT XXX */ -#if 0 -static int -nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) -{ - spinlock_t *lock = &chip->controller->lock; - wait_queue_head_t *wq = &chip->controller->wq; - DECLARE_WAITQUEUE(wait, current); - retry: - spin_lock(lock); - - /* Hardware controller shared among independend devices */ - /* Hardware controller shared among independend devices */ - if (!chip->controller->active) - chip->controller->active = chip; - - if (chip->controller->active == chip && chip->state == FL_READY) { - chip->state = new_state; - spin_unlock(lock); - return 0; - } - if (new_state == FL_PM_SUSPENDED) { - spin_unlock(lock); - return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; - } - set_current_state(TASK_UNINTERRUPTIBLE); - add_wait_queue(wq, &wait); - spin_unlock(lock); - schedule(); - remove_wait_queue(wq, &wait); - goto retry; -} -#else static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) { this->state = new_state; return 0; } -#endif /** * nand_wait - [DEFAULT] wait until the command is done @@ -808,46 +700,6 @@ static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int ne * Erase can take up to 400ms and program up to 20ms according to * general NAND and SmartMedia specs */ -/* XXX U-BOOT XXX */ -#if 0 -static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) -{ - - unsigned long timeo = jiffies; - int status, state = chip->state; - - if (state == FL_ERASING) - timeo += (HZ * 400) / 1000; - else - timeo += (HZ * 20) / 1000; - - led_trigger_event(nand_led_trigger, LED_FULL); - - /* Apply this short delay always to ensure that we do wait tWB in - * any case on any machine. */ - ndelay(100); - - if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) - chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); - else - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - - while (time_before(jiffies, timeo)) { - if (chip->dev_ready) { - if (chip->dev_ready(mtd)) - break; - } else { - if (chip->read_byte(mtd) & NAND_STATUS_READY) - break; - } - cond_resched(); - } - led_trigger_event(nand_led_trigger, LED_OFF); - - status = (int)chip->read_byte(mtd); - return status; -} -#else static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) { unsigned long timeo; @@ -886,7 +738,6 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) return this->read_byte(mtd); } -#endif /** * nand_read_page_raw - [Intern] read raw page data without ecc @@ -2001,13 +1852,6 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, if (!writelen) return 0; - /* reject writes, which are not page aligned */ - if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { - printk(KERN_NOTICE "nand_write: " - "Attempt to write not page aligned data\n"); - return -EINVAL; - } - column = to & (mtd->writesize - 1); subpage = column || (writelen & (mtd->writesize - 1)); @@ -2523,32 +2367,6 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) return chip->block_markbad(mtd, ofs); } -/** - * nand_suspend - [MTD Interface] Suspend the NAND flash - * @mtd: MTD device structure - */ -static int nand_suspend(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - - return nand_get_device(chip, mtd, FL_PM_SUSPENDED); -} - -/** - * nand_resume - [MTD Interface] Resume the NAND flash - * @mtd: MTD device structure - */ -static void nand_resume(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - - if (chip->state == FL_PM_SUSPENDED) - nand_release_device(mtd); - else - printk(KERN_ERR "nand_resume() called for a chip which is not " - "in suspended state\n"); -} - /* * Set default functions */ @@ -2584,17 +2402,8 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; - - if (!chip->controller) { + if (!chip->controller) chip->controller = &chip->hwcontrol; - - /* XXX U-BOOT XXX */ -#if 0 - spin_lock_init(&chip->controller->lock); - init_waitqueue_head(&chip->controller->wq); -#endif - } - } /* @@ -3028,8 +2837,6 @@ int nand_scan_tail(struct mtd_info *mtd) mtd->sync = nand_sync; mtd->lock = NULL; mtd->unlock = NULL; - mtd->suspend = nand_suspend; - mtd->resume = nand_resume; mtd->block_isbad = nand_block_isbad; mtd->block_markbad = nand_block_markbad; @@ -3043,16 +2850,6 @@ int nand_scan_tail(struct mtd_info *mtd) return 0; } -/* module_text_address() isn't exported, and it's mostly a pointless - test if this is a module _anyway_ -- they'd have to try _really_ hard - to call us from in-kernel code if the core NAND support is modular. */ -#ifdef MODULE -#define caller_is_module() (1) -#else -#define caller_is_module() \ - module_text_address((unsigned long)__builtin_return_address(0)) -#endif - /** * nand_scan - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure @@ -3069,15 +2866,6 @@ int nand_scan(struct mtd_info *mtd, int maxchips) { int ret; - /* Many callers got this wrong, so check for it for a while... */ - /* XXX U-BOOT XXX */ -#if 0 - if (!mtd->owner && caller_is_module()) { - printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); - BUG(); - } -#endif - ret = nand_scan_ident(mtd, maxchips); if (!ret) ret = nand_scan_tail(mtd); @@ -3096,40 +2884,9 @@ void nand_release(struct mtd_info *mtd) /* Deregister partitions */ del_mtd_partitions(mtd); #endif - /* Deregister the device */ - /* XXX U-BOOT XXX */ -#if 0 - del_mtd_device(mtd); -#endif /* Free bad block table memory */ kfree(chip->bbt); if (!(chip->options & NAND_OWN_BUFFERS)) kfree(chip->buffers); } - -/* XXX U-BOOT XXX */ -#if 0 -EXPORT_SYMBOL_GPL(nand_scan); -EXPORT_SYMBOL_GPL(nand_scan_ident); -EXPORT_SYMBOL_GPL(nand_scan_tail); -EXPORT_SYMBOL_GPL(nand_release); - -static int __init nand_base_init(void) -{ - led_trigger_register_simple("nand-disk", &nand_led_trigger); - return 0; -} - -static void __exit nand_base_exit(void) -{ - led_trigger_unregister_simple(nand_led_trigger); -} - -module_init(nand_base_init); -module_exit(nand_base_exit); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); -MODULE_DESCRIPTION("Generic NAND flash driver code"); -#endif diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 2fe68abe1d..521dddec27 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -58,19 +58,6 @@ #include <asm/errno.h> -/* XXX U-BOOT XXX */ -#if 0 -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/compatmac.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/vmalloc.h> -#endif - /** * check_pattern - [GENERIC] check if a pattern is in the buffer * @buf: the buffer to search @@ -1231,9 +1218,3 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) } return 1; } - -/* XXX U-BOOT XXX */ -#if 0 -EXPORT_SYMBOL(nand_scan_bbt); -EXPORT_SYMBOL(nand_default_bbt); -#endif diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c index 463f9cb4d4..52bc916afb 100644 --- a/drivers/mtd/nand/nand_ecc.c +++ b/drivers/mtd/nand/nand_ecc.c @@ -37,14 +37,6 @@ #include <common.h> -/* XXX U-BOOT XXX */ -#if 0 -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/mtd/nand_ecc.h> -#endif - #include <asm/errno.h> #include <linux/mtd/mtd.h> @@ -140,10 +132,6 @@ int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, return 0; } -/* XXX U-BOOT XXX */ -#if 0 -EXPORT_SYMBOL(nand_calculate_ecc); -#endif #endif /* CONFIG_NAND_SPL */ static inline int countbits(uint32_t byte) @@ -212,8 +200,3 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat, return -EBADMSG; } - -/* XXX U-BOOT XXX */ -#if 0 -EXPORT_SYMBOL(nand_correct_data); -#endif diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 29c42f73b1..22c7411694 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -28,6 +28,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * + * Copyright 2010 Freescale Semiconductor + * The portions of this file whose copyright is held by Freescale and which + * are not considered a derived work of GPL v2-only code may be distributed + * and/or modified under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. */ #include <common.h> @@ -69,7 +75,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) { struct jffs2_unknown_node cleanmarker; erase_info_t erase; - ulong erase_length; + unsigned long erase_length, erased_length; /* in blocks */ int bbtest = 1; int result; int percent_complete = -1; @@ -78,13 +84,19 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) struct mtd_oob_ops oob_opts; struct nand_chip *chip = meminfo->priv; + if ((opts->offset & (meminfo->writesize - 1)) != 0) { + printf("Attempt to erase non page aligned data\n"); + return -1; + } + memset(&erase, 0, sizeof(erase)); memset(&oob_opts, 0, sizeof(oob_opts)); erase.mtd = meminfo; erase.len = meminfo->erasesize; erase.addr = opts->offset; - erase_length = opts->length; + erase_length = lldiv(opts->length + meminfo->erasesize - 1, + meminfo->erasesize); cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK); cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER); @@ -108,15 +120,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) priv_nand->bbt = NULL; } - if (erase_length < meminfo->erasesize) { - printf("Warning: Erase size 0x%08lx smaller than one " \ - "erase block 0x%08x\n",erase_length, meminfo->erasesize); - printf(" Erasing 0x%08x instead\n", meminfo->erasesize); - erase_length = meminfo->erasesize; - } - - for (; - erase.addr < opts->offset + erase_length; + for (erased_length = 0; + erased_length < erase_length; erase.addr += meminfo->erasesize) { WATCHDOG_RESET (); @@ -129,6 +134,10 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) "0x%08llx " " \n", erase.addr); + + if (!opts->spread) + erased_length++; + continue; } else if (ret < 0) { @@ -139,6 +148,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) } } + erased_length++; + result = meminfo->erase(meminfo, &erase); if (result != 0) { printf("\n%s: MTD Erase failure: %d\n", @@ -165,9 +176,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) } if (!opts->quiet) { - unsigned long long n =(unsigned long long) - (erase.addr + meminfo->erasesize - opts->offset) - * 100; + unsigned long long n = erased_length * 100ULL; int percent; do_div(n, erase_length); @@ -202,41 +211,6 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) return 0; } -/* XXX U-BOOT XXX */ -#if 0 - -#define MAX_PAGE_SIZE 2048 -#define MAX_OOB_SIZE 64 - -/* - * buffer array used for writing data - */ -static unsigned char data_buf[MAX_PAGE_SIZE]; -static unsigned char oob_buf[MAX_OOB_SIZE]; - -/* OOB layouts to pass into the kernel as default */ -static struct nand_ecclayout none_ecclayout = { - .useecc = MTD_NANDECC_OFF, -}; - -static struct nand_ecclayout jffs2_ecclayout = { - .useecc = MTD_NANDECC_PLACE, - .eccbytes = 6, - .eccpos = { 0, 1, 2, 3, 6, 7 } -}; - -static struct nand_ecclayout yaffs_ecclayout = { - .useecc = MTD_NANDECC_PLACE, - .eccbytes = 6, - .eccpos = { 8, 9, 10, 13, 14, 15} -}; - -static struct nand_ecclayout autoplace_ecclayout = { - .useecc = MTD_NANDECC_AUTOPLACE -}; -#endif - -/* XXX U-BOOT XXX */ #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK /****************************************************************************** @@ -423,36 +397,43 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length) #endif /** - * get_len_incl_bad + * check_skip_len * - * Check if length including bad blocks fits into device. + * Check if there are any bad blocks, and whether length including bad + * blocks fits into device * * @param nand NAND device * @param offset offset in flash * @param length image length - * @return image length including bad blocks + * @return 0 if the image fits and there are no bad blocks + * 1 if the image fits, but there are bad blocks + * -1 if the image does not fit */ -static size_t get_len_incl_bad (nand_info_t *nand, loff_t offset, - const size_t length) +static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) { - size_t len_incl_bad = 0; size_t len_excl_bad = 0; - size_t block_len; + int ret = 0; while (len_excl_bad < length) { - block_len = nand->erasesize - (offset & (nand->erasesize - 1)); + size_t block_len, block_off; + loff_t block_start; - if (!nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) - len_excl_bad += block_len; + if (offset >= nand->size) + return -1; - len_incl_bad += block_len; - offset += block_len; + block_start = offset & ~(loff_t)(nand->erasesize - 1); + block_off = offset & (nand->erasesize - 1); + block_len = nand->erasesize - block_off; - if (offset >= nand->size) - break; + if (!nand_block_isbad(nand, block_start)) + len_excl_bad += block_len; + else + ret = 1; + + offset += block_len; } - return len_incl_bad; + return ret; } /** @@ -474,29 +455,41 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, { int rval; size_t left_to_write = *length; - size_t len_incl_bad; u_char *p_buffer = buffer; + int need_skip; - /* Reject writes, which are not page aligned */ - if ((offset & (nand->writesize - 1)) != 0 || - (*length & (nand->writesize - 1)) != 0) { + /* + * nand_write() handles unaligned, partial page writes. + * + * We allow length to be unaligned, for convenience in + * using the $filesize variable. + * + * However, starting at an unaligned offset makes the + * semantics of bad block skipping ambiguous (really, + * you should only start a block skipping access at a + * partition boundary). So don't try to handle that. + */ + if ((offset & (nand->writesize - 1)) != 0) { printf ("Attempt to write non page aligned data\n"); + *length = 0; return -EINVAL; } - len_incl_bad = get_len_incl_bad (nand, offset, *length); - - if ((offset + len_incl_bad) > nand->size) { + need_skip = check_skip_len(nand, offset, *length); + if (need_skip < 0) { printf ("Attempt to write outside the flash area\n"); + *length = 0; return -EINVAL; } - if (len_incl_bad == *length) { + if (!need_skip) { rval = nand_write (nand, offset, length, buffer); - if (rval != 0) - printf ("NAND write to offset %llx failed %d\n", - offset, rval); + if (rval == 0) + return 0; + *length = 0; + printf ("NAND write to offset %llx failed %d\n", + offset, rval); return rval; } @@ -553,20 +546,28 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, { int rval; size_t left_to_read = *length; - size_t len_incl_bad; u_char *p_buffer = buffer; + int need_skip; - len_incl_bad = get_len_incl_bad (nand, offset, *length); + if ((offset & (nand->writesize - 1)) != 0) { + printf ("Attempt to read non page aligned data\n"); + *length = 0; + return -EINVAL; + } - if ((offset + len_incl_bad) > nand->size) { + need_skip = check_skip_len(nand, offset, *length); + if (need_skip < 0) { printf ("Attempt to read outside the flash area\n"); + *length = 0; return -EINVAL; } - if (len_incl_bad == *length) { + if (!need_skip) { rval = nand_read (nand, offset, length, buffer); if (!rval || rval == -EUCLEAN) return 0; + + *length = 0; printf ("NAND read from offset %llx failed %d\n", offset, rval); return rval; diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index f9273ab970..24e02c2840 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2213,6 +2213,7 @@ char *onenand_print_device_info(int device, int version) } static const struct onenand_manufacturers onenand_manuf_ids[] = { + {ONENAND_MFR_NUMONYX, "Numonyx"}, {ONENAND_MFR_SAMSUNG, "Samsung"}, }; diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 218eeff86e..79eb66b267 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_ENC28J60_LPC2292) += enc28j60_lpc2292.o COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index d82459b1ce..c525eeda42 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -208,7 +208,7 @@ static int at91emac_phy_reset(struct eth_device *netdev) at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - for (i = 0; i < 100000 / 100; i++) { + for (i = 0; i < 30000; i++) { at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &status); if (status & BMSR_ANEGCOMPLETE) @@ -221,7 +221,7 @@ static int at91emac_phy_reset(struct eth_device *netdev) } else { printf("%s: Autonegotiation timed out (status=0x%04x)\n", netdev->name, status); - return 1; + return -1; } return 0; } @@ -240,7 +240,7 @@ static int at91emac_phy_init(struct eth_device *netdev) MII_PHYSID1, &phy_id); if (phy_id == 0xffff) { printf("%s: No PHY present\n", netdev->name); - return 1; + return -1; } at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, @@ -249,7 +249,7 @@ static int at91emac_phy_init(struct eth_device *netdev) if (!(status & BMSR_LSTATUS)) { /* Try to re-negotiate if we don't have link already. */ if (at91emac_phy_reset(netdev)) - return 2; + return -2; for (i = 0; i < 100000 / 100; i++) { at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, @@ -261,7 +261,7 @@ static int at91emac_phy_init(struct eth_device *netdev) } if (!(status & BMSR_LSTATUS)) { VERBOSEP("%s: link down\n", netdev->name); - return 3; + return -3; } else { at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_ADVERTISE, &adv); @@ -286,7 +286,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac) at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ - return 1; + return -1; if (stat1 & BMSR_100FULL) { /*set Emac for 100BaseTX and Full Duplex */ @@ -321,7 +321,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac) &emac->cfg); return 0; } - return 1; + return 0; } static int at91emac_init(struct eth_device *netdev, bd_t *bd) @@ -387,7 +387,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) at91emac_UpdateLinkSpeed(emac); return 0; } - return 1; + return -1; } static void at91emac_halt(struct eth_device *netdev) @@ -489,11 +489,11 @@ int at91emac_register(bd_t *bis, unsigned long iobase) iobase = AT91_EMAC_BASE; emac = malloc(sizeof(*emac)+512); if (emac == NULL) - return 1; + return -1; dev = malloc(sizeof(*dev)); if (dev == NULL) { free(emac); - return 1; + return -1; } /* alignment as per Errata (64 bytes) is insufficient! */ emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 41a9910919..e06896fea7 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -65,21 +65,6 @@ void eth_mdio_enable(void) davinci_eth_mdio_enable(); } -static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - -/* - * This function must be called before emac_open() if you want to override - * the default mac address. - */ -void davinci_eth_set_mac_addr(const u_int8_t *addr) -{ - int i; - - for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) { - davinci_eth_mac_addr[i] = addr[i]; - } -} - /* EMAC Addresses */ static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; @@ -100,6 +85,43 @@ static volatile u_int8_t active_phy_addr = 0xff; phy_t phy; +static int davinci_eth_set_mac_addr(struct eth_device *dev) +{ + unsigned long mac_hi; + unsigned long mac_lo; + + /* + * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast + * receive) + * Using channel 0 only - other channels are disabled + * */ + writel(0, &adap_emac->MACINDEX); + mac_hi = (dev->enetaddr[3] << 24) | + (dev->enetaddr[2] << 16) | + (dev->enetaddr[1] << 8) | + (dev->enetaddr[0]); + mac_lo = (dev->enetaddr[5] << 8) | + (dev->enetaddr[4]); + + writel(mac_hi, &adap_emac->MACADDRHI); +#if defined(DAVINCI_EMAC_VERSION2) + writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, + &adap_emac->MACADDRLO); +#else + writel(mac_lo, &adap_emac->MACADDRLO); +#endif + + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); + + /* Set source MAC address - REQUIRED */ + writel(mac_hi, &adap_emac->MACSRCADDRHI); + writel(mac_lo, &adap_emac->MACSRCADDRLO); + + + return 0; +} + static void davinci_eth_mdio_enable(void) { u_int32_t clkdiv; @@ -286,8 +308,6 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) dv_reg_p addr; u_int32_t clkdiv, cnt; volatile emac_desc *rx_desc; - unsigned long mac_hi; - unsigned long mac_lo; debug_emac("+ emac_open\n"); @@ -311,30 +331,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) writel(1, &adap_emac->TXCONTROL); writel(1, &adap_emac->RXCONTROL); - /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ - /* Using channel 0 only - other channels are disabled */ - writel(0, &adap_emac->MACINDEX); - mac_hi = (davinci_eth_mac_addr[3] << 24) | - (davinci_eth_mac_addr[2] << 16) | - (davinci_eth_mac_addr[1] << 8) | - (davinci_eth_mac_addr[0]); - mac_lo = (davinci_eth_mac_addr[5] << 8) | - (davinci_eth_mac_addr[4]); - - writel(mac_hi, &adap_emac->MACADDRHI); -#if defined(DAVINCI_EMAC_VERSION2) - writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, - &adap_emac->MACADDRLO); -#else - writel(mac_lo, &adap_emac->MACADDRLO); -#endif - - writel(0, &adap_emac->MACHASH1); - writel(0, &adap_emac->MACHASH2); - - /* Set source MAC address - REQUIRED */ - writel(mac_hi, &adap_emac->MACSRCADDRHI); - writel(mac_lo, &adap_emac->MACSRCADDRLO); + davinci_eth_set_mac_addr(dev); /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; @@ -636,6 +633,7 @@ int davinci_emac_initialize(void) dev->halt = davinci_eth_close; dev->send = davinci_eth_send_packet; dev->recv = davinci_eth_rcv_packet; + dev->write_hwaddr = davinci_eth_set_mac_addr; eth_register(dev); diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 3238a502ca..6c161b632f 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -1,4 +1,9 @@ /* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * Martin Krause, Martin.Krause@tqs.de + * reworked original enc28j60.c + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -6,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -15,968 +20,959 @@ * MA 02111-1307 USA */ -#include <config.h> #include <common.h> #include <net.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spi.h> - -/* - * Control Registers in Bank 0 - */ - -#define CTL_REG_ERDPTL 0x00 -#define CTL_REG_ERDPTH 0x01 -#define CTL_REG_EWRPTL 0x02 -#define CTL_REG_EWRPTH 0x03 -#define CTL_REG_ETXSTL 0x04 -#define CTL_REG_ETXSTH 0x05 -#define CTL_REG_ETXNDL 0x06 -#define CTL_REG_ETXNDH 0x07 -#define CTL_REG_ERXSTL 0x08 -#define CTL_REG_ERXSTH 0x09 -#define CTL_REG_ERXNDL 0x0A -#define CTL_REG_ERXNDH 0x0B -#define CTL_REG_ERXRDPTL 0x0C -#define CTL_REG_ERXRDPTH 0x0D -#define CTL_REG_ERXWRPTL 0x0E -#define CTL_REG_ERXWRPTH 0x0F -#define CTL_REG_EDMASTL 0x10 -#define CTL_REG_EDMASTH 0x11 -#define CTL_REG_EDMANDL 0x12 -#define CTL_REG_EDMANDH 0x13 -#define CTL_REG_EDMADSTL 0x14 -#define CTL_REG_EDMADSTH 0x15 -#define CTL_REG_EDMACSL 0x16 -#define CTL_REG_EDMACSH 0x17 -/* these are common in all banks */ -#define CTL_REG_EIE 0x1B -#define CTL_REG_EIR 0x1C -#define CTL_REG_ESTAT 0x1D -#define CTL_REG_ECON2 0x1E -#define CTL_REG_ECON1 0x1F - -/* - * Control Registers in Bank 1 - */ - -#define CTL_REG_EHT0 0x00 -#define CTL_REG_EHT1 0x01 -#define CTL_REG_EHT2 0x02 -#define CTL_REG_EHT3 0x03 -#define CTL_REG_EHT4 0x04 -#define CTL_REG_EHT5 0x05 -#define CTL_REG_EHT6 0x06 -#define CTL_REG_EHT7 0x07 -#define CTL_REG_EPMM0 0x08 -#define CTL_REG_EPMM1 0x09 -#define CTL_REG_EPMM2 0x0A -#define CTL_REG_EPMM3 0x0B -#define CTL_REG_EPMM4 0x0C -#define CTL_REG_EPMM5 0x0D -#define CTL_REG_EPMM6 0x0E -#define CTL_REG_EPMM7 0x0F -#define CTL_REG_EPMCSL 0x10 -#define CTL_REG_EPMCSH 0x11 -#define CTL_REG_EPMOL 0x14 -#define CTL_REG_EPMOH 0x15 -#define CTL_REG_EWOLIE 0x16 -#define CTL_REG_EWOLIR 0x17 -#define CTL_REG_ERXFCON 0x18 -#define CTL_REG_EPKTCNT 0x19 - -/* - * Control Registers in Bank 2 - */ - -#define CTL_REG_MACON1 0x00 -#define CTL_REG_MACON2 0x01 -#define CTL_REG_MACON3 0x02 -#define CTL_REG_MACON4 0x03 -#define CTL_REG_MABBIPG 0x04 -#define CTL_REG_MAIPGL 0x06 -#define CTL_REG_MAIPGH 0x07 -#define CTL_REG_MACLCON1 0x08 -#define CTL_REG_MACLCON2 0x09 -#define CTL_REG_MAMXFLL 0x0A -#define CTL_REG_MAMXFLH 0x0B -#define CTL_REG_MAPHSUP 0x0D -#define CTL_REG_MICON 0x11 -#define CTL_REG_MICMD 0x12 -#define CTL_REG_MIREGADR 0x14 -#define CTL_REG_MIWRL 0x16 -#define CTL_REG_MIWRH 0x17 -#define CTL_REG_MIRDL 0x18 -#define CTL_REG_MIRDH 0x19 - -/* - * Control Registers in Bank 3 - */ - -#define CTL_REG_MAADR1 0x00 -#define CTL_REG_MAADR0 0x01 -#define CTL_REG_MAADR3 0x02 -#define CTL_REG_MAADR2 0x03 -#define CTL_REG_MAADR5 0x04 -#define CTL_REG_MAADR4 0x05 -#define CTL_REG_EBSTSD 0x06 -#define CTL_REG_EBSTCON 0x07 -#define CTL_REG_EBSTCSL 0x08 -#define CTL_REG_EBSTCSH 0x09 -#define CTL_REG_MISTAT 0x0A -#define CTL_REG_EREVID 0x12 -#define CTL_REG_ECOCON 0x15 -#define CTL_REG_EFLOCON 0x17 -#define CTL_REG_EPAUSL 0x18 -#define CTL_REG_EPAUSH 0x19 - - -/* - * PHY Register - */ - -#define PHY_REG_PHID1 0x02 -#define PHY_REG_PHID2 0x03 -/* taken from the Linux driver */ -#define PHY_REG_PHCON1 0x00 -#define PHY_REG_PHCON2 0x10 -#define PHY_REG_PHLCON 0x14 - -/* - * Receive Filter Register (ERXFCON) bits - */ - -#define ENC_RFR_UCEN 0x80 -#define ENC_RFR_ANDOR 0x40 -#define ENC_RFR_CRCEN 0x20 -#define ENC_RFR_PMEN 0x10 -#define ENC_RFR_MPEN 0x08 -#define ENC_RFR_HTEN 0x04 -#define ENC_RFR_MCEN 0x02 -#define ENC_RFR_BCEN 0x01 +#include <spi.h> +#include <malloc.h> +#include <netdev.h> +#include <miiphy.h> +#include "enc28j60.h" /* - * ECON1 Register Bits + * IMPORTANT: spi_claim_bus() and spi_release_bus() + * are called at begin and end of each of the following functions: + * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(), + * enc_init(), enc_recv(), enc_send(), enc_halt() + * ALL other functions assume that the bus has already been claimed! + * Since NetReceive() might call enc_send() in return, the bus must be + * released, NetReceive() called and claimed again. */ -#define ENC_ECON1_TXRST 0x80 -#define ENC_ECON1_RXRST 0x40 -#define ENC_ECON1_DMAST 0x20 -#define ENC_ECON1_CSUMEN 0x10 -#define ENC_ECON1_TXRTS 0x08 -#define ENC_ECON1_RXEN 0x04 -#define ENC_ECON1_BSEL1 0x02 -#define ENC_ECON1_BSEL0 0x01 - /* - * ECON2 Register Bits + * Controller memory layout. + * We only allow 1 frame for transmission and reserve the rest + * for reception to handle as many broadcast packets as possible. + * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5 + * 0x0000 - 0x19ff 6656 bytes receive buffer + * 0x1a00 - 0x1fff 1536 bytes transmit buffer = + * control(1)+frame(1518)+status(7)+reserve(10). */ -#define ENC_ECON2_AUTOINC 0x80 -#define ENC_ECON2_PKTDEC 0x40 -#define ENC_ECON2_PWRSV 0x20 -#define ENC_ECON2_VRPS 0x08 +#define ENC_RX_BUF_START 0x0000 +#define ENC_RX_BUF_END 0x19ff +#define ENC_TX_BUF_START 0x1a00 +#define ENC_TX_BUF_END 0x1fff +#define ENC_MAX_FRM_LEN 1518 +#define RX_RESET_COUNTER 1000 /* - * EIR Register Bits + * For non data transfer functions, like phy read/write, set hwaddr, init + * we do not need a full, time consuming init including link ready wait. + * This enum helps to bring the chip through the minimum necessary inits. */ -#define ENC_EIR_PKTIF 0x40 -#define ENC_EIR_DMAIF 0x20 -#define ENC_EIR_LINKIF 0x10 -#define ENC_EIR_TXIF 0x08 -#define ENC_EIR_WOLIF 0x04 -#define ENC_EIR_TXERIF 0x02 -#define ENC_EIR_RXERIF 0x01 +enum enc_initstate {none=0, setupdone, linkready}; +typedef struct enc_device { + struct eth_device *dev; /* back pointer */ + struct spi_slave *slave; + int rx_reset_counter; + u16 next_pointer; + u8 bank; /* current bank in enc28j60 */ + enum enc_initstate initstate; +} enc_dev_t; /* - * ESTAT Register Bits + * enc_bset: set bits in a common register + * enc_bclr: clear bits in a common register + * + * making the reg parameter u8 will give a compile time warning if the + * functions are called with a register not accessible in all Banks */ +static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data) +{ + u8 dout[2]; -#define ENC_ESTAT_INT 0x80 -#define ENC_ESTAT_LATECOL 0x10 -#define ENC_ESTAT_RXBUSY 0x04 -#define ENC_ESTAT_TXABRT 0x02 -#define ENC_ESTAT_CLKRDY 0x01 + dout[0] = CMD_BFS(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} -/* - * EIE Register Bits - */ +static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data) +{ + u8 dout[2]; -#define ENC_EIE_INTIE 0x80 -#define ENC_EIE_PKTIE 0x40 -#define ENC_EIE_DMAIE 0x20 -#define ENC_EIE_LINKIE 0x10 -#define ENC_EIE_TXIE 0x08 -#define ENC_EIE_WOLIE 0x04 -#define ENC_EIE_TXERIE 0x02 -#define ENC_EIE_RXERIE 0x01 + dout[0] = CMD_BFC(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} /* - * MACON1 Register Bits + * high byte of the register contains bank number: + * 0: no bank switch necessary + * 1: switch to bank 0 + * 2: switch to bank 1 + * 3: switch to bank 2 + * 4: switch to bank 3 */ -#define ENC_MACON1_LOOPBK 0x10 -#define ENC_MACON1_TXPAUS 0x08 -#define ENC_MACON1_RXPAUS 0x04 -#define ENC_MACON1_PASSALL 0x02 -#define ENC_MACON1_MARXEN 0x01 - +static void enc_set_bank(enc_dev_t *enc, const u16 reg) +{ + u8 newbank = reg >> 8; + + if (newbank == 0 || newbank == enc->bank) + return; + switch (newbank) { + case 1: + enc_bclr(enc, CTL_REG_ECON1, + ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); + break; + case 2: + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); + break; + case 3: + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); + break; + case 4: + enc_bset(enc, CTL_REG_ECON1, + ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); + break; + } + enc->bank = newbank; +} /* - * MACON2 Register Bits + * local functions to access SPI + * + * reg: register inside ENC28J60 + * data: 8/16 bits to write + * c: number of retries + * + * enc_r8: read 8 bits + * enc_r16: read 16 bits + * enc_w8: write 8 bits + * enc_w16: write 16 bits + * enc_w8_retry: write 8 bits, verify and retry + * enc_rbuf: read from ENC28J60 into buffer + * enc_wbuf: write from buffer into ENC28J60 */ -#define ENC_MACON2_MARST 0x80 -#define ENC_MACON2_RNDRST 0x40 -#define ENC_MACON2_MARXRST 0x08 -#define ENC_MACON2_RFUNRST 0x04 -#define ENC_MACON2_MATXRST 0x02 -#define ENC_MACON2_TFUNRST 0x01 /* - * MACON3 Register Bits + * MAC and MII registers need a 3 byte SPI transfer to read, + * all other registers need a 2 byte SPI transfer. */ -#define ENC_MACON3_PADCFG2 0x80 -#define ENC_MACON3_PADCFG1 0x40 -#define ENC_MACON3_PADCFG0 0x20 -#define ENC_MACON3_TXCRCEN 0x10 -#define ENC_MACON3_PHDRLEN 0x08 -#define ENC_MACON3_HFRMEN 0x04 -#define ENC_MACON3_FRMLNEN 0x02 -#define ENC_MACON3_FULDPX 0x01 +static int enc_reg2nbytes(const u16 reg) +{ + /* check if MAC or MII register */ + return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) || + (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) || + (reg == CTL_REG_MISTAT)) ? 3 : 2; +} /* - * MICMD Register Bits + * Read a byte register */ -#define ENC_MICMD_MIISCAN 0x02 -#define ENC_MICMD_MIIRD 0x01 +static u8 enc_r8(enc_dev_t *enc, const u16 reg) +{ + u8 dout[3]; + u8 din[3]; + int nbytes = enc_reg2nbytes(reg); + + enc_set_bank(enc, reg); + dout[0] = CMD_RCR(reg); + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + return din[nbytes-1]; +} /* - * MISTAT Register Bits + * Read a L/H register pair and return a word. + * Must be called with the L register's address. */ -#define ENC_MISTAT_NVALID 0x04 -#define ENC_MISTAT_SCAN 0x02 -#define ENC_MISTAT_BUSY 0x01 +static u16 enc_r16(enc_dev_t *enc, const u16 reg) +{ + u8 dout[3]; + u8 din[3]; + u16 result; + int nbytes = enc_reg2nbytes(reg); + + enc_set_bank(enc, reg); + dout[0] = CMD_RCR(reg); + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + result = din[nbytes-1]; + dout[0]++; /* next register */ + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + result |= din[nbytes-1] << 8; + return result; +} /* - * PHID1 and PHID2 values + * Write a byte register */ -#define ENC_PHID1_VALUE 0x0083 -#define ENC_PHID2_VALUE 0x1400 -#define ENC_PHID2_MASK 0xFC00 - - -#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ -#define ENC_RESET 0x00020000 /* pin P1.17 */ +static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data) +{ + u8 dout[2]; -#define FAILSAFE_VALUE 5000 + enc_set_bank(enc, reg); + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} /* - * Controller memory layout: - * - * 0x0000 - 0x17ff 6k bytes receive buffer - * 0x1800 - 0x1fff 2k bytes transmit buffer - */ -/* Use the lower memory for receiver buffer. See errata pt. 5 */ -#define ENC_RX_BUF_START 0x0000 -#define ENC_TX_BUF_START 0x1800 -/* taken from the Linux driver */ -#define ENC_RX_BUF_END 0x17ff -#define ENC_TX_BUF_END 0x1fff - -/* maximum frame length */ -#define ENC_MAX_FRM_LEN 1518 - -#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) -#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) -#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); - - -static unsigned char encReadReg (unsigned char regNo); -static void encWriteReg (unsigned char regNo, unsigned char data); -static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); -static void encReadBuff (unsigned short length, unsigned char *pBuff); -static void encWriteBuff (unsigned short length, unsigned char *pBuff); -static void encBitSet (unsigned char regNo, unsigned char data); -static void encBitClr (unsigned char regNo, unsigned char data); -static void encReset (void); -static void encInit (unsigned char *pEthAddr); -static unsigned short phyRead (unsigned char addr); -static void phyWrite(unsigned char, unsigned short); -static void encPoll (void); -static void encRx (void); - -#define m_nic_read(reg) encReadReg(reg) -#define m_nic_write(reg, data) encWriteReg(reg, data) -#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) -#define m_nic_read_data(len, buf) encReadBuff((len), (buf)) -#define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) - -/* bit field set */ -#define m_nic_bfs(reg, data) encBitSet(reg, data) - -/* bit field clear */ -#define m_nic_bfc(reg, data) encBitClr(reg, data) - -static unsigned char bank = 0; /* current bank in enc28j60 */ -static unsigned char next_pointer_lsb; -static unsigned char next_pointer_msb; - -static unsigned char buffer[ENC_MAX_FRM_LEN]; -static int rxResetCounter = 0; - -#define RX_RESET_COUNTER 1000; - -/*----------------------------------------------------------------------------- - * Always returns 0 + * Write a L/H register pair. + * Must be called with the L register's address. */ -int eth_init (bd_t * bis) +static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data) { - unsigned char estatVal; - uchar enetaddr[6]; - - /* configure GPIO */ - (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; - (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; - - /* CS and RESET active low */ - PUT32 (IO1SET, ENC_SPI_SLAVE_CS); - PUT32 (IO1SET, ENC_RESET); - - spi_init (); - - /* taken from the Linux driver - dangerous stuff here! */ - /* Wait for CLKRDY to become set (i.e., check that we can communicate with - the ENC) */ - do - { - estatVal = m_nic_read(CTL_REG_ESTAT); - } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY)); - - /* initialize controller */ - encReset (); - eth_getenv_enetaddr("ethaddr", enetaddr); - encInit (enetaddr); - - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ - - return 0; + u8 dout[2]; + + enc_set_bank(enc, reg); + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); + dout[0]++; /* next register */ + dout[1] = data >> 8; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); } -int eth_send (volatile void *packet, int length) +/* + * Write a byte register, verify and retry + */ +static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c) { - /* check frame length, etc. */ - /* TODO: */ - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - - /* set EWRPT */ - m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); - m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); - - /* set ETXND */ - m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); - m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); - - /* set ETXST */ - m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); - m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); - - /* write packet */ - m_nic_write_data (length, (unsigned char *) packet); + u8 dout[2]; + u8 readback; + int i; - /* taken from the Linux driver */ - /* Verify that the internal transmit logic has not been altered by excessive - collisions. See Errata B4 12 and 14. - */ - if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) { - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST); - m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST); + enc_set_bank(enc, reg); + for (i = 0; i < c; i++) { + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); + readback = enc_r8(enc, reg); + if (readback == data) + break; + /* wait 1ms */ + udelay(1000); + } + if (i == c) { + printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg); } - m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); - - /* set ECON1.TXRTS */ - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); - - return 0; } - -/***************************************************************************** - * This function resets the receiver only. This function may be called from - * interrupt-context. +/* + * Read ENC RAM into buffer */ -static void encReceiverReset (void) +static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf) { - unsigned char econ1; - - econ1 = m_nic_read (CTL_REG_ECON1); - if ((econ1 & ENC_ECON1_RXRST) == 0) { - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); - rxResetCounter = RX_RESET_COUNTER; - } + u8 dout[1]; + + dout[0] = CMD_RBM; + spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN); + spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END); +#ifdef DEBUG + puts("Rx:\n"); + print_buffer(0, buf, 1, length, 0); +#endif } -/***************************************************************************** - * receiver reset timer +/* + * Write buffer into ENC RAM */ -static void encReceiverResetCallback (void) +static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control) { - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ + u8 dout[2]; + dout[0] = CMD_WBM; + dout[1] = control; + spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN); + spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END); +#ifdef DEBUG + puts("Tx:\n"); + print_buffer(0, buf, 1, length, 0); +#endif } -/*----------------------------------------------------------------------------- - * Check for received packets. Call NetReceive for each packet. The return - * value is ignored by the caller. +/* + * Try to claim the SPI bus. + * Print error message on failure. */ -int eth_rx (void) +static int enc_claim_bus(enc_dev_t *enc) { - if (rxResetCounter > 0 && --rxResetCounter == 0) { - encReceiverResetCallback (); - } - - encPoll (); - - return 0; + int rc = spi_claim_bus(enc->slave); + if (rc) + printf("%s: failed to claim SPI bus\n", enc->dev->name); + return rc; } -void eth_halt (void) +/* + * Release previously claimed SPI bus. + * This function is mainly for symmetry to enc_claim_bus(). + * Let the toolchain decide to inline it... + */ +static void enc_release_bus(enc_dev_t *enc) { - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ + spi_release_bus(enc->slave); } -/*****************************************************************************/ - -static void encPoll (void) +/* + * Read PHY register + */ +static u16 phy_read(enc_dev_t *enc, const u8 addr) { - unsigned char eir_reg; - volatile unsigned char estat_reg; - unsigned char pkt_cnt; + uint64_t etime; + u8 status; -#ifdef CONFIG_USE_IRQ - /* clear global interrupt enable bit in enc28j60 */ - m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); -#endif - estat_reg = m_nic_read (CTL_REG_ESTAT); - - eir_reg = m_nic_read (CTL_REG_EIR); - - if (eir_reg & ENC_EIR_TXIF) { - /* clear TXIF bit in EIR */ - m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); + enc_w8(enc, CTL_REG_MIREGADR, addr); + enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD); + /* 1 second timeout - only happens on hardware problem */ + etime = get_ticks() + get_tbclk(); + /* poll MISTAT.BUSY bit until operation is complete */ + do + { + status = enc_r8(enc, CTL_REG_MISTAT); + } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); + if (status & ENC_MISTAT_BUSY) { + printf("%s: timeout reading phy\n", enc->dev->name); + return 0; } + enc_w8(enc, CTL_REG_MICMD, 0); + return enc_r16(enc, CTL_REG_MIRDL); +} - /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ +/* + * Write PHY register + */ +static void phy_write(enc_dev_t *enc, const u8 addr, const u16 data) +{ + uint64_t etime; + u8 status; - /* move to bank 1 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); + enc_w8(enc, CTL_REG_MIREGADR, addr); + enc_w16(enc, CTL_REG_MIWRL, data); + /* 1 second timeout - only happens on hardware problem */ + etime = get_ticks() + get_tbclk(); + /* poll MISTAT.BUSY bit until operation is complete */ + do + { + status = enc_r8(enc, CTL_REG_MISTAT); + } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); + if (status & ENC_MISTAT_BUSY) { + printf("%s: timeout writing phy\n", enc->dev->name); + return; + } +} - /* read pktcnt */ - pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); +/* + * Verify link status, wait if necessary + * + * Note: with a 10 MBit/s only PHY there is no autonegotiation possible, + * half/full duplex is a pure setup matter. For the time being, this driver + * will setup in half duplex mode only. + */ +static int enc_phy_link_wait(enc_dev_t *enc) +{ + u16 status; + int duplex; + uint64_t etime; + +#ifdef CONFIG_ENC_SILENTLINK + /* check if we have a link, then just return */ + status = phy_read(enc, PHY_REG_PHSTAT1); + if (status & ENC_PHSTAT1_LLSTAT) + return 0; +#endif - if (pkt_cnt > 0) { - if ((eir_reg & ENC_EIR_PKTIF) == 0) { - /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ + /* wait for link with 1 second timeout */ + etime = get_ticks() + get_tbclk(); + while (get_ticks() <= etime) { + status = phy_read(enc, PHY_REG_PHSTAT1); + if (status & ENC_PHSTAT1_LLSTAT) { + /* now we have a link */ + status = phy_read(enc, PHY_REG_PHSTAT2); + duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0; + printf("%s: link up, 10Mbps %s-duplex\n", + enc->dev->name, duplex ? "full" : "half"); + return 0; } - encRx (); - /* clear PKTIF bit in EIR, this should not need to be done but it - seems like we get problems if we do not */ - m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); + udelay(1000); } - if (eir_reg & ENC_EIR_RXERIF) { - printf ("encPoll: rx error\n"); - m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); - } - if (eir_reg & ENC_EIR_TXERIF) { - printf ("encPoll: tx error\n"); - m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); - } - -#ifdef CONFIG_USE_IRQ - /* set global interrupt enable bit in enc28j60 */ - m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); -#endif + /* timeout occured */ + printf("%s: link down\n", enc->dev->name); + return 1; } -static void encRx (void) +/* + * This function resets the receiver only. + */ +static void enc_reset_rx(enc_dev_t *enc) { - unsigned short pkt_len; - unsigned short copy_len; - unsigned short status; - unsigned char eir_reg; - unsigned char pkt_cnt = 0; - unsigned short rxbuf_rdpt; + u8 econ1; - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + econ1 = enc_r8(enc, CTL_REG_ECON1); + if ((econ1 & ENC_ECON1_RXRST) == 0) { + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); + enc->rx_reset_counter = RX_RESET_COUNTER; + } +} - m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); - m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); +/* + * Reset receiver and reenable it. + */ +static void enc_reset_rx_call(enc_dev_t *enc) +{ + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); +} +/* + * Copy a packet from the receive ring and forward it to + * the protocol stack. + */ +static void enc_receive(enc_dev_t *enc) +{ + u8 *packet = (u8 *)NetRxPackets[0]; + u16 pkt_len; + u16 copy_len; + u16 status; + u8 eir_reg; + u8 pkt_cnt = 0; + u16 rxbuf_rdpt; + u8 hbuf[6]; + + enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); do { - m_nic_read_data (6, buffer); - next_pointer_lsb = buffer[0]; - next_pointer_msb = buffer[1]; - pkt_len = buffer[2]; - pkt_len |= (unsigned short) buffer[3] << 8; - status = buffer[4]; - status |= (unsigned short) buffer[5] << 8; - + enc_rbuf(enc, 6, hbuf); + enc->next_pointer = hbuf[0] | (hbuf[1] << 8); + pkt_len = hbuf[2] | (hbuf[3] << 8); + status = hbuf[4] | (hbuf[5] << 8); + debug("next_pointer=$%04x pkt_len=%u status=$%04x\n", + enc->next_pointer, pkt_len, status); if (pkt_len <= ENC_MAX_FRM_LEN) copy_len = pkt_len; else copy_len = 0; - if ((status & (1L << 7)) == 0) /* check Received Ok bit */ copy_len = 0; - - /* taken from the Linux driver */ /* check if next pointer is resonable */ - if ((((unsigned int)next_pointer_msb << 8) | - (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START) + if (enc->next_pointer >= ENC_TX_BUF_START) copy_len = 0; - if (copy_len > 0) { - m_nic_read_data (copy_len, buffer); + enc_rbuf(enc, copy_len, packet); } - /* advance read pointer to next pointer */ - m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); - m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); - + enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); /* decrease packet counter */ - m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); - - /* taken from the Linux driver */ - /* Only odd values should be written to ERXRDPTL, + enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC); + /* + * Only odd values should be written to ERXRDPTL, * see errata B4 pt.13 */ - rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; - if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | - m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > - (m_nic_read(CTL_REG_ERXNDH) << 8 | - m_nic_read(CTL_REG_ERXNDL)))) { - m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL)); - m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH)); + rxbuf_rdpt = enc->next_pointer - 1; + if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) || + (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) { + enc_w16(enc, CTL_REG_ERXRDPTL, + enc_r16(enc, CTL_REG_ERXNDL)); } else { - m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF); - m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8); + enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt); } - - /* move to bank 1 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); - /* read pktcnt */ - pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, - (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - + pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); if (copy_len == 0) { - eir_reg = m_nic_read (CTL_REG_EIR); - encReceiverReset (); - printf ("eth_rx: copy_len=0\n"); + eir_reg = enc_r8(enc, CTL_REG_EIR); + enc_reset_rx(enc); + printf("%s: receive copy_len=0\n", enc->dev->name); continue; } - - NetReceive ((unsigned char *) buffer, pkt_len); - - eir_reg = m_nic_read (CTL_REG_EIR); - } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ -} - -static void encWriteReg (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x40 | regNo); /* write in regNo */ - spi_write (data); - - enc_disable (); - enc_enable (); - - spi_write (0x1f); /* write reg 0x1f */ - - enc_disable (); - spi_unlock (); + /* + * Because NetReceive() might call enc_send(), we need to + * release the SPI bus, call NetReceive(), reclaim the bus + */ + enc_release_bus(enc); + NetReceive(packet, pkt_len); + if (enc_claim_bus(enc)) + return; + eir_reg = enc_r8(enc, CTL_REG_EIR); + } while (pkt_cnt); + /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ } -static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) +/* + * Poll for completely received packets. + */ +static void enc_poll(enc_dev_t *enc) { - unsigned char readback; - int i; - - spi_lock (); + u8 eir_reg; + u8 estat_reg; + u8 pkt_cnt; - for (i = 0; i < c; i++) { - enc_cfg_spi (); - enc_enable (); - - spi_write (0x40 | regNo); /* write in regNo */ - spi_write (data); - - enc_disable (); - enc_enable (); - - spi_write (0x1f); /* write reg 0x1f */ - - enc_disable (); - - spi_unlock (); /* we must unlock spi first */ - - readback = encReadReg (regNo); - - spi_lock (); - - if (readback == data) - break; +#ifdef CONFIG_USE_IRQ + /* clear global interrupt enable bit in enc28j60 */ + enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE); +#endif + estat_reg = enc_r8(enc, CTL_REG_ESTAT); + eir_reg = enc_r8(enc, CTL_REG_EIR); + if (eir_reg & ENC_EIR_TXIF) { + /* clear TXIF bit in EIR */ + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF); } - spi_unlock (); - - if (i == c) { - printf ("enc28j60: write reg %d failed\n", regNo); + /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ + pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); + if (pkt_cnt > 0) { + if ((eir_reg & ENC_EIR_PKTIF) == 0) { + debug("enc_poll: pkt cnt > 0, but pktif not set\n"); + } + enc_receive(enc); + /* + * clear PKTIF bit in EIR, this should not need to be done + * but it seems like we get problems if we do not + */ + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF); } -} - -static unsigned char encReadReg (unsigned char regNo) -{ - unsigned char rxByte; - - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x1f); /* read reg 0x1f */ - - bank = spi_read () & 0x3; - - enc_disable (); - enc_enable (); - - spi_write (regNo); - rxByte = spi_read (); - - /* check if MAC or MII register */ - if (((bank == 2) && (regNo <= 0x1a)) || - ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { - /* ignore first byte and read another byte */ - rxByte = spi_read (); + if (eir_reg & ENC_EIR_RXERIF) { + printf("%s: rx error\n", enc->dev->name); + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF); } - - enc_disable (); - spi_unlock (); - - return rxByte; -} - -static void encReadBuff (unsigned short length, unsigned char *pBuff) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x20 | 0x1a); /* read buffer memory */ - - while (length--) { - if (pBuff != NULL) - *pBuff++ = spi_read (); - else - spi_write (0); + if (eir_reg & ENC_EIR_TXERIF) { + printf("%s: tx error\n", enc->dev->name); + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF); } - - enc_disable (); - spi_unlock (); -} - -static void encWriteBuff (unsigned short length, unsigned char *pBuff) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x60 | 0x1a); /* write buffer memory */ - - spi_write (0x00); /* control byte */ - - while (length--) - spi_write (*pBuff++); - - enc_disable (); - spi_unlock (); -} - -static void encBitSet (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x80 | regNo); /* bit field set */ - spi_write (data); - - enc_disable (); - spi_unlock (); -} - -static void encBitClr (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0xA0 | regNo); /* bit field clear */ - spi_write (data); - - enc_disable (); - spi_unlock (); +#ifdef CONFIG_USE_IRQ + /* set global interrupt enable bit in enc28j60 */ + enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); +#endif } -static void encReset (void) +/* + * Completely Reset the ENC + */ +static void enc_reset(enc_dev_t *enc) { - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0xff); /* soft reset */ - - enc_disable (); - spi_unlock (); + u8 dout[1]; + dout[0] = CMD_SRC; + spi_xfer(enc->slave, 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); /* sleep 1 ms. See errata pt. 2 */ - udelay (1000); + udelay(1000); } -static void encInit (unsigned char *pEthAddr) -{ - unsigned short phid1 = 0; - unsigned short phid2 = 0; - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - +/* + * Initialisation data for most of the ENC registers + */ +static const u16 enc_initdata[] = { /* * Setup the buffer space. The reset values are valid for the * other pointers. + * + * We shall not write to ERXST, see errata pt. 5. Instead we + * have to make sure that ENC_RX_BUS_START is 0. */ - /* We shall not write to ERXST, see errata pt. 5. Instead we - have to make sure that ENC_RX_BUS_START is 0. */ - m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); - m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); - - /* taken from the Linux driver */ - m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1); - m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1); - - m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); - m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); - - next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); - next_pointer_msb = (ENC_RX_BUF_START >> 8); - - /* verify identification */ - phid1 = phyRead (PHY_REG_PHID1); - phid2 = phyRead (PHY_REG_PHID2); - - if (phid1 != ENC_PHID1_VALUE - || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { - printf ("ERROR: failed to identify controller\n"); - printf ("phid1 = %x, phid2 = %x\n", - phid1, (phid2 & ENC_PHID2_MASK)); - printf ("should be phid1 = %x, phid2 = %x\n", - ENC_PHID1_VALUE, ENC_PHID2_VALUE); - } - + CTL_REG_ERXSTL, ENC_RX_BUF_START, + CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8, + CTL_REG_ERXNDL, ENC_RX_BUF_END, + CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8, + CTL_REG_ERDPTL, ENC_RX_BUF_START, + CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8, /* - * --- MAC Initialization --- + * Set the filter to receive only good-CRC, unicast and broadcast + * frames. + * Note: some DHCP servers return their answers as broadcasts! + * So its unwise to remove broadcast from this. This driver + * might incur receiver overruns with packet loss on a broadcast + * flooded network. */ - - /* Pull MAC out of Reset */ - - /* switch to bank 2 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN, /* enable MAC to receive frames */ - /* added some bits from the Linux driver */ - m_nic_write_retry (CTL_REG_MACON1 - ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS) - ,10); + CTL_REG_MACON1, + ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS, /* configure pad, tx-crc and duplex */ - /* added a bit from the Linux driver */ - m_nic_write_retry (CTL_REG_MACON3 - ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN) - ,10); + CTL_REG_MACON3, + ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | + ENC_MACON3_FRMLNEN, - /* added 4 new lines from the Linux driver */ /* Allow infinite deferals if the medium is continously busy */ - m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10); + CTL_REG_MACON4, ENC_MACON4_DEFER, /* Late collisions occur beyond 63 bytes */ - m_nic_write_retry(CTL_REG_MACLCON2, 63, 10); + CTL_REG_MACLCON2, 63, - /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ - m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10); + /* + * Set (low byte) Non-Back-to_Back Inter-Packet Gap. + * Recommended 0x12 + */ + CTL_REG_MAIPGL, 0x12, /* - * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended - * 0x0c for half-duplex. Nothing for full-duplex - */ - m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10); + * Set (high byte) Non-Back-to_Back Inter-Packet Gap. + * Recommended 0x0c for half-duplex. Nothing for full-duplex + */ + CTL_REG_MAIPGH, 0x0C, /* set maximum frame length */ - m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); - m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); + CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN, + CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8, /* - * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex + * Set MAC back-to-back inter-packet gap. + * Recommended 0x12 for half duplex * and 0x15 for full duplex. */ - m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); + CTL_REG_MABBIPG, 0x12, - /* set MAC address */ + /* end of table */ + 0xffff +}; - /* switch to bank 3 */ - m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); +/* + * Wait for the XTAL oscillator to become ready + */ +static int enc_clock_wait(enc_dev_t *enc) +{ + uint64_t etime; - m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); - m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); - m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); - m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); - m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); - m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); + /* one second timeout */ + etime = get_ticks() + get_tbclk(); /* - * PHY Initialization taken from the Linux driver + * Wait for CLKRDY to become set (i.e., check that we can + * communicate with the ENC) */ + do + { + if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) + return 0; + } while (get_ticks() <= etime); + + printf("%s: timeout waiting for CLKRDY\n", enc->dev->name); + return -1; +} + +/* + * Write the MAC address into the ENC + */ +static int enc_write_macaddr(enc_dev_t *enc) +{ + unsigned char *p = enc->dev->enetaddr; + + enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5); + return 0; +} + +/* + * Setup most of the ENC registers + */ +static int enc_setup(enc_dev_t *enc) +{ + u16 phid1 = 0; + u16 phid2 = 0; + const u16 *tp; + + /* reset enc struct values */ + enc->next_pointer = ENC_RX_BUF_START; + enc->rx_reset_counter = RX_RESET_COUNTER; + enc->bank = 0xff; /* invalidate current bank in enc28j60 */ + + /* verify PHY identification */ + phid1 = phy_read(enc, PHY_REG_PHID1); + phid2 = phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; + if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { + printf("%s: failed to identify PHY. Found %04x:%04x\n", + enc->dev->name, phid1, phid2); + return -1; + } - /* Prevent automatic loopback of data beeing transmitted by setting - ENC_PHCON2_HDLDIS */ - phyWrite(PHY_REG_PHCON2, (1<<8)); + /* now program registers */ + for (tp = enc_initdata; *tp != 0xffff; tp += 2) + enc_w8_retry(enc, tp[0], tp[1], 10); + + /* + * Prevent automatic loopback of data beeing transmitted by setting + * ENC_PHCON2_HDLDIS + */ + phy_write(enc, PHY_REG_PHCON2, (1<<8)); - /* LEDs configuration + /* + * LEDs configuration * LEDA: LACFG = 0100 -> display link status * LEDB: LBCFG = 0111 -> display TX & RX activity * STRCH = 1 -> LED pulses */ - phyWrite(PHY_REG_PHLCON, 0x0472); + phy_write(enc, PHY_REG_PHLCON, 0x0472); /* Reset PDPXMD-bit => half duplex */ - phyWrite(PHY_REG_PHCON1, 0); - - /* - * Receive settings - */ + phy_write(enc, PHY_REG_PHCON1, 0); #ifdef CONFIG_USE_IRQ /* enable interrupts */ - m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); #endif + + return 0; } -/***************************************************************************** - * - * Description: - * Read PHY registers. - * - * NOTE! This function will change to Bank 2. - * - * Params: - * [in] addr address of the register to read - * - * Returns: - * The value in the register +/* + * Check if ENC has been initialized. + * If not, try to initialize it. + * Remember initialized state in struct. */ -static unsigned short phyRead (unsigned char addr) +static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) { - unsigned short ret = 0; - - /* move to bank 2 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + if (enc->initstate >= requiredstate) + return 0; + + if (enc->initstate < setupdone) { + /* Initialize the ENC only */ + enc_reset(enc); + /* if any of functions fails, skip the rest and return an error */ + if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) { + return -1; + } + enc->initstate = setupdone; + } + /* if that's all we need, return here */ + if (enc->initstate >= requiredstate) + return 0; - /* write address to MIREGADR */ - m_nic_write (CTL_REG_MIREGADR, addr); + /* now wait for link ready condition */ + if (enc_phy_link_wait(enc)) { + return -1; + } + enc->initstate = linkready; + return 0; +} - /* set MICMD.MIIRD */ - m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); +#if defined(CONFIG_CMD_MII) +/* + * Read a PHY register. + * + * This function is registered with miiphy_register(). + */ +int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + enc_dev_t *enc; + + if (!dev || phy_adr != 0) + return -1; + + enc = dev->priv; + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; + } + *value = phy_read(enc, reg); + enc_release_bus(enc); + return 0; +} - /* taken from the Linux driver */ - /* move to bank 3 */ - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); +/* + * Write a PHY register. + * + * This function is registered with miiphy_register(). + */ +int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + enc_dev_t *enc; + + if (!dev || phy_adr != 0) + return -1; + + enc = dev->priv; + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; + } + phy_write(enc, reg, value); + enc_release_bus(enc); + return 0; +} +#endif - /* poll MISTAT.BUSY bit until operation is complete */ - while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { - static int cnt = 0; +/* + * Write hardware (MAC) address. + * + * This function entered into eth_device structure. + */ +static int enc_write_hwaddr(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; - if (cnt++ >= 1000) { - /* GJ - this seems extremely dangerous! */ - /* printf("#"); */ - cnt = 0; - } + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; } + enc_release_bus(enc); + return 0; +} - /* taken from the Linux driver */ - /* move to bank 2 */ - m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); +/* + * Initialize ENC28J60 for use. + * + * This function entered into eth_device structure. + */ +static int enc_init(struct eth_device *dev, bd_t *bis) +{ + enc_dev_t *enc = dev->priv; - /* clear MICMD.MIIRD */ - m_nic_write (CTL_REG_MICMD, 0); + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* enable receive */ + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); + enc_release_bus(enc); + return 0; +} - ret = (m_nic_read (CTL_REG_MIRDH) << 8); - ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); +/* + * Check for received packets. + * + * This function entered into eth_device structure. + */ +static int enc_recv(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; - return ret; + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* Check for dead receiver */ + if (enc->rx_reset_counter > 0) + enc->rx_reset_counter--; + else + enc_reset_rx_call(enc); + enc_poll(enc); + enc_release_bus(enc); + return 0; } -/***************************************************************************** - * - * Taken from the Linux driver. - * Description: - * Write PHY registers. - * - * NOTE! This function will change to Bank 3. +/* + * Send a packet. * - * Params: - * [in] addr address of the register to write to - * [in] data to be written + * This function entered into eth_device structure. * - * Returns: - * None + * Should we wait here until we have a Link? Or shall we leave that to + * protocol retries? */ -static void phyWrite(unsigned char addr, unsigned short data) +static int enc_send( + struct eth_device *dev, + volatile void *packet, + int length) { - /* move to bank 2 */ - m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* setup transmit pointers */ + enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START); + enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START); + enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START); + /* write packet to ENC */ + enc_wbuf(enc, length, (u8 *) packet, 0x00); + /* + * Check that the internal transmit logic has not been altered + * by excessive collisions. Reset transmitter if so. + * See Errata B4 12 and 14. + */ + if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) { + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); + } + enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); + /* start transmitting */ + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS); + enc_release_bus(enc); + return 0; +} - /* write address to MIREGADR */ - m_nic_write(CTL_REG_MIREGADR, addr); +/* + * Finish use of ENC. + * + * This function entered into eth_device structure. + */ +static void enc_halt(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; - m_nic_write(CTL_REG_MIWRL, data & 0xff); - m_nic_write(CTL_REG_MIWRH, data >> 8); + if (enc_claim_bus(enc)) + return; + /* Just disable receiver */ + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); + enc_release_bus(enc); +} - /* move to bank 3 */ - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); +/* + * This is the only exported function. + * + * It may be called several times with different bus:cs combinations. + */ +int enc28j60_initialize(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct eth_device *dev; + enc_dev_t *enc; - /* poll MISTAT.BUSY bit until operation is complete */ - while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { - static int cnt = 0; + /* try to allocate, check and clear eth_device object */ + dev = malloc(sizeof(*dev)); + if (!dev) { + return -1; + } + memset(dev, 0, sizeof(*dev)); - if(cnt++ >= 1000) { - cnt = 0; - } + /* try to allocate, check and clear enc_dev_t object */ + enc = malloc(sizeof(*enc)); + if (!enc) { + free(dev); + return -1; + } + memset(enc, 0, sizeof(*enc)); + + /* try to setup the SPI slave */ + enc->slave = spi_setup_slave(bus, cs, max_hz, mode); + if (!enc->slave) { + printf("enc28j60: invalid SPI device %i:%i\n", bus, cs); + free(enc); + free(dev); + return -1; } + + enc->dev = dev; + /* now fill the eth_device object */ + dev->priv = enc; + dev->init = enc_init; + dev->halt = enc_halt; + dev->send = enc_send; + dev->recv = enc_recv; + dev->write_hwaddr = enc_write_hwaddr; + sprintf(dev->name, "enc%i.%i", bus, cs); + eth_register(dev); +#if defined(CONFIG_CMD_MII) + miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); +#endif + return 0; } diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h new file mode 100644 index 0000000000..888c59903d --- /dev/null +++ b/drivers/net/enc28j60.h @@ -0,0 +1,251 @@ +/* + * (X) extracted from enc28j60.c + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _enc28j60_h +#define _enc28j60_h + +/* + * SPI Commands + * + * Bits 7-5: Command + * Bits 4-0: Register + */ +#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */ +#define CMD_RBM 0x3a /* Read Buffer Memory */ +#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */ +#define CMD_WBM 0x7a /* Write Buffer Memory */ +#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */ +#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */ +#define CMD_SRC 0xff /* System Reset Command */ + +/* NEW: encode (bank number+1) in upper byte */ + +/* Common Control Registers accessible in all Banks */ +#define CTL_REG_EIE 0x01B +#define CTL_REG_EIR 0x01C +#define CTL_REG_ESTAT 0x01D +#define CTL_REG_ECON2 0x01E +#define CTL_REG_ECON1 0x01F + +/* Control Registers accessible in Bank 0 */ +#define CTL_REG_ERDPTL 0x100 +#define CTL_REG_ERDPTH 0x101 +#define CTL_REG_EWRPTL 0x102 +#define CTL_REG_EWRPTH 0x103 +#define CTL_REG_ETXSTL 0x104 +#define CTL_REG_ETXSTH 0x105 +#define CTL_REG_ETXNDL 0x106 +#define CTL_REG_ETXNDH 0x107 +#define CTL_REG_ERXSTL 0x108 +#define CTL_REG_ERXSTH 0x109 +#define CTL_REG_ERXNDL 0x10A +#define CTL_REG_ERXNDH 0x10B +#define CTL_REG_ERXRDPTL 0x10C +#define CTL_REG_ERXRDPTH 0x10D +#define CTL_REG_ERXWRPTL 0x10E +#define CTL_REG_ERXWRPTH 0x10F +#define CTL_REG_EDMASTL 0x110 +#define CTL_REG_EDMASTH 0x111 +#define CTL_REG_EDMANDL 0x112 +#define CTL_REG_EDMANDH 0x113 +#define CTL_REG_EDMADSTL 0x114 +#define CTL_REG_EDMADSTH 0x115 +#define CTL_REG_EDMACSL 0x116 +#define CTL_REG_EDMACSH 0x117 + +/* Control Registers accessible in Bank 1 */ +#define CTL_REG_EHT0 0x200 +#define CTL_REG_EHT1 0x201 +#define CTL_REG_EHT2 0x202 +#define CTL_REG_EHT3 0x203 +#define CTL_REG_EHT4 0x204 +#define CTL_REG_EHT5 0x205 +#define CTL_REG_EHT6 0x206 +#define CTL_REG_EHT7 0x207 +#define CTL_REG_EPMM0 0x208 +#define CTL_REG_EPMM1 0x209 +#define CTL_REG_EPMM2 0x20A +#define CTL_REG_EPMM3 0x20B +#define CTL_REG_EPMM4 0x20C +#define CTL_REG_EPMM5 0x20D +#define CTL_REG_EPMM6 0x20E +#define CTL_REG_EPMM7 0x20F +#define CTL_REG_EPMCSL 0x210 +#define CTL_REG_EPMCSH 0x211 +#define CTL_REG_EPMOL 0x214 +#define CTL_REG_EPMOH 0x215 +#define CTL_REG_EWOLIE 0x216 +#define CTL_REG_EWOLIR 0x217 +#define CTL_REG_ERXFCON 0x218 +#define CTL_REG_EPKTCNT 0x219 + +/* Control Registers accessible in Bank 2 */ +#define CTL_REG_MACON1 0x300 +#define CTL_REG_MACON2 0x301 +#define CTL_REG_MACON3 0x302 +#define CTL_REG_MACON4 0x303 +#define CTL_REG_MABBIPG 0x304 +#define CTL_REG_MAIPGL 0x306 +#define CTL_REG_MAIPGH 0x307 +#define CTL_REG_MACLCON1 0x308 +#define CTL_REG_MACLCON2 0x309 +#define CTL_REG_MAMXFLL 0x30A +#define CTL_REG_MAMXFLH 0x30B +#define CTL_REG_MAPHSUP 0x30D +#define CTL_REG_MICON 0x311 +#define CTL_REG_MICMD 0x312 +#define CTL_REG_MIREGADR 0x314 +#define CTL_REG_MIWRL 0x316 +#define CTL_REG_MIWRH 0x317 +#define CTL_REG_MIRDL 0x318 +#define CTL_REG_MIRDH 0x319 + +/* Control Registers accessible in Bank 3 */ +#define CTL_REG_MAADR1 0x400 +#define CTL_REG_MAADR0 0x401 +#define CTL_REG_MAADR3 0x402 +#define CTL_REG_MAADR2 0x403 +#define CTL_REG_MAADR5 0x404 +#define CTL_REG_MAADR4 0x405 +#define CTL_REG_EBSTSD 0x406 +#define CTL_REG_EBSTCON 0x407 +#define CTL_REG_EBSTCSL 0x408 +#define CTL_REG_EBSTCSH 0x409 +#define CTL_REG_MISTAT 0x40A +#define CTL_REG_EREVID 0x412 +#define CTL_REG_ECOCON 0x415 +#define CTL_REG_EFLOCON 0x417 +#define CTL_REG_EPAUSL 0x418 +#define CTL_REG_EPAUSH 0x419 + +/* PHY Register */ +#define PHY_REG_PHCON1 0x00 +#define PHY_REG_PHSTAT1 0x01 +#define PHY_REG_PHID1 0x02 +#define PHY_REG_PHID2 0x03 +#define PHY_REG_PHCON2 0x10 +#define PHY_REG_PHSTAT2 0x11 +#define PHY_REG_PHLCON 0x14 + +/* Receive Filter Register (ERXFCON) bits */ +#define ENC_RFR_UCEN 0x80 +#define ENC_RFR_ANDOR 0x40 +#define ENC_RFR_CRCEN 0x20 +#define ENC_RFR_PMEN 0x10 +#define ENC_RFR_MPEN 0x08 +#define ENC_RFR_HTEN 0x04 +#define ENC_RFR_MCEN 0x02 +#define ENC_RFR_BCEN 0x01 + +/* ECON1 Register Bits */ +#define ENC_ECON1_TXRST 0x80 +#define ENC_ECON1_RXRST 0x40 +#define ENC_ECON1_DMAST 0x20 +#define ENC_ECON1_CSUMEN 0x10 +#define ENC_ECON1_TXRTS 0x08 +#define ENC_ECON1_RXEN 0x04 +#define ENC_ECON1_BSEL1 0x02 +#define ENC_ECON1_BSEL0 0x01 + +/* ECON2 Register Bits */ +#define ENC_ECON2_AUTOINC 0x80 +#define ENC_ECON2_PKTDEC 0x40 +#define ENC_ECON2_PWRSV 0x20 +#define ENC_ECON2_VRPS 0x08 + +/* EIR Register Bits */ +#define ENC_EIR_PKTIF 0x40 +#define ENC_EIR_DMAIF 0x20 +#define ENC_EIR_LINKIF 0x10 +#define ENC_EIR_TXIF 0x08 +#define ENC_EIR_WOLIF 0x04 +#define ENC_EIR_TXERIF 0x02 +#define ENC_EIR_RXERIF 0x01 + +/* ESTAT Register Bits */ +#define ENC_ESTAT_INT 0x80 +#define ENC_ESTAT_LATECOL 0x10 +#define ENC_ESTAT_RXBUSY 0x04 +#define ENC_ESTAT_TXABRT 0x02 +#define ENC_ESTAT_CLKRDY 0x01 + +/* EIE Register Bits */ +#define ENC_EIE_INTIE 0x80 +#define ENC_EIE_PKTIE 0x40 +#define ENC_EIE_DMAIE 0x20 +#define ENC_EIE_LINKIE 0x10 +#define ENC_EIE_TXIE 0x08 +#define ENC_EIE_WOLIE 0x04 +#define ENC_EIE_TXERIE 0x02 +#define ENC_EIE_RXERIE 0x01 + +/* MACON1 Register Bits */ +#define ENC_MACON1_LOOPBK 0x10 +#define ENC_MACON1_TXPAUS 0x08 +#define ENC_MACON1_RXPAUS 0x04 +#define ENC_MACON1_PASSALL 0x02 +#define ENC_MACON1_MARXEN 0x01 + +/* MACON2 Register Bits */ +#define ENC_MACON2_MARST 0x80 +#define ENC_MACON2_RNDRST 0x40 +#define ENC_MACON2_MARXRST 0x08 +#define ENC_MACON2_RFUNRST 0x04 +#define ENC_MACON2_MATXRST 0x02 +#define ENC_MACON2_TFUNRST 0x01 + +/* MACON3 Register Bits */ +#define ENC_MACON3_PADCFG2 0x80 +#define ENC_MACON3_PADCFG1 0x40 +#define ENC_MACON3_PADCFG0 0x20 +#define ENC_MACON3_TXCRCEN 0x10 +#define ENC_MACON3_PHDRLEN 0x08 +#define ENC_MACON3_HFRMEN 0x04 +#define ENC_MACON3_FRMLNEN 0x02 +#define ENC_MACON3_FULDPX 0x01 + +/* MACON4 Register Bits */ +#define ENC_MACON4_DEFER 0x40 + +/* MICMD Register Bits */ +#define ENC_MICMD_MIISCAN 0x02 +#define ENC_MICMD_MIIRD 0x01 + +/* MISTAT Register Bits */ +#define ENC_MISTAT_NVALID 0x04 +#define ENC_MISTAT_SCAN 0x02 +#define ENC_MISTAT_BUSY 0x01 + +/* PHID1 and PHID2 values */ +#define ENC_PHID1_VALUE 0x0083 +#define ENC_PHID2_VALUE 0x1400 +#define ENC_PHID2_MASK 0xFC00 + +/* PHCON1 values */ +#define ENC_PHCON1_PDPXMD 0x0100 + +/* PHSTAT1 values */ +#define ENC_PHSTAT1_LLSTAT 0x0004 + +/* PHSTAT2 values */ +#define ENC_PHSTAT2_LSTAT 0x0400 +#define ENC_PHSTAT2_DPXSTAT 0x0200 + +#endif diff --git a/drivers/net/enc28j60_lpc2292.c b/drivers/net/enc28j60_lpc2292.c new file mode 100644 index 0000000000..bf9505206b --- /dev/null +++ b/drivers/net/enc28j60_lpc2292.c @@ -0,0 +1,983 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#warning This driver is depreciated. Please update to new SPI framework enc28j60 driver +#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spi.h> + +/* + * Control Registers in Bank 0 + */ + +#define CTL_REG_ERDPTL 0x00 +#define CTL_REG_ERDPTH 0x01 +#define CTL_REG_EWRPTL 0x02 +#define CTL_REG_EWRPTH 0x03 +#define CTL_REG_ETXSTL 0x04 +#define CTL_REG_ETXSTH 0x05 +#define CTL_REG_ETXNDL 0x06 +#define CTL_REG_ETXNDH 0x07 +#define CTL_REG_ERXSTL 0x08 +#define CTL_REG_ERXSTH 0x09 +#define CTL_REG_ERXNDL 0x0A +#define CTL_REG_ERXNDH 0x0B +#define CTL_REG_ERXRDPTL 0x0C +#define CTL_REG_ERXRDPTH 0x0D +#define CTL_REG_ERXWRPTL 0x0E +#define CTL_REG_ERXWRPTH 0x0F +#define CTL_REG_EDMASTL 0x10 +#define CTL_REG_EDMASTH 0x11 +#define CTL_REG_EDMANDL 0x12 +#define CTL_REG_EDMANDH 0x13 +#define CTL_REG_EDMADSTL 0x14 +#define CTL_REG_EDMADSTH 0x15 +#define CTL_REG_EDMACSL 0x16 +#define CTL_REG_EDMACSH 0x17 +/* these are common in all banks */ +#define CTL_REG_EIE 0x1B +#define CTL_REG_EIR 0x1C +#define CTL_REG_ESTAT 0x1D +#define CTL_REG_ECON2 0x1E +#define CTL_REG_ECON1 0x1F + +/* + * Control Registers in Bank 1 + */ + +#define CTL_REG_EHT0 0x00 +#define CTL_REG_EHT1 0x01 +#define CTL_REG_EHT2 0x02 +#define CTL_REG_EHT3 0x03 +#define CTL_REG_EHT4 0x04 +#define CTL_REG_EHT5 0x05 +#define CTL_REG_EHT6 0x06 +#define CTL_REG_EHT7 0x07 +#define CTL_REG_EPMM0 0x08 +#define CTL_REG_EPMM1 0x09 +#define CTL_REG_EPMM2 0x0A +#define CTL_REG_EPMM3 0x0B +#define CTL_REG_EPMM4 0x0C +#define CTL_REG_EPMM5 0x0D +#define CTL_REG_EPMM6 0x0E +#define CTL_REG_EPMM7 0x0F +#define CTL_REG_EPMCSL 0x10 +#define CTL_REG_EPMCSH 0x11 +#define CTL_REG_EPMOL 0x14 +#define CTL_REG_EPMOH 0x15 +#define CTL_REG_EWOLIE 0x16 +#define CTL_REG_EWOLIR 0x17 +#define CTL_REG_ERXFCON 0x18 +#define CTL_REG_EPKTCNT 0x19 + +/* + * Control Registers in Bank 2 + */ + +#define CTL_REG_MACON1 0x00 +#define CTL_REG_MACON2 0x01 +#define CTL_REG_MACON3 0x02 +#define CTL_REG_MACON4 0x03 +#define CTL_REG_MABBIPG 0x04 +#define CTL_REG_MAIPGL 0x06 +#define CTL_REG_MAIPGH 0x07 +#define CTL_REG_MACLCON1 0x08 +#define CTL_REG_MACLCON2 0x09 +#define CTL_REG_MAMXFLL 0x0A +#define CTL_REG_MAMXFLH 0x0B +#define CTL_REG_MAPHSUP 0x0D +#define CTL_REG_MICON 0x11 +#define CTL_REG_MICMD 0x12 +#define CTL_REG_MIREGADR 0x14 +#define CTL_REG_MIWRL 0x16 +#define CTL_REG_MIWRH 0x17 +#define CTL_REG_MIRDL 0x18 +#define CTL_REG_MIRDH 0x19 + +/* + * Control Registers in Bank 3 + */ + +#define CTL_REG_MAADR1 0x00 +#define CTL_REG_MAADR0 0x01 +#define CTL_REG_MAADR3 0x02 +#define CTL_REG_MAADR2 0x03 +#define CTL_REG_MAADR5 0x04 +#define CTL_REG_MAADR4 0x05 +#define CTL_REG_EBSTSD 0x06 +#define CTL_REG_EBSTCON 0x07 +#define CTL_REG_EBSTCSL 0x08 +#define CTL_REG_EBSTCSH 0x09 +#define CTL_REG_MISTAT 0x0A +#define CTL_REG_EREVID 0x12 +#define CTL_REG_ECOCON 0x15 +#define CTL_REG_EFLOCON 0x17 +#define CTL_REG_EPAUSL 0x18 +#define CTL_REG_EPAUSH 0x19 + + +/* + * PHY Register + */ + +#define PHY_REG_PHID1 0x02 +#define PHY_REG_PHID2 0x03 +/* taken from the Linux driver */ +#define PHY_REG_PHCON1 0x00 +#define PHY_REG_PHCON2 0x10 +#define PHY_REG_PHLCON 0x14 + +/* + * Receive Filter Register (ERXFCON) bits + */ + +#define ENC_RFR_UCEN 0x80 +#define ENC_RFR_ANDOR 0x40 +#define ENC_RFR_CRCEN 0x20 +#define ENC_RFR_PMEN 0x10 +#define ENC_RFR_MPEN 0x08 +#define ENC_RFR_HTEN 0x04 +#define ENC_RFR_MCEN 0x02 +#define ENC_RFR_BCEN 0x01 + +/* + * ECON1 Register Bits + */ + +#define ENC_ECON1_TXRST 0x80 +#define ENC_ECON1_RXRST 0x40 +#define ENC_ECON1_DMAST 0x20 +#define ENC_ECON1_CSUMEN 0x10 +#define ENC_ECON1_TXRTS 0x08 +#define ENC_ECON1_RXEN 0x04 +#define ENC_ECON1_BSEL1 0x02 +#define ENC_ECON1_BSEL0 0x01 + +/* + * ECON2 Register Bits + */ +#define ENC_ECON2_AUTOINC 0x80 +#define ENC_ECON2_PKTDEC 0x40 +#define ENC_ECON2_PWRSV 0x20 +#define ENC_ECON2_VRPS 0x08 + +/* + * EIR Register Bits + */ +#define ENC_EIR_PKTIF 0x40 +#define ENC_EIR_DMAIF 0x20 +#define ENC_EIR_LINKIF 0x10 +#define ENC_EIR_TXIF 0x08 +#define ENC_EIR_WOLIF 0x04 +#define ENC_EIR_TXERIF 0x02 +#define ENC_EIR_RXERIF 0x01 + +/* + * ESTAT Register Bits + */ + +#define ENC_ESTAT_INT 0x80 +#define ENC_ESTAT_LATECOL 0x10 +#define ENC_ESTAT_RXBUSY 0x04 +#define ENC_ESTAT_TXABRT 0x02 +#define ENC_ESTAT_CLKRDY 0x01 + +/* + * EIE Register Bits + */ + +#define ENC_EIE_INTIE 0x80 +#define ENC_EIE_PKTIE 0x40 +#define ENC_EIE_DMAIE 0x20 +#define ENC_EIE_LINKIE 0x10 +#define ENC_EIE_TXIE 0x08 +#define ENC_EIE_WOLIE 0x04 +#define ENC_EIE_TXERIE 0x02 +#define ENC_EIE_RXERIE 0x01 + +/* + * MACON1 Register Bits + */ +#define ENC_MACON1_LOOPBK 0x10 +#define ENC_MACON1_TXPAUS 0x08 +#define ENC_MACON1_RXPAUS 0x04 +#define ENC_MACON1_PASSALL 0x02 +#define ENC_MACON1_MARXEN 0x01 + + +/* + * MACON2 Register Bits + */ +#define ENC_MACON2_MARST 0x80 +#define ENC_MACON2_RNDRST 0x40 +#define ENC_MACON2_MARXRST 0x08 +#define ENC_MACON2_RFUNRST 0x04 +#define ENC_MACON2_MATXRST 0x02 +#define ENC_MACON2_TFUNRST 0x01 + +/* + * MACON3 Register Bits + */ +#define ENC_MACON3_PADCFG2 0x80 +#define ENC_MACON3_PADCFG1 0x40 +#define ENC_MACON3_PADCFG0 0x20 +#define ENC_MACON3_TXCRCEN 0x10 +#define ENC_MACON3_PHDRLEN 0x08 +#define ENC_MACON3_HFRMEN 0x04 +#define ENC_MACON3_FRMLNEN 0x02 +#define ENC_MACON3_FULDPX 0x01 + +/* + * MICMD Register Bits + */ +#define ENC_MICMD_MIISCAN 0x02 +#define ENC_MICMD_MIIRD 0x01 + +/* + * MISTAT Register Bits + */ +#define ENC_MISTAT_NVALID 0x04 +#define ENC_MISTAT_SCAN 0x02 +#define ENC_MISTAT_BUSY 0x01 + +/* + * PHID1 and PHID2 values + */ +#define ENC_PHID1_VALUE 0x0083 +#define ENC_PHID2_VALUE 0x1400 +#define ENC_PHID2_MASK 0xFC00 + + +#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ +#define ENC_RESET 0x00020000 /* pin P1.17 */ + +#define FAILSAFE_VALUE 5000 + +/* + * Controller memory layout: + * + * 0x0000 - 0x17ff 6k bytes receive buffer + * 0x1800 - 0x1fff 2k bytes transmit buffer + */ +/* Use the lower memory for receiver buffer. See errata pt. 5 */ +#define ENC_RX_BUF_START 0x0000 +#define ENC_TX_BUF_START 0x1800 +/* taken from the Linux driver */ +#define ENC_RX_BUF_END 0x17ff +#define ENC_TX_BUF_END 0x1fff + +/* maximum frame length */ +#define ENC_MAX_FRM_LEN 1518 + +#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) +#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) +#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); + + +static unsigned char encReadReg (unsigned char regNo); +static void encWriteReg (unsigned char regNo, unsigned char data); +static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); +static void encReadBuff (unsigned short length, unsigned char *pBuff); +static void encWriteBuff (unsigned short length, unsigned char *pBuff); +static void encBitSet (unsigned char regNo, unsigned char data); +static void encBitClr (unsigned char regNo, unsigned char data); +static void encReset (void); +static void encInit (unsigned char *pEthAddr); +static unsigned short phyRead (unsigned char addr); +static void phyWrite(unsigned char, unsigned short); +static void encPoll (void); +static void encRx (void); + +#define m_nic_read(reg) encReadReg(reg) +#define m_nic_write(reg, data) encWriteReg(reg, data) +#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) +#define m_nic_read_data(len, buf) encReadBuff((len), (buf)) +#define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) + +/* bit field set */ +#define m_nic_bfs(reg, data) encBitSet(reg, data) + +/* bit field clear */ +#define m_nic_bfc(reg, data) encBitClr(reg, data) + +static unsigned char bank = 0; /* current bank in enc28j60 */ +static unsigned char next_pointer_lsb; +static unsigned char next_pointer_msb; + +static unsigned char buffer[ENC_MAX_FRM_LEN]; +static int rxResetCounter = 0; + +#define RX_RESET_COUNTER 1000; + +/*----------------------------------------------------------------------------- + * Always returns 0 + */ +int eth_init (bd_t * bis) +{ + unsigned char estatVal; + uchar enetaddr[6]; + + /* configure GPIO */ + (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; + (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; + + /* CS and RESET active low */ + PUT32 (IO1SET, ENC_SPI_SLAVE_CS); + PUT32 (IO1SET, ENC_RESET); + + spi_init (); + + /* taken from the Linux driver - dangerous stuff here! */ + /* Wait for CLKRDY to become set (i.e., check that we can communicate with + the ENC) */ + do + { + estatVal = m_nic_read(CTL_REG_ESTAT); + } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY)); + + /* initialize controller */ + encReset (); + eth_getenv_enetaddr("ethaddr", enetaddr); + encInit (enetaddr); + + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ + + return 0; +} + +int eth_send (volatile void *packet, int length) +{ + /* check frame length, etc. */ + /* TODO: */ + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + /* set EWRPT */ + m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); + m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); + + /* set ETXND */ + m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); + m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); + + /* set ETXST */ + m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); + m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); + + /* write packet */ + m_nic_write_data (length, (unsigned char *) packet); + + /* taken from the Linux driver */ + /* Verify that the internal transmit logic has not been altered by excessive + collisions. See Errata B4 12 and 14. + */ + if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) { + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST); + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST); + } + m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); + + /* set ECON1.TXRTS */ + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); + + return 0; +} + + +/***************************************************************************** + * This function resets the receiver only. This function may be called from + * interrupt-context. + */ +static void encReceiverReset (void) +{ + unsigned char econ1; + + econ1 = m_nic_read (CTL_REG_ECON1); + if ((econ1 & ENC_ECON1_RXRST) == 0) { + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); + rxResetCounter = RX_RESET_COUNTER; + } +} + +/***************************************************************************** + * receiver reset timer + */ +static void encReceiverResetCallback (void) +{ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ +} + +/*----------------------------------------------------------------------------- + * Check for received packets. Call NetReceive for each packet. The return + * value is ignored by the caller. + */ +int eth_rx (void) +{ + if (rxResetCounter > 0 && --rxResetCounter == 0) { + encReceiverResetCallback (); + } + + encPoll (); + + return 0; +} + +void eth_halt (void) +{ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ +} + +/*****************************************************************************/ + +static void encPoll (void) +{ + unsigned char eir_reg; + volatile unsigned char estat_reg; + unsigned char pkt_cnt; + +#ifdef CONFIG_USE_IRQ + /* clear global interrupt enable bit in enc28j60 */ + m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); +#endif + estat_reg = m_nic_read (CTL_REG_ESTAT); + + eir_reg = m_nic_read (CTL_REG_EIR); + + if (eir_reg & ENC_EIR_TXIF) { + /* clear TXIF bit in EIR */ + m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); + } + + /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ + + /* move to bank 1 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); + + /* read pktcnt */ + pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); + + if (pkt_cnt > 0) { + if ((eir_reg & ENC_EIR_PKTIF) == 0) { + /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ + } + encRx (); + /* clear PKTIF bit in EIR, this should not need to be done but it + seems like we get problems if we do not */ + m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); + } + + if (eir_reg & ENC_EIR_RXERIF) { + printf ("encPoll: rx error\n"); + m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); + } + if (eir_reg & ENC_EIR_TXERIF) { + printf ("encPoll: tx error\n"); + m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); + } + +#ifdef CONFIG_USE_IRQ + /* set global interrupt enable bit in enc28j60 */ + m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); +#endif +} + +static void encRx (void) +{ + unsigned short pkt_len; + unsigned short copy_len; + unsigned short status; + unsigned char eir_reg; + unsigned char pkt_cnt = 0; + unsigned short rxbuf_rdpt; + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); + m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); + + do { + m_nic_read_data (6, buffer); + next_pointer_lsb = buffer[0]; + next_pointer_msb = buffer[1]; + pkt_len = buffer[2]; + pkt_len |= (unsigned short) buffer[3] << 8; + status = buffer[4]; + status |= (unsigned short) buffer[5] << 8; + + if (pkt_len <= ENC_MAX_FRM_LEN) + copy_len = pkt_len; + else + copy_len = 0; + + if ((status & (1L << 7)) == 0) /* check Received Ok bit */ + copy_len = 0; + + /* taken from the Linux driver */ + /* check if next pointer is resonable */ + if ((((unsigned int)next_pointer_msb << 8) | + (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START) + copy_len = 0; + + if (copy_len > 0) { + m_nic_read_data (copy_len, buffer); + } + + /* advance read pointer to next pointer */ + m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); + m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); + + /* decrease packet counter */ + m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); + + /* taken from the Linux driver */ + /* Only odd values should be written to ERXRDPTL, + * see errata B4 pt.13 + */ + rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; + if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | + m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > + (m_nic_read(CTL_REG_ERXNDH) << 8 | + m_nic_read(CTL_REG_ERXNDL)))) { + m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL)); + m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH)); + } else { + m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF); + m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8); + } + + /* move to bank 1 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); + + /* read pktcnt */ + pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, + (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + if (copy_len == 0) { + eir_reg = m_nic_read (CTL_REG_EIR); + encReceiverReset (); + printf ("eth_rx: copy_len=0\n"); + continue; + } + + NetReceive ((unsigned char *) buffer, pkt_len); + + eir_reg = m_nic_read (CTL_REG_EIR); + } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ +} + +static void encWriteReg (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x40 | regNo); /* write in regNo */ + spi_write (data); + + enc_disable (); + enc_enable (); + + spi_write (0x1f); /* write reg 0x1f */ + + enc_disable (); + spi_unlock (); +} + +static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) +{ + unsigned char readback; + int i; + + spi_lock (); + + for (i = 0; i < c; i++) { + enc_cfg_spi (); + enc_enable (); + + spi_write (0x40 | regNo); /* write in regNo */ + spi_write (data); + + enc_disable (); + enc_enable (); + + spi_write (0x1f); /* write reg 0x1f */ + + enc_disable (); + + spi_unlock (); /* we must unlock spi first */ + + readback = encReadReg (regNo); + + spi_lock (); + + if (readback == data) + break; + } + spi_unlock (); + + if (i == c) { + printf ("enc28j60: write reg %d failed\n", regNo); + } +} + +static unsigned char encReadReg (unsigned char regNo) +{ + unsigned char rxByte; + + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x1f); /* read reg 0x1f */ + + bank = spi_read () & 0x3; + + enc_disable (); + enc_enable (); + + spi_write (regNo); + rxByte = spi_read (); + + /* check if MAC or MII register */ + if (((bank == 2) && (regNo <= 0x1a)) || + ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { + /* ignore first byte and read another byte */ + rxByte = spi_read (); + } + + enc_disable (); + spi_unlock (); + + return rxByte; +} + +static void encReadBuff (unsigned short length, unsigned char *pBuff) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x20 | 0x1a); /* read buffer memory */ + + while (length--) { + if (pBuff != NULL) + *pBuff++ = spi_read (); + else + spi_write (0); + } + + enc_disable (); + spi_unlock (); +} + +static void encWriteBuff (unsigned short length, unsigned char *pBuff) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x60 | 0x1a); /* write buffer memory */ + + spi_write (0x00); /* control byte */ + + while (length--) + spi_write (*pBuff++); + + enc_disable (); + spi_unlock (); +} + +static void encBitSet (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x80 | regNo); /* bit field set */ + spi_write (data); + + enc_disable (); + spi_unlock (); +} + +static void encBitClr (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0xA0 | regNo); /* bit field clear */ + spi_write (data); + + enc_disable (); + spi_unlock (); +} + +static void encReset (void) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0xff); /* soft reset */ + + enc_disable (); + spi_unlock (); + + /* sleep 1 ms. See errata pt. 2 */ + udelay (1000); +} + +static void encInit (unsigned char *pEthAddr) +{ + unsigned short phid1 = 0; + unsigned short phid2 = 0; + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + /* + * Setup the buffer space. The reset values are valid for the + * other pointers. + */ + /* We shall not write to ERXST, see errata pt. 5. Instead we + have to make sure that ENC_RX_BUS_START is 0. */ + m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); + + /* taken from the Linux driver */ + m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1); + + m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); + + next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); + next_pointer_msb = (ENC_RX_BUF_START >> 8); + + /* verify identification */ + phid1 = phyRead (PHY_REG_PHID1); + phid2 = phyRead (PHY_REG_PHID2); + + if (phid1 != ENC_PHID1_VALUE + || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { + printf ("ERROR: failed to identify controller\n"); + printf ("phid1 = %x, phid2 = %x\n", + phid1, (phid2 & ENC_PHID2_MASK)); + printf ("should be phid1 = %x, phid2 = %x\n", + ENC_PHID1_VALUE, ENC_PHID2_VALUE); + } + + /* + * --- MAC Initialization --- + */ + + /* Pull MAC out of Reset */ + + /* switch to bank 2 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* enable MAC to receive frames */ + /* added some bits from the Linux driver */ + m_nic_write_retry (CTL_REG_MACON1 + ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS) + ,10); + + /* configure pad, tx-crc and duplex */ + /* added a bit from the Linux driver */ + m_nic_write_retry (CTL_REG_MACON3 + ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN) + ,10); + + /* added 4 new lines from the Linux driver */ + /* Allow infinite deferals if the medium is continously busy */ + m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10); + + /* Late collisions occur beyond 63 bytes */ + m_nic_write_retry(CTL_REG_MACLCON2, 63, 10); + + /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ + m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10); + + /* + * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended + * 0x0c for half-duplex. Nothing for full-duplex + */ + m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10); + + /* set maximum frame length */ + m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); + m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); + + /* + * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex + * and 0x15 for full duplex. + */ + m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); + + /* set MAC address */ + + /* switch to bank 3 */ + m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); + + m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); + m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); + m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); + m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); + m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); + m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); + + /* + * PHY Initialization taken from the Linux driver + */ + + /* Prevent automatic loopback of data beeing transmitted by setting + ENC_PHCON2_HDLDIS */ + phyWrite(PHY_REG_PHCON2, (1<<8)); + + /* LEDs configuration + * LEDA: LACFG = 0100 -> display link status + * LEDB: LBCFG = 0111 -> display TX & RX activity + * STRCH = 1 -> LED pulses + */ + phyWrite(PHY_REG_PHLCON, 0x0472); + + /* Reset PDPXMD-bit => half duplex */ + phyWrite(PHY_REG_PHCON1, 0); + + /* + * Receive settings + */ + +#ifdef CONFIG_USE_IRQ + /* enable interrupts */ + m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); +#endif +} + +/***************************************************************************** + * + * Description: + * Read PHY registers. + * + * NOTE! This function will change to Bank 2. + * + * Params: + * [in] addr address of the register to read + * + * Returns: + * The value in the register + */ +static unsigned short phyRead (unsigned char addr) +{ + unsigned short ret = 0; + + /* move to bank 2 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* write address to MIREGADR */ + m_nic_write (CTL_REG_MIREGADR, addr); + + /* set MICMD.MIIRD */ + m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); + + /* taken from the Linux driver */ + /* move to bank 3 */ + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* poll MISTAT.BUSY bit until operation is complete */ + while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { + static int cnt = 0; + + if (cnt++ >= 1000) { + /* GJ - this seems extremely dangerous! */ + /* printf("#"); */ + cnt = 0; + } + } + + /* taken from the Linux driver */ + /* move to bank 2 */ + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* clear MICMD.MIIRD */ + m_nic_write (CTL_REG_MICMD, 0); + + ret = (m_nic_read (CTL_REG_MIRDH) << 8); + ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); + + return ret; +} + +/***************************************************************************** + * + * Taken from the Linux driver. + * Description: + * Write PHY registers. + * + * NOTE! This function will change to Bank 3. + * + * Params: + * [in] addr address of the register to write to + * [in] data to be written + * + * Returns: + * None + */ +static void phyWrite(unsigned char addr, unsigned short data) +{ + /* move to bank 2 */ + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* write address to MIREGADR */ + m_nic_write(CTL_REG_MIREGADR, addr); + + m_nic_write(CTL_REG_MIWRL, data & 0xff); + m_nic_write(CTL_REG_MIWRH, data >> 8); + + /* move to bank 3 */ + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* poll MISTAT.BUSY bit until operation is complete */ + while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { + static int cnt = 0; + + if(cnt++ >= 1000) { + cnt = 0; + } + } +} diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index c88e596c01..bc8c9222dc 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -250,6 +250,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) mpc5xxx_fec_init_phy(dev, bis); /* + * Call board-specific PHY fixups (if any) + */ +#ifdef CONFIG_RESET_PHY_R + reset_phy(); +#endif + + /* * Initialize RxBD/TxBD rings */ mpc5xxx_fec_rbd_init(fec); diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 54a1bfb2a9..ba9c67e4c9 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -654,6 +654,28 @@ again: return length; } +static int smc_write_hwaddr(struct eth_device *dev) +{ + int i; + + swap_to(ETHERNET); + SMC_SELECT_BANK (dev, 1); +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = dev->enetaddr[i + 1] << 8; + address |= dev->enetaddr[i]; + SMC_outw(dev, address, (ADDR0_REG + i)); + } +#else + for (i = 0; i < 6; i++) + SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); +#endif + swap_to(FLASH); + return 0; +} + /* * Open and Initialize the board * @@ -662,8 +684,6 @@ again: */ static int smc_init(struct eth_device *dev, bd_t *bd) { - int i; - swap_to(ETHERNET); PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); @@ -680,20 +700,6 @@ static int smc_init(struct eth_device *dev, bd_t *bd) /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ /* SMC_SELECT_BANK(dev, 0); */ /* SMC_outw(dev, 0, RPC_REG); */ - SMC_SELECT_BANK (dev, 1); - -#ifdef USE_32_BIT - for (i = 0; i < 6; i += 2) { - word address; - - address = dev->enetaddr[i + 1] << 8; - address |= dev->enetaddr[i]; - SMC_outw(dev, address, (ADDR0_REG + i)); - } -#else - for (i = 0; i < 6; i++) - SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); -#endif printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); @@ -1360,6 +1366,7 @@ int smc91111_initialize(u8 dev_num, int base_addr) return 0; } + memset(dev, 0, sizeof(*dev)); priv->dev_num = dev_num; dev->priv = priv; dev->iobase = base_addr; @@ -1374,6 +1381,7 @@ int smc91111_initialize(u8 dev_num, int base_addr) dev->halt = smc_halt; dev->send = smc_send; dev->recv = smc_rcv; + dev->write_hwaddr = smc_write_hwaddr; sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); eth_register(dev); diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 0820daa2bb..76af939e98 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -26,6 +26,7 @@ #include <common.h> #include <net.h> #include <config.h> +#include <malloc.h> #include <asm/io.h> #undef DEBUG @@ -63,26 +64,19 @@ #define XEL_RSR_RECV_IE_MASK 0x00000008UL typedef struct { - unsigned int baseaddress; /* Base address for device (IPIF) */ - unsigned int nexttxbuffertouse; /* Next TX buffer to write to */ - unsigned int nextrxbuffertouse; /* Next RX buffer to read from */ - unsigned char deviceid; /* Unique ID of device - for future */ + u32 baseaddress; /* Base address for device (IPIF) */ + u32 nexttxbuffertouse; /* Next TX buffer to write to */ + u32 nextrxbuffertouse; /* Next RX buffer to read from */ + uchar deviceid; /* Unique ID of device - for future */ } xemaclite; static xemaclite emaclite; static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ -/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ -#ifdef CONFIG_ENV_IS_NOWHERE -static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; -#else -static u8 emacaddr[ENET_ADDR_LENGTH]; -#endif - -void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) +static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount) { - unsigned int i; + u32 i; u32 alignbuffer; u32 *to32ptr; u32 *from32ptr; @@ -107,9 +101,9 @@ void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) } } -void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) +static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount) { - unsigned i; + u32 i; u32 alignbuffer; u32 *to32ptr = (u32 *) destptr; u32 *from32ptr; @@ -134,23 +128,16 @@ void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) *to32ptr++ = alignbuffer; } -void eth_halt (void) +static void emaclite_halt(struct eth_device *dev) { debug ("eth_halt\n"); } -int eth_init (bd_t * bis) +static int emaclite_init(struct eth_device *dev, bd_t *bis) { - uchar enetaddr[6]; - debug ("EmacLite Initialization Started\n"); memset (&emaclite, 0, sizeof (xemaclite)); - emaclite.baseaddress = XILINX_EMACLITE_BASEADDR; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH); - eth_setenv_enetaddr("ethaddr", enetaddr); - } + emaclite.baseaddress = dev->iobase; /* * TX - TX_PING & TX_PONG initialization @@ -158,7 +145,7 @@ int eth_init (bd_t * bis) /* Restart PING TX */ out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); /* Copy MAC address */ - xemaclite_alignedwrite (enetaddr, + xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress, ENET_ADDR_LENGTH); /* Set the length */ out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); @@ -171,7 +158,7 @@ int eth_init (bd_t * bis) #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG /* The same operation with PONG TX */ out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite (enetaddr, emaclite.baseaddress + + xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, @@ -194,7 +181,7 @@ int eth_init (bd_t * bis) return 0; } -int xemaclite_txbufferavailable (xemaclite * instanceptr) +static int xemaclite_txbufferavailable (xemaclite *instanceptr) { u32 reg; u32 txpingbusy; @@ -216,12 +203,12 @@ int xemaclite_txbufferavailable (xemaclite * instanceptr) return (!(txpingbusy && txpongbusy)); } -int eth_send (volatile void *ptr, int len) { - - unsigned int reg; - unsigned int baseaddress; +static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) +{ + u32 reg; + u32 baseaddress; - unsigned maxtry = 1000; + u32 maxtry = 1000; if (len > ENET_MAX_MTU) len = ENET_MAX_MTU; @@ -293,11 +280,11 @@ int eth_send (volatile void *ptr, int len) { return 0; } -int eth_rx (void) +static int emaclite_recv(struct eth_device *dev) { - unsigned int length; - unsigned int reg; - unsigned int baseaddress; + u32 length; + u32 reg; + u32 baseaddress; baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; reg = in_be32 (baseaddress + XEL_RSR_OFFSET); @@ -322,7 +309,7 @@ int eth_rx (void) #endif } /* Get the length of the frame that arrived */ - switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) & + switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & 0xFFFF0000 ) >> 16) { case 0x806: length = 42 + 20; /* FIXME size of ARP */ @@ -330,7 +317,7 @@ int eth_rx (void) break; case 0x800: length = 14 + 14 + - (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) & + (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) & 0xFFFF0000) >> 16); /* FIXME size of IP packet */ debug ("IP Packet\n"); break; @@ -353,3 +340,26 @@ int eth_rx (void) return 1; } + +int xilinx_emaclite_initialize (bd_t *bis, int base_addr) +{ + struct eth_device *dev; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "Xilinx_Emaclite"); + + dev->iobase = base_addr; + dev->priv = 0; + dev->init = emaclite_init; + dev->halt = emaclite_halt; + dev->send = emaclite_send; + dev->recv = emaclite_recv; + + eth_register(dev); + + return 0; +} diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index e10c0f328c..48033d750c 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1223,8 +1223,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) i = 50; do { err = curphy->read_status(uec->mii_info); + if (!(((i-- > 0) && !uec->mii_info->link) || err)) + break; udelay(100000); - } while (((i-- > 0) && !uec->mii_info->link) || err); + } while (1); if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 2d3a896d6f..9be784e6ad 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -351,6 +351,15 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info) static int genmii_config_aneg (struct uec_mii_info *mii_info) { if (mii_info->autoneg) { + /* Speed up the common case, if link is already up, speed and + duplex match, skip auto neg as it already matches */ + if (!genmii_read_status(mii_info) && mii_info->link) + if (mii_info->duplex == DUPLEX_FULL && + mii_info->speed == SPEED_100) + if (mii_info->advertising & + ADVERTISED_100baseT_Full) + return 0; + config_genmii_advert (mii_info); genmii_restart_aneg (mii_info); } else @@ -389,7 +398,6 @@ static int genmii_update_link (struct uec_mii_info *mii_info) status = phy_read(mii_info, PHY_BMSR); } mii_info->link = 1; - udelay(500000); /* another 500 ms (results in faster booting) */ } else { if (status & PHY_BMSR_LS) mii_info->link = 1; diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 746bf18f04..cdc5ff10fa 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_PORTIO /* Port I/O */ #define CONFIG_CMD_REGINFO /* Register dump */ #define CONFIG_CMD_REISER /* Reiserfs support */ +#define CONFIG_CMD_RARP /* rarpboot support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index adb6ac52e1..ba3ada13a5 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -198,6 +198,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_MMC 1 /* we use this ethernet chip */ -#define CONFIG_ENC28J60 +#define CONFIG_ENC28J60_LPC2292 #endif /* __CONFIG_H */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 7ce8d6de1f..65276a27c0 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -156,6 +156,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_MMC 1 /* we use this ethernet chip */ -#define CONFIG_ENC28J60 +#define CONFIG_ENC28J60_LPC2292 #endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 9b1569a6d4..c30cc4cbc8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 Michal Simek + * (C) Copyright 2007-2010 Michal Simek * * Michal SIMEK <monstr@monstr.eu> * @@ -27,31 +27,33 @@ #include "../board/xilinx/microblaze-generic/xparameters.h" -#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +/* MicroBlaze CPU */ +#define CONFIG_MICROBLAZE 1 #define MICROBLAZE_V5 1 /* uart */ #ifdef XILINX_UARTLITE_BASEADDR - #define CONFIG_XILINX_UARTLITE - #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR - #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE - #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } - #define CONSOLE_ARG "console=console=ttyUL0,115200\0" +# define CONFIG_XILINX_UARTLITE +# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR +# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE +# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } +# define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR - #define CONFIG_SYS_NS16550 1 - #define CONFIG_SYS_NS16550_SERIAL - #define CONFIG_SYS_NS16550_REG_SIZE -4 - #define CONFIG_CONS_INDEX 1 - #define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) - #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ - #define CONFIG_BAUDRATE 115200 - - /* The following table includes the supported baudrates */ - #define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - #define CONSOLE_ARG "console=console=ttyS0,115200\0" +# define CONFIG_SYS_NS16550 1 +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# define CONFIG_CONS_INDEX 1 +# define CONFIG_SYS_NS16550_COM1 \ + (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) +# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ +# define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +# define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +# define CONSOLE_ARG "console=console=ttyS0,115200\0" #else - #error Undefined uart +# error Undefined uart #endif /* setting reset address */ @@ -59,41 +61,41 @@ /* ethernet */ #ifdef XILINX_EMACLITE_BASEADDR - #define CONFIG_XILINX_EMACLITE 1 - #define CONFIG_SYS_ENET +# define CONFIG_XILINX_EMACLITE 1 +# define CONFIG_SYS_ENET #elif XILINX_LLTEMAC_BASEADDR - #define CONFIG_XILINX_LL_TEMAC 1 - #define CONFIG_SYS_ENET +# define CONFIG_XILINX_LL_TEMAC 1 +# define CONFIG_SYS_ENET #endif #undef ET_DEBUG /* gpio */ #ifdef XILINX_GPIO_BASEADDR - #define CONFIG_SYS_GPIO_0 1 - #define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR +# define CONFIG_SYS_GPIO_0 1 +# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0 1 - #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +# define CONFIG_SYS_INTC_0 1 +# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR +# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS #endif /* timer */ #ifdef XILINX_TIMER_BASEADDR - #if (XILINX_TIMER_IRQ != -1) - #define CONFIG_SYS_TIMER_0 1 - #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR - #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ - #define FREQUENCE XILINX_CLOCK_FREQ - #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) - #endif +# if (XILINX_TIMER_IRQ != -1) +# define CONFIG_SYS_TIMER_0 1 +# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR +# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ +# define FREQUENCE XILINX_CLOCK_FREQ +# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +# endif #elif XILINX_CLOCK_FREQ - #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ +# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ #else - #error BAD CLOCK FREQ +# error BAD CLOCK FREQ #endif /* FSL */ /* #define CONFIG_SYS_FSL_2 */ @@ -135,15 +137,20 @@ /* global pointer */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size of global data */ /* start of global data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE \ + - CONFIG_SYS_GBL_DATA_SIZE) /* monitor code */ -#define SIZE 0x40000 +#define SIZE 0x40000 #define CONFIG_SYS_MONITOR_LEN (SIZE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MONITOR_BASE \ + (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MONITOR_END \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN SIZE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE \ + (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) /* stack */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE @@ -152,55 +159,62 @@ #define FLASH #ifdef FLASH - #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START - #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE - #define CONFIG_SYS_FLASH_CFI 1 - #define CONFIG_FLASH_CFI_DRIVER 1 - #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ - - #ifdef RAMENV - #define CONFIG_ENV_IS_NOWHERE 1 - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - - #else /* !RAMENV */ - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) - #define CONFIG_ENV_SIZE 0x20000 - #endif /* !RAMBOOT */ +# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START +# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE +# define CONFIG_SYS_FLASH_CFI 1 +# define CONFIG_FLASH_CFI_DRIVER 1 +/* ?empty sector */ +# define CONFIG_SYS_FLASH_EMPTY_INFO 1 +/* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +# define CONFIG_SYS_MAX_FLASH_SECT 512 +/* hardware flash protection */ +# define CONFIG_SYS_FLASH_PROTECTION + +# ifdef RAMENV +# define CONFIG_ENV_IS_NOWHERE 1 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + +# else /* !RAMENV */ +# define CONFIG_ENV_IS_IN_FLASH 1 +/* 128K(one sector) for env */ +# define CONFIG_ENV_SECT_SIZE 0x20000 +# define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) +# define CONFIG_ENV_SIZE 0x20000 +# endif /* !RAMBOOT */ #else /* !FLASH */ - /* ENV in RAM */ - #define CONFIG_SYS_NO_FLASH 1 - #define CONFIG_ENV_IS_NOWHERE 1 - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ +/* ENV in RAM */ +# define CONFIG_SYS_NO_FLASH 1 +# define CONFIG_ENV_IS_NOWHERE 1 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +/* hardware flash protection */ +# define CONFIG_SYS_FLASH_PROTECTION #endif /* !FLASH */ /* system ace */ #ifdef XILINX_SYSACE_BASEADDR - #define CONFIG_SYSTEMACE - /* #define DEBUG_SYSTEMACE */ - #define SYSTEMACE_CONFIG_FPGA - #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR - #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH - #define CONFIG_DOS_PARTITION +# define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +# define SYSTEMACE_CONFIG_FPGA +# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +# define CONFIG_DOS_PARTITION #endif #if defined(XILINX_USE_ICACHE) - #define CONFIG_ICACHE +# define CONFIG_ICACHE #else - #undef CONFIG_ICACHE +# undef CONFIG_ICACHE #endif #if defined(XILINX_USE_DCACHE) - #define CONFIG_DCACHE +# define CONFIG_DCACHE #else - #undef CONFIG_DCACHE +# undef CONFIG_DCACHE #endif /* @@ -222,36 +236,39 @@ #define CONFIG_CMD_ECHO #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) - #define CONFIG_CMD_CACHE +# define CONFIG_CMD_CACHE #else - #undef CONFIG_CMD_CACHE +# undef CONFIG_CMD_CACHE #endif #ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET +# undef CONFIG_CMD_NET +# undef CONFIG_NET_MULTI #else - #define CONFIG_CMD_PING +# define CONFIG_CMD_PING +# define CONFIG_CMD_DHCP +# define CONFIG_NET_MULTI #endif #if defined(CONFIG_SYSTEMACE) - #define CONFIG_CMD_EXT2 - #define CONFIG_CMD_FAT +# define CONFIG_CMD_EXT2 +# define CONFIG_CMD_FAT #endif #if defined(FLASH) - #define CONFIG_CMD_ECHO - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_IMLS - #define CONFIG_CMD_JFFS2 - - #if !defined(RAMENV) - #define CONFIG_CMD_SAVEENV - #define CONFIG_CMD_SAVES - #endif +# define CONFIG_CMD_ECHO +# define CONFIG_CMD_FLASH +# define CONFIG_CMD_IMLS +# define CONFIG_CMD_JFFS2 + +# if !defined(RAMENV) +# define CONFIG_CMD_SAVEENV +# define CONFIG_CMD_SAVES +# endif #else - #undef CONFIG_CMD_IMLS - #undef CONFIG_CMD_FLASH - #undef CONFIG_CMD_JFFS2 +# undef CONFIG_CMD_IMLS +# undef CONFIG_CMD_FLASH +# undef CONFIG_CMD_JFFS2 #endif #if defined(CONFIG_CMD_JFFS2) @@ -259,21 +276,26 @@ #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=ml401-0" +#define MTDIDS_DEFAULT "nor0=flash-0" /* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ +#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ "256k(env),3m(kernel),1m(romfs),"\ "1m(cramfs),-(jffs2)" #endif /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "U-Boot-mONStR> " -#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +/* size of console buffer */ +#define CONFIG_SYS_CBSIZE 512 + /* print buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 15 #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" @@ -290,9 +312,9 @@ #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ - "nor0=ml401-0\0"\ - "mtdparts=mtdparts=ml401-0:"\ +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ + "nor0=flash-0\0"\ + "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ "1m(romfs),1m(cramfs),-(jffs2)\0" @@ -301,7 +323,7 @@ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +# define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif #endif /* __CONFIG_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 16556c4798..3b18d7d688 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -208,10 +208,6 @@ struct mtd_info { int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); - /* Power Management functions */ - int (*suspend) (struct mtd_info *mtd); - void (*resume) (struct mtd_info *mtd); - /* Bad block management functions */ int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); @@ -259,7 +255,9 @@ extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); extern struct mtd_info *get_mtd_device_nm(const char *name); extern void put_mtd_device(struct mtd_info *mtd); - +extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, + const uint64_t length, uint64_t *len_incl_bad, + int *truncated); /* XXX U-BOOT XXX */ #if 0 struct mtd_notifier { diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 68e174e310..5465562639 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -154,6 +154,7 @@ struct onenand_chip { /* * OneNAND Flash Manufacturer ID Codes */ +#define ONENAND_MFR_NUMONYX 0x20 #define ONENAND_MFR_SAMSUNG 0xec /** diff --git a/include/nand.h b/include/nand.h index 8bdf4191a6..a4524113d0 100644 --- a/include/nand.h +++ b/include/nand.h @@ -98,13 +98,16 @@ struct nand_read_options { typedef struct nand_read_options nand_read_options_t; struct nand_erase_options { - ulong length; /* number of bytes to erase */ - ulong offset; /* first address in NAND to erase */ + loff_t length; /* number of bytes to erase */ + loff_t offset; /* first address in NAND to erase */ int quiet; /* don't display progress messages */ int jffs2; /* if true: format for jffs2 usage * (write appropriate cleanmarker blocks) */ int scrub; /* if true, really clean NAND by erasing * bad blocks (UNSAFE) */ + + /* Don't include skipped bad blocks in size to be erased */ + int spread; }; typedef struct nand_erase_options nand_erase_options_t; diff --git a/include/netdev.h b/include/netdev.h index 94eedfe29d..7f66419350 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -54,6 +54,8 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); +int enc28j60_initialize(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); int ep93xx_eth_initialize(u8 dev_num, int base_addr); int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); @@ -85,9 +87,9 @@ int skge_initialize(bd_t *bis); int smc911x_initialize(u8 dev_num, int base_addr); int smc91111_initialize(u8 dev_num, int base_addr); int tsi108_eth_initialize(bd_t *bis); -int uec_initialize(int index); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); +int xilinx_emaclite_initialize (bd_t *bis, int base_addr); int sh_eth_initialize(bd_t *bis); int dm9000_initialize(bd_t *bis); diff --git a/net/Makefile b/net/Makefile index 4f819dd515..216d1ec959 100644 --- a/net/Makefile +++ b/net/Makefile @@ -32,7 +32,7 @@ COBJS-$(CONFIG_CMD_DNS) += dns.o COBJS-$(CONFIG_CMD_NET) += eth.o COBJS-$(CONFIG_CMD_NET) += net.o COBJS-$(CONFIG_CMD_NFS) += nfs.o -COBJS-$(CONFIG_CMD_NET) += rarp.o +COBJS-$(CONFIG_CMD_RARP) += rarp.o COBJS-$(CONFIG_CMD_SNTP) += sntp.o COBJS-$(CONFIG_CMD_NET) += tftp.o @@ -263,7 +263,6 @@ int eth_initialize(bd_t *bis) dev = dev->next; } while(dev != eth_devices); -#ifdef CONFIG_NET_MULTI /* update current ethernet name */ if (eth_current) { char *act = getenv("ethact"); @@ -271,7 +270,6 @@ int eth_initialize(bd_t *bis) setenv("ethact", eth_current->name); } else setenv("ethact", NULL); -#endif putc ('\n'); } @@ -441,7 +439,7 @@ int eth_receive(volatile void *packet, int length) void eth_try_another(int first_restart) { static struct eth_device *first_failed = NULL; - char *ethrotate; + char *ethrotate, *act; /* * Do not rotate between network interfaces when @@ -460,21 +458,16 @@ void eth_try_another(int first_restart) eth_current = eth_current->next; -#ifdef CONFIG_NET_MULTI /* update current ethernet name */ - { - char *act = getenv("ethact"); - if (act == NULL || strcmp(act, eth_current->name) != 0) - setenv("ethact", eth_current->name); - } -#endif + act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); if (first_failed == eth_current) { NetRestartWrap = 1; } } -#ifdef CONFIG_NET_MULTI void eth_set_current(void) { static char *act = NULL; @@ -501,7 +494,6 @@ void eth_set_current(void) setenv("ethact", eth_current->name); } -#endif char *eth_get_name (void) { @@ -80,7 +80,9 @@ #include <net.h> #include "bootp.h" #include "tftp.h" +#ifdef CONFIG_CMD_RARP #include "rarp.h" +#endif #include "nfs.h" #ifdef CONFIG_STATUS_LED #include <status_led.h> @@ -401,11 +403,13 @@ restart: BootpRequest (); break; +#if defined(CONFIG_CMD_RARP) case RARP: RarpTry = 0; NetOurIP = 0; RarpRequest (); break; +#endif #if defined(CONFIG_CMD_PING) case PING: PingStart(); @@ -1492,6 +1496,7 @@ NetReceive(volatile uchar * inpkt, int len) } break; +#ifdef CONFIG_CMD_RARP case PROT_RARP: debug("Got RARP\n"); arp = (ARP_t *)ip; @@ -1515,7 +1520,7 @@ NetReceive(volatile uchar * inpkt, int len) (*packetHandler)(0,0,0,0); } break; - +#endif case PROT_IP: debug("Got IP\n"); /* Before we start poking the header, make sure it is there */ @@ -1729,10 +1734,12 @@ static int net_check_prereq (proto_t protocol) } /* Fall through */ - case DHCP: +#ifdef CONFIG_CMD_RARP case RARP: +#endif case BOOTP: case CDP: + case DHCP: if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) { #ifdef CONFIG_NET_MULTI extern int eth_get_dev_index (void); |
