diff options
61 files changed, 2371 insertions, 906 deletions
@@ -511,6 +511,11 @@ N: Martin Winistoerfer E: martinwinistoerfer@gmx.ch D: Port to MPC555/556 microcontrollers and support for cmi board +N: David Wu +E: support@arcturusnetworks.com +D: Mercury Security EP2500 +W: http://www.arcturusnetworks.com + N: Ming-Len Wu E: minglen_wu@techware.com.tw D: Motorola MX1ADS board support diff --git a/MAINTAINERS b/MAINTAINERS index 0abeb26dcd..bb03f17784 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -889,6 +889,10 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com> M5475EVB mcf547x_8x M5485EVB mcf547x_8x +Wolfgang Wegner <w.wegner@astro-kom.de> + + astro_mcf5373l MCF5373L + ######################################################################### # AVR32 Systems: # # # @@ -839,6 +839,7 @@ LIST_microblaze=" \ ######################################################################### LIST_coldfire=" \ + astro_mcf5373l \ cobra5272 \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ @@ -1976,6 +1976,10 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +astro_mcf5373l_config \ +astro_mcf5373l_RAM_config : unconfig + @$(MKCONFIG) -t $(@:_config=) astro_mcf5373l m68k mcf532x mcf5373l astro + M5208EVBE_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale @@ -2044,6 +2048,9 @@ EB+MCF-EV123_internal_config : unconfig @echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS +EP2500_config: unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 ep2500 Mercury + idmr_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile new file mode 100644 index 0000000000..c7a1d05518 --- /dev/null +++ b/board/astro/mcf5373l/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h new file mode 100644 index 0000000000..b55a6f785c --- /dev/null +++ b/board/astro/mcf5373l/astro.h @@ -0,0 +1,44 @@ +#ifndef __ASTRO_H__ +#define __ASTRO_H__ + +/* in mcf5373l.c */ +int rs_serial_init(int port, int baud); +void astro_put_char(char ch); +int astro_is_char(void); +int astro_get_char(void); + +/* in fpga.c */ +int astro5373l_altera_load(void); +int astro5373l_xilinx_load(void); + +/* data structures used for communication (update.c) */ +typedef struct card_id { + char card_type; + char hardware_version; + char software_version; + char software_subversion; /* " ","a".."z" */ + char fpga_version_altera; + char fpga_version_xilinx; +} card_id_t; + +typedef struct { + unsigned char mode; + unsigned char deviation; + unsigned short freq; +} __attribute__ ((packed)) output_params_t; + +typedef struct { + unsigned short satfreq; + unsigned char satdatallg; + unsigned short symbolrate; + unsigned char viterbirate; + unsigned char symbolrate_l; + output_params_t output_params; + unsigned char reserve; + unsigned char card_error; + unsigned short dummy_ts_id; + unsigned char dummy_pat_ver; + unsigned char dummy_sdt_ver; +} __attribute__ ((packed)) parameters_t; + +#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/config.mk b/board/astro/mcf5373l/config.mk new file mode 100644 index 0000000000..6316a3029a --- /dev/null +++ b/board/astro/mcf5373l/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = $(CONFIG_TEXT_BASE) + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c new file mode 100644 index 0000000000..467461b8e8 --- /dev/null +++ b/board/astro/mcf5373l/fpga.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2006 + * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, + * w.wegner@astro-kom.de + * + * based on the files by + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * and + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ + +#include <common.h> +#include <watchdog.h> +#include <altera.h> +#include <ACEX1K.h> +#include <spartan3.h> +#include <command.h> +#include <asm/immap_5329.h> +#include <asm/io.h> +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int altera_pre_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + + /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ + writeb(0xFE, &gpiop->pclrr_timer); + writeb(0xDF, &gpiop->pclrr_qspi); + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int altera_config_fn(int assert_config, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_config) + writeb(0x04, &gpiop->ppd_uart); + else + writeb(0xFB, &gpiop->pclrr_uart); + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int altera_status_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x08) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int altera_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x20) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* + * writes the complete buffer to the FPGA + * writing the complete buffer in one function is much faster, + * then calling it for every bit + */ +int altera_write_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + while (bytecount < len) { + val = data[bytecount++]; + i = 8; + do { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x01) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val >>= 1; + i--; + } while (i > 0); + + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int altera_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + writeb(0x20, &gpiop->ppd_qspi); + writeb(0x08, &gpiop->ppd_uart); + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int altera_post_fn(int cookie) +{ + return altera_abort_fn(cookie); +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Altera_CYC2_Passive_Serial_fns altera_fns = { + altera_pre_fn, + altera_config_fn, + altera_status_fn, + altera_done_fn, + altera_write_fn, + altera_abort_fn, + altera_post_fn +}; + +Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + 85903, + (void *)&altera_fns, + NULL, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_altera_load(void) +{ + int i; + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + altera_fns.pre = altera_pre_fn; + altera_fns.config = altera_config_fn; + altera_fns.status = altera_status_fn; + altera_fns.done = altera_done_fn; + altera_fns.write = altera_write_fn; + altera_fns.abort = altera_abort_fn; + altera_fns.post = altera_post_fn; + altera_fpga[i].iface_fns = (void *)&altera_fns; + fpga_add(fpga_altera, &altera_fpga[i]); + } + return 1; +} + +/* Set the FPGA's PROG_B line to the specified level */ +int xilinx_pgm_fn(int assert, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert) + writeb(0xFB, &gpiop->pclrr_uart); + else + writeb(0x04, &gpiop->ppd_uart); + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int xilinx_init_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x08) == 0; +} + +/* Test the state of the active-high FPGA DONE pin */ +int xilinx_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; +} + +/* Abort an FPGA operation */ +int xilinx_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + /* ensure all SPI peripherals and FPGAs are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x01, &gpiop->ppd_timer); + writeb(0x38, &gpiop->ppd_qspi); + return FPGA_FAIL; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int xilinx_pre_config_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + writeb(0x01, &gpiop->ppd_timer); + + /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ + writeb(0xF7, &gpiop->pclrr_uart); + writeb(0xDF, &gpiop->pclrr_qspi); + return 0; +} + +/* + * FPGA post configuration function. Should perform a test if FPGA is running. + */ +int xilinx_post_config_fn(int cookie) +{ + int rc = 0; + + /* + * no test yet + */ + return rc; +} + +int xilinx_clk_fn(int assert_clk, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_clk) + writeb(0x04, &gpiop->ppd_qspi); + else + writeb(0xFB, &gpiop->pclrr_qspi); + return assert_clk; +} + +int xilinx_wr_fn(int assert_write, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_write) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + return assert_write; +} + +int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + for (bytecount = 0; bytecount < len; bytecount++) { + val = *(data++); + for (i = 8; i > 0; i--) { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x80) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val <<= 1; + } + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { + xilinx_pre_config_fn, + xilinx_pgm_fn, + xilinx_clk_fn, + xilinx_init_fn, + xilinx_done_fn, + xilinx_wr_fn, + 0, + xilinx_fastwr_fn +}; + +Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_serial, + XILINX_XC3S4000_SIZE, + (void *)&xilinx_fns, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_xilinx_load(void) +{ + int i; + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + xilinx_fns.pre = xilinx_pre_config_fn; + xilinx_fns.pgm = xilinx_pgm_fn; + xilinx_fns.clk = xilinx_clk_fn; + xilinx_fns.init = xilinx_init_fn; + xilinx_fns.done = xilinx_done_fn; + xilinx_fns.wr = xilinx_wr_fn; + xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; + fpga_add(fpga_xilinx, &xilinx_fpga[i]); + } + return 1; +} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c new file mode 100644 index 0000000000..3c09a21eed --- /dev/null +++ b/board/astro/mcf5373l/mcf5373l.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/m5329.h> +#include <asm/immap_5329.h> +#include <asm/io.h> + +/* needed for astro bus: */ +#include <asm/uart.h> +#include "astro.h" + +DECLARE_GLOBAL_DATA_PTR; +extern void uart_port_conf(void); + +int checkboard(void) +{ + puts("Board: "); + puts("ASTRO MCF5373L (Urmel) Board\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); + + /* + * GPIO configuration for bus should be set correctly from reset, + * so we do not care! First, set up address space: at this point, + * we should be running from internal SRAM; + * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * and do not care where it is + */ + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + &sdp->cs0); + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + &sdp->cs1); + /* + * I am not sure from the data sheet, but it seems burst length + * has to be 8 for the 16 bit data bus we use; + * so these values are for BL = 8 + */ + __raw_writel(0x33211530, &sdp->cfg1); + __raw_writel(0x56570000, &sdp->cfg2); + /* send PrechargeALL, REF and IREF remain cleared! */ + __raw_writel(0xE1462C02, &sdp->ctrl); + udelay(1); + /* refresh SDRAM twice */ + __raw_writel(0xE1462C04, &sdp->ctrl); + udelay(1); + __raw_writel(0xE1462C04, &sdp->ctrl); + /* init MR */ + __raw_writel(0x008D0000, &sdp->mode); + /* initialize EMR */ + __raw_writel(0x80010000, &sdp->mode); + /* wait until DLL is locked */ + udelay(1); + /* + * enable automatic refresh, lock mode register, + * clear iref and ipall + */ + __raw_writel(0x71462C00, &sdp->ctrl); + /* Dummy write to start SDRAM */ + writel(0, CONFIG_SYS_SDRAM_BASE); +#endif + + /* + * for get_ram_size() to work, both CS areas have to be + * configured, i.e. CS1 has to be explicitely disabled, else + * probing for memory will cause the SDRAM bus to hang! + * (Do not rely on the SDCS register(s) being set to 0x00000000 + * during reset as stated in the data sheet.) + */ + return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + 0x80000000 - CONFIG_SYS_SDRAM_BASE); +} + +#define UART_BASE MMAP_UART0 +int rs_serial_init(int port, int baud) +{ + uart_t *uart; + u32 counter; + + switch (port) { + case 0: + uart = (uart_t *)(MMAP_UART0); + break; + case 1: + uart = (uart_t *)(MMAP_UART1); + break; + case 2: + uart = (uart_t *)(MMAP_UART2); + break; + default: + uart = (uart_t *)(MMAP_UART0); + } + + uart_port_conf(); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + writeb(UART_UCR_RESET_RX, &uart->ucr); + writeb(UART_UCR_RESET_TX, &uart->ucr); + writeb(UART_UCR_RESET_ERROR, &uart->ucr); + writeb(UART_UCR_RESET_MR, &uart->ucr); + __asm__ ("nop"); + + writeb(0, &uart->uimr); + + /* write to CSR: RX/TX baud rate from timers */ + writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); + + writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); + writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (baud)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); + /* write to CTLR: divide counter lower byte */ + writeb((u8) (counter & 0x00ff), &uart->ubg2); + + writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); + + return 0; +} + +void astro_put_char(char ch) +{ + uart_t *uart; + unsigned long timer; + + uart = (uart_t *)(MMAP_UART0); + /* + * Wait for last character to go. Timeout of 6ms should + * be enough for our lowest baud rate of 2400. + */ + timer = get_timer(0); + while (get_timer(timer) < 6) { + if (readb(&uart->usr) & UART_USR_TXRDY) + break; + } + writeb(ch, &uart->utb); + + return; +} + +int astro_is_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + return readb(&uart->usr) & UART_USR_RXRDY; +} + +int astro_get_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; + return readb(&uart->urb); +} + +int misc_init_r(void) +{ + int retval = 0; + + puts("Configure Xilinx FPGA..."); + retval = astro5373l_xilinx_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + puts("Configure Altera FPGA..."); + retval = astro5373l_altera_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + return retval; +} diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds new file mode 100644 index 0000000000..a9a4e0a233 --- /dev/null +++ b/board/astro/mcf5373l/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) +/* *(.fixup)*/ + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c index 5505cc42c6..446f102e58 100644 --- a/board/freescale/m5271evb/m5271evb.c +++ b/board/freescale/m5271evb/m5271evb.c @@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) { MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | MCF_GPIO_SDRAM_SDCS_11); + asm(" nop"); /* * Check to see if the SDRAM has already been initialized @@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) { if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { /* Initialize DRAM Control Register: DCR */ mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x01) - | MCF_SDRAMC_DCR_RC(0x30)); + MCF_SDRAMC_DCR_RTIM(2) + | MCF_SDRAMC_DCR_RC(0x2E)); + asm(" nop"); /* * Initialize DACR0 @@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) { | MCF_SDRAMC_DACRn_CASL(1) | MCF_SDRAMC_DACRn_CBM(3) | MCF_SDRAMC_DACRn_PS(0)); + asm(" nop"); /* Initialize DMR0 */ mbar_writeLong(MCF_SDRAMC_DMR0, MCF_SDRAMC_DMRn_BAM_16M | MCF_SDRAMC_DMRn_V); + asm(" nop"); /* Set IP bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_IP); + asm(" nop"); /* Wait at least 20ns to allow banks to precharge */ for (i = 0; i < 5; i++) @@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) { /* Write to this block to initiate precharge */ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + asm(" nop"); /* Set RE bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) @@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) { /* Finish the configuration by issuing the MRS */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_MRS); + asm(" nop"); /* * Write to the SDRAM Mode Register A0-A11 = 0x400 @@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) { * Burst Length = 1 */ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + asm(" nop"); } return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 293b5b0e41..2a84514a3d 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -107,7 +107,7 @@ int ide_preinit(void) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; gpio->par_feci2c |= (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); @@ -185,7 +185,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->flash_id = 0x01000000; info->portwidth = 1; info->chipwidth = 1; - info->buffer_size = 32; + info->buffer_size = 1; info->erase_blk_tout = 16384; info->write_tout = 2; info->buffer_write_tout = 5; diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index f8400bcc04..d22eb6634a 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; static void print_num(const char *, ulong); -#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET) +#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET) static void print_eth(int idx); #endif @@ -350,7 +350,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET) +#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET) static void print_eth(int idx) { char name[10], *val; diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index e160ee1aff..beb78f5839 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -125,27 +125,27 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); + (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); + (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); break; case 2: gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); + (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); gpio->par_dspi = (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); break; @@ -175,11 +175,11 @@ int cfspi_claim_bus(uint bus, uint cs) switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK; + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; break; } @@ -199,7 +199,7 @@ void cfspi_release_bus(uint bus, uint cs) gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; break; } } diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 0c9c89c402..30428f15d8 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - #define _START _start #define _FAULT _fault @@ -378,21 +374,19 @@ _start: movec %d0, %RAMBAR1 #endif + /* invalidate and disable cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + /* initialize general use internal ram */ move.l #0, %d0 move.l #(ICACHE_STATUS), %a1 /* icache */ move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ @@ -510,84 +504,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR0 - - move.l #0x81600610, %d0 /* Enable cache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01F00000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600610, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #0x81300610, %d0 - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0x81600610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #0x81100610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index 3c04fd4134..0f299f0c3c 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -130,21 +130,32 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); break; case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + gpio->par_uart &= + ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); break; case 2: - gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + gpio->feci2c |= + (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); +#endif break; } } @@ -156,7 +167,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear) if (setclear) { gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + (GPIO_PAR_FECI2C_EMDC_FECEMDC | + GPIO_PAR_FECI2C_EMDIO_FECEMDIO); } else { gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index d44da37ec7..20b50e7579 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -24,6 +24,7 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -135,7 +136,7 @@ _start: movec %d0, %RAMBAR1 /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ nop move.l #0, %d0 @@ -144,8 +145,8 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ move.l %d0, (%a1) move.l %d0, (%a2) @@ -265,74 +266,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - nop - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 7cea6558fd..170bbfc356 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -5,6 +5,8 @@ * MCF5282 additionals * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> + * (c) Copyright 2010 + * Arcturus Networks Inc. <www.arcturusnetworks.com> * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) @@ -133,36 +135,36 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: - gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO gpio->par_timer &= - (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK); + (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK); gpio->par_timer |= (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_feci2c &= - (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK); + (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_feci2c &= - (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif @@ -182,8 +184,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear) GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; } else { gpio->par_fec &= - (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK; + (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK; } return 0; } @@ -245,15 +247,19 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { + volatile u32 *par = (u32 *) MMAP_PAR; + /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; + switch (port) { case 1: + *par &= 0xFFE7FFFF; + *par |= 0x00180000; break; case 2: + *par &= 0xFFFFFFFC; + *par &= 0x00000003; break; } } @@ -289,21 +295,26 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { + u16 temp; + /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; + temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; case 1: - mbar_writeShort(MCF_GPIO_PAR_UART, - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; + temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; case 2: - mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; + temp |= (0x3000); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; } } @@ -407,12 +418,12 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); @@ -485,19 +496,22 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: + gpio->par_uart &= ~UART0_ENABLE_MASK; gpio->par_uart |= UART0_ENABLE_MASK; break; case 1: + gpio->par_uart &= ~UART1_ENABLE_MASK; gpio->par_uart |= UART1_ENABLE_MASK; break; case 2: + gpio->par_uart &= ~UART2_ENABLE_MASK; gpio->par_uart |= UART2_ENABLE_MASK; break; } @@ -582,6 +596,12 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTCPAR MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; #endif +#if defined(CONFIG_SYS_PORTTC) + MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; +#endif +#if defined(CONFIG_SYS_DDRTC) + MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; +#endif #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif @@ -589,6 +609,9 @@ void cpu_init_f(void) MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; #endif +#if defined(CONFIG_SYS_DDRD) + MCFGPIO_DDRD = CONFIG_SYS_DDRD; +#endif #ifdef CONFIG_SYS_DDRUA MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; #endif @@ -610,10 +633,10 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: MCFGPIO_PUAPAR &= 0xFc; MCFGPIO_PUAPAR |= 0x03; @@ -718,14 +741,7 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; - case 1: - break; - } } #endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 0dd4de5160..9ef206aa0f 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -24,12 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif - #define _START _start #define _FAULT _fault @@ -201,6 +201,13 @@ _after_flashbar_copy: movec %d0, %RAMBAR1 #endif + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- @@ -283,23 +290,6 @@ clear_bss: cmp.l %a2, %a1 bne 7b -#if defined(CONFIG_M5281) || defined(CONFIG_M5282) - /* patch the 3 accesspoints to 3 ichache_state */ - /* quick and dirty */ - - move.l %a0,%d1 - add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1 - move.l %a0,%a1 - add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) -#endif - /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 @@ -336,156 +326,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ -#ifdef CONFIG_M5208 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5271 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5272 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5275) -/* - * Instruction cache only - */ - .globl icache_enable -icache_enable: - move.l #0x01400000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup SDRAM caching */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0x00000000, %d0 /* No other caching */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#ifdef CONFIG_M5282 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 -icache_state_access_1: - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) - .globl icache_enable -icache_enable: - /* - * Note: The 5249 Documentation doesn't give a bit position for CINV! - * From the 5272 and the 5307 documentation, I have deduced that it is - * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy - */ - move.l #0x01000000, %d0 /* Invalidate whole cache */ - move.c %d0,%CACR - move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ - move.c %d0, %ACR0 - move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ - move.c %d0, %ACR1 - move.l #0x90000200, %d0 /* Set cache enable cmd */ - move.c %d0,%CACR - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ - moveq #0, %d0 -icache_state_access_2: - move.l %d0, icache_state - rts - - .globl icache_status -icache_status: -icache_state_access_3: - move.l #(icache_state), %a0 - move.l (%a0), %d0 - rts - - .data -icache_state: - .long 0 /* cache is diabled on inirialization */ - - .globl dcache_enable -dcache_enable: - /* dummy function */ - rts - - .globl dcache_disable -dcache_disable: - /* dummy function */ - rts - - .globl dcache_status -dcache_status: - /* dummy function */ - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk index 0cb90ac4e2..b783444ae8 100644 --- a/cpu/mcf532x/config.mk +++ b/cpu/mcf532x/config.mk @@ -24,8 +24,20 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg)) + ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) + +ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) +PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC +endif +ifneq (,$(findstring CONFIG_MCF532x,$(is532x))) PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC +endif + else PLATFORM_CPPFLAGS += -m5307 -fPIC endif diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 4f1695cef8..6f551b60c9 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -133,24 +133,26 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_ALT1_GPIO gpio->par_simp1h &= - ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK); + ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | + GPIO_PAR_SIMP1H_VEN1_UNMASK); gpio->par_simp1h |= (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) gpio->par_ssih &= - ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK); + ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); gpio->par_ssih |= (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); #endif @@ -160,12 +162,12 @@ void uart_port_conf(void) gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) gpio->par_dspih &= - ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK); + ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); gpio->par_dspih |= (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif @@ -195,11 +197,11 @@ int fecpin_setclear(struct eth_device *dev, int setclear) if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { gpio->par_fec &= ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK; + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; } else { gpio->par_fec &= ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK; + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; } } return 0; @@ -297,22 +299,33 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); break; case 1: - gpio->par_uart = + gpio->par_uart &= + ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + gpio->par_uart |= (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); break; case 2: +#ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_timer &= 0x0F; gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_feci2c &= 0xFF00; + gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); +#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) + gpio->par_ssi &= 0xF0FF; + gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); +#endif break; } } diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index 67f08c7602..5a29e2567a 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -229,7 +229,7 @@ int clock_pll(int fsys, int flags) PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | PLL_PDR_OUTDIV4(USBDIV - 1); - pll->pcr &= PLL_PCR_FBDIV_MASK; + pll->pcr &= PLL_PCR_FBDIV_UNMASK; pll->pcr |= PLL_PCR_FBDIV(mfd - 1); #endif #ifdef CONFIG_MCF532x diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 5b134aa47c..a80b0a9946 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -27,6 +27,7 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -142,7 +143,7 @@ _start: movec %d0, %RAMBAR1 /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ + move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -158,8 +159,8 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ move.l %d0, (%a1) move.l %d0, (%a2) @@ -279,71 +280,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x81000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - .globl version_string version_string: .ascii U_BOOT_VERSION diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 48b37dfe7d..8d51d35d68 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/processor.h> #include <asm/rtc.h> #if defined(CONFIG_CMD_NET) @@ -105,6 +106,14 @@ void cpu_init_f(void) fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif + /* + * now the flash base address is no longer at 0 (Newer ColdFire family + * boot at address 0 instead of 0xFFnn_nnnn). The vector table must + * also move to the new location. + */ + if (CONFIG_SYS_CS0_BASE != 0) + setvbr(CONFIG_SYS_CS0_BASE); + #ifdef CONFIG_FSL_I2C gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; #endif @@ -128,19 +137,43 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = + gpio->par_uart &= + ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + gpio->par_uart |= (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: - gpio->par_uart = +#ifdef CONFIG_SYS_UART1_PRI_GPIO + gpio->par_uart &= + ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + gpio->par_uart |= (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); +#elif defined(CONFIG_SYS_UART1_ALT1_GPIO) + gpio->par_ssi &= + (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); + gpio->par_ssi |= + (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); +#endif + break; + case 2: +#if defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->par_timer &= + (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); + gpio->par_timer |= + (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_timer &= + (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); + gpio->par_timer |= + (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); +#endif break; } } @@ -164,9 +197,9 @@ int fecpin_setclear(struct eth_device *dev, int setclear) ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; } return 0; } diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d2d4439151..738e4a7110 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) - #define _START _start #define _FAULT _fault @@ -160,15 +156,13 @@ asm_dram_init: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -411,15 +405,13 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -544,107 +536,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */ - movec %d0, %ACR2 - - move.l #0x04088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0xFFF77BFF, %d0 - or.l #0x00040100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x01040100, %d0 - movec %d0, %CACR /* Invalidate dcache */ - - move.l #0x80088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - and.l #0x7FFFFFFF, %d0 - or.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable dcache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x81088020, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c index 96a3132b78..60c91267a7 100644 --- a/cpu/mcf547x_8x/cpu_init.c +++ b/cpu/mcf547x_8x/cpu_init.c @@ -113,13 +113,13 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index 94ef14bf3d..84118629e2 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - #define _START _start #define _FAULT _fault @@ -158,10 +154,8 @@ _start: move.l #0, %d0 move.l #(ICACHE_STATUS), %a1 /* icache */ move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ @@ -279,81 +273,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR2 /* Enable cache */ - - move.l #0x020C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_invalid -icache_invalid: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl dcache_enable -dcache_enable: - bsr icache_disable - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0xA30C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 0fe30410a6..7a89b5692c 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } while ((*fn->init) (cookie)); /* Load the data */ - while (bytecount < bsize) { - - /* Xilinx detects an error if INIT goes low (active) - while DONE is low (inactive) */ - if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { - puts ("** CRC error during FPGA load.\n"); - return (FPGA_FAIL); - } - val = data [bytecount ++]; - i = 8; - do { - /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - val <<= 1; - i --; - } while (i > 0); + if(*fn->bwr) + (*fn->bwr) (data, bsize, TRUE, cookie); + else { + while (bytecount < bsize) { + + /* Xilinx detects an error if INIT goes low (active) + while DONE is low (inactive) */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + return (FPGA_FAIL); + } + val = data [bytecount ++]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->wr) ((val & 0x80), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val <<= 1; + i --; + } while (i > 0); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); /* let them know we are alive */ + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ #endif + } } CONFIG_FPGA_DELAY (); diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 0b531402e4..d93b24b897 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); +extern void uart_port_conf(int port); int serial_init(void) { @@ -43,7 +43,7 @@ int serial_init(void) uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); - uart_port_conf(); + uart_port_conf(CONFIG_SYS_UART_PORT); /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ uart->ucr = UART_UCR_RESET_RX; diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h new file mode 100644 index 0000000000..7c84e48471 --- /dev/null +++ b/include/asm-m68k/cache.h @@ -0,0 +1,210 @@ +/* + * ColdFire cache + * + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CACHE_H +#define __CACHE_H + +#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ + defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) +#define CONFIG_CF_V2 +#endif + +#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#define CONFIG_CF_V3 +#endif + +#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) +#define CONFIG_CF_V4 +#if defined(CONFIG_MCF5441x) +#define CONFIG_CF_V4E /* Four Extra ACRn */ +#endif +#endif + +/* ***** CACR ***** */ +/* V2 Core */ +#ifdef CONFIG_CF_V2 + +#define CF_CACR_CENB (1 << 31) +#define CF_CACR_CPD (1 << 28) +#define CF_CACR_CFRZ (1 << 27) +#define CF_CACR_CEIB (1 << 10) +#define CF_CACR_DCM (1 << 9) +#define CF_CACR_DBWE (1 << 8) + +#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) +#define CF_CACR_DWP (1 << 6) +#else +#define CF_CACR_CINV (1 << 24) +#define CF_CACR_DISI (1 << 23) +#define CF_CACR_DISD (1 << 22) +#define CF_CACR_INVI (1 << 21) +#define CF_CACR_INVD (1 << 20) +#define CF_CACR_DWP (1 << 5) +#define CF_CACR_EUSP (1 << 4) +#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ + +#endif /* CONFIG_CF_V2 */ + +/* V3 Core */ +#ifdef CONFIG_CF_V3 + +#define CF_CACR_EC (1 << 31) +#define CF_CACR_ESB (1 << 29) +#define CF_CACR_DPI (1 << 28) +#define CF_CACR_HLCK (1 << 27) +#define CF_CACR_CINVA (1 << 24) +#define CF_CACR_DNFB (1 << 10) +#define CF_CACR_DCM_UNMASK 0xFFFFFCFF +#define CF_CACR_DCM_WT (0 << 8) +#define CF_CACR_DCM_CB (1 << 8) +#define CF_CACR_DCM_P (2 << 8) +#define CF_CACR_DCM_IP (3 << 8) +#define CF_CACR_DW (1 << 5) +#define CF_CACR_EUSP (1 << 4) + +#endif /* CONFIG_CF_V3 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 + +#define CF_CACR_DEC (1 << 31) +#define CF_CACR_DW (1 << 30) +#define CF_CACR_DESB (1 << 29) +#define CF_CACR_DDPI (1 << 28) +#define CF_CACR_DHLCK (1 << 27) +#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) +#define CF_CACR_DDCM_WT (0 << 25) +#define CF_CACR_DDCM_CB (1 << 25) +#define CF_CACR_DDCM_P (2 << 25) +#define CF_CACR_DDCM_IP (3 << 25) +#define CF_CACR_DCINVA (1 << 24) + +#define CF_CACR_DDSP (1 << 23) +#define CF_CACR_BEC (1 << 19) +#define CF_CACR_BCINVA (1 << 18) +#define CF_CACR_IEC (1 << 15) +#define CF_CACR_DNFB (1 << 13) +#define CF_CACR_IDPI (1 << 12) +#define CF_CACR_IHLCK (1 << 11) +#define CF_CACR_IDCM (1 << 10) +#define CF_CACR_ICINVA (1 << 8) +#define CF_CACR_IDSP (1 << 7) +#define CF_CACR_EUSP (1 << 5) + +#ifdef CONFIG_MCF5445x +#define CF_CACR_IVO (1 << 20) +#define CF_CACR_SPA (1 << 14) +#else +#define CF_CACR_DF (1 << 4) +#endif + +#endif /* CONFIG_CF_V4 */ + +/* ***** ACR ***** */ +#define CF_ACR_ADR_UNMASK (0x00FFFFFF) +#define CF_ACR_ADR(x) ((x & 0xFF) << 24) +#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) +#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) +#define CF_ACR_EN (1 << 15) +#define CF_ACR_SM_UNMASK (0xFFFF9FFF) +#define CF_ACR_SM_UM (0 << 13) +#define CF_ACR_SM_SM (1 << 13) +#define CF_ACR_SM_ALL (3 << 13) +#define CF_ACR_WP (1 << 2) + +/* V2 Core */ +#ifdef CONFIG_CF_V2 +#define CF_ACR_CM (1 << 6) +#define CF_ACR_BWE (1 << 5) +#else +/* V3 & V4 */ +#define CF_ACR_CM_UNMASK (0xFFFFFF9F) +#define CF_ACR_CM_WT (0 << 5) +#define CF_ACR_CM_CB (1 << 5) +#define CF_ACR_CM_P (2 << 5) +#define CF_ACR_CM_IP (3 << 5) +#endif /* CONFIG_CF_V2 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 +#define CF_ACR_AMM (1 << 10) +#define CF_ACR_SP (1 << 3) +#endif /* CONFIG_CF_V4 */ + + +#ifndef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_ICACR 0 +#endif + +#ifndef CONFIG_SYS_CACHE_DCACR +#ifdef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#else +#define CONFIG_SYS_CACHE_DCACR 0 +#endif +#endif + +#ifndef CONFIG_SYS_CACHE_ACR0 +#define CONFIG_SYS_CACHE_ACR0 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR1 +#define CONFIG_SYS_CACHE_ACR1 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR2 +#define CONFIG_SYS_CACHE_ACR2 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR3 +#define CONFIG_SYS_CACHE_ACR3 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR4 +#define CONFIG_SYS_CACHE_ACR4 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR5 +#define CONFIG_SYS_CACHE_ACR5 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR6 +#define CONFIG_SYS_CACHE_ACR6 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR7 +#define CONFIG_SYS_CACHE_ACR7 0 +#endif + +#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ + +void icache_invalid(void); +void dcache_invalid(void); + +#endif + +#endif /* __CACHE_H */ diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h index b5a4cb54a7..28cd107a82 100644 --- a/include/asm-m68k/immap_5253.h +++ b/include/asm-m68k/immap_5253.h @@ -37,6 +37,7 @@ #define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) #define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) #define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h index 267bfd994a..71f147e751 100644 --- a/include/asm-m68k/m520x.h +++ b/include/asm-m68k/m520x.h @@ -70,7 +70,6 @@ #define PACR_TP 1 #define SCM_BMT_BME (0x00000008) -#define SCM_BMT_BMT_MASK (0x07) #define SCM_BMT_BMT(x) ((x) & 0x07) #define SCM_BMT_BMT1024 (0x0000) #define SCM_BMT_BMT512 (0x0001) @@ -179,7 +178,7 @@ #define CCM_CCR_PLL_MODE (0x0002) #define CCM_CCR_RESERVED (0x0001) -#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) #define CCM_CIR_PRN(x) ((x) & 0x003F) /* *** General Purpose I/O (GPIO) *** */ @@ -196,7 +195,7 @@ #define GPIO_PAR_FBCTL_OE (0x10) #define GPIO_PAR_FBCTL_TA (0x08) #define GPIO_PAR_FBCTL_RWB (0x04) -#define GPIO_PAR_FBCTL_TS_MASK (0xFC) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC) #define GPIO_PAR_FBCTL_TS_TS (0x03) #define GPIO_PAR_FBCTL_TS_DMA (0x02) @@ -207,39 +206,39 @@ #define GPIO_PAR_CS3 (0x08) #define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS1_MASK (0xFC) +#define GPIO_PAR_CS1_UNMASK (0xFC) #define GPIO_PAR_CS1_CS1 (0x03) #define GPIO_PAR_CS1_SDCS1 (0x02) -#define GPIO_PAR_FECI2C_RMII_MASK (0x0F) -#define GPIO_PAR_FECI2C_MDC_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F) +#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC_MDC (0xC0) #define GPIO_PAR_FECI2C_MDC_SCL (0x80) #define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) +#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) #define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_I2C_MASK (0xF0) -#define GPIO_PAR_FECI2C_SCL_MASK (0xF3) +#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x03) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) -#define GPIO_PAR_QSPI_PCS2_MASK (0x3F) +#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F) #define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) #define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) #define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) -#define GPIO_PAR_QSPI_DIN_MASK (0xCF) +#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF) #define GPIO_PAR_QSPI_DIN_DIN (0x30) #define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) #define GPIO_PAR_QSPI_DIN_U2CTS (0x10) -#define GPIO_PAR_QSPI_DOUT_MASK (0xF3) +#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3) #define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) #define GPIO_PAR_QSPI_DOUT_SDA (0x08) -#define GPIO_PAR_QSPI_SCK_MASK (0xFC) +#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_QSPI_SCK_SCK (0x03) #define GPIO_PAR_QSPI_SCK_SCL (0x02) @@ -247,50 +246,50 @@ #define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TMR_TIN3_MASK (0x3F) +#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TMR_TIN3_U2CTS (0x40) -#define GPIO_PAR_TMR_TIN2_MASK (0xCF) +#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TMR_TIN2_TIN2 (0x30) #define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TMR_TIN2_U2RTS (0x10) -#define GPIO_PAR_TMR_TIN1_MASK (0xF3) +#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TMR_TIN1_U2RXD (0x04) -#define GPIO_PAR_TMR_TIN0_MASK (0xFC) +#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TMR_TIN0_TIN0 (0x03) #define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TMR_TIN0_U2TXD (0x01) -#define GPIO_PAR_UART1_MASK (0xF03F) -#define GPIO_PAR_UART0_MASK (0xFFC0) -#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) +#define GPIO_PAR_UART1_UNMASK (0xF03F) +#define GPIO_PAR_UART0_UNMASK (0xFFC0) +#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) #define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) #define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) -#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) #define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) #define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) #define GPIO_PAR_UART_U1TXD (0x0080) #define GPIO_PAR_UART_U1RXD (0x0040) -#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) #define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) #define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) #define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) #define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) #define GPIO_PAR_UART_U0TXD (0x0002) #define GPIO_PAR_UART_U0RXD (0x0001) -#define GPIO_PAR_FEC_7W_MASK (0xF3) +#define GPIO_PAR_FEC_7W_UNMASK (0xF3) #define GPIO_PAR_FEC_7W_FEC (0x0C) #define GPIO_PAR_FEC_7W_U1RTS (0x04) -#define GPIO_PAR_FEC_MII_MASK (0xFC) +#define GPIO_PAR_FEC_MII_UNMASK (0xFC) #define GPIO_PAR_FEC_MII_FEC (0x03) #define GPIO_PAR_FEC_MII_UnCTS (0x01) @@ -300,17 +299,17 @@ #define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) #define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) #define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) -#define GPIO_MSCR_FB_FBCLK_MASK (0x3F) -#define GPIO_MSCR_FB_DUP_MASK (0xCF) -#define GPIO_MSCR_FB_DLO_MASK (0xF3) -#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F) +#define GPIO_MSCR_FB_DUP_UNMASK (0xCF) +#define GPIO_MSCR_FB_DLO_UNMASK (0xF3) +#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC) #define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) #define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) #define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) -#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) -#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) +#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF) +#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC) #define MSCR_25VDDR (0x03) #define MSCR_18VDDR_FULL (0x02) @@ -318,27 +317,27 @@ #define MSCR_18VDDR_HALF (0x00) #define GPIO_DSCR_I2C(x) ((x) & 0x03) -#define GPIO_DSCR_I2C_MASK (0xFC) +#define GPIO_DSCR_I2C_UNMASK (0xFC) #define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_MISC_DBG_MASK (0xCF) +#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF) #define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) +#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3) #define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) -#define GPIO_DSCR_MISC_TIMER_MASK (0xFC) +#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC) #define GPIO_DSCR_FEC(x) ((x) & 0x03) -#define GPIO_DSCR_FEC_MASK (0xFC) +#define GPIO_DSCR_FEC_UNMASK (0xFC) #define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_UART_UART1_MASK (0xCF) +#define GPIO_DSCR_UART_UART1_UNMASK (0xCF) #define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_UART_UART0_MASK (0xF3) +#define GPIO_DSCR_UART_UART0_UNMASK (0xF3) #define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) -#define GPIO_DSCR_UART_IRQ_MASK (0xFC) +#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC) #define GPIO_DSCR_QSPI(x) ((x) & 0x03) -#define GPIO_DSCR_QSPI_MASK (0xFC) +#define GPIO_DSCR_QSPI_UNMASK (0xFC) #define DSCR_50PF (0x03) #define DSCR_30PF (0x02) @@ -347,12 +346,12 @@ /* *** Phase Locked Loop (PLL) *** */ #define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) -#define PLL_PODR_CPUDIV_MASK (0x0F) +#define PLL_PODR_CPUDIV_UNMASK (0x0F) #define PLL_PODR_BUSDIV(x) ((x) & 0x0F) -#define PLL_PODR_BUSDIV_MASK (0xF0) +#define PLL_PODR_BUSDIV_UNMASK (0xF0) #define PLL_PCR_DITHEN (0x80) #define PLL_PCR_DITHDEV(x) ((x) & 0x07) -#define PLL_PCR_DITHDEV_MASK (0xF8) +#define PLL_PCR_DITHDEV_UNMASK (0xF8) #endif /* __M520X__ */ diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h index 824d333114..c77d5dd657 100644 --- a/include/asm-m68k/m5227x.h +++ b/include/asm-m68k/m5227x.h @@ -117,36 +117,34 @@ /* Bit definitions and macros for CCR */ #define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_MASK (0xFF3F) +#define CCM_CCR_CSC_UNMASK (0xFF3F) #define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) #define CCM_CCR_CSC_FBCS5_A22 (0x0080) #define CCM_CCR_CSC_FB_A23_A22 (0x0040) #define CCM_CCR_LIMP (0x0020) #define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_MASK (0xFFF3) +#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) #define CCM_CCR_BOOTPS_PS16 (0x0008) #define CCM_CCR_BOOTPS_PS8 (0x0004) #define CCM_CCR_BOOTPS_PS32 (0x0000) #define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_MASK (0xFF3F) +#define CCM_RCON_CSC_UNMASK (0xFF3F) #define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) #define CCM_RCON_CSC_FBCS5_A22 (0x0080) #define CCM_RCON_CSC_FB_A23_A22 (0x0040) #define CCM_RCON_LIMP (0x0020) #define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_MASK (0xFFF3) +#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) #define CCM_RCON_BOOTPS_PS16 (0x0008) #define CCM_RCON_BOOTPS_PS8 (0x0004) #define CCM_RCON_BOOTPS_PS32 (0x0000) #define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) #define CCM_CIR_PIN_MCF52277 (0x0000) /* Bit definitions and macros for MISCCR */ @@ -195,7 +193,7 @@ * General Purpose I/O Module (GPIO) *********************************************************************/ /* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_MASK (0x0F) +#define GPIO_PAR_BE_UNMASK (0x0F) #define GPIO_PAR_BE_BE3_BE3 (0x08) #define GPIO_PAR_BE_BE3_GPIO (0x00) #define GPIO_PAR_BE_BE2_BE2 (0x04) @@ -217,111 +215,111 @@ #define GPIO_PAR_FBCTL_OE (0x80) #define GPIO_PAR_FBCTL_TA (0x40) #define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_FBTS (0x18) #define GPIO_PAR_FBCTL_TS_DMAACK (0x10) #define GPIO_PAR_FBCTL_TS_GPIO (0x00) /* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_MASK (0xF3) +#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) #define GPIO_PAR_I2C_SCL_SCL (0x0C) #define GPIO_PAR_I2C_SCL_CANTXD (0x08) #define GPIO_PAR_I2C_SCL_U2TXD (0x04) #define GPIO_PAR_I2C_SCL_GPIO (0x00) -#define GPIO_PAR_I2C_SDA_MASK (0xFC) +#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) #define GPIO_PAR_I2C_SDA_SDA (0x03) #define GPIO_PAR_I2C_SDA_CANRXD (0x02) #define GPIO_PAR_I2C_SDA_U2RXD (0x01) #define GPIO_PAR_I2C_SDA_GPIO (0x00) /* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF) +#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) #define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) #define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) #define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) #define GPIO_PAR_UART_U1CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) #define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) #define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) #define GPIO_PAR_UART_U1RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF) +#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) #define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) #define GPIO_PAR_UART_U1RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF) +#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) #define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) #define GPIO_PAR_UART_U1TXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) #define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) #define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) #define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) #define GPIO_PAR_UART_U0CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) #define GPIO_PAR_UART_U0RTS_T1IN (0x0020) #define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) #define GPIO_PAR_UART_U0RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) #define GPIO_PAR_UART_U0RXD_CANRX (0x0008) #define GPIO_PAR_UART_U0RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC) +#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) #define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) #define GPIO_PAR_UART_U0TXD_CANTX (0x0002) #define GPIO_PAR_UART_U0TXD_GPIO (0x0000) /* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_MASK (0x3F) +#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) #define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) #define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_MASK (0xCF) +#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) #define GPIO_PAR_DSPI_SIN_SIN (0x30) #define GPIO_PAR_DSPI_SIN_U2RXD (0x20) #define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_MASK (0xF3) +#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) #define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) #define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_MASK (0xFC) +#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_DSPI_SCK_SCK (0x03) #define GPIO_PAR_DSPI_SCK_U2CTS (0x02) #define GPIO_PAR_DSPI_SCK_GPIO (0x00) /* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7) +#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) #define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) #define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) @@ -330,141 +328,141 @@ #define GPIO_PAR_LCDCTL_LSCLK (0x01) /* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3) +#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) #define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC) +#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) #define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) #define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) #define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) #define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) #define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) #define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) #define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F) +#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) #define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) #define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) #define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF) +#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) #define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) #define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) #define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3) +#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) #define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) #define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) #define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC) +#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) #define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) #define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) #define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) /* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF) +#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) #define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) #define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) #define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF) +#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) #define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) #define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) #define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF) +#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) #define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) #define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) #define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF) +#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) #define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) #define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) #define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF) +#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) #define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) #define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) #define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF) +#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) #define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) #define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) #define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF) +#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) #define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) #define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) #define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF) +#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) #define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) #define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) #define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF) +#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) #define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) #define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) #define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF) +#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) #define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) #define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) #define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) #define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) #define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) #define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) #define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) /* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_MASK (0xCF) +#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) #define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) #define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) #define GPIO_MSCR_FB_DUPPER_OD (0x10) #define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) -#define GPIO_MSCR_FB_DLOWER_MASK (0xF3) +#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) #define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) #define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) #define GPIO_MSCR_FB_DLOWER_OD (0x04) #define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) -#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) #define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) #define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) #define GPIO_MSCR_FB_ADDRCTL_OD (0x01) #define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) /* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) #define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) #define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) #define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h index 22987ac778..71a40d33d2 100644 --- a/include/asm-m68k/m5235.h +++ b/include/asm-m68k/m5235.h @@ -557,8 +557,8 @@ #define CCM_RCON_MODE (0x0001) /* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define CCM_CIR_PRN(x) ((x)&0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) /********************************************************************* * PLL Clock Module diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h index 80cefc40aa..0920a0dc2a 100644 --- a/include/asm-m68k/m5301x.h +++ b/include/asm-m68k/m5301x.h @@ -254,7 +254,7 @@ #define CCM_MISCCR_PLL_LOCK (0x2000) #define CCM_MISCCR_LIMP (0x1000) #define CCM_MISCCR_BME (0x8000) -#define CCM_MISCCR_BMT_MASK (0xF8FF) +#define CCM_MISCCR_BMT_UNMASK (0xF8FF) #define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) #define CCM_MISCCR_BMT_512 (0x0700) #define CCM_MISCCR_BMT_1024 (0x0600) @@ -330,32 +330,32 @@ #define GPIO_PAR_CS5 (0x40) #define GPIO_PAR_CS4 (0x10) -#define GPIO_PAR_CS1_MASK (0xF3) +#define GPIO_PAR_CS1_UNMASK (0xF3) #define GPIO_PAR_CS1_CS1 (0x0C) #define GPIO_PAR_CS1_SDCS1 (0x08) -#define GPIO_PAR_CS0_MASK (0xFC) +#define GPIO_PAR_CS0_UNMASK (0xFC) #define GPIO_PAR_CS0_CS0 (0x03) #define GPIO_PAR_CS0_CS4 (0x02) -#define GPIO_PAR_DSPIH_SIN_MASK (0x3F) +#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F) #define GPIO_PAR_DSPIH_SIN (0xC0) #define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) -#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF) +#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF) #define GPIO_PAR_DSPIH_SOUT (0x30) #define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) -#define GPIO_PAR_DSPIH_SCK_MASK (0xF3) +#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3) #define GPIO_PAR_DSPIH_SCK (0x0C) #define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) -#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC) +#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC) #define GPIO_PAR_DSPIH_PCS0 (0x03) #define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) -#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F) +#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F) #define GPIO_PAR_DSPIL_PCS1 (0xC0) -#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF) +#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF) #define GPIO_PAR_DSPIL_PCS2 (0x30) #define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) -#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3) +#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3) #define GPIO_PAR_DSPIL_PCS3 (0x0C) #define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) @@ -365,30 +365,30 @@ #define GPIO_PAR_FEC0_RMII_FEC (0x01) /* GPIO_PAR_FECI2C */ -#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC0 (0x80) #define GPIO_PAR_FECI2C_MDIO0 (0x40) -#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF) +#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDC1 (0x20) #define GPIO_PAR_FECI2C_MDIO1 (0x10) -#define GPIO_PAR_FECI2C_SDA_MASK (0xF3) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) #define GPIO_PAR_FECI2C_SDA_SDA (0x0C) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) #define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFC) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) #define GPIO_PAR_FECI2C_SCL_SCL (0x03) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) #define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) -#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F) -#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF) +#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F) +#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF) #define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) -#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC) +#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC) #define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) -#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3) +#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3) #define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) #define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) @@ -401,24 +401,24 @@ #define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) #define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) -#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F) +#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F) #define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) #define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) #define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) -#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF) +#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF) #define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) #define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) #define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) -#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3) +#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3) #define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) #define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) #define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) -#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC) +#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC) #define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) #define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) #define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) -#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F) +#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F) #define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) #define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) @@ -432,19 +432,19 @@ #define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TIN3_MASK (0x3F) +#define GPIO_PAR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TIN3_IRQ03 (0x40) -#define GPIO_PAR_TIN2_MASK (0xCF) +#define GPIO_PAR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TIN2_TIN2 (0x30) #define GPIO_PAR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TIN2_IRQ02 (0x10) -#define GPIO_PAR_TIN1_MASK (0xF3) +#define GPIO_PAR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TIN1_DACK1 (0x04) -#define GPIO_PAR_TIN0_MASK (0xFC) +#define GPIO_PAR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TIN0_TIN0 (0x03) #define GPIO_PAR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) @@ -455,10 +455,10 @@ #define GPIO_PAR_UART_U0RXD (0x10) #define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) #define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) -#define GPIO_PAR_UART_RTS0_MASK (0xF3) +#define GPIO_PAR_UART_RTS0_UNMASK (0xF3) #define GPIO_PAR_UART_RTS0_U0RTS (0x0C) #define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) -#define GPIO_PAR_UART_CTS0_MASK (0xFC) +#define GPIO_PAR_UART_CTS0_UNMASK (0xFC) #define GPIO_PAR_UART_CTS0_U0CTS (0x03) #define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) #define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) @@ -476,20 +476,20 @@ #define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) #define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) #define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) -#define GPIO_PAR_SSIH_RXD_MASK (0x3F) +#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F) #define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) #define GPIO_PAR_SSIH_RXD_U1RXD (0x40) -#define GPIO_PAR_SSIH_TXD_MASK (0xCF) +#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF) #define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) #define GPIO_PAR_SSIH_TXD_U1TXD (0x10) -#define GPIO_PAR_SSIH_FS_MASK (0xF3) +#define GPIO_PAR_SSIH_FS_UNMASK (0xF3) #define GPIO_PAR_SSIH_FS_SSIFS (0x0C) #define GPIO_PAR_SSIH_FS_U1RTS (0x04) -#define GPIO_PAR_SSIH_MCLK_MASK (0xFC) +#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC) #define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) #define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) -#define GPIO_PAR_SSIL_MASK (0x3F) +#define GPIO_PAR_SSIL_UNMASK (0x3F) #define GPIO_PAR_SSIL_BCLK (0xC0) #define GPIO_PAR_SSIL_U1CTS (0x40) @@ -497,40 +497,40 @@ #define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCRn_MASK (0x1F) +#define GPIO_MSCR_MSCRn_UNMASK (0x1F) #define GPIO_MSCR_MSCRn_SDR (0xE0) #define GPIO_MSCR_MSCRn_25VDDR (0x60) #define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) #define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) #define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) -#define GPIO_MSCR_MSCR5_MASK (0xE3) +#define GPIO_MSCR_MSCR5_UNMASK (0xE3) #define GPIO_MSCR_MSCR5_SDR (0x1C) #define GPIO_MSCR_MSCR5_25VDDR (0x0C) #define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) #define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) -#define GPIO_SRCR_DSPI_MASK (0xFC) +#define GPIO_SRCR_DSPI_UNMASK (0xFC) #define GPIO_SRCR_DSPI(x) ((x) & 0x03) -#define GPIO_SRCR_I2C_MASK (0xFC) +#define GPIO_SRCR_I2C_UNMASK (0xFC) #define GPIO_SRCR_I2C(x) ((x) & 0x03) -#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3) +#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3) #define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC) +#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC) #define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) -#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3) +#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3) #define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC) +#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC) #define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) -#define GPIO_SRCR_TIMER_MASK (0xFC) +#define GPIO_SRCR_TIMER_UNMASK (0xFC) #define GPIO_SRCR_TIMER(x) ((x) & 0x03) -#define GPIO_SRCR_UART2_MASK (0xF3) +#define GPIO_SRCR_UART2_UNMASK (0xF3) #define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_UART0_MASK (0xFC) +#define GPIO_SRCR_UART0_UNMASK (0xFC) #define GPIO_SRCR_UART0(x) ((x) & 0x03) -#define GPIO_SRCR_SDHC_MASK (0xFC) +#define GPIO_SRCR_SDHC_UNMASK (0xFC) #define GPIO_SRCR_SDHC(x) ((x) & 0x03) -#define GPIO_SRCR_SSI_MASK (0xFC) +#define GPIO_SRCR_SSI_UNMASK (0xFC) #define GPIO_SRCR_SSI(x) ((x) & 0x03) #define SRCR_HIGHEST (0x03) @@ -538,11 +538,11 @@ #define SRCR_LOW (0x01) #define SRCR_LOWEST (0x00) -#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF) +#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF) #define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_FEC_RMII0_MASK (0xF3) +#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3) #define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_FEC_RMII1_MASK (0xFC) +#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC) #define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) #define DSCR_50PF (0x03) @@ -572,18 +572,18 @@ #define PLL_PCR_LOL_IRQ (0x00004000) #define PLL_PCR_LOL_RE (0x00002000) #define PLL_PCR_LOL_EN (0x00001000) -#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF) +#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF) #define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) -#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0) +#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0) #define PLL_PCR_FBDIV(x) ((x) & 0x3F) -#define PLL_PDR_OUTDIV4_MASK (0x0FFF) +#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF) #define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) -#define PLL_PDR_OUTDIV3_MASK (0xF0FF) +#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF) #define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) -#define PLL_PDR_OUTDIV2_MASK (0xFF0F) +#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F) #define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) -#define PLL_PDR_OUTDIV1_MASK (0xFFF0) +#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0) #define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) #define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) #define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index 596662191c..dfddde62ad 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -286,13 +286,13 @@ /* Bit definitions and macros for PAR_FEC */ #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) -#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) #define GPIO_PAR_FEC_FEC1_MII (0x70) #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) #define GPIO_PAR_FEC_FEC1_ATA (0x10) #define GPIO_PAR_FEC_FEC1_GPIO (0x00) -#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) #define GPIO_PAR_FEC_FEC0_MII (0x07) #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) @@ -304,15 +304,15 @@ #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) #define GPIO_PAR_DMA_DACK1_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) -#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) #define GPIO_PAR_DMA_DACK0_GPIO (0x00) @@ -330,7 +330,7 @@ #define GPIO_PAR_FBCTL_TA_GPIO (0x00) #define GPIO_PAR_FBCTL_RW_RW (0x20) #define GPIO_PAR_FBCTL_RW_GPIO (0x00) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_TS (0x18) #define GPIO_PAR_FBCTL_TS_ALE (0x10) #define GPIO_PAR_FBCTL_TS_TBST (0x08) @@ -364,11 +364,11 @@ #define GPIO_PAR_BE_BS1 (0x04) #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_UNMASK (0x3F) #define GPIO_PAR_BE_BE3_BE3 (0xC0) #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) #define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_UNMASK (0xCF) #define GPIO_PAR_BE_BE2_BE2 (0x30) #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) #define GPIO_PAR_BE_BE2_GPIO (0x00) @@ -393,22 +393,22 @@ #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) @@ -417,12 +417,12 @@ /* Bit definitions and macros for PAR_USB */ #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) -#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) -#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) @@ -460,11 +460,11 @@ #define GPIO_PAR_FECI2C_MDC0 (0x0040) #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) @@ -472,11 +472,11 @@ #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) @@ -487,19 +487,19 @@ #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) -#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) #define GPIO_PAR_SSI_FS_FS (0x00C0) #define GPIO_PAR_SSI_FS_U1RTS (0x0080) #define GPIO_PAR_SSI_FS_GPIO (0x0000) -#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) -#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) #define GPIO_PAR_SSI_STXD_STXD (0x000C) #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) #define GPIO_PAR_SSI_STXD_GPIO (0x0000) @@ -552,7 +552,7 @@ #define GPIO_PAR_PCI_GNT1 (0x0400) #define GPIO_PAR_PCI_GNT2 (0x1000) #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) -#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) @@ -562,7 +562,7 @@ #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) @@ -578,22 +578,22 @@ #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) -#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a0b27a89c4..880cb4ee6b 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -208,6 +208,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 32123d2f54..e6632acbe7 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -158,7 +158,7 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 @@ -207,6 +207,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chipselect bank definitions */ /* * CS0 - NOR Flash diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1801d9d7d5..6c6b5d6d57 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -302,6 +302,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 2b816ceae2..5c0dc842aa 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -237,6 +237,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index e3830e5369..33ac2859df 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -60,6 +60,7 @@ * Command line configuration. */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_SYS_PROMPT "=> " @@ -165,6 +166,20 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 5e86e4cb90..b5af493b80 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -57,6 +57,7 @@ */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS #define CONFIG_CMD_EXT2 @@ -95,11 +96,6 @@ # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 10.82.121.249 -# define CONFIG_NETMASK 255.255.252.0 -# define CONFIG_SERVERIP 10.82.120.80 -# define CONFIG_GATEWAYIP 10.82.123.254 # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ @@ -109,9 +105,9 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ "save\0" \ "" #endif @@ -231,6 +227,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index df6970cdfa..206d1152ee 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS @@ -179,6 +180,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 50b3ab2808..798949cc56 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -72,6 +72,7 @@ */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -229,6 +230,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chip Select 0 : Boot Flash */ #define CONFIG_SYS_CS0_BASE 0xFFE00000 #define CONFIG_SYS_CS0_MASK 0x001F0001 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index f824158a69..f704bb3ff7 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -74,6 +74,7 @@ */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -211,6 +212,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index b380159812..981670ac06 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -72,6 +72,7 @@ /* Available command configuration */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -121,11 +122,6 @@ #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60 -#endif - #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -145,6 +141,23 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 150000000 @@ -208,6 +221,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 15590cfcd5..6e0aa14d3a 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -209,6 +210,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 30855bdaa2..d983a8fedb 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -69,6 +69,8 @@ # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 @@ -166,7 +168,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -180,7 +182,7 @@ #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 @@ -231,6 +233,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8180c05e67..159b178f40 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 8652a80aa1..af1988ce0a 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index a5acfd2846..a80d33047f 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -309,6 +309,21 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7737284aab..5b4bba8c26 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -279,7 +279,7 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) @@ -408,6 +408,21 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 4534002e47..d0077667f3 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -286,6 +286,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 971cb67bad..f23b8b0efa 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -272,6 +272,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 25f3a26f35..b69f015c7c 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -252,6 +252,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h new file mode 100644 index 0000000000..7c8281cae7 --- /dev/null +++ b/include/configs/astro_mcf5373l.h @@ -0,0 +1,400 @@ +/* + * Configuration settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner <w.wegner@astro-kom.de> + * Please do not bother the original author with bug reports + * concerning this file. + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +/* + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* + * Define processor + * possible values for Urmel board: only Coldfire M5373 processor supported + * (please do not change) + */ + +/* it seems not clear yet which processor defines we should use */ +#define CONFIG_MCF537x /* define processor family */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ +#define CONFIG_ASTRO5373L /* define board type */ + +/* Command line configuration */ +#include <config_cmd_default.h> + +/* + * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from + * a different bootloader that has already performed RAM setup) or + * started directly from flash, which is the regular case for production + * boards. + */ +#ifdef CONFIG_MK_RAM +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_TEXT_BASE 0x40020000 +#define ENABLE_JFFS 0 +#else +#define CONFIG_TEXT_BASE 0x00000000 +#define ENABLE_JFFS 1 +#endif + +/* Define which commmands should be available at u-boot command prompt */ + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_XIMG +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#if ENABLE_JFFS +#define CONFIG_CMD_JFFS2 +#endif +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_FPGA +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * in u-boot command interface + */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* + * Watchdog configuration; Watchdog is disabled for running from RAM + * and set to highest possible value else. Beware there is no check + * in the watchdog code to validate the timeout value set here! + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* + * Configuration for environment + * Environment is located in the last sector of the flash + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_ENV_OFFSET 0x1FF8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#else +/* + * environment in RAM - This is used to use a single PC-based application + * to load an image, load U-Boot, load an environment and then start U-Boot + * to execute the commands from the environment. Feedback is done via setting + * and reading memory locations. + */ +#define CONFIG_ENV_ADDR 0x40060000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* here we put our FPGA configuration... */ +#define CONFIG_MISC_INIT_R 1 + +/* Define user parameters that have to be customized most likely */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* + * used for autoboot, delay in seconds u-boot will wait before starting + * defined (auto-)boot command, setting to -1 disables delay, setting to + * 0 will too prevent access to u-boot command interface: u-boot then has + * to be reflashed + * beware - watchdog is not serviced during autoboot delay time! + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTDELAY 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * The following settings will be contained in the environment block ; if you + * want to use a neutral environment all those settings can be manually set in + * u-boot: 'set' command + */ + +#define _QUOTEME(x) #x +#define QUOTEME(x) _QUOTEME(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="QUOTEME(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ + "fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ + "fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then setenv env_default 0;saveenv;fi\0" + +/* + * "update" is a non-standard command that has to be supplied + * by external update.c; This is not included in mainline because + * it needs non-blocking CFI routines. + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default bootargs that are considered during boot */ +#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ + " loaderversion=$loaderversion" + +#define CONFIG_SYS_PROMPT "URMEL > " + +/* default RAM address for user programs */ +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_SYS_LONGHELP + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* End of user parameters to be customized */ + +/* Defines memory range for test */ + +#define CONFIG_SYS_MEMTEST_START 0x40020000 +#define CONFIG_SYS_MEMTEST_END 0x41ffffff + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* Base register address */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* System Conf. Reg. & System Protection Reg. */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* + * Chipselect bank definitions + * + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - unused + * CS5 - unused + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE +#else +/* This is mainly used during relocation in start.S */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +#endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1c3ea23c77..330e3ac667 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -331,6 +331,19 @@ from which user programs will be started */ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions * diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 841affb7cc..61e3bad4f3 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -224,6 +224,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d62d..d5a589d099 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; + Xilinx_bwr_fn bwr; /* block write function */ } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc572..2cb2e5b6aa 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie ); typedef int (*Xilinx_abort_fn)( int cookie ); typedef int (*Xilinx_pre_fn)( int cookie ); typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); #endif /* _XILINX_H_ */ diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c index 84fb6c2fbc..ed881783f1 100644 --- a/lib_m68k/cache.c +++ b/lib_m68k/cache.c @@ -22,8 +22,129 @@ */ #include <common.h> +#include <asm/immap.h> +#include <asm/cache.h> -void flush_cache (ulong start_addr, ulong size) +volatile int *cf_icache_status = (int *)ICACHE_STATUS; +volatile int *cf_dcache_status = (int *)DCACHE_STATUS; + +void flush_cache(ulong start_addr, ulong size) { /* Must be implemented for all M68k processors with copy-back data cache */ } + +int icache_status(void) +{ + return *cf_icache_status; +} + +int dcache_status(void) +{ + return *cf_dcache_status; +} + +void icache_enable(void) +{ + icache_invalid(); + + *cf_icache_status = 1; + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); + __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); +#else + __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); +#endif + + __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); +} + +void icache_disable(void) +{ + u32 temp = 0; + + *cf_icache_status = 0; + icache_invalid(); + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr2"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr3"::"r"(temp)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr6"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr7"::"r"(temp)); +#else + __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); + +#endif +} + +void icache_invalid(void) +{ + u32 temp; + + temp = CONFIG_SYS_ICACHE_INV; + if (*cf_icache_status) + temp |= CONFIG_SYS_CACHE_ICACR; + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); +} + +/* + * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x + * the dcache will be dummy in ColdFire V2 and V3 + */ +void dcache_enable(void) +{ + dcache_invalid(); + *cf_dcache_status = 1; + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); + __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); + +#endif + + __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); +} + +void dcache_disable(void) +{ + u32 temp = 0; + + *cf_dcache_status = 0; + dcache_invalid(); + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr4"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr5"::"r"(temp)); + +#endif +} + +void dcache_invalid(void) +{ +#ifdef CONFIG_CF_V4 + u32 temp; + + temp = CONFIG_SYS_DCACHE_INV; + if (*cf_dcache_status) + temp |= CONFIG_SYS_CACHE_DCACR; + if (*cf_icache_status) + temp |= CONFIG_SYS_CACHE_ICACR; + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); +#endif +} |
