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-rw-r--r--arch/arc/Kconfig40
-rw-r--r--arch/arc/config.mk4
-rw-r--r--arch/arc/include/asm/arcregs.h2
-rw-r--r--arch/arc/include/asm/cache.h6
-rw-r--r--include/configs/arcangel4-be.h1
-rw-r--r--include/configs/arcangel4.h1
-rw-r--r--include/configs/axs101.h1
-rw-r--r--include/configs/tb100.h1
8 files changed, 52 insertions, 4 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index c6b1efeb8b..f7d2964144 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -8,6 +8,46 @@ config SYS_CPU
default "arcv1"
choice
+ prompt "CPU selection"
+ default CPU_ARC770D
+
+config CPU_ARC750D
+ bool "ARC 750D"
+ select ARC_MMU_V2
+ help
+ Choose this option to build an U-Boot for ARC750D CPU.
+
+config CPU_ARC770D
+ bool "ARC 770D"
+ select ARC_MMU_V3
+ help
+ Choose this option to build an U-Boot for ARC770D CPU.
+
+endchoice
+
+choice
+ prompt "MMU Version"
+ default ARC_MMU_V3 if CPU_ARC770D
+ default ARC_MMU_V2 if CPU_ARC750D
+
+config ARC_MMU_V2
+ bool "MMU v2"
+ depends on CPU_ARC750D
+ help
+ Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
+ when 2 D-TLB and 1 I-TLB entries index into same 2way set.
+
+config ARC_MMU_V3
+ bool "MMU v3"
+ depends on CPU_ARC770D
+ help
+ Introduced with ARC700 4.10: New Features
+ Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
+ Shared Address Spaces (SASID)
+
+endchoice
+
+choice
prompt "Target select"
config TARGET_TB100
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 5321987a56..dd180ef187 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -25,6 +25,10 @@ ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
+ifdef CONFIG_CPU_ARC770D
+PLATFORM_CPPFLAGS += -mlock -mswape
+endif
+
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 8ace87fa0f..31627e65b9 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -7,6 +7,8 @@
#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H
+#include <asm/cache.h>
+
/*
* ARC architecture has additional address space - auxiliary registers.
* These registers are mostly used for configuration purposes.
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 16e7568ef0..368d1f016e 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -20,4 +20,10 @@
#define ARCH_DMA_MINALIGN 128
#endif
+#if defined(CONFIG_ARC_MMU_V2)
+#define CONFIG_ARC_MMU_VER 2
+#elif defined(CONFIG_ARC_MMU_V3)
+#define CONFIG_ARC_MMU_VER 3
+#endif
+
#endif /* __ASM_ARC_CACHE_H */
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h
index 2ca209e1e4..a43590bef5 100644
--- a/include/configs/arcangel4-be.h
+++ b/include/configs/arcangel4-be.h
@@ -11,7 +11,6 @@
* CPU configuration
*/
#define CONFIG_SYS_BIG_ENDIAN
-#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 2afb63d80d..565f70e165 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -10,7 +10,6 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index a8a9cb3cba..b94687c230 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -10,7 +10,6 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index a59834383a..f3539506c2 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -12,7 +12,6 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
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