diff options
230 files changed, 61692 insertions, 13133 deletions
diff --git a/.gitignore b/.gitignore index 37f2c1dcd9..7c56594381 100644 --- a/.gitignore +++ b/.gitignore @@ -18,9 +18,13 @@ /System.map /u-boot +/u-boot.hex /u-boot.map /u-boot.bin /u-boot.srec +/u-boot.ldr +/u-boot.ldr.hex +/u-boot.ldr.srec # # Generated files @@ -185,18 +185,6 @@ endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif -ifeq ($(CPU),bf533) -OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o -OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o -endif -ifeq ($(CPU),bf537) -OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o -OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o -endif -ifeq ($(CPU),bf561) -OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o -OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o -endif OBJS := $(addprefix $(obj),$(OBJS)) @@ -286,6 +274,9 @@ __LIBS := $(subst $(obj),,$(LIBS)) ######################################################################### ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ifeq ($(ARCH),blackfin) +ALL += $(obj)u-boot.ldr +endif all: $(ALL) @@ -298,6 +289,15 @@ $(obj)u-boot.srec: $(obj)u-boot $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ +$(obj)u-boot.ldr: $(obj)u-boot + $(LDR) -T $(CONFIG_BFIN_CPU) -f -c $@ $< $(LDR_FLAGS) + +$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr + $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary + +$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr + $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary + $(obj)u-boot.img: $(obj)u-boot.bin ./tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(TEXT_BASE) -e 0 \ @@ -312,7 +312,7 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) - UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot @@ -2824,20 +2824,19 @@ xupv2p_config: unconfig @echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx -######################################################################### -## Blackfin -######################################################################### -bf533-ezkit_config: unconfig - @$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit +#======================================================================== +# Blackfin +#======================================================================== -bf533-stamp_config: unconfig - @$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp +# Analog Devices boards +BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit -bf537-stamp_config: unconfig - @$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp +$(BFIN_BOARDS:%=%_config) : unconfig + @$(MKCONFIG) $(@:_config=) blackfin $(firstword $(subst -, ,$@)) $(@:_config=) -bf561-ezkit_config: unconfig - @$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit +$(BFIN_BOARDS): + $(MAKE) $@_config + $(MAKE) #======================================================================== # AVR32 @@ -3517,6 +3517,11 @@ For PowerPC, the following registers have specific use: average for all boards 752 bytes for the whole U-Boot image, 624 text + 127 data). +On Blackfin, the normal C ABI (except for P5) is followed as documented here: + http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface + + ==> U-Boot will use P5 to hold a pointer to the global data + On ARM, the following registers are used: R0: function argument word/integer result diff --git a/blackfin_config.mk b/blackfin_config.mk index f71a31370e..a7513ea4dc 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -21,4 +21,12 @@ # MA 02111-1307 USA # -PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__ +PLATFORM_RELFLAGS += -ffixed-P5 +PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN + +SYM_PREFIX = _ + +LDR_FLAGS += --use-vmas +ifeq (,$(findstring s,$(MAKEFLAGS))) +LDR_FLAGS += --quiet +endif diff --git a/board/bf533-ezkit/.gitignore b/board/bf533-ezkit/.gitignore new file mode 100644 index 0000000000..945f324549 --- /dev/null +++ b/board/bf533-ezkit/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index 299cdbae73..cdf4dc69ba 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -286,9 +286,9 @@ int write_flash(long nOffset, int nValue) long addr; addr = (CFG_FLASH_BASE + nOffset); - sync(); + SSYNC(); *(unsigned volatile short *)addr = nValue; - sync(); + SSYNC(); if (poll_toggle_bit(nOffset) < 0) return FLASH_FAIL; return FLASH_SUCCESS; @@ -301,9 +301,9 @@ int read_flash(long nOffset, int *pnValue) if (nOffset != 0x2) reset_flash(); - sync(); + SSYNC(); nValue = *(volatile unsigned short *)addr; - sync(); + SSYNC(); *pnValue = nValue; return TRUE; } diff --git a/board/bf533-stamp/.gitignore b/board/bf533-stamp/.gitignore new file mode 100644 index 0000000000..945f324549 --- /dev/null +++ b/board/bf533-stamp/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 69e425bf97..af035976ff 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -76,9 +76,9 @@ void swap_to(int device_id) if (device_id == ETHERNET) { *pFIO_DIR = PF0; - sync(); + SSYNC(); *pFIO_FLAG_S = PF0; - sync(); + SSYNC(); } else if (device_id == FLASH) { *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); *pFIO_FLAG_S = (PF4 | PF3 | PF2); @@ -88,7 +88,7 @@ void swap_to(int device_id) *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); *pFIO_FLAG_D = (PF4 | PF3 | PF2); - sync(); + SSYNC(); } else { printf("Unknown bank to switch\n"); } @@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr) */ *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); *(addr) = val; - sync(); + SSYNC(); /* Setback PF1 PF0 to 0 0 to address external * memory banks */ *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } unsigned char cf_inb(volatile unsigned char *addr) @@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); c = *(addr); - sync(); + SSYNC(); *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); return c; } @@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); for (i = 0; i < words; i++) { *(sect_buf + i) = *(addr); - sync(); + SSYNC(); } *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) @@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); for (i = 0; i < words; i++) { *(addr) = *(sect_buf + i); - sync(); + SSYNC(); } *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } #endif @@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3) *pFIO_FLAG_S = PF4; else *pFIO_FLAG_C = PF4; - sync(); + SSYNC(); } void show_boot_progress(int status) diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c index d30750faa3..15141cf743 100644 --- a/board/bf533-stamp/spi.c +++ b/board/bf533-stamp/spi.c @@ -4,6 +4,7 @@ #include <common.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/mach-common/bits/spi.h> #if defined(CONFIG_SPI) @@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand) /*sends the actual command to the SPI TX register */ *pSPI_TDBR = iCommand; - sync(); + SSYNC(); /*The SPI status register will be polled to check the SPIF bit */ Wait_For_SPIF(); @@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting) *pSPI_FLG = 0xFB04; *pSPI_BAUD = CONFIG_SPI_BAUD; *pSPI_CTL = spi_setting; - sync(); + SSYNC(); } void SPI_OFF(void) @@ -183,7 +184,7 @@ void SPI_OFF(void) *pSPI_CTL = 0x0400; /* disable SPI */ *pSPI_FLG = 0; *pSPI_BAUD = 0; - sync(); + SSYNC(); udelay(CONFIG_CCLK_HZ / 50000000); } @@ -241,10 +242,10 @@ char ReadStatusRegister(void) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ *pSPI_TDBR = 0; /*send dummy to receive the status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the data has been sent */ status_register = *pSPI_RDBR; /*read the status register */ @@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock) /* Send the erase block command to the flash followed by the 24 address */ /* to point to the start of a sector. */ *pSPI_TDBR = SPI_SE; - sync(); + SSYNC(); Wait_For_SPIF(); ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ *pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ /*Turns off the SPI */ @@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); *pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */ *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */ *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ *pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ /* After the SPI device address has been placed on the MOSI pin the data can be */ /* received on the MISO pin. */ for (i = 0; i < lCount; i++) { *pSPI_TDBR = 0; /*send dummy */ - sync(); + SSYNC(); while (!(*pSPI_STAT & RXS)) ; *cnData++ = *pSPI_RDBR; /*read */ @@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, /* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */ *pSPI_TDBR = SPI_PP; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = (ulStartAddr >> 16); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = (ulStartAddr >> 8); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = ulStartAddr; *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ /* Fourth, maximum number of 256 bytes will be taken from the Buffer */ /* and sent to the SPI device. */ for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) { iData = *temp; *pSPI_TDBR = iData; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ temp++; } diff --git a/board/bf537-stamp/.gitignore b/board/bf537-stamp/.gitignore new file mode 100644 index 0000000000..945f324549 --- /dev/null +++ b/board/bf537-stamp/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 6954b3003d..d279817bba 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <net.h> #include "ether_bf537.h" +#include <asm/mach-common/bits/bootrom.h> /** * is_valid_ether_addr - Determine if the given Ethernet address is valid @@ -117,7 +118,7 @@ int checkboard(void) void cf_outb(unsigned char val, volatile unsigned char *addr) { *(addr) = val; - sync(); + SSYNC(); } unsigned char cf_inb(volatile unsigned char *addr) @@ -125,7 +126,7 @@ unsigned char cf_inb(volatile unsigned char *addr) volatile unsigned char c; c = *(addr); - sync(); + SSYNC(); return c; } @@ -136,7 +137,7 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) for (i = 0; i < words; i++) *(sect_buf + i) = *(addr); - sync(); + SSYNC(); } void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) @@ -145,7 +146,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) for (i = 0; i < words; i++) *(addr) = *(sect_buf + i); - sync(); + SSYNC(); } #endif /* CONFIG_BFIN_IDE */ diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c index 36c1536e39..6c514c6609 100644 --- a/board/bf537-stamp/ether_bf537.c +++ b/board/bf537-stamp/ether_bf537.c @@ -30,6 +30,10 @@ #include <malloc.h> #include "ether_bf537.h" +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/emac.h> +#include <asm/mach-common/bits/pll.h> + #ifdef CONFIG_POST #include <post.h> #endif @@ -364,7 +368,7 @@ int SetupSystemRegs(int *opmode) u16 sysctl, phydat; int count = 0; /* Enable PHY output */ - *pVR_CTL |= PHYCLKOE; + *pVR_CTL |= CLKBUFOE; /* MDC = 2.5 MHz */ sysctl = SET_MDCDIV(24); /* Odd word alignment for Receive Frame DMA word */ diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c index ed85841479..8252c42fd8 100644 --- a/board/bf537-stamp/flash.c +++ b/board/bf537-stamp/flash.c @@ -255,7 +255,7 @@ int write_flash(long nOffset, int nValue) addr = (CFG_FLASH_BASE + nOffset); *(unsigned volatile short *)addr = nValue; - sync(); + SSYNC(); #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) if (icache_status()) udelay(CONFIG_CCLK_HZ / 1000000); diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index f95b584b31..6ff0f4f96c 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -64,13 +64,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd) this->IO_ADDR_R = this->IO_ADDR_W; /* Drain the writebuffer */ - sync(); + SSYNC(); } int bfin_device_ready(struct mtd_info *mtd) { int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0; - sync(); + SSYNC(); return ret; } diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 60393505a2..fa119919b3 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -104,15 +104,15 @@ void post_init_uart(int sclk) *pUART_GCTL = 0x00; *pUART_LCR = 0x83; - sync(); + SSYNC(); *pUART_DLL = (divisor & 0xFF); - sync(); + SSYNC(); *pUART_DLH = ((divisor >> 8) & 0xFF); - sync(); + SSYNC(); *pUART_LCR = 0x03; - sync(); + SSYNC(); *pUART_GCTL = 0x01; - sync(); + SSYNC(); } void post_out_buff(char *buff) @@ -124,7 +124,7 @@ void post_out_buff(char *buff) while ((buff[i] != '\0') && (i != 100)) { while (!(*pUART_LSR & 0x20)) ; *pUART_THR = buff[i]; - sync(); + SSYNC(); i++; } for (i = 0; i < 0x80000; i++) ; @@ -141,7 +141,7 @@ int post_key_pressed(void) *pPORTF_FER &= ~PF5; *pPORTFIO_DIR &= ~PF5; *pPORTFIO_INEN |= PF5; - sync(); + SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { @@ -303,7 +303,7 @@ int post_init_sdram(int sclk) (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS); - sync(); + SSYNC(); *pEBIU_SDGCTL |= 0x1000000; /* Set the SDRAM Refresh Rate control register based on SSCLK value */ @@ -314,7 +314,7 @@ int post_init_sdram(int sclk) /* SDRAM Memory Global Control Register */ *pEBIU_SDGCTL = mem_SDGCTL; - sync(); + SSYNC(); return mem_SDRRC; } diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c index d9c08ee8e6..c48c3c7c7e 100644 --- a/board/bf537-stamp/stm_m25p64.c +++ b/board/bf537-stamp/stm_m25p64.c @@ -4,6 +4,7 @@ #include <common.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/mach-common/bits/spi.h> #if defined(CONFIG_SPI) @@ -142,7 +143,7 @@ void SendSingleCommand(const int iCommand) /* sends the actual command to the SPI TX register */ *pSPI_TDBR = iCommand; - sync(); + SSYNC(); /* The SPI status register will be polled to check the SPIF bit */ Wait_For_SPIF(); @@ -164,10 +165,10 @@ void SetupSPI(const int spi_setting) *pSPI_FLG = 0xFF02; *pSPI_BAUD = CONFIG_SPI_BAUD; *pSPI_CTL = spi_setting; - sync(); + SSYNC(); *pSPI_FLG = 0xFD02; - sync(); + SSYNC(); } void SPI_OFF(void) @@ -176,7 +177,7 @@ void SPI_OFF(void) *pSPI_CTL = 0x0400; /* disable SPI */ *pSPI_FLG = 0; *pSPI_BAUD = 0; - sync(); + SSYNC(); udelay(CONFIG_CCLK_HZ / 50000000); } @@ -234,10 +235,10 @@ char ReadStatusRegister(void) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ *pSPI_TDBR = 0; /*send dummy to receive the status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the data has been sent */ status_register = *pSPI_RDBR; /*read the status register */ @@ -300,23 +301,23 @@ ERROR_CODE EraseBlock(int nBlock) * to point to the start of a sector */ *pSPI_TDBR = SPI_SE; - sync(); + SSYNC(); Wait_For_SPIF(); /* Send the highest byte of the 24 bit address at first */ ShiftValue = (ulSectorOff >> 16); *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the middle byte of the 24 bit address at second */ ShiftValue = (ulSectorOff >> 8); *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the lowest byte of the 24 bit address finally */ *pSPI_TDBR = ulSectorOff; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); @@ -357,33 +358,33 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) /* Send the read command to SPI device */ *pSPI_TDBR = SPI_READ; #endif - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the highest byte of the 24 bit address at first */ ShiftValue = (ulStart >> 16); /* Send the byte to the SPI device */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the middle byte of the 24 bit address at second */ ShiftValue = (ulStart >> 8); /* Send the byte to the SPI device */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the lowest byte of the 24 bit address finally */ *pSPI_TDBR = ulStart; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); #ifdef CONFIG_SPI_FLASH_FAST_READ /* Send dummy for FAST_READ */ *pSPI_TDBR = 0; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); #endif @@ -392,7 +393,7 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) /* received on the MISO pin. */ for (i = 0; i < lCount; i++) { *pSPI_TDBR = 0; - sync(); + SSYNC(); while (!(*pSPI_STAT & RXS)) ; *cnData++ = *pSPI_RDBR; @@ -435,22 +436,22 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, */ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); *pSPI_TDBR = SPI_PP; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = (ulStartAddr >> 16); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = (ulStartAddr >> 8); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = ulStartAddr; *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); /* @@ -460,7 +461,7 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) { iData = *temp; *pSPI_TDBR = iData; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); temp++; diff --git a/board/bf561-ezkit/.gitignore b/board/bf561-ezkit/.gitignore new file mode 100644 index 0000000000..945f324549 --- /dev/null +++ b/board/bf561-ezkit/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 2ff44a7152..d504217a1a 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -65,9 +65,9 @@ int misc_init_r(void) /* Keep PF12 low to be able to drive the USB-LAN Extender */ *pFIO0_DIR = 0x0000; *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */ - sync(); + SSYNC(); *pFIO0_POLAR = 0x0000; - sync(); + SSYNC(); return 0; } diff --git a/common/Makefile b/common/Makefile index fbfa536a30..a88d1ef536 100644 --- a/common/Makefile +++ b/common/Makefile @@ -76,6 +76,7 @@ COBJS-y += cmd_nand.o COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-y += cmd_nvedit.o COBJS-y += cmd_onenand.o +COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif @@ -86,6 +87,7 @@ COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o COBJS-y += cmd_sata.o COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o +COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o COBJS-$(CONFIG_CMD_USB) += cmd_usb.o diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 4e7746120b..bbb01921df 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -273,6 +273,37 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#elif defined(CONFIG_BLACKFIN) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + bd_t *bd = gd->bd; + + printf("U-Boot = %s\n", bd->bi_r_version); + printf("CPU = %s\n", bd->bi_cpu); + printf("Board = %s\n", bd->bi_board_name); + printf("VCO = %lu MHz\n", bd->bi_vco / 1000000); + printf("CCLK = %lu MHz\n", bd->bi_cclk / 1000000); + printf("SCLK = %lu MHz\n", bd->bi_sclk / 1000000); + + print_num("boot_params", (ulong)bd->bi_boot_params); + print_num("memstart", (ulong)bd->bi_memstart); + print_num("memsize", (ulong)bd->bi_memsize); + print_num("flashstart", (ulong)bd->bi_flashstart); + print_num("flashsize", (ulong)bd->bi_flashsize); + print_num("flashoffset", (ulong)bd->bi_flashoffset); + + puts("ethaddr ="); + for (i = 0; i < 6; ++i) + printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + puts("\nip_addr = "); + print_IPaddr(bd->bi_ip_addr); + printf("\nbaudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else /* ! PPC, which leaves MIPS */ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 5fce773a9b..000107f726 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -154,9 +154,32 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } while (nbytes > 0); #else - /* Print the lines. */ - print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size); - addr += size*length; + +# if defined(CONFIG_BLACKFIN) + /* See if we're trying to display L1 inst */ + if (addr_bfin_on_chip_mem(addr)) { + char linebuf[DISP_LINE_LEN]; + ulong linebytes, nbytes = length * size; + do { + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + memcpy(linebuf, (void *)addr, linebytes); + print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size); + + nbytes -= linebytes; + addr += linebytes; + if (ctrlc()) { + rc = 1; + break; + } + } while (nbytes > 0); + } else +# endif + + { + /* Print the lines. */ + print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size); + addr += size*length; + } #endif dp_last_addr = addr; @@ -308,6 +331,13 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif +#ifdef CONFIG_BLACKFIN + if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) { + puts ("Comparison with L1 instruction memory not supported.\n\r"); + return 0; + } +#endif + ngood = 0; while (count-- > 0) { @@ -478,6 +508,14 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif +#ifdef CONFIG_BLACKFIN + /* See if we're copying to/from L1 inst */ + if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) { + memcpy((void *)dest, (void *)addr, count * size); + return 0; + } +#endif + while (count-- > 0) { if (size == 4) *((ulong *)dest) = *((ulong *)addr); @@ -1006,6 +1044,13 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) } #endif +#ifdef CONFIG_BLACKFIN + if (addr_bfin_on_chip_mem(addr)) { + puts ("Can't modify L1 instruction in place. Use cp instead.\n\r"); + return 0; + } +#endif + /* Print the address, followed by value. Then accept input for * the next value. A non-converted value exits. */ diff --git a/common/cmd_otp.c b/common/cmd_otp.c new file mode 100644 index 0000000000..825fa34ceb --- /dev/null +++ b/common/cmd_otp.c @@ -0,0 +1,163 @@ +/* + * cmd_otp.c - interface to Blackfin on-chip One-Time-Programmable memory + * + * Copyright (c) 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +/* There are 512 128-bit "pages" (0x000 to 0x1FF). + * The pages are accessable as 64-bit "halfpages" (an upper and lower half). + * The pages are not part of the memory map. There is an OTP controller which + * handles scanning in/out of bits. While access is done through OTP MMRs, + * the bootrom provides C-callable helper functions to handle the interaction. + */ + +#include <config.h> +#include <common.h> +#include <command.h> + +#ifdef CONFIG_CMD_OTP + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/otp.h> + +static const char *otp_strerror(uint32_t err) +{ + switch (err) { + case 0: return "no error"; + case OTP_WRITE_ERROR: return "OTP fuse write error"; + case OTP_READ_ERROR: return "OTP fuse read error"; + case OTP_ACC_VIO_ERROR: return "invalid OTP address"; + case OTP_DATA_MULT_ERROR: return "multiple bad bits detected"; + case OTP_ECC_MULT_ERROR: return "error in ECC bits"; + case OTP_PREV_WR_ERROR: return "space already written"; + case OTP_DATA_SB_WARN: return "single bad bit in half page"; + case OTP_ECC_SB_WARN: return "single bad bit in ECC"; + default: return "unknown error"; + } +} + +#define lowup(x) ((x) % 2 ? "upper" : "lower") + +int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + bool force = false; + if (!strcmp(argv[1], "--force")) { + force = true; + argv[1] = argv[0]; + argv++; + --argc; + } + + uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content); + if (!strcmp(argv[1], "read")) + otp_func = otp_read; + else if (!strcmp(argv[1], "write")) + otp_func = otp_write; + else { + usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + uint64_t *addr = (uint64_t *)simple_strtoul(argv[2], NULL, 16); + uint32_t page = simple_strtoul(argv[3], NULL, 16); + uint32_t flags, ret; + size_t i, count; + ulong half; + + if (argc > 4) + count = simple_strtoul(argv[4], NULL, 16); + else + count = 2; + + if (argc > 5) { + half = simple_strtoul(argv[5], NULL, 16); + if (half != 0 && half != 1) { + puts("Error: 'half' can only be '0' or '1'\n"); + goto usage; + } + } else + half = 0; + + /* do to the nature of OTP, make sure users are sure */ + if (!force && otp_func == otp_write) { + printf( + "Writing one time programmable memory\n" + "Make sure your operating voltages and temperature are within spec\n" + " source address: 0x%p\n" + " OTP destination: %s page 0x%03X - %s page 0x%03X\n" + " number to write: %ld halfpages\n" + " type \"YES\" (no quotes) to confirm: ", + addr, + lowup(half), page, + lowup(half + count - 1), page + (half + count - 1) / 2, + half + count + ); + + i = 0; + while (1) { + if (tstc()) { + const char exp_ans[] = "YES\r"; + char c; + putc(c = getc()); + if (exp_ans[i++] != c) { + printf(" Aborting\n"); + return 1; + } else if (!exp_ans[i]) { + puts("\n"); + break; + } + } + } + + /* Only supported in newer silicon ... enable writing */ +#if (0) + otp_command(OTP_INIT, ...); +#else + *pOTP_TIMING = 0x32149485; +#endif + } + + printf("OTP memory %s: addr 0x%08lx page 0x%03X count %ld ... ", + argv[1], addr, page, count); + + ret = 0; + for (i = half; i < count + half; ++i) { + flags = (i % 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF; + ret = otp_func(page, flags, addr); + if (ret & 0x1) + break; + else if (ret) + puts("W"); + else + puts("."); + ++addr; + if (i % 2) + ++page; + } + if (ret & 0x1) + printf("\nERROR at page 0x%03X (%s-halfpage): 0x%03X: %s\n", + page, lowup(i), ret, otp_strerror(ret)); + else + puts(" done\n"); + + if (otp_func == otp_write) + /* Only supported in newer silicon ... disable writing */ +#if (0) + otp_command(OTP_INIT, ...); +#else + *pOTP_TIMING = 0x1485; +#endif + + return ret; +} + +U_BOOT_CMD(otp, 6, 0, do_otp, + "otp - One-Time-Programmable sub-system\n", + "read <addr> <page> [count] [half]\n" + "otp write [--force] <addr> <page> [count] [half]\n" + " - read/write 'count' half-pages starting at page 'page' (offset 'half')\n"); + +#endif diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index bb6aa30d18..980664d142 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -329,16 +329,53 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); printf ("\tSDRAMCS1: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); + +#elif defined(CONFIG_BLACKFIN) + puts("\nSystem Configuration registers\n"); + + puts("\nPLL Registers\n"); + printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", + bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); + printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n", + bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT()); + printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL()); + + puts("\nEBIU AMC Registers\n"); + printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL()); + printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n", + bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1()); +# ifdef EBIU_MODE + printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n", + bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT()); + printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n", + bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL()); +# endif + +# ifdef EBIU_RSTCTL + puts("\nEBIU DDR Registers\n"); + printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n", + bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1()); + printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n", + bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3()); + printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n", + bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL()); + printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n", + bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST()); +# else + puts("\nEBIU SDC Registers\n"); + printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n", + bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL()); + printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", + bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); +# endif + #endif /* CONFIG_MPC5200 */ return 0; } /**************************************************/ -#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \ - defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) && \ - defined(CONFIG_CMD_REGINFO) - +#if defined(CONFIG_CMD_REGINFO) U_BOOT_CMD( reginfo, 2, 1, do_reginfo, "reginfo - print register information\n", diff --git a/common/cmd_strings.c b/common/cmd_strings.c new file mode 100644 index 0000000000..bbf56a033b --- /dev/null +++ b/common/cmd_strings.c @@ -0,0 +1,49 @@ +/* + * cmd_strings.c - just like `strings` command + * + * Copyright (c) 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <common.h> +#include <command.h> + +#ifdef CONFIG_CFG_STRINGS + +static char *start_addr, *last_addr; + +int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc == 1) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((flag & CMD_FLAG_REPEAT) == 0) { + start_addr = (char *)simple_strtoul(argv[1], NULL, 16); + if (argc > 2) + last_addr = (char *)simple_strtoul(argv[2], NULL, 16); + else + last_addr = (char *)-1; + } + + char *addr = start_addr; + do { + printf("%s\n", addr); + addr += strlen(addr) + 1; + } while (addr[0] && addr < last_addr); + + last_addr = addr + (last_addr - start_addr); + start_addr = addr; + + return 0; +} + +U_BOOT_CMD(strings, 3, 1, do_strings, + "strings - display strings\n", + "<addr> [byte count]\n" + " - display strings at <addr> for at least [byte count] or first double NUL\n"); + +#endif diff --git a/common/environment.c b/common/environment.c index 24257f7c52..3b9914f498 100644 --- a/common/environment.c +++ b/common/environment.c @@ -70,11 +70,16 @@ /* * Macros to generate global absolutes. */ +#if defined(__bfin__) +# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value)) +#else +# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) +#endif #define GEN_SYMNAME(str) SYM_CHAR #str #define GEN_VALUE(str) #str #define GEN_ABS(name, value) \ asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + GEN_SET_VALUE(name, value) /* * Macros to transform values @@ -121,6 +121,7 @@ CC = $(CROSS_COMPILE)gcc CPP = $(CC) -E AR = $(CROSS_COMPILE)ar NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr STRIP = $(CROSS_COMPILE)strip OBJCOPY = $(CROSS_COMPILE)objcopy OBJDUMP = $(CROSS_COMPILE)objdump diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile index dd4f299acd..ad48f1c5c1 100644 --- a/cpu/bf533/Makefile +++ b/cpu/bf533/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index 25b96a9f69..9970b723d5 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index 03aebe4b4c..d9015c6d1a 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 @@ -11,7 +12,7 @@ ENTRY(_blackfin_icache_flush_range) P0 = R2; P1 = R1; CSYNC; -1: + 1: IFLUSH[P0++]; CC = P0 < P1(iu); IF CC JUMP 1b(bp); diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk index 6a713c3f51..2caa3cc7d3 100644 --- a/cpu/bf533/config.mk +++ b/cpu/bf533/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf533 diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index 8118861f8d..edb771e33c 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -190,13 +184,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S index e1a8e2ff88..67a99e46bd 100644 --- a/cpu/bf533/init_sdram.S +++ b/cpu/bf533/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S index 99ed920328..8694ca2c2c 100644 --- a/cpu/bf533/init_sdram_bootrom_initblock.S +++ b/cpu/bf533/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index c356d53aa6..7556ec9fbd 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c index 14d06cf8df..3d1c3bc8c2 100644 --- a/cpu/bf533/interrupts.c +++ b/cpu/bf533/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c index 55866896a0..05d9a1b67e 100644 --- a/cpu/bf533/ints.c +++ b/cpu/bf533/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 8ac6e3ff64..05fcfcccce 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "bf533_serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 67a60cf21e..c32fef6163 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; #if (CONFIG_CCLK_DIV == 1) @@ -143,8 +140,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -200,8 +197,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -209,8 +206,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -236,8 +233,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c index 19b1fde41d..7e156d5110 100644 --- a/cpu/bf533/traps.c +++ b/cpu/bf533/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile index 8b0f9c0e93..06d1aae4e2 100644 --- a/cpu/bf537/Makefile +++ b/cpu/bf537/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S index 5bda5bf97f..d9015c6d1a 100644 --- a/cpu/bf537/cache.S +++ b/cpu/bf537/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk index 8a35789f13..fbbe75dede 100644 --- a/cpu/bf537/config.mk +++ b/cpu/bf537/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf537 diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c index 62f603bdb0..7233908a07 100644 --- a/cpu/bf537/cpu.c +++ b/cpu/bf537/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -103,24 +103,20 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { if ((*pCHIPID >> 28) < 2) return; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -180,14 +176,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -195,13 +189,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 0daba63b68..ab7dd388c9 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -21,53 +21,10 @@ #include <asm/blackfin.h> #include <i2c.h> #include <asm/io.h> +#include <asm/mach-common/bits/twi.h> DECLARE_GLOBAL_DATA_PTR; -#define bfin_read16(addr) ({ unsigned __v; \ - __asm__ __volatile__ (\ - "%0 = w[%1] (z);\n\t"\ - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) - -#define bfin_write16(addr,val) ({\ - __asm__ __volatile__ (\ - "w[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val) - #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ if (gd->have_console) \ diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S index 897a5890ed..e9975000a2 100644 --- a/cpu/bf537/init_sdram.S +++ b/cpu/bf537/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S index f9adbb9715..197b836067 100644 --- a/cpu/bf537/init_sdram_bootrom_initblock.S +++ b/cpu/bf537/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S index a71df55a93..fe850bf2e3 100644 --- a/cpu/bf537/interrupt.S +++ b/cpu/bf537/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c index d2213b1156..853fa492c7 100644 --- a/cpu/bf537/interrupts.c +++ b/cpu/bf537/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk (void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c index 55866896a0..05d9a1b67e 100644 --- a/cpu/bf537/ints.c +++ b/cpu/bf537/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index f7a2483ffb..3c6a37016d 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART0_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); - *pUART_DLL = hw_baud_table[i].dl_low; - sync(); - *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + *pUART0_DLL = hw_baud_table[i].dl_low; + SSYNC(); + *pUART0_DLH = hw_baud_table[i].dl_high; + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART0_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART0_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART0_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART0_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART0_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); - uart_lsr_val = *pUART_LSR; /* Clear status bit */ - uart_rbr_val = *pUART_RBR; /* getc() */ + uart_lsr_val = *pUART0_LSR; /* Clear status bit */ + uart_rbr_val = *pUART0_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART0_LSR & THRE)) + continue; asm("csync;"); - *pUART_THR = ch; /* putc() */ - - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); + *pUART0_THR = ch; /* putc() */ return; } diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h index 76555c279d..e4e0b9aec6 100644 --- a/cpu/bf537/serial.h +++ b/cpu/bf537/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART0_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S index 4e02bcb9e5..a48f3c6c7b 100644 --- a/cpu/bf537/start.S +++ b/cpu/bf537/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .global _icache_enable; .global _dcache_enable; @@ -151,8 +148,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -291,8 +288,8 @@ postcopy: R1.H = (CFG_FLASH_BASE >> 16); R1.L = (CFG_FLASH_BASE & 0xFFFF); R0 = R0 + R1; /* Source Address */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); @@ -415,8 +412,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -424,8 +421,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -495,8 +492,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c index 4e18e27df4..51de322aed 100644 --- a/cpu/bf537/traps.c +++ b/cpu/bf537/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile index 29471694d9..418a4370eb 100644 --- a/cpu/bf561/Makefile +++ b/cpu/bf561/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S index 5bda5bf97f..d9015c6d1a 100644 --- a/cpu/bf561/cache.S +++ b/cpu/bf561/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk index f4dc04bfc9..3628a026b0 100644 --- a/cpu/bf561/config.mk +++ b/cpu/bf561/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf561 diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c index 5b907cd1ef..e0dd2f5ea8 100644 --- a/cpu/bf561/cpu.c +++ b/cpu/bf561/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -191,13 +185,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, clear it so we don't confuse the next application */ I0 = (unsigned int *)DCPLB_ADDR0; diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S index d763f274f9..f5ccf30f9a 100644 --- a/cpu/bf561/init_sdram.S +++ b/cpu/bf561/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S index 5e3c88ab6f..9cc5e78b04 100644 --- a/cpu/bf561/init_sdram_bootrom_initblock.S +++ b/cpu/bf561/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S index 21839ce7de..a10eaabe54 100644 --- a/cpu/bf561/interrupt.S +++ b/cpu/bf561/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c index ecbc6addfc..78800611a3 100644 --- a/cpu/bf561/interrupts.c +++ b/cpu/bf561/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c index 27a38a3493..d6aa393170 100644 --- a/cpu/bf561/ints.c +++ b/cpu/bf561/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SICA_IMASK0) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index bc5a4f5726..a398fd5f84 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include "serial.h" #include <asm/io.h> +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,32 +83,32 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* * Enable ERBFI and ELSI interrupts * to poll SIC_ISR register */ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -123,14 +121,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -138,7 +136,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -151,14 +149,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -179,19 +177,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h index c1cbf36acf..647560c35c 100644 --- a/cpu/bf561/serial.h +++ b/cpu/bf561/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S index bd26cf32f6..6565de8cfd 100644 --- a/cpu/bf561/start.S +++ b/cpu/bf561/start.S @@ -41,17 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .text @@ -127,16 +126,16 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); + p0.h = hi(SICA_IWR0); + p0.l = lo(SICA_IWR0); r0.l = 0x1; w[p0] = r0.l; SSYNC; @@ -193,8 +192,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -202,8 +201,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -218,13 +217,6 @@ WAIT_HERE: _real_start: [ -- sp ] = reti; -#ifdef CONFIG_EZKIT561 - p0.l = (WDOG_CTL & 0xFFFF); - p0.h = (WDOG_CTL >> 16); - r0 = WATCHDOG_DISABLE(z); - w[p0] = r0; -#endif - /* DMA reset code to Hi of L1 SRAM */ copy: P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ @@ -235,37 +227,37 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ DMA: R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */ /* Set Source DMAConfig = DMA Enable, Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3; - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4; WAIT_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); + p0.h = hi(IMDMA_D0_IRQ_STATUS); + p0.l = lo(IMDMA_D0_IRQ_STATUS); R0 = W[P0](Z); CC = BITTST(R0, 0); if ! CC jump WAIT_DMA_DONE R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ /* Initialize BSS Section with 0 s */ p1.l = __bss_start; diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c index 7e2dcd17ad..e35620c9ae 100644 --- a/cpu/bf561/traps.c +++ b/cpu/bf561/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, return * without doing anything. Then, if we get the same fault again, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/doc/README.blackfin b/doc/README.blackfin new file mode 100644 index 0000000000..a837d90f21 --- /dev/null +++ b/doc/README.blackfin @@ -0,0 +1,46 @@ +Notes for the Blackfin architecture port of Das U-Boot + + ========= + ! ABOUT ! + ========= + +<marketing blurb> +Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally +suited for products where a convergence of capabilities are necessary - +multi-format audio, video, voice and image processing; multi-mode baseband and +packet processing; control processing; and real-time security. The Blackfin's +unique combination of software flexibility and scalability has gained it +widespread adoption in convergent applications. +</marketing blurb> + +The Blackfin processor is wholly developed by Analog Devices Inc. + + =========== + ! SUPPORT ! + =========== + +All open source code for the Blackfin processors are being handled via our +collaborative website: +http://blackfin.uclinux.org/ + +In particular, bug reports, feature requests, help etc... for Das U-Boot are +handled in the Das U-Boot sub project: +http://blackfin.uclinux.org/gf/project/u-boot + +This website is backed both by an open source community as well as a dedicated +team from Analog Devices Inc. + + ============= + ! TOOLCHAIN ! + ============= + +To compile the Blackfin aspects, you'll need the GNU toolchain configured for +the Blackfin processor. You can obtain such a cross-compiler here: +http://blackfin.uclinux.org/gf/project/toolchain + + ================= + ! DOCUMENTATION ! + ================= + +For Blackfin specific documentation, you can visit our dedicated doc wiki: +http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot diff --git a/doc/README.standalone b/doc/README.standalone index f9237a65f5..81b949a0aa 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -19,11 +19,12 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: thus the compiler cannot perform type checks on these assignments. 2. The pointer to the jump table is passed to the application in a - machine-dependent way. PowerPC, ARM and MIPS architectures use a - dedicated register to hold the pointer to the 'global_data' - structure: r2 on PowerPC, r8 on ARM and k0 on MIPS. The x86 - architecture does not use such a register; instead, the pointer to - the 'global_data' structure is passed as 'argv[-1]' pointer. + machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures + use a dedicated register to hold the pointer to the 'global_data' + structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin. + The x86 architecture does not use such a register; instead, the + pointer to the 'global_data' structure is passed as 'argv[-1]' + pointer. The application can access the 'global_data' structure in the same way as U-Boot does: @@ -49,11 +50,12 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: 4. The default load and start addresses of the applications are as follows: - Load address Start address - x86 0x00040000 0x00040000 - PowerPC 0x00040000 0x00040004 - ARM 0x0c100000 0x0c100000 - MIPS 0x80200000 0x80200000 + Load address Start address + x86 0x00040000 0x00040000 + PowerPC 0x00040000 0x00040004 + ARM 0x0c100000 0x0c100000 + MIPS 0x80200000 0x80200000 + Blackfin 0x00001000 0x00001000 For example, the "hello world" application may be loaded and executed on a PowerPC board with the following commands: diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8c7f1484b6..2af2bf4a51 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)librtc.a COBJS-y += date.o -COBJS-y += bf5xx_rtc.o +COBJS-y += bfin_rtc.o COBJS-y += ds12887.o COBJS-y += ds1302.o COBJS-y += ds1306.o diff --git a/drivers/rtc/bf5xx_rtc.c b/drivers/rtc/bf5xx_rtc.c deleted file mode 100644 index 8856bb9b5f..0000000000 --- a/drivers/rtc/bf5xx_rtc.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux - * - * Copyright (C) 2003 Motorola Corporation. All rights reserved. - * Richard Xiao (A2590C@email.mot.com) - * - * Copyright (C) 1996 Paul Gortmaker - * - * - * Based on other minimal char device drivers, like Alan's - * watchdog, Ted's random, etc. etc. - * - * 1.07 Paul Gortmaker. - * 1.08 Miquel van Smoorenburg: disallow certain things on the - * DEC Alpha as the CMOS clock is also used for other things. - * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. - * 1.09a Pete Zaitcev: Sun SPARC - * 1.09b Jeff Garzik: Modularize, init cleanup - * 1.09c Jeff Garzik: SMP cleanup - * 1.10 Paul Barton-Davis: add support for async I/O - * 1.10a Andrea Arcangeli: Alpha updates - * 1.10b Andrew Morton: SMP lock fix - * 1.10c Cesar Barros: SMP locking fixes and cleanup - * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit - * 1.10e LG Soft India: Register access is different in BF533. - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE) - -#include <asm/blackfin.h> -#include <asm/arch/bf5xx_rtc.h> - -void rtc_reset(void) -{ - return; /* nothing to do */ -} - -/* Wait for pending writes to complete */ -void wait_for_complete(void) -{ - while (!(*(volatile unsigned short *)RTC_ISTAT & 0x8000)) { - printf(""); - } - *(volatile unsigned short *)RTC_ISTAT = 0x8000; -} - -/* Enable the RTC prescaler enable register */ -void rtc_init() -{ - *(volatile unsigned short *)RTC_PREN = 0x1; - wait_for_complete(); -} - -/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers - * based on this value. - */ -void rtc_set(struct rtc_time *tmp) -{ - unsigned long n_days_1970 = 0; - unsigned long n_secs_rem = 0; - unsigned long n_hrs = 0; - unsigned long n_mins = 0; - unsigned long n_secs = 0; - unsigned long time_in_secs; - - if (tmp == NULL) { - printf("Error setting the date/time \n"); - return; - } - - time_in_secs = - mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, - tmp->tm_min, tmp->tm_sec); - - /* Compute no. of days since 1970 */ - n_days_1970 = (unsigned long)(time_in_secs / (NUM_SECS_IN_DAY)); - - /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ - n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY)); - n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR); - n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR); - n_mins = n_secs_rem / (NUM_SECS_IN_MIN); - n_secs = n_secs_rem % (NUM_SECS_IN_MIN); - - /* Store the new time in the RTC_STAT register */ - *(volatile unsigned long *)RTC_STAT = - ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) | - (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF)); - - wait_for_complete(); -} - -/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ -void rtc_get(struct rtc_time *tmp) -{ - unsigned long cur_rtc_stat = 0; - unsigned long time_in_sec; - unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; - - if (tmp == NULL) { - printf("Error getting the date/time \n"); - return; - } - - /* Read the RTC_STAT register */ - cur_rtc_stat = *(volatile unsigned long *)RTC_STAT; - - /* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */ - tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f; - tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f; - tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f; - tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff; - - /* Calculate the total number of seconds since Jan 1970 */ - time_in_sec = (tm_sec) + - MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day); - to_tm(time_in_sec, tmp); -} -#endif diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c new file mode 100644 index 0000000000..5755a20bc5 --- /dev/null +++ b/drivers/rtc/bfin_rtc.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2004-2008 Analog Devices Inc. + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> + +#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE) + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/rtc.h> + +#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__) + +#define MIN_TO_SECS(x) (60 * (x)) +#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x)) +#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x)) + +#define NUM_SECS_IN_MIN MIN_TO_SECS(1) +#define NUM_SECS_IN_HR HRS_TO_SECS(1) +#define NUM_SECS_IN_DAY DAYS_TO_SECS(1) + +/* Our on-chip RTC has no notion of "reset" */ +void rtc_reset(void) +{ + return; +} + +/* Wait for pending writes to complete */ +static void wait_for_complete(void) +{ + pr_stamp(); + while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE)) + if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING)) + break; + bfin_write_RTC_ISTAT(WRITE_COMPLETE); +} + +/* Enable the RTC prescaler enable register */ +int rtc_init(void) +{ + pr_stamp(); + bfin_write_RTC_PREN(0x1); + return 0; +} + +/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers + * based on this value. + */ +void rtc_set(struct rtc_time *tmp) +{ + unsigned long remain, days, hrs, mins, secs; + + pr_stamp(); + + if (tmp == NULL) { + puts("Error setting the date/time\n"); + return; + } + + wait_for_complete(); + + /* Calculate number of seconds this incoming time represents */ + remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* Figure out how many days since epoch */ + days = remain / NUM_SECS_IN_DAY; + + /* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ + remain = remain % NUM_SECS_IN_DAY; + hrs = remain / NUM_SECS_IN_HR; + remain = remain % NUM_SECS_IN_HR; + mins = remain / NUM_SECS_IN_MIN; + secs = remain % NUM_SECS_IN_MIN; + + /* Encode these time values into our RTC_STAT register */ + bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs)); +} + +/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ +void rtc_get(struct rtc_time *tmp) +{ + uint32_t cur_rtc_stat; + int time_in_sec; + int tm_sec, tm_min, tm_hr, tm_day; + + pr_stamp(); + + if (tmp == NULL) { + puts("Error getting the date/time\n"); + return; + } + + wait_for_complete(); + + /* Read the RTC_STAT register */ + cur_rtc_stat = bfin_read_RTC_STAT(); + + /* Convert our encoded format into actual time values */ + tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P; + tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P; + tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P; + tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P; + + /* Calculate the total number of seconds since epoch */ + time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day); + to_tm(time_in_sec, tmp); +} + +#endif diff --git a/examples/.gitignore b/examples/.gitignore index f547024784..059b09641a 100644 --- a/examples/.gitignore +++ b/examples/.gitignore @@ -1,5 +1,6 @@ /hello_world /interrupt /sched +/smc91111_eeprom *.bin *.srec diff --git a/examples/Makefile b/examples/Makefile index 71a8c7f3ab..d63fa70323 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -91,13 +91,9 @@ BIN += sched.bin endif ifeq ($(ARCH),blackfin) -ifneq ($(BOARD),bf537-stamp) -ifneq ($(BOARD),bf537-pnav) ELF += smc91111_eeprom SREC += smc91111_eeprom.srec -BIN += smc91111_eeprom.bin -endif -endif +BIN += smc91111_eeprom.bin endif # The following example is pretty 8xx specific... @@ -166,7 +162,7 @@ $(LIB): $(obj).depend $(LIBOBJS) $(ELF): $(obj)%: $(obj)%.o $(LIB) $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ - -o $@ -e $(notdir $(<:.o=)) $< $(LIB) \ + -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc $(SREC): diff --git a/examples/smc91111_eeprom b/examples/smc91111_eeprom Binary files differnew file mode 100755 index 0000000000..1009fecaca --- /dev/null +++ b/examples/smc91111_eeprom diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c index b8a3594e9e..f5d8c6ab42 100644 --- a/examples/smc91111_eeprom.c +++ b/examples/smc91111_eeprom.c @@ -31,6 +31,13 @@ #include <exports.h> #include "../drivers/net/smc91111.h" +#ifdef CONFIG_DRIVER_SMC91111 + +#ifdef pFIO0_DIR +# define pFIO_DIR pFIO0_DIR +# define pFIO_FLAG_S pFIO0_FLAG_S +#endif + #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE #define EEPROM 0x1; #define MAC 0x2; @@ -59,17 +66,9 @@ int smc91111_eeprom (int argc, char *argv[]) return (0); } - asm ("p2.h = 0xFFC0;"); - asm ("p2.l = 0x0730;"); - asm ("r0 = 0x01;"); - asm ("w[p2] = r0;"); - asm ("ssync;"); - - asm ("p2.h = 0xffc0;"); - asm ("p2.l = 0x0708;"); - asm ("r0 = 0x01;"); - asm ("w[p2] = r0;"); - asm ("ssync;"); + *pFIO_DIR = 0x01; + *pFIO_FLAG_S = 0x01; + SSYNC(); if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { printf ("Can't find SMSC91111\n"); @@ -387,3 +386,13 @@ void dump_reg (void) printf ("\n"); } } + +#else + +int smc91111_eeprom (int argc, char *argv[]) +{ + printf("Not supported for this board\n"); + return 1; +} + +#endif diff --git a/include/.gitignore b/include/.gitignore index ab7d4c76f4..03a533ced4 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,5 +1,6 @@ /autoconf.mk* /asm +/asm-blackfin/arch /asm-ppc/arch /bmp_logo.h /config.h diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h deleted file mode 100644 index 4fe425c9c1..0000000000 --- a/include/asm-blackfin/arch-bf533/anomaly.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * File: include/asm-blackfin/arch-bf533/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* This file shoule be up to date with: - * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List - * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List - * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 or 0.2 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) -#error Kernel will not work on BF533 Version 0.1 or 0.2 -#endif - -/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on - every corresponding match */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ -#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ -#endif - -/* These issues only occur on 0.3 or 0.4 BF533 */ -#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ -#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data - Cache Fill can be corrupted after or during - Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ -#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by - preceding memory read */ -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ -#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag - situation */ -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data*/ -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ -#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware - errors */ -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to increase. */ -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ -#endif - -/* These issues are only on 0.4 silicon */ -#if (defined(CONFIG_BF_REV_0_4)) -#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ -#endif - -/* These issues are only on 0.3 silicon */ -#if defined(CONFIG_BF_REV_0_3) -#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ -#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative - Instruction or Data Fetches, or by Fetches at the - boundary of reserved memory space */ -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ -#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data - corruption */ -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ -#define ANOMALY_05000201 /* Receive frame sync not ignored during active - frames in sport MCM */ -#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA - stopping */ -#if defined(CONFIG_BF533) -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ -#endif /* CONFIG_BF533 */ -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ -#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame - Sync Transmit Mode */ -#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ -#endif - -#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf533/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h deleted file mode 100644 index 65749ee458..0000000000 --- a/include/asm-blackfin/arch-bf533/bf533_serial.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * U-boot bf533_serial.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF533_SERIAL_H_ -#define _BF533_SERIAL_H_ - -#define BYTE_REF(addr) (*((volatile char*)addr)) -#define HALFWORD_REF(addr) (*((volatile short*)addr)) -#define WORD_REF(addr) (*((volatile long*)addr)) - -#define UART_THR_LO HALFWORD_REF(UART_THR) -#define UART_RBR_LO HALFWORD_REF(UART_RBR) -#define UART_DLL_LO HALFWORD_REF(UART_DLL) -#define UART_IER_LO HALFWORD_REF(UART_IER) -#define UART_IER_ERBFI 0x01 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ELSI 0x04 -#define UART_IER_EDDSI 0x08 - -#define UART_DLH_LO HALFWORD_REF(UART_DLH) -#define UART_IIR_LO HALFWORD_REF(UART_IIR) -#define UART_IIR_NOINT 0x01 -#define UART_IIR_STATUS 0x06 -#define UART_IIR_LSR 0x06 -#define UART_IIR_RBR 0x04 -#define UART_IIR_THR 0x02 -#define UART_IIR_MSR 0x00 - -#define UART_LCR_LO HALFWORD_REF(UART_LCR) -#define UART_LCR_WLS5 0 -#define UART_LCR_WLS6 0x01 -#define UART_LCR_WLS7 0x02 -#define UART_LCR_WLS8 0x03 -#define UART_LCR_STB 0x04 -#define UART_LCR_PEN 0x08 -#define UART_LCR_EPS 0x10 -#define UART_LCR_SP 0x20 -#define UART_LCR_SB 0x40 -#define UART_LCR_DLAB 0x80 - -#define UART_MCR_LO HALFWORD_REF(UART_MCR) - -#define UART_LSR_LO HALFWORD_REF(UART_LSR) -#define UART_LSR_DR 0x01 -#define UART_LSR_OE 0x02 -#define UART_LSR_PE 0x04 -#define UART_LSR_FE 0x08 -#define UART_LSR_BI 0x10 -#define UART_LSR_THRE 0x20 -#define UART_LSR_TEMT 0x40 - -#define UART_MSR_LO HALFWORD_REF(UART_MSR) -#define UART_SCR_LO HALFWORD_REF(UART_SCR) -#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) -#define UART_GCTL_UCEN 0x01 - -#endif diff --git a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h deleted file mode 100644 index f4440a8d47..0000000000 --- a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * U-boot - bf533_rtc.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF533_RTC_H_ -#define _BF533_RTC_H_ - -void rtc_init(void); -void wait_for_complete(void); -void rtc_reset(void); - -#define MIN_TO_SECS(_x_) (60 * _x_) -#define HRS_TO_SECS(_x_) (60 * 60 * _x_) -#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) - -#define NUM_SECS_IN_DAY (24 * 3600) -#define NUM_SECS_IN_HOUR (3600) -#define NUM_SECS_IN_MIN (60) - -/* Shift values for RTC_STAT register */ -#define DAY_BITS_OFF 17 -#define HOUR_BITS_OFF 12 -#define MIN_BITS_OFF 6 -#define SEC_BITS_OFF 0 - -#endif diff --git a/include/asm-blackfin/arch-bf533/cdefBF531.h b/include/asm-blackfin/arch-bf533/cdefBF531.h deleted file mode 100644 index 3877db89e2..0000000000 --- a/include/asm-blackfin/arch-bf533/cdefBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF531_H -#define _CDEFBF531_H - -#include <asm/arch-bf533/cdefBF532.h> - -#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/arch-bf533/cdefBF532.h b/include/asm-blackfin/arch-bf533/cdefBF532.h deleted file mode 100644 index bca1ed1ac1..0000000000 --- a/include/asm-blackfin/arch-bf533/cdefBF532.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * cdefBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEF_BF532_H -#define _CDEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning cdefBF532.h should only be included for 532 compatible chips. - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/arch-bf533/defBF532.h> - -/* include core specific register pointer definitions */ -#include <asm/arch-common/cdef_LPBlackfin.h> - -/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ -#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) -#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) -#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) -#define pCHIPID ((volatile unsigned long *)CHIPID) -#define pSWRST ((volatile unsigned short *)SWRST) -#define pSYSCR ((volatile unsigned short *)SYSCR) -#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) -#define pVR_CTL ((volatile unsigned short *)VR_CTL) - -/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ -#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) -#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) -#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) -#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) -#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) -#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) -#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) - -/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ -#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) -#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) -#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) - -/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ -#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) -#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) -#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) -#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) -#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) -#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) -#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) - -/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ -#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) -#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) -#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) -#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) -#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) -#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) -#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) -#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) -#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) -#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) -#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) -#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) -#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) -#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) -#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) -#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) -#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) - -/* DMA Test Registers */ -#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) -#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) -#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) -#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) -#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) -#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) -#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) -#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) -#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) -#define pDMA_TMMA ((volatile void **)DMA_TMMA) - -/* DMA Controller */ -#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) -#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) -#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) -#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) -#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) -#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) -#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) -#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) -#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) -#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) -#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) -#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) -#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) - -#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) -#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) -#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) -#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) -#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) -#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) -#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) -#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) -#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) -#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) -#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) -#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) -#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) - -#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) -#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) -#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) -#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) -#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) -#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) -#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) -#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) -#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) -#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) -#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) -#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) -#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) - -#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) -#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) -#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) -#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) -#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) -#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) -#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) -#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) -#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) -#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) -#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) -#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) -#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) - -#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) -#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) -#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) -#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) -#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) -#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) -#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) -#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) -#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) -#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) -#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) -#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) -#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) - -#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) -#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) -#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) -#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) -#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) -#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) -#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) -#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) -#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) -#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) -#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) -#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) -#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) - -#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) -#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) -#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) -#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) -#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) -#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) -#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) -#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) -#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) -#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) -#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) -#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) -#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) - -#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) -#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) -#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) -#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) -#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) -#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) -#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) -#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) -#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) -#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) -#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) -#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) -#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) - -#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) -#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) -#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) -#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) -#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) -#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) -#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) -#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) -#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) -#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) -#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) -#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) -#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) - -#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) -#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) -#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) -#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) -#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) -#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) -#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) -#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) -#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) -#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) -#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) -#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) -#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) - -#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) -#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) -#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) -#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) -#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) -#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) -#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) -#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) -#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) -#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) -#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) -#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) -#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) - -#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) -#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) -#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) -#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) -#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) -#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) -#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) -#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) -#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) -#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) -#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) -#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) -#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) - -/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ -#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) -#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) -#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) - -/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ -/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ -/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ - -/* - * #define pDB_ACOMP ((volatile void **)DB_ACOMP) - * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) - */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ -#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) -#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) -#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) -#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) - -/* UART Controller */ -#define pUART_THR ((volatile unsigned short *)UART_THR) -#define pUART_RBR ((volatile unsigned short *)UART_RBR) -#define pUART_DLL ((volatile unsigned short *)UART_DLL) -#define pUART_IER ((volatile unsigned short *)UART_IER) -#define pUART_DLH ((volatile unsigned short *)UART_DLH) -#define pUART_IIR ((volatile unsigned short *)UART_IIR) -#define pUART_LCR ((volatile unsigned short *)UART_LCR) -#define pUART_MCR ((volatile unsigned short *)UART_MCR) -#define pUART_LSR ((volatile unsigned short *)UART_LSR) - -/* - * #define UART_MSR - */ -#define pUART_SCR ((volatile unsigned short *)UART_SCR) -#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) - -/* SPI Controller */ -#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) -#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) -#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) -#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) -#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) -#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) -#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) - -/* TIMER 0, 1, 2 Registers */ -#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) -#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) -#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) -#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) - -#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) -#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) -#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) -#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) - -#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) -#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) -#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) -#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) - -#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) -#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) -#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) - -/* SPORT0 Controller */ -#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) -#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) -#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) -#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) -#define pSPORT0_TX ((volatile long *)SPORT0_TX) -#define pSPORT0_RX ((volatile long *)SPORT0_RX) -#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) -#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) -#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) -#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) -#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) -#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) -#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) -#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) -#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) -#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) -#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) -#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) -#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) -#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) -#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) -#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) - -/* SPORT1 Controller */ -#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) -#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) -#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) -#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) -#define pSPORT1_TX ((volatile long *)SPORT1_TX) -#define pSPORT1_RX ((volatile long *)SPORT1_RX) -#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) -#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) -#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) -#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) -#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) -#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) -#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) -#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) -#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) -#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) -#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) -#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) -#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) -#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) -#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) -#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) - -/* Parallel Peripheral Interface (PPI) */ -#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) -#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) -#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) -#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) -#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) - -#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/arch-bf533/cdefBF533.h b/include/asm-blackfin/arch-bf533/cdefBF533.h deleted file mode 100644 index c72bac91e0..0000000000 --- a/include/asm-blackfin/arch-bf533/cdefBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF533_H -#define _CDEFBF533_H - -#include <asm/arch-bf533/cdefBF532.h> - -#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF531.h b/include/asm-blackfin/arch-bf533/defBF531.h deleted file mode 100644 index 6c7cd5a6db..0000000000 --- a/include/asm-blackfin/arch-bf533/defBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF531_H -#define _DEFBF531_H - -#include <defBF532.h> - -#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h deleted file mode 100644 index 25a74e6846..0000000000 --- a/include/asm-blackfin/arch-bf533/defBF532.h +++ /dev/null @@ -1,1159 +0,0 @@ -/* - * defBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ - -#ifndef _DEF_BF532_H -#define _DEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning defBF532.h should only be included for 532 compatible chips - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/arch-common/def_LPBlackfin.h> - -/* Helper macros - * usage: - * P0.H = HI(UART_THR); - * P0.L = LO(UART_THR); - */ - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Test Registers */ -#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ -#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ -#define DMA_MISR 0xFFC00B08 /* MISR Register */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ -#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ -#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ -#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ -#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ -#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ -#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ -#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ - -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ - -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ - -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ - -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ - -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ - -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ - -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ - -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ - -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ - -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ - -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/* - * System MMR Register Bits - */ -/* - * PLL AND RESET MASKS - */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ -#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x00000008 /* Core clock off */ -#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ -#define BYPASS 0x00000100 /* Bypass the PLL */ - -/* PLL_DIV Masks */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ - -/* - * SYSTEM INTERRUPT CONTROLLER MASKS - */ - -/* SIC_IAR0 Masks */ -#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Masks */ -#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Masks */ -#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* - * WATCHDOG TIMER MASKS - */ -/* Watchdog Timer WDOG_CTL Register */ -#define ICTL(x) ((x<<1) & 0x0006) -#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ -#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ -#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ -#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ - -#define TMR_EN 0x0000 -#define TMR_DIS 0x0AD0 -#define TRO 0x8000 - -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -/* RTC_STAT and RTC_ALARM register */ -#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ -#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ -#define RTHR 0x0001F000 /* Real-Time Clock Hours */ -#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ - -/* RTC_ICTL register */ -#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ -#define AIE 0x0002 /* Alarm Interrupt Enable */ -#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ -#define MIE 0x0008 /* Minutes Interrupt Enable */ -#define HIE 0x0010 /* Hours Interrupt Enable */ -#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ -#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ -#define WCIE 0x8000 /* Write Complete Interrupt Enable */ - -/* RTC_ISTAT register */ -#define SWEF 0x0001 /* Stopwatch Event Flag */ -#define AEF 0x0002 /* Alarm Event Flag */ -#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ -#define MEF 0x0008 /* Minutes Event Flag */ -#define HEF 0x0010 /* Hours Event Flag */ -#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ -#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ -#define WPS 0x4000 /* Write Pending Status (RO) */ -#define WCOM 0x8000 /* Write Complete */ - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ -#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR Register */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* - * SERIAL PORT MASKS - */ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /*TX Word Length */ -#define TXSE 0x0100 /*TX Secondary Enable */ -#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /*TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define RULAW 0x0008 /* u-Law enable */ -#define RALAW 0x000C /* A-Law enable */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ -#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ -#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /* Multichannel Frame Delay */ - -/* - * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS - */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* - * DMA CONTROLLER MASKS - */ - -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define FLOW 0x00007000 /* Flow Control */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -/* - * GENERAL PURPOSE TIMER MASKS - */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 -#define TIMIL1 0x0002 -#define TIMIL2 0x0004 -#define TOVL_ERR0 0x0010 -#define TOVL_ERR1 0x0020 -#define TOVL_ERR2 0x0040 -#define TRUN0 0x1000 -#define TRUN1 0x2000 -#define TRUN2 0x4000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVL_ERR0_P 0x04 -#define TOVL_ERR1_P 0x05 -#define TOVL_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* - * PROGRAMMABLE FLAG MASKS - */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* - * SERIAL PERIPHERAL INTERFACE (SPI) MASKS - */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* - * ASYNCHRONOUS MEMORY CONTROLLER MASKS - */ - -/* AMGCTL Masks */ -#define AMCKEN 0x00000001 /* Enable CLKOUT */ -#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* - * SDRAM CONTROLLER MASKS - */ - -/* SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - -#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF533.h b/include/asm-blackfin/arch-bf533/defBF533.h deleted file mode 100644 index 90e50afa7f..0000000000 --- a/include/asm-blackfin/arch-bf533/defBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF533_H -#define _DEFBF533_H - -#include <asm/cpu/defBF532.h> - -#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF533_extn.h b/include/asm-blackfin/arch-bf533/defBF533_extn.h deleted file mode 100644 index 045e8e49f8..0000000000 --- a/include/asm-blackfin/arch-bf533/defBF533_extn.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * defBF533_extn.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEF_BF533_EXTN_H -#define _DEF_BF533_EXTN_H - -/* define macro for offset */ -#define OFFSET_( x ) ((x) & 0x0000FFFF) -/* Delay inserted for PLL transition */ -#define PLL_DELAY 0x1000 - -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA10000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF808000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF908000 -#define SYSMMR_BASE 0xFFC00000 -#define WDSIZE16 0x00000004 - -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 - -/* IMASK Bit values */ -#define IVG15_POS 0x00008000 -#define IVG14_POS 0x00004000 -#define IVG13_POS 0x00002000 -#define IVG12_POS 0x00001000 -#define IVG11_POS 0x00000800 -#define IVG10_POS 0x00000400 -#define IVG9_POS 0x00000200 -#define IVG8_POS 0x00000100 -#define IVG7_POS 0x00000080 -#define IVGTMR_POS 0x00000040 -#define IVGHW_POS 0x00000020 - -#define WDOG_TMR_DISABLE (0xAD << 4) -#define ICTL_RST 0x00000000 -#define ICTL_NMI 0x00000002 -#define ICTL_GP 0x00000004 -#define ICTL_DISABLE 0x00000003 - -/* Watch Dog timer values setup */ -#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE - -#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/arch-bf533/irq.h b/include/asm-blackfin/arch-bf533/irq.h deleted file mode 100644 index 323574590b..0000000000 --- a/include/asm-blackfin/arch-bf533/irq.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * U-boot bf533_irq.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c - * Changed by HuTao Apr18, 2003 - * - * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- - * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle - * - * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> - * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) - * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> - * - * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF533_IRQ_H_ -#define _BF533_IRQ_H_ - -/* - * Interrupt source definitions - * Event Source Core Event Name Number - * EMU 0 - * Reset RST 1 - * NMI NMI 2 - * Exception EVX 3 - * Reserved -- 4 - * Hardware Error IVHW 5 - * Core Timer IVTMR 6 - * PLL Wakeup Interrupt IVG7 7 - * DMA Error (generic) IVG7 8 - * PPI Error Interrupt IVG7 9 - * SPORT0 Error Interrupt IVG7 10 - * SPORT1 Error Interrupt IVG7 11 - * SPI Error Interrupt IVG7 12 - * UART Error Interrupt IVG7 13 - * RTC Interrupt IVG8 14 - * DMA0 Interrupt (PPI) IVG8 15 - * DMA1 (SPORT0 RX) IVG9 16 - * DMA2 (SPORT0 TX) IVG9 17 - * DMA3 (SPORT1 RX) IVG9 18 - * DMA4 (SPORT1 TX) IVG9 19 - * DMA5 (PPI) IVG10 20 - * DMA6 (UART RX) IVG10 21 - * DMA7 (UART TX) IVG10 22 - * Timer0 IVG11 23 - * Timer1 IVG11 24 - * Timer2 IVG11 25 - * PF Interrupt A IVG12 26 - * PF Interrupt B IVG12 27 - * DMA8/9 Interrupt IVG13 28 - * DMA10/11 Interrupt IVG13 29 - * Watchdog Timer IVG13 30 - * Software Interrupt 1 IVG14 31 - * Software Interrupt 2 -- - * (lowest priority) IVG15 32 - */ - -/* The ABSTRACT IRQ definitions */ - -/* The first seven of the following are fixed, - * the rest you change if you need to - */ - -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ -#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ -#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ -#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ -#define IRQ_RTC 14 /* RTC Interrupt */ -#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ -#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ -#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ -#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ -#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ -#define IRQ_TMR0 23 /* Timer 0 */ -#define IRQ_TMR1 24 /* Timer 1 */ -#define IRQ_TMR2 25 /* Timer 2 */ -#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ -#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ -#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ -#define IRQ_WATCH 30 /* Watch Dog Timer */ -#define IRQ_SW_INT1 31 /* Software Int 1 */ -#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ - -#define IRQ_UART_RX_BIT 0x4000 -#define IRQ_UART_TX_BIT 0x8000 -#define IRQ_UART_ERROR_BIT 0x40 - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 -#define SYS_IRQS 33 - -#endif diff --git a/include/asm-blackfin/arch-bf537/anomaly.h b/include/asm-blackfin/arch-bf537/anomaly.h deleted file mode 100644 index 50b44da986..0000000000 --- a/include/asm-blackfin/arch-bf537/anomaly.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * File: include/asm-blackfin/arch-bf537/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* This file shoule be up to date with: - * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List - * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List - * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1)) -#error Kernel will not work on BF537/6/4 Version 0.1 -#endif - -#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits */ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is - Changed */ -#endif -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage */ -#endif - -#if defined(CONFIG_BF_REV_0_2) -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */ -#endif -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */ -#endif -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ -#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running - and non-zero DEB_TRAFFIC_PERIOD value */ -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000280 /* SPI Master boot mode does not work well with - Atmel Dataflash devices */ - -#endif /* CONFIG_BF_REV_0_2 */ - -#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h deleted file mode 100644 index 64088f243c..0000000000 --- a/include/asm-blackfin/arch-bf537/bf537_serial.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * U-boot bf537_serial.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF537_SERIAL_H_ -#define _BF537_SERIAL_H_ - -#define BYTE_REF(addr) (*((volatile char*)addr)) -#define HALFWORD_REF(addr) (*((volatile short*)addr)) -#define WORD_REF(addr) (*((volatile long*)addr)) - -#define UART_THR_LO HALFWORD_REF(UART_THR) -#define UART_RBR_LO HALFWORD_REF(UART_RBR) -#define UART_DLL_LO HALFWORD_REF(UART_DLL) -#define UART_IER_LO HALFWORD_REF(UART_IER) -#define UART_IER_ERBFI 0x01 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ELSI 0x04 -#define UART_IER_EDDSI 0x08 - -#define UART_DLH_LO HALFWORD_REF(UART_DLH) -#define UART_IIR_LO HALFWORD_REF(UART_IIR) -#define UART_IIR_NOINT 0x01 -#define UART_IIR_STATUS 0x06 -#define UART_IIR_LSR 0x06 -#define UART_IIR_RBR 0x04 -#define UART_IIR_THR 0x02 -#define UART_IIR_MSR 0x00 - -#define UART_LCR_LO HALFWORD_REF(UART_LCR) -#define UART_LCR_WLS5 0 -#define UART_LCR_WLS6 0x01 -#define UART_LCR_WLS7 0x02 -#define UART_LCR_WLS8 0x03 -#define UART_LCR_STB 0x04 -#define UART_LCR_PEN 0x08 -#define UART_LCR_EPS 0x10 -#define UART_LCR_SP 0x20 -#define UART_LCR_SB 0x40 -#define UART_LCR_DLAB 0x80 - -#define UART_MCR_LO HALFWORD_REF(UART_MCR) - -#define UART_LSR_LO HALFWORD_REF(UART_LSR) -#define UART_LSR_DR 0x01 -#define UART_LSR_OE 0x02 -#define UART_LSR_PE 0x04 -#define UART_LSR_FE 0x08 -#define UART_LSR_BI 0x10 -#define UART_LSR_THRE 0x20 -#define UART_LSR_TEMT 0x40 - -#define UART_MSR_LO HALFWORD_REF(UART_MSR) -#define UART_SCR_LO HALFWORD_REF(UART_SCR) -#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) -#define UART_GCTL_UCEN 0x01 - -#endif diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h deleted file mode 100644 index db5cc6f226..0000000000 --- a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * U-boot - bf537_rtc.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF537_RTC_H_ -#define _BF537_RTC_H_ - -void rtc_init(void); -void wait_for_complete(void); -void rtc_reset(void); - -#define MIN_TO_SECS(_x_) (60 * _x_) -#define HRS_TO_SECS(_x_) (60 * 60 * _x_) -#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) - -#define NUM_SECS_IN_DAY (24 * 3600) -#define NUM_SECS_IN_HOUR (3600) -#define NUM_SECS_IN_MIN (60) - -/* Shift values for RTC_STAT register */ -#define DAY_BITS_OFF 17 -#define HOUR_BITS_OFF 12 -#define MIN_BITS_OFF 6 -#define SEC_BITS_OFF 0 - -#endif diff --git a/include/asm-blackfin/arch-bf537/cdefBF534.h b/include/asm-blackfin/arch-bf537/cdefBF534.h deleted file mode 100644 index 5a89e92536..0000000000 --- a/include/asm-blackfin/arch-bf537/cdefBF534.h +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * Copyright (C) 2005 Analog Devices Inc., All Rights Reserved. - * - *********************************************************************************** - * - * This include file contains a list of macro "defines" to enable the programmer - * to use symbolic names for register-access. - * - * ---------------------------- - * revision 0.1 - * date: 2005/01/27 14:31:01; author: joeb - * Initial revision - */ - -/* - * System MMR Register Map - */ - -#ifndef _CDEF_BF534_H -#define _CDEF_BF534_H - -/* Include all Core registers and bit definitions */ -#include <asm/arch-bf537/defBF534.h> - -/* Include core specific register pointer definitions */ -#include <asm/arch-common/cdef_LPBlackfin.h> - -#define pCHIPID ((volatile unsigned long *)CHIPID) - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) -#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) -#define pVR_CTL ((volatile unsigned short *)VR_CTL) -#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) -#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define pSWRST ((volatile unsigned short *)SWRST) -#define pSYSCR ((volatile unsigned short *)SYSCR) -#define pSIC_RVECT ((void * volatile *)SIC_RVECT) -#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) -#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) -#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) -#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) -#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) -#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) -#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) -#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) -#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) -#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) -#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) -#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) -#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) -#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) -#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define pUART0_THR ((volatile unsigned short *)UART0_THR) -#define pUART0_RBR ((volatile unsigned short *)UART0_RBR) -#define pUART0_DLL ((volatile unsigned short *)UART0_DLL) -#define pUART0_IER ((volatile unsigned short *)UART0_IER) -#define pUART0_DLH ((volatile unsigned short *)UART0_DLH) -#define pUART0_IIR ((volatile unsigned short *)UART0_IIR) -#define pUART0_LCR ((volatile unsigned short *)UART0_LCR) -#define pUART0_MCR ((volatile unsigned short *)UART0_MCR) -#define pUART0_LSR ((volatile unsigned short *)UART0_LSR) -#define pUART0_MSR ((volatile unsigned short *)UART0_LSR) -#define pUART0_SCR ((volatile unsigned short *)UART0_SCR) -#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL) - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) -#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) -#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) -#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) -#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) -#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) -#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) -#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) -#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) -#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) - -#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) -#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) -#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) -#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) - -#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) -#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) -#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) -#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) - -#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG) -#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER) -#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD) -#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH) - -#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG) -#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER) -#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD) -#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH) - -#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG) -#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER) -#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD) -#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH) - -#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG) -#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER) -#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD) -#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH) - -#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG) -#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER) -#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD) -#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH) - -#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) -#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) -#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS) - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define pPORTFIO ((volatile unsigned short *)PORTFIO) -#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR) -#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET) -#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE) -#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA) -#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR) -#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET) -#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE) -#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB) -#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR) -#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET) -#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE) -#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR) -#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR) -#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE) -#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH) -#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN) - -#define pFIO_DIR pPORTFIO_DIR -#define pFIO_FLAG_C pPORTFIO_CLEAR -#define pFIO_FLAG_S pPORTFIO_SET -#define pFIO_INEN pPORTFIO_INEN -#define pFIO_FLAG_D pPORTFIO - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) -#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) -#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) -#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) -#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX) -#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX) -#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) -#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) -#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) -#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) -#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) -#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) -#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) -#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) -#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) -#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) -#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) -#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) -#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) -#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) -#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) -#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) -#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) -#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) -#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) -#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX) -#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX) -#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) -#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) -#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) -#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) -#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) -#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) -#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) -#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) -#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) -#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) -#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) -#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) -#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) -#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) -#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) -#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) -#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) -#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) -#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) -#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) -#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) -#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) - -/* DMA Traffic Control Registers */ -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) - -/* DMA Controller */ -#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) -#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) -#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) -#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) -#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) -#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) -#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) -#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) -#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) - -#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) -#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) -#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) -#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) -#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) -#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) -#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) -#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) -#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) - -#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) -#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) -#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) -#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) -#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) -#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) -#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) -#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) -#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) - -#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) -#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) -#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) -#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) -#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) -#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) -#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) -#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) -#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) - -#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) -#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) -#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) -#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) -#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) -#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) -#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) -#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) -#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) - -#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) -#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) -#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) -#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) -#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) -#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) -#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) -#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) -#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) - -#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) -#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) -#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) -#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) -#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) -#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) -#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) -#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) -#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) - -#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) -#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) -#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) -#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) -#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) -#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) -#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) -#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) -#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) - -#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) -#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT) -#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT) -#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY) -#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) -#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT) -#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT) -#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS) -#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP) - -#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) -#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT) -#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT) -#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY) -#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) -#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT) -#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT) -#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS) -#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP) - -#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) -#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT) -#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT) -#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY) -#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) -#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT) -#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT) -#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS) -#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP) - -#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) -#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT) -#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT) -#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY) -#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) -#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT) -#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT) -#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS) -#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP) - -#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) -#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) -#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) -#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) -#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) -#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) -#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) -#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) -#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) - -#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) -#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) -#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) -#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) -#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) -#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) -#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) -#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) -#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) - -#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) -#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) -#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) -#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) -#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) -#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) -#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) -#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) -#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) - -#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) -#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) -#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) -#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) -#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) -#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) -#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) -#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) -#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) -#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) -#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) -#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) -#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV) -#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL) -#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL) -#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT) -#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR) -#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL) -#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT) -#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR) -#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT) -#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK) -#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL) -#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT) -#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8) -#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16) -#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8) -#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16) - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define pPORTGIO ((volatile unsigned short *)PORTGIO) -#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR) -#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET) -#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE) -#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA) -#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR) -#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET) -#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE) -#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB) -#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR) -#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET) -#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE) -#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR) -#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR) -#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE) -#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH) -#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN) - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define pPORTHIO ((volatile unsigned short *)PORTHIO) -#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR) -#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET) -#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE) -#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA) -#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR) -#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET) -#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE) -#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB) -#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR) -#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET) -#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE) -#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR) -#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR) -#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE) -#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH) -#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN) - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define pUART1_THR ((volatile unsigned short *)UART1_THR) -#define pUART1_RBR ((volatile unsigned short *)UART1_RBR) -#define pUART1_DLL ((volatile unsigned short *)UART1_DLL) -#define pUART1_IER ((volatile unsigned short *)UART1_IER) -#define pUART1_DLH ((volatile unsigned short *)UART1_DLH) -#define pUART1_IIR ((volatile unsigned short *)UART1_IIR) -#define pUART1_LCR ((volatile unsigned short *)UART1_LCR) -#define pUART1_MCR ((volatile unsigned short *)UART1_MCR) -#define pUART1_LSR ((volatile unsigned short *)UART1_LSR) -#define pUART1_MSR ((volatile unsigned short *)UART1_LSR) -#define pUART1_SCR ((volatile unsigned short *)UART1_SCR) -#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL) - -/* default UART controller */ -#if (CONFIG_UART_CONSOLE==1) - -#define pUART_THR pUART1_THR -#define pUART_RBR pUART1_RBR -#define pUART_DLL pUART1_DLL -#define pUART_IER pUART1_IER -#define pUART_DLH pUART1_DLH -#define pUART_IIR pUART1_IIR -#define pUART_LCR pUART1_LCR -#define pUART_MCR pUART1_MCR -#define pUART_LSR pUART1_LSR -#define pUART_MSR pUART1_MSR -#define pUART_SCR pUART1_SCR -#define pUART_GCTL pUART1_GCTL - -#else - -#define pUART_THR pUART0_THR -#define pUART_RBR pUART0_RBR -#define pUART_DLL pUART0_DLL -#define pUART_IER pUART0_IER -#define pUART_DLH pUART0_DLH -#define pUART_IIR pUART0_IIR -#define pUART_LCR pUART0_LCR -#define pUART_MCR pUART0_MCR -#define pUART_LSR pUART0_LSR -#define pUART_MSR pUART0_MSR -#define pUART_SCR pUART0_SCR -#define pUART_GCTL pUART0_GCTL - -#endif - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1) -#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1) -#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1) -#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1) -#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1) -#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1) -#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1) -#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1) -#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1) -#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1) -#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1) -#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1) -#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1) - -/* For Mailboxes 16-31 */ -#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2) -#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2) -#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2) -#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2) -#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2) -#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2) -#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2) -#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2) -#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2) -#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2) -#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2) -#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2) -#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2) - -#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK) -#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING) -#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG) -#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS) -#define pCAN_CEC ((volatile unsigned short *)CAN_CEC) -#define pCAN_GIS ((volatile unsigned short *)CAN_GIS) -#define pCAN_GIM ((volatile unsigned short *)CAN_GIM) -#define pCAN_GIF ((volatile unsigned short *)CAN_GIF) -#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL) -#define pCAN_INTR ((volatile unsigned short *)CAN_INTR) -#define pCAN_SFCMVER ((volatile unsigned short *)CAN_SFCMVER) -#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD) -#define pCAN_EWR ((volatile unsigned short *)CAN_EWR) -#define pCAN_ESR ((volatile unsigned short *)CAN_ESR) -#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG) -#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT) -#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC) -#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF) -#define pCAN_SFCMVER2 ((volatile unsigned short *)CAN_SFCMVER2) - -/* Mailbox Acceptance Masks */ -#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L) -#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H) -#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L) -#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H) -#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L) -#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H) -#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L) -#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H) -#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L) -#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H) -#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L) -#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H) -#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L) -#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H) -#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L) -#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H) -#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L) -#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H) -#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L) -#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H) -#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L) -#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H) -#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L) -#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H) -#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L) -#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H) -#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L) -#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H) -#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L) -#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H) -#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L) -#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H) - -#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L) -#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H) -#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L) -#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H) -#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L) -#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H) -#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L) -#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H) -#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L) -#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H) -#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L) -#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H) -#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L) -#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H) -#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L) -#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H) -#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L) -#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H) -#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L) -#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H) -#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L) -#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H) -#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L) -#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H) -#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L) -#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H) -#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L) -#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H) -#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L) -#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H) -#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L) -#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H) - -/* CAN Acceptance Mask Area Macros */ -#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x)) -#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x)) - -/* Mailbox Registers */ -#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1) -#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0) -#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP) -#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH) -#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3) -#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2) -#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1) -#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0) - -#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1) -#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0) -#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP) -#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH) -#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3) -#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2) -#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1) -#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0) - -#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1) -#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0) -#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP) -#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH) -#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3) -#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2) -#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1) -#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0) - -#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1) -#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0) -#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP) -#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH) -#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3) -#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2) -#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1) -#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0) - -#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1) -#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0) -#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP) -#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH) -#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3) -#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2) -#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1) -#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0) - -#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1) -#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0) -#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP) -#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH) -#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3) -#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2) -#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1) -#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0) - -#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1) -#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0) -#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP) -#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH) -#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3) -#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2) -#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1) -#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0) - -#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1) -#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0) -#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP) -#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH) -#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3) -#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2) -#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1) -#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0) - -#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1) -#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0) -#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP) -#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH) -#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3) -#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2) -#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1) -#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0) - -#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1) -#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0) -#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP) -#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH) -#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3) -#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2) -#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1) -#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0) - -#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1) -#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0) -#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP) -#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH) -#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3) -#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2) -#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1) -#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0) - -#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1) -#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0) -#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP) -#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH) -#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3) -#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2) -#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1) -#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0) - -#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1) -#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0) -#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP) -#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH) -#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3) -#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2) -#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1) -#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0) - -#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1) -#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0) -#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP) -#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH) -#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3) -#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2) -#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1) -#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0) - -#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1) -#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0) -#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP) -#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH) -#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3) -#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2) -#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1) -#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0) - -#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1) -#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0) -#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP) -#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH) -#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3) -#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2) -#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1) -#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0) - -#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1) -#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0) -#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP) -#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH) -#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3) -#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2) -#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1) -#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0) - -#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1) -#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0) -#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP) -#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH) -#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3) -#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2) -#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1) -#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0) - -#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1) -#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0) -#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP) -#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH) -#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3) -#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2) -#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1) -#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0) - -#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1) -#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0) -#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP) -#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH) -#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3) -#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2) -#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1) -#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0) - -#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1) -#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0) -#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP) -#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH) -#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3) -#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2) -#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1) -#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0) - -#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1) -#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0) -#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP) -#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH) -#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3) -#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2) -#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1) -#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0) - -#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1) -#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0) -#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP) -#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH) -#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3) -#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2) -#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1) -#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0) - -#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1) -#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0) -#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP) -#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH) -#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3) -#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2) -#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1) -#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0) - -#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1) -#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0) -#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP) -#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH) -#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3) -#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2) -#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1) -#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0) - -#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1) -#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0) -#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP) -#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH) -#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3) -#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2) -#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1) -#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0) - -#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1) -#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0) -#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP) -#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH) -#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3) -#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2) -#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1) -#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0) - -#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1) -#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0) -#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP) -#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH) -#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3) -#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2) -#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1) -#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0) - -#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1) -#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0) -#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP) -#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH) -#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3) -#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2) -#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1) -#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0) - -#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1) -#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0) -#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP) -#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH) -#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3) -#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2) -#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1) -#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0) - -#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1) -#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0) -#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP) -#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH) -#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3) -#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2) -#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1) -#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0) - -#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1) -#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0) -#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP) -#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH) -#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3) -#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2) -#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1) -#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0) - -/* CAN Mailbox Area Macros */ -#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x)) -#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x)) -#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x)) -#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x)) -#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x)) -#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x)) -#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x)) -#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x)) - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define pPORTF_FER ((volatile unsigned short *)PORTF_FER) -#define pPORTG_FER ((volatile unsigned short *)PORTG_FER) -#define pPORTH_FER ((volatile unsigned short *)PORTH_FER) -#define pPORT_MUX ((volatile unsigned short *)PORT_MUX) - -#define PORTF_UART0_TX 0x0001 -#define PORTF_UART0_RX 0x0002 - -#define PORT_MUX_PFDE 0x0040 /* 0: Enable UART0 RX, UART0 TX; 1: Enable DMAR0, DMAr1 */ - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL) -#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT) -#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT) -#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT) -#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW) -#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT) -#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT) - -#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL) -#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT) -#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT) -#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT) -#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW) -#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT) -#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT) - -#endif /* _CDEF_BF534_H */ diff --git a/include/asm-blackfin/arch-bf537/cdefBF537.h b/include/asm-blackfin/arch-bf537/cdefBF537.h deleted file mode 100644 index 3de1d936d0..0000000000 --- a/include/asm-blackfin/arch-bf537/cdefBF537.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved. - * - *********************************************************************************** - * - * This include file contains a list of macro "defines" to enable the programmer - * to use symbolic names for register-access. - * - * ---------------------------- - * revision 0.1 - * date: 2004/03/01 21:23:01; author: joeb - * Initial revision - * - * ---------------------------- - * revision 0.2 - * date: 2004/05/15 16:30:00; author: joeb - * comments: removed I2C/IIC references to TWI, changed GPIO sections - * - * ---------------------------- - * revision 0.3 - * date: 2004/06/08 12:25:00; author: joeb - * comments: renamed some TWI and GPIO registers - * - * ---------------------------- - * revision 0.4 - * date: 2004/06/09 14:25:00; author: joeb - * comments: changed Timer status register to 32-bit, renamed EMAC count registers - * - * ---------------------------- - * revision 0.5 - * date: 2004/08/10 10:25:00; author: joeb - * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers - * - * ---------------------------- - * revision 0.6 - * date: 2004/08/17 16:25:00; author: joeb - * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK - * - * ---------------------------- - * revision 0.7 - * date: 2004/08/18 13:21:00; author: joeb - * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes - * - * ---------------------------- - * revision 0.8 - * date: 2004/08/20 10:27:00; author: joeb - * comments: Renamed External DMA to Handshake DMA - * - * ---------------------------- - * revision 0.9 - * date: 2004/08/23 13:42:00; author: joeb - * comments: Renamed Handshake DMA Register Set - * - * ---------------------------- - * revision 0.10 - * date: 2004/10/28 15:40:00; author: joeb - * comments: Shortened EMAC Count Register Names - * - * ---------------------------- - * revision 0.11 - * date: 2004/12/13 11:05:00; author: joeb - * comments: Fixed address pointers - (volatile void **) to (void * volatile *) - * - * ---------------------------- - * revision 0.12 - * date: 2004/12/17 14:25:00; author: joeb - * comments: Replaced C++ Single-Line Comments w/C-standard Comments - * Changed EMAC EQ1024 TX/RX References to GE1024 - * - * ---------------------------- - * revision 0.13 - * date: 2005/01/05 10:50:00; author: joeb - * comments: Removed excess white space in CAN_AM section - * Added support for CAN Macros to Index AM and Mailbox Areas - * - * ---------------------------- - * revision 0.14 - * date: 2005/01/26 14:10:00; author: joeb - * comments: Fixed Typo In EMAC_RXC_PAUSE register - * - * ---------------------------- - * revision 0.15 - * date: 2005/01/27 14:41:00; author: joeb - * comments: Moved Common MMRs to cdefBF534.h - */ - -/* - * System MMR Register Map - */ - -#ifndef _CDEF_BF537_H -#define _CDEF_BF537_H - -/* Include MMRs Common to BF534 */ -#include <asm/arch-bf537/cdefBF534.h> - -/* Include all Core registers and bit definitions */ -#include <asm/arch-bf537/defBF537.h> - -/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ -#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE) -#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO) -#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI) -#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO) -#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI) -#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD) -#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT) -#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC) -#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1) -#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2) -#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL) -#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0) -#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1) -#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2) -#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3) -#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD) -#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF) -#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0) -#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1) - -#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL) -#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT) -#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT) -#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY) -#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE) -#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT) -#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY) -#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE) - -#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL) -#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS) -#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE) -#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS) -#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE) - -#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK) -#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS) -#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN) -#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET) -#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF) -#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST) -#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI) -#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD) -#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI) -#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO) -#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG) -#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL) -#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE) -#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE) -#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM) -#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT) -#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED) -#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT) -#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64) -#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128) -#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256) -#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512) -#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024) -#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024) - -#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK) -#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL) -#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL) -#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET) -#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER) -#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL) -#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL) -#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND) -#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR) -#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST) -#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI) -#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD) -#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR) -#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL) -#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM) -#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT) -#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64) -#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128) -#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256) -#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512) -#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024) -#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024) -#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT) - -#endif /* _CDEF_BF537_H */ diff --git a/include/asm-blackfin/arch-bf537/defBF534.h b/include/asm-blackfin/arch-bf537/defBF534.h deleted file mode 100644 index c603d448ec..0000000000 --- a/include/asm-blackfin/arch-bf537/defBF534.h +++ /dev/null @@ -1,2627 +0,0 @@ -/* - * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved. - * - *********************************************************************************** - * - * This include file contains a list of macro "defines" to enable the programmer - * to use symbolic names for register-access and bit-manipulation. - * - * ---------------------------- - * revision 0.1 - * date: 2004/03/01 21:23:01; author: joeb - * Initial revision - * - */ -#ifndef _DEF_BF534_H -#define _DEF_BF534_H - -/* Include all Core registers and bit definitions */ -#include <asm/arch-common/def_LPBlackfin.h> - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* - * System MMR Register Map - */ -/* Clock and System Control (0xFFC00000 - 0xFFC000FF)*/ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic Control Registers */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ - -/* For Mailboxes 16-31 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ - -/* CAN Configuration, Control, and Status Registers */ -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ -#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ -#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */ -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ - -/* Mailbox Acceptance Masks */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ - -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ - -/* CAN Acceptance Mask Macros */ -#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) -#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) - -/* Mailbox Registers */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ - -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ - -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ - -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ - -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ - -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ - -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ - -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ - -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ - -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ - -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ - -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ - -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ - -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ - -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ - -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ - -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ - -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ - -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ - -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ - -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ - -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ - -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ - -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ - -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ - -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ - -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ - -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ - -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ - -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ - -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ - -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ - -/* CAN Mailbox Area Macros */ -#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) -#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) -#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) -#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) -#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) -#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) -#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) -#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - -/* - * System MMR Register Bits And Macros - * - * Disclaimer: All macros are intended to make C and Assembly code more readable. - * Use these macros carefully, as any that do left shifts for field - * depositing will result in the lower order bits being destroyed. Any - * macro that shifts left to properly position the bit-field should be - * used as part of an OR to initialize a register and NOT as a dynamic - * modifier UNLESS the lower order bits are saved and ORed back in when - * the macro is used. - */ -/* - * PLL AND RESET MASKS - * PLL_CTL Masks - */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -#define CCLK_DIV1 CSEL_DIV1 -#define CCLK_DIV2 CSEL_DIV2 -#define CCLK_DIV4 CSEL_DIV4 -#define CCLK_DIV8 CSEL_DIV8 -/* PLL_DIV Macros */ -#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ - -/* VR_CTL Masks */ -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 10 */ -#define GAIN_20 0x0008 /* GAIN = 20 */ -#define GAIN_50 0x000C /* GAIN = 50 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ -#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - -/* - * SYSTEM INTERRUPT CONTROLLER MASKS - */ -/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ -#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ -#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ -#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ -#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ -#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ -#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ -#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ -#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ - -#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ -#define IRQ_TWI 0x00000200 /* TWI Interrupt */ -#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ -#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ -#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ -#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ -#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ -#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ - -#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ -#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ -#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ -#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ -#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ -#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ -#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ -#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ -#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ -#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ - -#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ -#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ -#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ -#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ -#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ -#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ -#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ -#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ -#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ -#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ -#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - -/* ********* WATCHDOG TIMER MASKS ******************** */ - -/* Watchdog Timer WDOG_CTL Register Masks */ - -#define WDEV(x) ((x<<1) & 0x0006) /* event generated on roll over */ -#define WDEV_RESET 0x0000 /* generate reset event on roll over */ -#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ -#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ -#define WDEV_NONE 0x0006 /* no event on roll over */ -#define WDEN 0x0FF0 /* enable watchdog */ -#define WDDIS 0x0AD0 /* disable watchdog */ -#define WDRO 0x8000 /* watchdog rolled over latch */ - -/* depreciated WDOG_CTL Register Masks for legacy code */ - -#define ICTL WDEV -#define ENABLE_RESET WDEV_RESET -#define WDOG_RESET WDEV_RESET -#define ENABLE_NMI WDEV_NMI -#define WDOG_NMI WDEV_NMI -#define ENABLE_GPI WDEV_GPI -#define WDOG_GPI WDEV_GPI -#define DISABLE_EVT WDEV_NONE -#define WDOG_NONE WDEV_NONE - -#define TMR_EN WDEN -#define TMR_DIS WDDIS -#define TRO WDRO -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -/* - * REAL TIME CLOCK MASKS - */ -/* RTC_STAT and RTC_ALARM Masks */ -#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ -#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ -#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ -#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ - -/* - * RTC_ALARM Macro - * z=day y=hr x=min w=sec - */ -#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) - -/* RTC_ICTL and RTC_ISTAT Masks */ -#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ -#define ALARM 0x0002 /* Alarm Interrupt Enable */ -#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ -#define MINUTE 0x0008 /* Minutes Interrupt Enable */ -#define HOUR 0x0010 /* Hours Interrupt Enable */ -#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ -#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ -#define WRITE_PENDING 0x4000 /* Write Pending Status */ -#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ - -/* RTC_FAST / RTC_PREN Mask */ -#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ - -/* - * UART CONTROLLER MASKS - */ -/* UARTx_LCR Masks */ -#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -/* UARTx_MCR Mask */ -#define LOOP 0x10 /* Loopback Mode Enable */ - -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define STATUS 0x06 /* Highest Priority Pending Interrupt */ - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - -/* - * SERIAL PERIPHERAL INTERFACE (SPI) MASKS - */ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - -/* - * GENERAL PURPOSE TIMER MASKS - */ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - -/* - * GPIO PORTS F, G, H MASKS - * General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks - */ -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 -#define PH14 0x4000 -#define PH15 0x8000 - -/* - * SERIAL PORT MASKS - */ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* Transmit Enable */ -#define ITCLK 0x0002 /* Internal Transmit Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* Transmit Bit Order */ -#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ -#define TFSR 0x0400 /* Transmit Frame Sync Required Select */ -#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ -#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define LATFS 0x2000 /* Late Transmit Frame Sync Select */ -#define TCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks and Macro */ -#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* Receive Enable */ -#define IRCLK 0x0002 /* Internal Receive Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* Receive Bit Order */ -#define IRFS 0x0200 /* Internal Receive Frame Sync Select */ -#define RFSR 0x0400 /* Receive Frame Sync Required Select */ -#define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define LARFS 0x2000 /* Late Receive Frame Sync Select */ -#define RCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* Receive FIFO Not Empty Status */ -#define RUVF 0x0002 /* Sticky Receive Underflow Status */ -#define ROVF 0x0004 /* Sticky Receive Overflow Status */ -#define TXF 0x0008 /* Transmit FIFO Full Status */ -#define TUVF 0x0010 /* Sticky Transmit Underflow Status */ -#define TOVF 0x0020 /* Sticky Transmit Overflow Status */ -#define TXHRE 0x0040 /* Transmit Hold Register Empty */ - -/* SPORTx_MCMC1 Macros */ -#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ - -/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ -#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ - -/* SPORTx_MCMC2 Masks */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - -/* - * ASYNCHRONOUS MEMORY CONTROLLER MASKS - */ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - -/* - * SDRAM CONTROLLER MASKS - */ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - -/* - * DMA CONTROLLER MASKS - */ -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define FLOW_STOP 0x0000 /* Stop Mode */ -#define FLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ - -/* - * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS - */ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - -/* - * TWO-WIRE INTERFACE (TWI) MASKS - */ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTRL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTRL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - -/* - * CONTROLLER AREA NETWORK (CAN) MASKS - */ -/* CAN_CONTROL Masks */ -#define SRS 0x0001 /* Software Reset */ -#define DNM 0x0002 /* Device Net Mode */ -#define ABO 0x0004 /* Auto-Bus On Enable */ -#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ -#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ -#define SMR 0x0020 /* Sleep Mode Request */ -#define CSR 0x0040 /* CAN Suspend Mode Request */ -#define CCR 0x0080 /* CAN Configuration Mode Request */ - -/* CAN_STATUS Masks */ -#define WT 0x0001 /* TX Warning Flag */ -#define WR 0x0002 /* RX Warning Flag */ -#define EP 0x0004 /* Error Passive Mode */ -#define EBO 0x0008 /* Error Bus Off Mode */ -#define SMA 0x0020 /* Sleep Mode Acknowledge */ -#define CSA 0x0040 /* Suspend Mode Acknowledge */ -#define CCA 0x0080 /* Configuration Mode Acknowledge */ -#define MBPTR 0x1F00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode */ -#define REC 0x8000 /* Receive Mode */ - -/* CAN_CLOCK Masks */ -#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ - -/* CAN_TIMING Masks */ -#define TSEG1 0x000F /* Time Segment 1 */ -#define TSEG2 0x0070 /* Time Segment 2 */ -#define SAM 0x0080 /* Sampling */ -#define SJW 0x0300 /* Synchronization Jump Width */ - -/* CAN_DEBUG Masks */ -#define DEC 0x0001 /* Disable CAN Error Counters */ -#define DRI 0x0002 /* Disable CAN RX Input */ -#define DTO 0x0004 /* Disable CAN TX Output */ -#define DIL 0x0008 /* Disable CAN Internal Loop */ -#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ -#define MRB 0x0020 /* Mode Read Back Enable */ -#define CDE 0x8000 /* CAN Debug Enable */ - -/* CAN_CEC Masks */ -#define RXECNT 0x00FF /* Receive Error Counter */ -#define TXECNT 0xFF00 /* Transmit Error Counter */ - -/* CAN_INTR Masks */ -#define MBRIF 0x0001 /* Mailbox Receive Interrupt */ -#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */ -#define GIRQ 0x0004 /* Global Interrupt */ -#define SMACK 0x0008 /* Sleep Mode Acknowledge */ -#define CANTX 0x0040 /* CAN TX Bus Value */ -#define CANRX 0x0080 /* CAN RX Bus Value */ - -/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ -#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define IDE 0x2000 /* Identifier Extension */ -#define RTR 0x4000 /* Remote Frame Transmission Request */ -#define AME 0x8000 /* Acceptance Mask Enable */ - -/* CAN_MBxx_TIMESTAMP Masks */ -#define TSV 0xFFFF /* Timestamp */ - -/* CAN_MBxx_LENGTH Masks */ -#define DLC 0x000F /* Data Length Code */ - -/* CAN_AMxxH and CAN_AMxxL Masks */ -#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ -#define FMD 0x4000 /* Full Mask Data Field Enable */ -#define FDF 0x8000 /* Filter On Data Field Enable */ - -/* CAN_MC1 Masks */ -#define MC0 0x0001 /* Enable Mailbox 0 */ -#define MC1 0x0002 /* Enable Mailbox 1 */ -#define MC2 0x0004 /* Enable Mailbox 2 */ -#define MC3 0x0008 /* Enable Mailbox 3 */ -#define MC4 0x0010 /* Enable Mailbox 4 */ -#define MC5 0x0020 /* Enable Mailbox 5 */ -#define MC6 0x0040 /* Enable Mailbox 6 */ -#define MC7 0x0080 /* Enable Mailbox 7 */ -#define MC8 0x0100 /* Enable Mailbox 8 */ -#define MC9 0x0200 /* Enable Mailbox 9 */ -#define MC10 0x0400 /* Enable Mailbox 10 */ -#define MC11 0x0800 /* Enable Mailbox 11 */ -#define MC12 0x1000 /* Enable Mailbox 12 */ -#define MC13 0x2000 /* Enable Mailbox 13 */ -#define MC14 0x4000 /* Enable Mailbox 14 */ -#define MC15 0x8000 /* Enable Mailbox 15 */ - -/* CAN_MC2 Masks */ -#define MC16 0x0001 /* Enable Mailbox 16 */ -#define MC17 0x0002 /* Enable Mailbox 17 */ -#define MC18 0x0004 /* Enable Mailbox 18 */ -#define MC19 0x0008 /* Enable Mailbox 19 */ -#define MC20 0x0010 /* Enable Mailbox 20 */ -#define MC21 0x0020 /* Enable Mailbox 21 */ -#define MC22 0x0040 /* Enable Mailbox 22 */ -#define MC23 0x0080 /* Enable Mailbox 23 */ -#define MC24 0x0100 /* Enable Mailbox 24 */ -#define MC25 0x0200 /* Enable Mailbox 25 */ -#define MC26 0x0400 /* Enable Mailbox 26 */ -#define MC27 0x0800 /* Enable Mailbox 27 */ -#define MC28 0x1000 /* Enable Mailbox 28 */ -#define MC29 0x2000 /* Enable Mailbox 29 */ -#define MC30 0x4000 /* Enable Mailbox 30 */ -#define MC31 0x8000 /* Enable Mailbox 31 */ - -/* CAN_MD1 Masks */ -#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ -#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ -#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ -#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ -#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ -#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ -#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ -#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ -#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ -#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ -#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ -#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ -#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ -#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ -#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ -#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ - -/* CAN_MD2 Masks */ -#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ -#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ -#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ -#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ -#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ -#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ -#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ -#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ -#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ -#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ -#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ -#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ -#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ -#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ -#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ -#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ - -/* CAN_RMP1 Masks */ -#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ -#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ -#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ -#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ -#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ -#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ -#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ -#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ -#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ -#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ -#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ -#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ -#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ -#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ -#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ -#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ - -/* CAN_RMP2 Masks */ -#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ -#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ -#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ -#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ -#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ -#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ -#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ -#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ -#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ -#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ -#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ -#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ -#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ -#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ -#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ -#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ - -/* CAN_RML1 Masks */ -#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ -#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ -#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ -#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ -#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ -#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ -#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ -#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ -#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ -#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ -#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ -#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ -#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ -#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ -#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ -#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ - -/* CAN_RML2 Masks */ -#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ -#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ -#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ -#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ -#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ -#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ -#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ -#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ -#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ -#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ -#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ -#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ -#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ -#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ -#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ -#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ - -/* CAN_OPSS1 Masks */ -#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ -#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ -#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ -#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ -#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ -#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ -#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ -#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ -#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ -#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ -#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ -#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ -#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ -#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ -#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ -#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ - -/* CAN_OPSS2 Masks */ -#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ -#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ -#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ -#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ -#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ -#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ -#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ -#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ -#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ -#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ -#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ -#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ -#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ -#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ -#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ -#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ - -/* CAN_TRR1 Masks */ -#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ -#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ -#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ -#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ -#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ -#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ -#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ -#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ -#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ -#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ -#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ -#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ -#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ -#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ -#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ -#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ - -/* CAN_TRR2 Masks */ -#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ -#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ -#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ -#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ -#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ -#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ -#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ -#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ -#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ -#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ -#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ -#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ -#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ -#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ -#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ -#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ - -/* CAN_TRS1 Masks */ -#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ -#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ -#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ -#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ -#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ -#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ -#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ -#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ -#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ -#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ -#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ -#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ -#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ -#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ -#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ -#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ - -/* CAN_TRS2 Masks */ -#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ -#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ -#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ -#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ -#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ -#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ -#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ -#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ -#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ -#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ -#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ -#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ -#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ -#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ -#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ -#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ - -/* CAN_AA1 Masks */ -#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ -#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ -#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ -#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ -#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ -#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ -#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ -#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ -#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ -#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ -#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ -#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ -#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ -#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ -#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ -#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ - -/* CAN_AA2 Masks */ -#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ -#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ -#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ -#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ -#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ -#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ -#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ -#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ -#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ -#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ -#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ -#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ -#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ -#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ -#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ -#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ - -/* CAN_TA1 Masks */ -#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ -#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ -#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ -#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ -#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ -#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ -#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ -#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ -#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ -#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ -#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ -#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ -#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ -#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ -#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ -#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ - -/* CAN_TA2 Masks */ -#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ -#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ -#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ -#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ -#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ -#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ -#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ -#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ -#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ -#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ -#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ -#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ -#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ -#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ -#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ -#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ - -/* CAN_MBTD Masks */ -#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ -#define TDA 0x0040 /* Temporary Disable Acknowledge */ -#define TDR 0x0080 /* Temporary Disable Request */ - -/* CAN_RFH1 Masks */ -#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ -#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ -#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ -#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ -#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ -#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ -#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ -#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ -#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ -#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ -#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ -#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ -#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ -#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ -#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ -#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ - -/* CAN_RFH2 Masks */ -#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ -#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ -#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ -#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ -#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ -#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ -#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ -#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ -#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ -#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ -#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ -#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ -#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ -#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ -#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ -#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ - -/* CAN_MBTIF1 Masks */ -#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ -#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ -#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ -#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ -#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ -#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ -#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ -#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ -#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ -#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ -#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ -#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ -#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ -#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ -#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ -#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ - -/* CAN_MBTIF2 Masks */ -#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ -#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ -#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ -#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ -#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ -#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ -#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ -#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ -#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ -#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ -#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ -#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ -#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ -#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ -#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ -#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ - -/* CAN_MBRIF1 Masks */ -#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ -#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ -#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ -#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ -#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ -#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ -#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ -#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ -#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ -#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ -#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ -#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ -#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ -#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ -#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ -#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ - -/* CAN_MBRIF2 Masks */ -#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ -#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ -#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ -#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ -#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ -#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ -#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ -#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ -#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ -#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ -#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ -#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ -#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ -#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ -#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ -#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ - -/* CAN_MBIM1 Masks */ -#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ -#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ -#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ -#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ -#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ -#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ -#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ -#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ -#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ -#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ -#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ -#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ -#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ -#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ -#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ -#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ - -/* CAN_MBIM2 Masks */ -#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ -#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ -#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ -#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ -#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ -#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ -#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ -#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ -#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ -#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ -#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ -#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ -#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ -#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ -#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ -#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ - -/* CAN_GIM Masks */ -#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ -#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ -#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ -#define BOIM 0x0008 /* Enable Bus Off Interrupt */ -#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ -#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ -#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ -#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ -#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ -#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ -#define ADIM 0x0400 /* Enable Access Denied Interrupt */ - -/* CAN_GIS Masks */ -#define EWTIS 0x0001 /* TX Error Count IRQ Status */ -#define EWRIS 0x0002 /* RX Error Count IRQ Status */ -#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ -#define BOIS 0x0008 /* Bus Off IRQ Status */ -#define WUIS 0x0010 /* Wake-Up IRQ Status */ -#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ -#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ -#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ -#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ -#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ -#define ADIS 0x0400 /* Access Denied IRQ Status */ - -/* CAN_GIF Masks */ -#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ -#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ -#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ -#define BOIF 0x0008 /* Bus Off IRQ Flag */ -#define WUIF 0x0010 /* Wake-Up IRQ Flag */ -#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ -#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ -#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ -#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ -#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ -#define ADIF 0x0400 /* Access Denied IRQ Flag */ - -/* CAN_UCCNF Masks */ -#define UCCNF 0x000F /* Universal Counter Mode */ -#define UC_STAMP 0x0001 /* Timestamp Mode */ -#define UC_WDOG 0x0002 /* Watchdog Mode */ -#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ -#define UC_ERROR 0x0006 /* CAN Error Frame Count */ -#define UC_OVER 0x0007 /* CAN Overload Frame Count */ -#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ -#define UC_AA 0x0009 /* TX Abort Count */ -#define UC_TA 0x000A /* TX Successful Count */ -#define UC_REJECT 0x000B /* RX Message Rejected Count */ -#define UC_RML 0x000C /* RX Message Lost Count */ -#define UC_RX 0x000D /* Total Successful RX Messages Count */ -#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ -#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ -#define UCRC 0x0020 /* Universal Counter Reload/Clear */ -#define UCCT 0x0040 /* Universal Counter CAN Trigger */ -#define UCE 0x0080 /* Universal Counter Enable */ - -/* CAN_ESR Masks */ -#define ACKE 0x0004 /* Acknowledge Error */ -#define SER 0x0008 /* Stuff Error */ -#define CRCE 0x0010 /* CRC Error */ -#define SA0 0x0020 /* Stuck At Dominant Error */ -#define BEF 0x0040 /* Bit Error Flag */ -#define FER 0x0080 /* Form Error Flag */ - -/* CAN_EWR Masks */ -#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ -#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ - -/* - * PIN CONTROL REGISTER MASKS - */ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* - * HANDSHAKE DMA (HDMA) MASKS - */ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -#endif /* _DEF_BF534_H */ diff --git a/include/asm-blackfin/arch-bf537/defBF537.h b/include/asm-blackfin/arch-bf537/defBF537.h deleted file mode 100644 index 8d16c374a0..0000000000 --- a/include/asm-blackfin/arch-bf537/defBF537.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved. - * - *********************************************************************************** - * - * This include file contains a list of macro "defines" to enable the programmer - * to use symbolic names for register-access and bit-manipulation. - * - * ---------------------------- - * revision 0.1 - * date: 2004/03/01 21:23:01; author: joeb - * Initial revision - * - * ---------------------------- - * revision 0.2 - * date: 2004/05/15 16:30:00; author: joeb - * comments: removed I2C/IIC references, changed GPIO sections - * - * ---------------------------- - * revision 0.3 - * date: 2004/06/08 12:25:00; author: joeb - * comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed - * FLAG references in GPIO register names - * - * ---------------------------- - * revision 0.4 - * date: 2004/06/09 2:25:00; author: joeb - * comments: fixed bit-defines for EMAC section, renamed EMAC count registers, - * combined 2 Timer status registers into one - * - * ---------------------------- - * revision 0.5 - * date: 2004/08/10 10:25:00; author: joeb - * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers - * - * ---------------------------- - * revision 0.6 - * date: 2004/08/17 16:25:00; author: joeb - * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK - * - * ---------------------------- - * revision 0.7 - * date: 2004/08/18 13:21:00; author: joeb - * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes - * - * ---------------------------- - * revision 0.8 - * date: 2004/08/20 10:24:00; author: joeb - * comments: Renamed External DMA to Handshake MDMA - * - * ---------------------------- - * revision 0.9 - * date: 2004/08/23 13:42:00; author: joeb - * comments: Renamed Handshake DMA Register Set - * - * ---------------------------- - * revision 0.10 - * date: 2004/09/07 11:21:00; author: joeb - * comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names) - * - * ---------------------------- - * revision 0.11 - * date: 2004/09/28 15:14:00; author: joeb - * comments: Fixed CAN Mailbox Area - * - * ---------------------------- - * revision 0.12 - * date: 2004/10/27 13:18:00; author: joeb - * comments: Added IEEE EMAC Register Support - * - * ---------------------------- - * revision 0.13 - * date: 2004/10/28 15:40:00; author: joeb - * comments: Shortened EMAC Count Register Names - * - * ---------------------------- - * revision 0.14 - * date: 2004/11/09 10:45:00; author: joeb - * comments: Fixed WDSIZE macros - * - * ---------------------------- - * revision 0.15 - * date: 2004/11/18 07:45:00; author: joeb - * comments: Fixed TIMER_STATUS register, added EMAC macros - * - * ---------------------------- - * revision 0.16 - * date: 2004/12/13 11:05:00; author: joeb - * comments: Removed HI/LO macros (now Assembler mnemonics) - * Renamed enable bit for HMDMA from EN to HMDMAEN - * - * ---------------------------- - * revision 0.17 - * date: 2004/12/17 14:25:00; author: joeb - * comments: Replaced C++ Single-Line Comments w/C-standard Comments - * Changed EMAC EQ1024 TX/RX References to GE1024 - * - * ---------------------------- - * revision 0.18 - * date: 2005/01/05 10:50:00; author: joeb - * comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks - * Added mask values for field deposit protection - * - * ---------------------------- - * revision 0.19 - * date: 2005/01/10 10:30:00; author: joeb - * comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10. - * - * ---------------------------- - * revision 0.20 - * date: 2005/01/27 14:25:15; author: joeb - * comments: Moved MMRs common to BF534 to BF534 header. - */ -#ifndef _DEF_BF537_H -#define _DEF_BF537_H - -/* Include all Core registers and bit definitions */ -#include <asm/arch-common/def_LPBlackfin.h> - -/* Include all MMR and bit defines common to BF534 */ -#include <asm/arch-bf537/defBF534.h> - -/* - * Define EMAC Section Unique to BF536/BF537 - */ - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ - -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ - -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ - -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ - -/* Listing for IEEE-Supported Count Registers */ -#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ -#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ -#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ -#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ -#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ -#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ -#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ -#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ -#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ -#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ -#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ -#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ -#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ -#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ -#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ -#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ -#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ -#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ -#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ -#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ -#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ -#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ -#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ -#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ -#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ -#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ -#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ -#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ -#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ -#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ -#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ -#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ -#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ -#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ -#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ - -/* - * System MMR Register Bits And Macros - * - * Disclaimer: All macros are intended to make C and Assembly code more readable. - * Use these macros carefully, as any that do left shifts for field - * depositing will result in the lower order bits being destroyed. Any - * macro that shifts left to properly position the bit-field should be - * used as part of an OR to initialize a register and NOT as a dynamic - * modifier UNLESS the lower order bits are saved and ORed back in when - * the macro is used. - */ -/* - * ETHERNET 10/100 CONTROLLER MASKS - */ -/* EMAC_OPMODE Masks */ -#define RE 0x00000001 /* Receiver Enable */ -#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ -#define HU 0x00000010 /* Hash Filter Unicast Address */ -#define HM 0x00000020 /* Hash Filter Multicast Address */ -#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ -#define PR 0x00000080 /* Promiscuous Mode Enable */ -#define IFE 0x00000100 /* Inverse Filtering Enable */ -#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ -#define PBF 0x00000400 /* Pass Bad Frames Enable */ -#define PSF 0x00000800 /* Pass Short Frames Enable */ -#define RAF 0x00001000 /* Receive-All Mode */ -#define TE 0x00010000 /* Transmitter Enable */ -#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ -#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ -#define DC 0x00080000 /* Deferral Check */ -#define BOLMT 0x00300000 /* Back-Off Limit */ -#define BOLMT_10 0x00000000 /* 10-bit range */ -#define BOLMT_8 0x00100000 /* 8-bit range */ -#define BOLMT_4 0x00200000 /* 4-bit range */ -#define BOLMT_1 0x00300000 /* 1-bit range */ -#define DRTY 0x00400000 /* Disable TX Retry On Collision */ -#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ -#define RMII 0x01000000 /* RMII/MII* Mode */ -#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ -#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ -#define LB 0x08000000 /* Internal Loopback Enable */ -#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ - -/* EMAC_STAADD Masks */ -#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ -#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ -#define STADISPRE 0x00000004 /* Disable Preamble Generation */ -#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ -#define REGAD 0x000007C0 /* STA Register Address */ -#define PHYAD 0x0000F800 /* PHY Device Address */ - -#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ -#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ - -/* EMAC_STADAT Mask */ -#define STADATA 0x0000FFFF /* Station Management Data */ - -/* EMAC_FLC Masks */ -#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ -#define FLCE 0x00000002 /* Flow Control Enable */ -#define PCF 0x00000004 /* Pass Control Frames */ -#define BKPRSEN 0x00000008 /* Enable Backpressure */ -#define FLCPAUSE 0xFFFF0000 /* Pause Time */ - -#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ - -/* EMAC_WKUP_CTL Masks */ -#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ -#define MPKE 0x00000002 /* Magic Packet Enable */ -#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ -#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ -#define MPKS 0x00000020 /* Magic Packet Received Status */ -#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ - -/* EMAC_WKUP_FFCMD Masks */ -#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ -#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ -#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ -#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ -#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ -#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ -#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ -#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ - -/* EMAC_WKUP_FFOFF Masks */ -#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ -#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ -#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ -#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ - -#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ -#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ -#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ -#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ -/* Set ALL Offsets */ -#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) - -/* EMAC_WKUP_FFCRC0 Masks */ -#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ -#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ - -#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */ -#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */ - -/* EMAC_WKUP_FFCRC1 Masks */ -#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ -#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ - -#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */ -#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */ - -/* EMAC_SYSCTL Masks */ -#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ -#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ -#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ -#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ - -#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ - -/* EMAC_SYSTAT Masks */ -#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ -#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ -#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ -#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ -#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ -#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ -#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ -#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ - -/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ -#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ -#define RX_COMP 0x00001000 /* RX Frame Complete */ -#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ -#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ -#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ -#define RX_CRC 0x00010000 /* RX Frame CRC Error */ -#define RX_LEN 0x00020000 /* RX Frame Length Error */ -#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ -#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ -#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ -#define RX_PHY 0x00200000 /* RX Frame PHY Error */ -#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ -#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ -#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ -#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ -#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ -#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ -#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ -#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ -#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ -#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ - -/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ -#define TX_COMP 0x00000001 /* TX Frame Complete */ -#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ -#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ -#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ -#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ -#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ -#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ -#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ -#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ -#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ -#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ -#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ -#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ -#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ -#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ - -/* EMAC_MMC_CTL Masks */ -#define RSTC 0x00000001 /* Reset All Counters */ -#define CROLL 0x00000002 /* Counter Roll-Over Enable */ -#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ -#define MMCE 0x00000008 /* Enable MMC Counter Operation */ - -/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ -#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ -#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ -#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ -#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ -#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ -#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ -#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ -#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ -#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ -#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ -#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ -#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ -#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ -#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ -#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ -#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ -#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ -#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ -#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ -#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ -#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ -#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ -#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ -#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ - -/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ -#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ -#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ -#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ -#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ -#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ -#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ -#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ -#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ -#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ -#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ -#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ -#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ -#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ -#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ -#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ -#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ -#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ -#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ -#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ -#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ -#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ -#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ -#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ - -#endif /* _DEF_BF537_H */ diff --git a/include/asm-blackfin/arch-bf537/defBF537_extn.h b/include/asm-blackfin/arch-bf537/defBF537_extn.h deleted file mode 100644 index 8090da66b6..0000000000 --- a/include/asm-blackfin/arch-bf537/defBF537_extn.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * defBF537_extn.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEF_BF537_EXTN_H -#define _DEF_BF537_EXTN_H - -#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ -/* Delay inserted for PLL transition */ -#define PLL_DELAY 0x1000 - -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA10000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF808000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF908000 -#define SYSMMR_BASE 0xFFC00000 -#define WDSIZE16 0x00000004 - -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 - -/* IMASK Bit values */ -#define IVG15_POS 0x00008000 -#define IVG14_POS 0x00004000 -#define IVG13_POS 0x00002000 -#define IVG12_POS 0x00001000 -#define IVG11_POS 0x00000800 -#define IVG10_POS 0x00000400 -#define IVG9_POS 0x00000200 -#define IVG8_POS 0x00000100 -#define IVG7_POS 0x00000080 -#define IVGTMR_POS 0x00000040 -#define IVGHW_POS 0x00000020 - -#define WDOG_TMR_DISABLE (0xAD << 4) -#define ICTL_RST 0x00000000 -#define ICTL_NMI 0x00000002 -#define ICTL_GP 0x00000004 -#define ICTL_DISABLE 0x00000003 - -/* Watch Dog timer values setup */ -#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE - -#endif /* _DEF_BF537_EXTN_H */ diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h deleted file mode 100644 index 527d8a21f2..0000000000 --- a/include/asm-blackfin/arch-bf537/irq.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * U-boot bf537_irq.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c - * Changed by HuTao Apr18, 2003 - * - * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- - * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle - * - * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> - * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) - * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> - * - * Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF537_IRQ_H_ -#define _BF537_IRQ_H_ - -/* - * Interrupt source definitions - * Event Source Core Event Name Number - * EMU 0 - * Reset RST 1 - * NMI NMI 2 - * Exception EVX 3 - * Reserved -- 4 - * Hardware Error IVHW 5 - * Core Timer IVTMR 6 - * PLL Wakeup Interrupt IVG7 7 - * DMA Error (generic) IVG7 8 - * PPI Error Interrupt IVG7 9 - * SPORT0 Error Interrupt IVG7 10 - * SPORT1 Error Interrupt IVG7 11 - * SPI Error Interrupt IVG7 12 - * UART Error Interrupt IVG7 13 - * RTC Interrupt IVG8 14 - * DMA0 Interrupt (PPI) IVG8 15 - * DMA1 (SPORT0 RX) IVG9 16 - * DMA2 (SPORT0 TX) IVG9 17 - * DMA3 (SPORT1 RX) IVG9 18 - * DMA4 (SPORT1 TX) IVG9 19 - * DMA5 (PPI) IVG10 20 - * DMA6 (UART RX) IVG10 21 - * DMA7 (UART TX) IVG10 22 - * Timer0 IVG11 23 - * Timer1 IVG11 24 - * Timer2 IVG11 25 - * PF Interrupt A IVG12 26 - * PF Interrupt B IVG12 27 - * DMA8/9 Interrupt IVG13 28 - * DMA10/11 Interrupt IVG13 29 - * Watchdog Timer IVG13 30 - * Software Interrupt 1 IVG14 31 - * Software Interrupt 2 -- - * (lowest priority) IVG15 32 - */ - -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define IRQ_UART_RX_BIT 0x0800 -#define IRQ_UART_TX_BIT 0x1000 -#define IRQ_UART_ERROR_BIT 0x40 - -#endif diff --git a/include/asm-blackfin/arch-bf561/anomaly.h b/include/asm-blackfin/arch-bf561/anomaly.h deleted file mode 100644 index 467649b5a7..0000000000 --- a/include/asm-blackfin/arch-bf561/anomaly.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * File: include/asm-blackfin/arch-bf561/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* - * This file shoule be up to date with: - * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 or 0.4 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) -#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 -#endif - -/* Issues that are common to 0.5 and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ -#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned - memory locations */ -#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR - registers */ -#define ANOMALY_05000127 /* Signbits instruction not functional under certain - conditions */ -#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits */ -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz - and higher devices */ -#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ -#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ -#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop - may cause bad instruction fetches */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - external SPORT TX and RX clocks */ -#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ -#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal - voltage regulator (VDDint) to increase */ -#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal - voltage regulator (VDDint) to decrease */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000274 /* Data cache write back to external synchronous memory - may be lost */ -#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ -#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ - -#if (defined(CONFIG_BF_REV_0_5)) -#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT - mode with external clock */ -#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to - using IMDMA */ -#endif - -#if (defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) - Mode with 0 Frame Syncs */ -#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ -#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through - cache data writes */ -#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ -#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ -#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an - accumulator saturation */ -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ -#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration - registers */ -#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ -#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits - (not a meaningful mode) */ -#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer - Placement in Memory */ -#define ANOMALY_05000189 /* False Protection Exception */ -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ -#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data - corruption */ -#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding - memory read */ -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ -#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG - situation */ -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ -#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA - stopping */ -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ -#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and - Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data */ -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ -#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in - multichannel mode */ -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ -#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of - Control causes failures */ -#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) mode in certain conditions */ -#define ANOMALY_05000251 /* Exception not generated for MMR accesses in - reserved region */ -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 - of the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB - exception */ -#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second - to last instruction in hardware loop */ -#define ANOMALY_05000276 /* Timing requirements change for External Frame - Sync PPI Modes with non-zero PPI_DELAY */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed - in a particular stage */ -#define ANOMALY_05000287 /* A read will receive incorrect data under certain - conditions */ -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ -#endif - -#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h deleted file mode 100644 index eb01ca25ba..0000000000 --- a/include/asm-blackfin/arch-bf561/bf561_serial.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * U-boot bf561_serial.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BF561_SERIAL_H_ -#define _BF561_SERIAL_H_ - -#define BYTE_REF(addr) (*((volatile char*)addr)) -#define HALFWORD_REF(addr) (*((volatile short*)addr)) -#define WORD_REF(addr) (*((volatile long*)addr)) - -#define UART_THR_LO HALFWORD_REF(UART_THR) -#define UART_RBR_LO HALFWORD_REF(UART_RBR) -#define UART_DLL_LO HALFWORD_REF(UART_DLL) -#define UART_IER_LO HALFWORD_REF(UART_IER) -#define UART_IER_ERBFI 0x01 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ELSI 0x04 -#define UART_IER_EDDSI 0x08 - -#define UART_DLH_LO HALFWORD_REF(UART_DLH) -#define UART_IIR_LO HALFWORD_REF(UART_IIR) -#define UART_IIR_NOINT 0x01 -#define UART_IIR_STATUS 0x06 -#define UART_IIR_LSR 0x06 -#define UART_IIR_RBR 0x04 -#define UART_IIR_THR 0x02 -#define UART_IIR_MSR 0x00 - -#define UART_LCR_LO HALFWORD_REF(UART_LCR) -#define UART_LCR_WLS5 0 -#define UART_LCR_WLS6 0x01 -#define UART_LCR_WLS7 0x02 -#define UART_LCR_WLS8 0x03 -#define UART_LCR_STB 0x04 -#define UART_LCR_PEN 0x08 -#define UART_LCR_EPS 0x10 -#define UART_LCR_SP 0x20 -#define UART_LCR_SB 0x40 -#define UART_LCR_DLAB 0x80 - -#define UART_MCR_LO HALFWORD_REF(UART_MCR) - -#define UART_LSR_LO HALFWORD_REF(UART_LSR) -#define UART_LSR_DR 0x01 -#define UART_LSR_OE 0x02 -#define UART_LSR_PE 0x04 -#define UART_LSR_FE 0x08 -#define UART_LSR_BI 0x10 -#define UART_LSR_THRE 0x20 -#define UART_LSR_TEMT 0x40 - -#define UART_MSR_LO HALFWORD_REF(UART_MSR) -#define UART_SCR_LO HALFWORD_REF(UART_SCR) -#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) -#define UART_GCTL_UCEN 0x01 - -#endif diff --git a/include/asm-blackfin/arch-bf561/cdefBF561.h b/include/asm-blackfin/arch-bf561/cdefBF561.h deleted file mode 100644 index f217ba720a..0000000000 --- a/include/asm-blackfin/arch-bf561/cdefBF561.h +++ /dev/null @@ -1,998 +0,0 @@ -/* - * cdefBF561.h - * - * (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved. - * - */ - -/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ - -#ifndef _CDEF_BF561_H -#define _CDEF_BF561_H - -/* - * #if !defined(__ADSPBF561__) - * #warning cdefBF561.h should only be included for BF561 chip. - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/arch-bf561/defBF561.h> -#include <asm/arch-common/cdef_LPBlackfin.h> - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define pPLL_CTL (volatile unsigned short *)PLL_CTL -#define pPLL_DIV (volatile unsigned short *)PLL_DIV -#define pVR_CTL (volatile unsigned short *)VR_CTL -#define pPLL_STAT (volatile unsigned short *)PLL_STAT -#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT - -/* - * System Reset and Interrupt Controller registers for - * core A (0xFFC0 0100-0xFFC0 01FF) - */ -#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST -#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR -#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT -#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK -#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0 -#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1 -#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0 -#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1 -#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2 -#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3 -#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4 -#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5 -#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6 -#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7 -#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0 -#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1 -#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0 -#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1 - -/* - * System Reset and Interrupt Controller registers for - * Core B (0xFFC0 1100-0xFFC0 11FF) - */ -#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST -#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR -#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT -#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0 -#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1 -#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0 -#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1 -#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2 -#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3 -#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4 -#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5 -#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6 -#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7 -#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0 -#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1 -#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0 -#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1 - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL -#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT -#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT - -/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ -#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL -#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT -#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define pUART_THR (volatile unsigned short *)UART_THR -#define pUART_RBR (volatile unsigned short *)UART_RBR -#define pUART_DLL (volatile unsigned short *)UART_DLL -#define pUART_IER (volatile unsigned short *)UART_IER -#define pUART_DLH (volatile unsigned short *)UART_DLH -#define pUART_IIR (volatile unsigned short *)UART_IIR -#define pUART_LCR (volatile unsigned short *)UART_LCR -#define pUART_MCR (volatile unsigned short *)UART_MCR -#define pUART_LSR (volatile unsigned short *)UART_LSR -#define pUART_MSR (volatile unsigned short *)UART_MSR -#define pUART_SCR (volatile unsigned short *)UART_SCR -#define pUART_GCTL (volatile unsigned short *)UART_GCTL - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define pSPI_CTL (volatile unsigned short *)SPI_CTL -#define pSPI_FLG (volatile unsigned short *)SPI_FLG -#define pSPI_STAT (volatile unsigned short *)SPI_STAT -#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR -#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR -#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD -#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW - -/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ -#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG -#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER -#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD -#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH -#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG -#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER -#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD -#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH -#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG -#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER -#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD -#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH -#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG -#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER -#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD -#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH -#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG -#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER -#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD -#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH -#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG -#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER -#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD -#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH -#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG -#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER -#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD -#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH -#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG -#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER -#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD -#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH - -/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ -#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE -#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE -#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS -#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG -#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER -#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD -#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH -#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG -#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER -#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD -#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH -#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG -#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER -#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD -#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH -#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG -#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER -#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD -#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH -#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE -#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE -#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D -#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C -#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S -#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T -#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D -#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C -#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S -#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T -#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D -#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C -#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S -#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T -#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR -#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR -#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE -#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH -#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN - -/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ -#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D -#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C -#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S -#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T -#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D -#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C -#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S -#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T -#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D -#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C -#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S -#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T -#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR -#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR -#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE -#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH -#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN - -/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ -#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D -#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C -#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S -#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T -#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D -#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C -#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S -#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T -#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D -#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C -#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S -#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T -#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR -#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR -#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE -#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH -#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1 -#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2 -#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV -#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV -#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX -#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX -#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1 -#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2 -#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV -#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV -#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT -#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL -#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1 -#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2 -#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0 -#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1 -#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2 -#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3 -#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0 -#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1 -#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2 -#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3 - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1 -#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2 -#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV -#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV -#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX -#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX -#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1 -#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2 -#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV -#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV -#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT -#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL -#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1 -#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2 -#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0 -#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1 -#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2 -#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3 -#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0 -#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1 -#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2 -#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3 - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL -#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0 -#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1 - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL -#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL -#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC -#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ -#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL -#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS -#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT -#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY -#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME - -/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/ -#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL -#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS -#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT -#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY -#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME - -/*DMA Traffic controls*/ -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) -#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER) -#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT) - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG -#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR -#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR -#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT -#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT -#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY -#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY -#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR -#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR -#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT -#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT -#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS -#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP -#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG -#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR -#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR -#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT -#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT -#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY -#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY -#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR -#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR -#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT -#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT -#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS -#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP -#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG -#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR -#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR -#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT -#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT -#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY -#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY -#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR -#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR -#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT -#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT -#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS -#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP -#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG -#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR -#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR -#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT -#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT -#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY -#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY -#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR -#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR -#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT -#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT -#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS -#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP -#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG -#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR -#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR -#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT -#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT -#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY -#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY -#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR -#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR -#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT -#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT -#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS -#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP -#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG -#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR -#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR -#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT -#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT -#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY -#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY -#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR -#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR -#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT -#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT -#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS -#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP -#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG -#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR -#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR -#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT -#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT -#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY -#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY -#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR -#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR -#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT -#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT -#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS -#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP -#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG -#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR -#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR -#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT -#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT -#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY -#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY -#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR -#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR -#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT -#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT -#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS -#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP -#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG -#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR -#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR -#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT -#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT -#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY -#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY -#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR -#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR -#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT -#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT -#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS -#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP -#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG -#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR -#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR -#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT -#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT -#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY -#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY -#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR -#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR -#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT -#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT -#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS -#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP -#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG -#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR -#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR -#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT -#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT -#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY -#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY -#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR -#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR -#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT -#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT -#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS -#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP -#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG -#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR -#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR -#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT -#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT -#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY -#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY -#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR -#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR -#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT -#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT -#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS -#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/ -#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG -#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR -#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR -#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT -#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT -#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY -#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY -#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR -#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR -#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT -#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT -#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS -#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP -#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG -#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR -#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR -#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT -#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT -#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY -#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY -#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR -#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR -#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT -#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT -#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS -#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP -#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG -#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR -#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR -#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT -#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT -#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY -#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY -#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR -#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR -#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT -#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT -#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS -#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP -#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG -#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR -#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR -#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT -#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT -#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY -#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY -#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR -#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR -#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT -#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT -#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS -#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG -#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR -#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR -#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT -#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT -#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY -#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY -#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR -#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR -#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT -#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT -#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS -#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP -#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG -#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR -#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR -#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT -#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT -#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY -#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY -#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR -#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR -#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT -#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT -#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS -#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP -#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG -#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR -#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR -#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT -#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT -#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY -#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY -#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR -#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR -#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT -#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT -#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS -#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP -#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG -#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR -#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR -#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT -#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT -#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY -#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY -#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR -#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR -#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT -#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT -#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS -#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP -#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG -#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR -#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR -#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT -#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT -#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY -#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY -#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR -#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR -#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT -#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT -#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS -#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP -#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG -#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR -#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR -#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT -#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT -#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY -#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY -#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR -#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR -#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT -#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT -#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS -#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP -#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG -#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR -#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR -#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT -#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT -#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY -#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY -#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR -#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR -#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT -#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT -#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS -#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP -#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG -#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR -#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR -#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT -#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT -#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY -#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY -#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR -#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR -#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT -#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT -#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS -#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP -#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG -#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR -#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR -#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT -#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT -#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY -#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY -#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR -#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR -#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT -#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT -#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS -#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP -#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG -#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR -#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR -#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT -#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT -#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY -#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY -#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR -#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR -#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT -#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT -#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS -#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP -#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG -#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR -#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR -#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT -#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT -#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY -#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY -#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR -#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR -#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT -#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT -#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS -#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP -#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG -#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR -#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR -#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT -#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT -#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY -#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY -#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR -#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR -#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT -#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT -#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS -#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP - -/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG -#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR -#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR -#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT -#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT -#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY -#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY -#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR -#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR -#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT -#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT -#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS -#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP -#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG -#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR -#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR -#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT -#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT -#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY -#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY -#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR -#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR -#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT -#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT -#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS -#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP -#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG -#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR -#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR -#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT -#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT -#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY -#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY -#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR -#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR -#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT -#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT -#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS -#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP -#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG -#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR -#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR -#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT -#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT -#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY -#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY -#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR -#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR -#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT -#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT -#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS -#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP - -/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ -#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG -#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR -#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR -#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT -#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT -#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY -#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY -#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR -#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR -#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT -#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT -#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS -#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG -#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR -#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR -#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT -#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT -#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY -#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY -#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR -#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR -#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT -#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT -#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS -#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG -#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR -#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR -#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT -#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT -#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY -#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY -#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR -#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR -#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT -#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT -#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS -#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG -#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR -#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR -#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT -#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT -#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY -#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY -#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR -#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR -#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT -#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT -#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS - -/* - * System Reset and Interrupt Controller registers for - * core A (0xFFC0 0100-0xFFC0 01FF) - */ -#define pSWRST (volatile unsigned short *)SICA_SWRST -#define pSYSCR (volatile unsigned short *)SICA_SYSCR -#define pRVECT (volatile unsigned short *)SICA_RVECT -#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST -#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR -#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT -#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK -#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0) -#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1 -#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2 -#define pSIC_ISR (volatile unsigned long *)SICA_ISR0 -#define pSIC_IWR (volatile unsigned long *)SICA_IWR0 - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL -#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT -#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D -#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C -#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S -#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T -#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D -#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C -#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S -#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T -#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D -#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C -#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S -#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T -#define pFIO_DIR (volatile unsigned short *)FIO0_DIR -#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR -#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE -#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH -#define pFIO_INEN (volatile unsigned short *)FIO0_INEN - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ -#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL -#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS -#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT -#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY -#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG -#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR -#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR -#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT -#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT -#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY -#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY -#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR -#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR -#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT -#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT -#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS -#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG -#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR -#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR -#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT -#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT -#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY -#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY -#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR -#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR -#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT -#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT -#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS -#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP -#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG -#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR -#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR -#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT -#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT -#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY -#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY -#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR -#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR -#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT -#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT -#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS -#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP -#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG -#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR -#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR -#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT -#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT -#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY -#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY -#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR -#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR -#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT -#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT -#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS -#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP -#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG -#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR -#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR -#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT -#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT -#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY -#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY -#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR -#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR -#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT -#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT -#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS -#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG -#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR -#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR -#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT -#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT -#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY -#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY -#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR -#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR -#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT -#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT -#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS -#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP -#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG -#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR -#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR -#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT -#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT -#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY -#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY -#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR -#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR -#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT -#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT -#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS -#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP -#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG -#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR -#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR -#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT -#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT -#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY -#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY -#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR -#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR -#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT -#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT -#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS -#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP -#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG -#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR -#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR -#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT -#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT -#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY -#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY -#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR -#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR -#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT -#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT -#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS -#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP -#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG -#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR -#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR -#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT -#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT -#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY -#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY -#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR -#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR -#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT -#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT -#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS -#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP -#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG -#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR -#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR -#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT -#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT -#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY -#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY -#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR -#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR -#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT -#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT -#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS -#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP -#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG -#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR -#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR -#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT -#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT -#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY -#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY -#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR -#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR -#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT -#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT -#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS -#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP - -#endif /* _CDEF_BF561_H */ diff --git a/include/asm-blackfin/arch-bf561/defBF561.h b/include/asm-blackfin/arch-bf561/defBF561.h deleted file mode 100644 index c6e3de5bf4..0000000000 --- a/include/asm-blackfin/arch-bf561/defBF561.h +++ /dev/null @@ -1,1941 +0,0 @@ -/* - * defBF561.h - * - * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. - * - */ - -/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ - -#ifndef _DEF_BF561_H -#define _DEF_BF561_H - -/* - * #if !defined(__ADSPBF561__) - * #warning defBF561.h should only be included for BF561 chip. - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/arch-common/def_LPBlackfin.h> - -/* - * Helper macros - * usage: - * P0.H = HI(UART_THR); - * P0.L = LO(UART_THR); - */ - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register */ - -/* - * System Reset and Interrupt Controller registers for - * core A (0xFFC0 0100-0xFFC0 01FF) - */ -#define SICA_SWRST 0xFFC00100 /* Software Reset register */ -#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ -#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ -#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ -#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ -#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ -#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ -#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ -#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ -#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ -#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ -#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ -#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ -#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ -#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ - -/* - * System Reset and Interrupt Controller registers for - * Core B (0xFFC0 1100-0xFFC0 11FF) - */ -#define SICB_SWRST 0xFFC01100 /* reserved */ -#define SICB_SYSCR 0xFFC01104 /* reserved */ -#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ -#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ -#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ -#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ -#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ -#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ -#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ -#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ -#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ -#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ -#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ -#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ -#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ -#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ -#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ -#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ - -/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ -#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ -#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ -#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -#define UART_MSR 0xFFC00418 /* Modem Status Register */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ -#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ -#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ -#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ -#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ -#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ -#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ -#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ -#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ -#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ - -/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ -#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ -#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ -#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ -#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ -#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ -#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ -#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ -#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ -#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ -#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ -#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ -#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ -#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ -#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ -#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ -#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ -#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ -#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ -#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ -#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ -#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ -#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ -#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ -#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ -#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ -#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ -#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ -#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ -#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ -#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ -#define FIO0_DIR 0xFFC00730 /* Flag Direction register */ -#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ -#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ -#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ -#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ - -/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ -#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register */ -#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ -#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ -#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register */ -#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ -#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ -#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ -#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ -#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ -#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ -#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ -#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ -#define FIO1_DIR 0xFFC01530 /* Flag Direction register */ -#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ -#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ -#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ -#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ - -/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ -#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register */ -#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ -#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ -#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register */ -#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ -#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ -#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ -#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ -#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ -#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ -#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ -#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ -#define FIO2_DIR 0xFFC01730 /* Flag Direction register */ -#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ -#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ -#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ -#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ -#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ -#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ -#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ -#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ -#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ - -/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ -#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ -#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ -#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ -#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ -#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ - -/* DMA Traffic controls */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ -#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ -#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ -#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ -#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ -#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ -#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ -#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ -#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ -#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ -#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ -#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt Status Register */ -#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ - -#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ -#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ -#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ -#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ -#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ -#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ -#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ -#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ -#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ -#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ -#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ -#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt Status Register */ -#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ - -#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ -#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ -#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ -#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ -#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ -#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ -#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ -#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ -#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ -#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ -#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ -#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt Status Register */ -#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ - -#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ -#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ -#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ -#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ -#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ -#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ -#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ -#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ -#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ -#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ -#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ -#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt Status Register */ -#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ - -#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ -#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ -#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ -#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ -#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ -#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ -#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ -#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ -#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ -#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ -#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ -#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt Status Register */ -#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ - -#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ -#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ -#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ -#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ -#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ -#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ -#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ -#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ -#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ -#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ -#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ -#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt Status Register */ -#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ - -#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ -#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ -#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ -#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ -#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ -#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ -#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ -#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ -#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ -#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ -#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ -#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt Status Register */ -#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ - -#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ -#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ -#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ -#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ -#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ -#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ -#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ -#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ -#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ -#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ -#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ -#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt Status Register */ -#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ - -#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ -#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ -#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ -#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ -#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ -#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ -#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ -#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ -#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ -#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ -#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ -#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt Status Register */ -#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ - -#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ -#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ -#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ -#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ -#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ -#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ -#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ -#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ -#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ -#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ -#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ -#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt Status Register */ -#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ - -#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ -#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ -#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ -#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ -#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ -#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ -#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ -#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ -#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ -#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ -#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ -#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt Status Register */ -#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ - -#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ -#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ -#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ -#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ -#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ -#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ -#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ -#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ -#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ -#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ -#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ -#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt Status Register */ -#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration */ -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address */ -#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination Inner-Loop Count */ -#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Outer-Loop Count */ -#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address */ -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Dest Current Inner-Loop Count */ -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Dest Current Outer-Loop Count */ -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status */ -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map */ - -#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration */ -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address */ -#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source Inner-Loop Count */ -#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Outer-Loop Count */ -#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address */ -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current Inner-Loop Count */ -#define MDMA1_S0_CURR_Y_COUNT ` 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Outer-Loop Count */ -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status */ -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map */ - -#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration */ -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address */ -#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination Inner-Loop Count */ -#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Outer-Loop Count */ -#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Dest Current Address */ -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Dest Current Inner-Loop Count */ -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Dest Current Outer-Loop Count */ -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Dest Interrupt/Status */ -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Dest Peripheral Map */ - -#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration */ -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address */ -#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source Inner-Loop Count */ -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Outer-Loop Count */ -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address */ -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current Inner-Loop Count */ -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Outer-Loop Count */ -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status */ -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map */ - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ -#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ -#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ -#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ -#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ -#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ -#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ -#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ -#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ -#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ -#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ -#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt Status Register */ -#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ - -#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ -#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ -#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ -#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ -#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ -#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ -#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ -#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ -#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ -#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ -#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ -#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt Status Register */ -#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ - -#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ -#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ -#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ -#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ -#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ -#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ -#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ -#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ -#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ -#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ -#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ -#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt Status Register */ -#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ - -#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ -#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ -#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ -#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ -#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ -#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ -#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ -#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ -#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ -#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ -#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ -#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt Status Register */ -#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ - -#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ -#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ -#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ -#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ -#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ -#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ -#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ -#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ -#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ -#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ -#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ -#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt Status Register */ -#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ - -#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ -#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ -#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ -#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ -#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ -#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ -#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ -#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ -#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ -#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ -#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ -#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt Status Register */ -#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ - -#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ -#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ -#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ -#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ -#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ -#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ -#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ -#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ -#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ -#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ -#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ -#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt Status Register */ -#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ - -#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ -#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ -#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ -#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ -#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ -#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ -#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ -#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ -#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ -#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ -#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ -#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt Status Register */ -#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ - -#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ -#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ -#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ -#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ -#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ -#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ -#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ -#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ -#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ -#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ -#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ -#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt Status Register */ -#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ - -#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ -#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ -#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ -#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ -#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ -#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ -#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ -#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ -#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ -#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ -#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ -#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt Status Register */ -#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ - -#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ -#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ -#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ -#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ -#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ -#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ -#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ -#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ -#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ -#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ -#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ -#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt Status Register */ -#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ - -#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ -#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ -#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ -#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ -#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ -#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ -#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ -#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ -#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ -#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ -#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ -#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt Status Register */ -#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ - -/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define MDMA2_D0_CONFIG 0xFFC00F08 /* MemDMA2 Stream 0 Destination Configuration register */ -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D0_START_ADDR 0xFFC00F04 /* MemDMA2 Stream 0 Destination Start Address */ -#define MDMA2_D0_X_COUNT 0xFFC00F10 /* MemDMA2 Stream 0 Dest Inner-Loop Count register */ -#define MDMA2_D0_Y_COUNT 0xFFC00F18 /* MemDMA2 Stream 0 Dest Outer-Loop Count register */ -#define MDMA2_D0_X_MODIFY 0xFFC00F14 /* MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /* MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /* MemDMA2 Stream 0 Destination Current Address */ -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA2 Stream 0 Dest Interrupt/Status Register */ -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA2 Stream 0 Destination Peripheral Map register */ - -#define MDMA2_S0_CONFIG 0xFFC00F48 /* MemDMA2 Stream 0 Source Configuration register */ -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA2_S0_START_ADDR 0xFFC00F44 /* MemDMA2 Stream 0 Source Start Address */ -#define MDMA2_S0_X_COUNT 0xFFC00F50 /* MemDMA2 Stream 0 Source Inner-Loop Count register */ -#define MDMA2_S0_Y_COUNT 0xFFC00F58 /* MemDMA2 Stream 0 Source Outer-Loop Count register */ -#define MDMA2_S0_X_MODIFY 0xFFC00F54 /* MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /* MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /* MemDMA2 Stream 0 Source Current Address */ -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA2 Stream 0 Source Interrupt/Status Register */ -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA2 Stream 0 Source Peripheral Map register */ - -#define MDMA2_D1_CONFIG 0xFFC00F88 /* MemDMA2 Stream 1 Destination Configuration register */ -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D1_START_ADDR 0xFFC00F84 /* MemDMA2 Stream 1 Destination Start Address */ -#define MDMA2_D1_X_COUNT 0xFFC00F90 /* MemDMA2 Stream 1 Dest Inner-Loop Count register */ -#define MDMA2_D1_Y_COUNT 0xFFC00F98 /* MemDMA2 Stream 1 Dest Outer-Loop Count register */ -#define MDMA2_D1_X_MODIFY 0xFFC00F94 /* MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /* MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA2 Stream 1 Destination Current Descriptor Ptr */ -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA2 Stream 1 Destination Current Address reg */ -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA2 Stream 1 Destination Interrupt/Status Reg */ -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA2 Stream 1 Destination Peripheral Map register */ - -#define MDMA2_S1_CONFIG 0xFFC00FC8 /* MemDMA2 Stream 1 Source Configuration register */ -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA2_S1_START_ADDR 0xFFC00FC4 /* MemDMA2 Stream 1 Source Start Address */ -#define MDMA2_S1_X_COUNT 0xFFC00FD0 /* MemDMA2 Stream 1 Source Inner-Loop Count register */ -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /* MemDMA2 Stream 1 Source Outer-Loop Count register */ -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /* MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /* MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA2 Stream 1 Source Current Address */ -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA2 Stream 1 Source Current Inner-Loop Count */ -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA2 Stream 1 Source Current Outer-Loop Count */ -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA2 Stream 1 Source Interrupt/Status Register */ -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA2 Stream 1 Source Peripheral Map register */ - -/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ -#define IMDMA_D0_CONFIG 0xFFC01808 /* IMDMA Stream 0 Destination Configuration */ -#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /* IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ -#define IMDMA_D0_START_ADDR 0xFFC01804 /* IMDMA Stream 0 Destination Start Address */ -#define IMDMA_D0_X_COUNT 0xFFC01810 /* IMDMA Stream 0 Destination Inner-Loop Count */ -#define IMDMA_D0_Y_COUNT 0xFFC01818 /* IMDMA Stream 0 Destination Outer-Loop Count */ -#define IMDMA_D0_X_MODIFY 0xFFC01814 /* IMDMA Stream 0 Dest Inner-Loop Address-Increment */ -#define IMDMA_D0_Y_MODIFY 0xFFC0181C /* IMDMA Stream 0 Dest Outer-Loop Address-Increment */ -#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /* IMDMA Stream 0 Destination Current Descriptor Ptr */ -#define IMDMA_D0_CURR_ADDR 0xFFC01824 /* IMDMA Stream 0 Destination Current Address */ -#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /* IMDMA Stream 0 Destination Current Inner-Loop Count */ -#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /* IMDMA Stream 0 Destination Current Outer-Loop Count */ -#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /* IMDMA Stream 0 Destination Interrupt/Status */ - -#define IMDMA_S0_CONFIG 0xFFC01848 /* IMDMA Stream 0 Source Configuration */ -#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /* IMDMA Stream 0 Source Next Descriptor Ptr Reg */ -#define IMDMA_S0_START_ADDR 0xFFC01844 /* IMDMA Stream 0 Source Start Address */ -#define IMDMA_S0_X_COUNT 0xFFC01850 /* IMDMA Stream 0 Source Inner-Loop Count */ -#define IMDMA_S0_Y_COUNT 0xFFC01858 /* IMDMA Stream 0 Source Outer-Loop Count */ -#define IMDMA_S0_X_MODIFY 0xFFC01854 /* IMDMA Stream 0 Source Inner-Loop Address-Increment */ -#define IMDMA_S0_Y_MODIFY 0xFFC0185C /* IMDMA Stream 0 Source Outer-Loop Address-Increment */ -#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /* IMDMA Stream 0 Source Current Descriptor Ptr reg */ -#define IMDMA_S0_CURR_ADDR 0xFFC01864 /* IMDMA Stream 0 Source Current Address */ -#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /* IMDMA Stream 0 Source Current Inner-Loop Count */ -#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /* IMDMA Stream 0 Source Current Outer-Loop Count */ -#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /* IMDMA Stream 0 Source Interrupt/Status */ - -#define IMDMA_D1_CONFIG 0xFFC01888 /* IMDMA Stream 1 Destination Configuration */ -#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /* IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ -#define IMDMA_D1_START_ADDR 0xFFC01884 /* IMDMA Stream 1 Destination Start Address */ -#define IMDMA_D1_X_COUNT 0xFFC01890 /* IMDMA Stream 1 Destination Inner-Loop Count */ -#define IMDMA_D1_Y_COUNT 0xFFC01898 /* IMDMA Stream 1 Destination Outer-Loop Count */ -#define IMDMA_D1_X_MODIFY 0xFFC01894 /* IMDMA Stream 1 Dest Inner-Loop Address-Increment */ -#define IMDMA_D1_Y_MODIFY 0xFFC0189C /* IMDMA Stream 1 Dest Outer-Loop Address-Increment */ -#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /* IMDMA Stream 1 Destination Current Descriptor Ptr */ -#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /* IMDMA Stream 1 Destination Current Address */ -#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /* IMDMA Stream 1 Destination Current Inner-Loop Count */ -#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /* IMDMA Stream 1 Destination Current Outer-Loop Count */ -#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /* IMDMA Stream 1 Destination Interrupt/Status */ - -#define IMDMA_S1_CONFIG 0xFFC018C8 /* IMDMA Stream 1 Source Configuration */ -#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /* IMDMA Stream 1 Source Next Descriptor Ptr Reg */ -#define IMDMA_S1_START_ADDR 0xFFC018C4 /* IMDMA Stream 1 Source Start Address */ -#define IMDMA_S1_X_COUNT 0xFFC018D0 /* IMDMA Stream 1 Source Inner-Loop Count */ -#define IMDMA_S1_Y_COUNT 0xFFC018D8 /* IMDMA Stream 1 Source Outer-Loop Count */ -#define IMDMA_S1_X_MODIFY 0xFFC018D4 /* IMDMA Stream 1 Source Inner-Loop Address-Increment */ -#define IMDMA_S1_Y_MODIFY 0xFFC018DC /* IMDMA Stream 1 Source Outer-Loop Address-Increment */ -#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /* IMDMA Stream 1 Source Current Descriptor Ptr reg */ -#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /* IMDMA Stream 1 Source Current Address */ -#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /* IMDMA Stream 1 Source Current Inner-Loop Count */ -#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /* IMDMA Stream 1 Source Current Outer-Loop Count */ -#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /* IMDMA Stream 1 Source Interrupt/Status */ - -/* - * System MMR Register Bits - */ - -/* PLL AND RESET MASKS */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ -#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x00000008 /* Core clock off */ -#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ -#define BYPASS 0x00000100 /* Bypass the PLL */ - -/* PLL_DIV Masks */ - -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ -#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ -#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ -#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ -#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ -#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ - -/* - * SYSTEM INTERRUPT CONTROLLER MASKS - * SICu_IARv Masks - * u = A or B - * v = 0 to 7 - * w = 0 or 1 - - * Per_number = 0 to 63 - * IVG_number = 7 to 15 - * Peripheral #Per_number assigned IVG #IVG_number - * Usage: - * r0.l = lo(Peripheral_IVG(62, 10)); - * r0.h = hi(Peripheral_IVG(62, 10)); - */ -#define Peripheral_IVG(Per_number, IVG_number) \ - ( (IVG_number) -7) << ( ((Per_number)%8) *4) - -/* SICx_IMASKw Masks */ -/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x)))/* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -/* x = pos 0 to 31, for 32-63 use value-32 */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -/* Wakeup Disable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) - -/* - * WATCHDOG TIMER MASKS - */ - -/* Watchdog Timer WDOG_CTL Register */ -#define WDOGA_CTL 0xFFC00200 -#define WDOGA_CNT 0xFFC00204 -#define WDOGA_STAT 0xFFC00208 -#define WDOGB_CTL 0xFFC01200 -#define WDOGB_CNT 0xFFC01204 -#define WDOGB_STAT 0xFFC01208 -#define ICTL(x) ((x<<1) & 0x0006) -#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ -#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ -#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ -#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ - -#define TMR_EN 0x0000 -#define TMR_DIS 0x0AD0 -#define TRO 0x8000 - -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR Register */ - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* - * SERIAL PORT MASKS - */ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /* TX Word Length */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define RULAW 0x0008 /* u-Law enable */ -#define RALAW 0x000C /* A-Law enable */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ -#define WOFF 0x000003FF /* Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ -#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /* Multichannel Frame Delay */ - -/* - * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS - */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* - * DMA CONTROLLER MASKS - */ - -/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define FLOW 0x00007000 /* Flow Control */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ - -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -/* - * GENERAL PURPOSE TIMER MASKS - */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 -#define TIMEN3 0x0008 -#define TIMEN4 0x0010 -#define TIMEN5 0x0020 -#define TIMEN6 0x0040 -#define TIMEN7 0x0080 -#define TIMEN8 0x0001 -#define TIMEN9 0x0002 -#define TIMEN10 0x0004 -#define TIMEN11 0x0008 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 -#define TIMEN3_P 0x03 -#define TIMEN4_P 0x04 -#define TIMEN5_P 0x05 -#define TIMEN6_P 0x06 -#define TIMEN7_P 0x07 -#define TIMEN8_P 0x00 -#define TIMEN9_P 0x01 -#define TIMEN10_P 0x02 -#define TIMEN11_P 0x03 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 -#define TIMDIS3 0x0008 -#define TIMDIS4 0x0010 -#define TIMDIS5 0x0020 -#define TIMDIS6 0x0040 -#define TIMDIS7 0x0080 -#define TIMDIS8 0x0001 -#define TIMDIS9 0x0002 -#define TIMDIS10 0x0004 -#define TIMDIS11 0x0008 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 -#define TIMDIS3_P 0x03 -#define TIMDIS4_P 0x04 -#define TIMDIS5_P 0x05 -#define TIMDIS6_P 0x06 -#define TIMDIS7_P 0x07 -#define TIMDIS8_P 0x00 -#define TIMDIS9_P 0x01 -#define TIMDIS10_P 0x02 -#define TIMDIS11_P 0x03 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x00000001 -#define TIMIL1 0x00000002 -#define TIMIL2 0x00000004 -#define TIMIL3 0x00000008 -#define TIMIL4 0x00010000 -#define TIMIL5 0x00020000 -#define TIMIL6 0x00040000 -#define TIMIL7 0x00080000 -#define TIMIL8 0x0001 -#define TIMIL9 0x0002 -#define TIMIL10 0x0004 -#define TIMIL11 0x0008 -#define TOVL_ERR0 0x00000010 -#define TOVL_ERR1 0x00000020 -#define TOVL_ERR2 0x00000040 -#define TOVL_ERR3 0x00000080 -#define TOVL_ERR4 0x00100000 -#define TOVL_ERR5 0x00200000 -#define TOVL_ERR6 0x00400000 -#define TOVL_ERR7 0x00800000 -#define TOVL_ERR8 0x0010 -#define TOVL_ERR9 0x0020 -#define TOVL_ERR10 0x0040 -#define TOVL_ERR11 0x0080 -#define TRUN0 0x00001000 -#define TRUN1 0x00002000 -#define TRUN2 0x00004000 -#define TRUN3 0x00008000 -#define TRUN4 0x10000000 -#define TRUN5 0x20000000 -#define TRUN6 0x40000000 -#define TRUN7 0x80000000 -#define TRUN8 0x1000 -#define TRUN9 0x2000 -#define TRUN10 0x4000 -#define TRUN11 0x8000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TIMIL3_P 0x03 -#define TIMIL4_P 0x10 -#define TIMIL5_P 0x11 -#define TIMIL6_P 0x12 -#define TIMIL7_P 0x13 -#define TIMIL8_P 0x00 -#define TIMIL9_P 0x01 -#define TIMIL10_P 0x02 -#define TIMIL11_P 0x03 -#define TOVL_ERR0_P 0x04 -#define TOVL_ERR1_P 0x05 -#define TOVL_ERR2_P 0x06 -#define TOVL_ERR3_P 0x07 -#define TOVL_ERR4_P 0x14 -#define TOVL_ERR5_P 0x15 -#define TOVL_ERR6_P 0x16 -#define TOVL_ERR7_P 0x17 -#define TOVL_ERR8_P 0x04 -#define TOVL_ERR9_P 0x05 -#define TOVL_ERR10_P 0x06 -#define TOVL_ERR11_P 0x07 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E -#define TRUN3_P 0x0F -#define TRUN4_P 0x1C -#define TRUN5_P 0x1D -#define TRUN6_P 0x1E -#define TRUN7_P 0x1F -#define TRUN8_P 0x0C -#define TRUN9_P 0x0D -#define TRUN10_P 0x0E -#define TRUN11_P 0x0F - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* - * PROGRAMMABLE FLAG MASKS - */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* - * SERIAL PERIPHERAL INTERFACE (SPI) MASKS - */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ - -/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer.*/ -#define CPHA 0x00000400 -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* - * ASYNCHRONOUS MEMORY CONTROLLER MASKS - */ - -/* AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0,/ 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ -#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ -#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ |