diff options
713 files changed, 13555 insertions, 6634 deletions
diff --git a/.travis.yml b/.travis.yml index 67674e2f58..18bf2ed4fc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,6 +3,8 @@ # build U-Boot on Travis CI - https://travis-ci.org/ +sudo: true + language: c addons: @@ -14,6 +16,8 @@ addons: - bc - build-essential - libsdl1.2-dev + - python + - python-virtualenv cache: - apt @@ -36,6 +40,9 @@ install: - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman - cat ~/.buildman + - virtualenv /tmp/venv + - . /tmp/venv/bin/activate + - pip install pytest env: global: @@ -175,5 +182,8 @@ matrix: # some statistics about the code base - env: - TEST_CMD="sloccount ." + # test/py + - env: + - TEST_CMD="./test/py/test.py --bd sandbox --build" # TODO make it perfect ;-r @@ -5,7 +5,7 @@ VERSION = 2016 PATCHLEVEL = 03 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -562,10 +562,6 @@ else KBUILD_CFLAGS += -O2 endif -ifdef BUILD_TAG -KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' -endif - KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks) @@ -732,7 +728,7 @@ DO_STATIC_RELA = endif # Always append ALL so that arch config.mk's can add custom ones -ALL-y += u-boot.srec u-boot.bin System.map u-boot.cfg binary_size_check +ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) @@ -924,7 +920,7 @@ u-boot.sha1: u-boot.bin u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -u-boot.cfg: include/config.h +u-boot.cfg: include/config.h FORCE $(call if_changed,cpp_cfg) ifdef CONFIG_TPL @@ -945,15 +941,15 @@ lpc32xx-spl.img: spl/u-boot-spl.bin FORCE OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) -lpc32xx-boot-0.bin: lpc32xx-spl.img +lpc32xx-boot-0.bin: lpc32xx-spl.img FORCE $(call if_changed,objcopy) OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) -lpc32xx-boot-1.bin: lpc32xx-spl.img +lpc32xx-boot-1.bin: lpc32xx-spl.img FORCE $(call if_changed,objcopy) -lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img FORCE $(call if_changed,cat) CLEAN_FILES += lpc32xx-* @@ -1056,7 +1052,7 @@ endif cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp; cmd_ifdtool += mv u-boot.tmp $@ -u-boot.rom: u-boot-x86-16bit.bin u-boot.bin +u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE $(call if_changed,ifdtool) OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec @@ -1171,13 +1167,18 @@ cmd_smap = \ $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ -c $(srctree)/common/system_map.c -o common/system_map.o -u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds +u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE $(call if_changed,u-boot__) ifeq ($(CONFIG_KALLSYMS),y) $(call cmd,smap) $(call cmd,u-boot__) common/system_map.o endif +quiet_cmd_sym ?= SYM $@ + cmd_sym ?= $(OBJDUMP) -t $< > $@ +u-boot.sym: u-boot FORCE + $(call if_changed,sym) + # The actual objects are generated when descending, # make sure no implicit rule kicks in $(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ; @@ -460,7 +460,7 @@ The following options need to be configured: CONFIG_SYS_CPC_REINIT_F This CONFIG is defined when the CPC is configured as SRAM at the - time of U-boot entry and is required to be re-initialized. + time of U-Boot entry and is required to be re-initialized. CONFIG_DEEP_SLEEP Indicates this SoC supports deep sleep feature. If deep sleep is @@ -1023,7 +1023,6 @@ The following options need to be configured: CONFIG_CMD_GO * the 'go' command (exec code) CONFIG_CMD_GREPENV * search environment CONFIG_CMD_HASH * calculate hash / digest - CONFIG_CMD_HWFLOW * RTS/CTS hw flow control CONFIG_CMD_I2C * I2C serial bus support CONFIG_CMD_IDE * IDE harddisk support CONFIG_CMD_IMI iminfo @@ -2905,6 +2904,14 @@ CBFS (Coreboot Filesystem) support Enable editing and History functions for interactive command line input operations +- Command Line PS1/PS2 support: + CONFIG_CMDLINE_PS_SUPPORT + + Enable support for changing the command prompt string + at run-time. Only static string is supported so far. + The string is obtained from environment variables PS1 + and PS2. + - Default Environment: CONFIG_EXTRA_ENV_SETTINGS @@ -2963,7 +2970,7 @@ CBFS (Coreboot Filesystem) support - Parallel Flash support: CONFIG_SYS_NO_FLASH - Traditionally U-boot was run on systems with parallel NOR + Traditionally U-Boot was run on systems with parallel NOR flash. This option is used to disable support for parallel NOR flash. This option should be defined if the board does not have parallel flash. @@ -3712,17 +3719,6 @@ FIT uImage format: CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL payload without any padding, or >= CONFIG_SPL_MAX_SIZE. -Modem Support: --------------- - -[so far only for SMDK2400 boards] - -- Modem support enable: - CONFIG_MODEM_SUPPORT - -- RTS/CTS Flow control enable: - CONFIG_HWFLOW - - Interrupt support (PPC): There are common interrupt_init() and timer_interrupt() @@ -3736,22 +3732,6 @@ Modem Support: / other_activity_monitor it works automatically from general timer_interrupt(). -- General: - - In the target system modem support is enabled when a - specific key (key combination) is pressed during - power-on. Otherwise U-Boot will boot normally - (autoboot). The key_pressed() function is called from - board_init(). Currently key_pressed() is a dummy - function, returning 1 and thus enabling modem - initialization. - - If there are no modem init strings in the - environment, U-Boot proceed to autoboot; the - previous output (banner, info printfs) will be - suppressed, though. - - See also: doc/README.Modem Board initialization settings: ------------------------------ diff --git a/api/Makefile b/api/Makefile index 3c095eedb6..14b7608596 100644 --- a/api/Makefile +++ b/api/Makefile @@ -7,3 +7,4 @@ obj-y += api.o api_display.o api_net.o api_storage.o obj-$(CONFIG_ARM) += api_platform-arm.o obj-$(CONFIG_PPC) += api_platform-powerpc.o +obj-$(CONFIG_MIPS) += api_platform-mips.o diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c new file mode 100644 index 0000000000..a75b0f6195 --- /dev/null +++ b/api/api_platform-mips.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2007 Stanislav Galabov <sgalabov@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file contains routines that fetch data from bd_info sources + */ + +#include <config.h> +#include <linux/types.h> +#include <api_public.h> + +#include <asm/u-boot.h> +#include <asm/global_data.h> + +#include "api_private.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Important notice: handling of individual fields MUST be kept in sync with + * include/asm-generic/u-boot.h, so any changes + * need to reflect their current state and layout of structures involved! + */ +int platform_sys_info(struct sys_info *si) +{ + + platform_set_mr(si, gd->bd->bi_memstart, + gd->bd->bi_memsize, MR_ATTR_DRAM); + + return 1; +} diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 264c83d261..f1dc6c8d77 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -116,17 +116,6 @@ config SYS_DCACHE_OFF bool "Do not use Data Cache" default n -config ARC_CACHE_LINE_SHIFT - int "Cache Line Length (as power of 2)" - range 5 7 - default "6" - depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF - help - Starting with ARC700 4.9, Cache line length is configurable, - This option specifies "N", with Line-len = 2 power N - So line lengths of 32, 64, 128 are specified by 5,6,7, respectively - Linux only supports same line lengths for I and D caches. - choice prompt "Target select" default TARGET_AXS101 diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 667f218bd8..cf999b0280 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -53,6 +53,13 @@ #define ARC_AUX_SLC_INVALIDATE 0x905 #define ARC_AUX_SLC_IVDL 0x910 #define ARC_AUX_SLC_FLDL 0x912 +#define ARC_BCR_CLUSTER 0xcf + +/* IO coherency related auxiliary registers */ +#define ARC_AUX_IO_COH_ENABLE 0x500 +#define ARC_AUX_IO_COH_PARTIAL 0x501 +#define ARC_AUX_IO_COH_AP0_BASE 0x508 +#define ARC_AUX_IO_COH_AP0_SIZE 0x509 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 432606a433..d26d9fb18d 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,13 +9,13 @@ #include <config.h> -#ifdef CONFIG_ARC_CACHE_LINE_SHIFT -#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -/* Satisfy users of ARCH_DMA_MINALIGN */ -#define ARCH_DMA_MINALIGN 128 -#endif +/* + * As of today we may handle any L1 cache line length right in software. + * For that essentially cache line length is a variable not constant. + * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length + * that may exist in either L1 or L2 (AKA SLC) caches on ARC. + */ +#define ARCH_DMA_MINALIGN 128 #if defined(ARC_MMU_ABSENT) #define CONFIG_ARC_MMU_VER 0 diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index ed8e8e74e2..56988dda18 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -5,13 +5,12 @@ */ #include <config.h> +#include <common.h> #include <linux/compiler.h> #include <linux/kernel.h> #include <asm/arcregs.h> #include <asm/cache.h> -#define CACHE_LINE_MASK (~(CONFIG_SYS_CACHELINE_SIZE - 1)) - /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE (1 << 0) @@ -26,14 +25,21 @@ #define OP_FLUSH 0x2 #define OP_INV_IC 0x3 -#ifdef CONFIG_ISA_ARCV2 /* * By default that variable will fall into .bss section. * But .bss section is not relocated and so it will be initilized before * relocation but will be used after being zeroed. */ +int l1_line_sz __section(".data"); +int dcache_exists __section(".data"); +int icache_exists __section(".data"); + +#define CACHE_LINE_MASK (~(l1_line_sz - 1)) + +#ifdef CONFIG_ISA_ARCV2 int slc_line_sz __section(".data"); int slc_exists __section(".data"); +int ioc_exists __section(".data"); static unsigned int __before_slc_op(const int op) { @@ -111,46 +117,113 @@ static inline void __slc_line_op(unsigned long paddr, unsigned long sz, #define __slc_line_op(paddr, sz, cacheop) #endif -static inline int icache_exists(void) +#ifdef CONFIG_ISA_ARCV2 +static void read_decode_cache_bcr_arcv2(void) { - /* Check if Instruction Cache is available */ - if (read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK) - return 1; - else - return 0; + union { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, way:2, lsz:2, sz:4; +#else + unsigned int sz:4, lsz:2, way:2, pad:24; +#endif + } fields; + unsigned int word; + } slc_cfg; + + union { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, ver:8; +#else + unsigned int ver:8, pad:24; +#endif + } fields; + unsigned int word; + } sbcr; + + sbcr.word = read_aux_reg(ARC_BCR_SLC); + if (sbcr.fields.ver) { + slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); + slc_exists = 1; + slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; + } + + union { + struct bcr_clust_cfg { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; +#else + unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; +#endif + } fields; + unsigned int word; + } cbcr; + + cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); + if (cbcr.fields.c) + ioc_exists = 1; } +#endif -static inline int dcache_exists(void) +void read_decode_cache_bcr(void) { - /* Check if Data Cache is available */ - if (read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK) - return 1; - else - return 0; + int dc_line_sz = 0, ic_line_sz = 0; + + union { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif + } fields; + unsigned int word; + } ibcr, dbcr; + + ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); + if (ibcr.fields.ver) { + icache_exists = 1; + l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; + if (!ic_line_sz) + panic("Instruction exists but line length is 0\n"); + } + + dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); + if (dbcr.fields.ver){ + dcache_exists = 1; + l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; + if (!dc_line_sz) + panic("Data cache exists but line length is 0\n"); + } + + if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) + panic("Instruction and data cache line lengths differ\n"); } void cache_init(void) { + read_decode_cache_bcr(); + #ifdef CONFIG_ISA_ARCV2 - /* Check if System-Level Cache (SLC) is available */ - if (read_aux_reg(ARC_BCR_SLC) & CACHE_VER_NUM_MASK) { -#define LSIZE_OFFSET 4 -#define LSIZE_MASK 3 - if (read_aux_reg(ARC_AUX_SLC_CONFIG) & - (LSIZE_MASK << LSIZE_OFFSET)) - slc_line_sz = 64; - else - slc_line_sz = 128; - slc_exists = 1; - } else { - slc_exists = 0; + read_decode_cache_bcr_arcv2(); + + if (ioc_exists) { + /* IO coherency base - 0x8z */ + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); + /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11); + /* Enable partial writes */ + write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); + /* Enable IO coherency */ + write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); } #endif } int icache_status(void) { - if (!icache_exists()) + if (!icache_exists) return 0; if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) @@ -161,14 +234,14 @@ int icache_status(void) void icache_enable(void) { - if (icache_exists()) + if (icache_exists) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & ~IC_CTRL_CACHE_DISABLE); } void icache_disable(void) { - if (icache_exists()) + if (icache_exists) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | IC_CTRL_CACHE_DISABLE); } @@ -190,7 +263,7 @@ void invalidate_icache_all(void) int dcache_status(void) { - if (!dcache_exists()) + if (!dcache_exists) return 0; if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) @@ -201,7 +274,7 @@ int dcache_status(void) void dcache_enable(void) { - if (!dcache_exists()) + if (!dcache_exists) return; write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & @@ -210,7 +283,7 @@ void dcache_enable(void) void dcache_disable(void) { - if (!dcache_exists()) + if (!dcache_exists) return; write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | @@ -246,14 +319,14 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long sz, sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK; - num_lines = DIV_ROUND_UP(sz, CONFIG_SYS_CACHELINE_SIZE); + num_lines = DIV_ROUND_UP(sz, l1_line_sz); while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER == 3) write_aux_reg(aux_tag, paddr); #endif write_aux_reg(aux_cmd, paddr); - paddr += CONFIG_SYS_CACHELINE_SIZE; + paddr += l1_line_sz; } } @@ -313,18 +386,26 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz, void invalidate_dcache_range(unsigned long start, unsigned long end) { - __dc_line_op(start, end - start, OP_INV); #ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (!ioc_exists) +#endif + __dc_line_op(start, end - start, OP_INV); + +#ifdef CONFIG_ISA_ARCV2 + if (slc_exists && !ioc_exists) __slc_line_op(start, end - start, OP_INV); #endif } void flush_dcache_range(unsigned long start, unsigned long end) { - __dc_line_op(start, end - start, OP_FLUSH); #ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (!ioc_exists) +#endif + __dc_line_op(start, end - start, OP_FLUSH); + +#ifdef CONFIG_ISA_ARCV2 + if (slc_exists && !ioc_exists) __slc_line_op(start, end - start, OP_FLUSH); #endif } @@ -336,18 +417,26 @@ void flush_cache(unsigned long start, unsigned long size) void invalidate_dcache_all(void) { - __dc_entire_op(OP_INV); #ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (!ioc_exists) +#endif + __dc_entire_op(OP_INV); + +#ifdef CONFIG_ISA_ARCV2 + if (slc_exists && !ioc_exists) __slc_entire_op(OP_INV); #endif } void flush_dcache_all(void) { - __dc_entire_op(OP_FLUSH); #ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (!ioc_exists) +#endif + __dc_entire_op(OP_FLUSH); + +#ifdef CONFIG_ISA_ARCV2 + if (slc_exists && !ioc_exists) __slc_entire_op(OP_FLUSH); #endif } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d2dbb1a5c2..d8b63e9407 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -689,6 +689,7 @@ config TARGET_COLIBRI_PXA270 config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" + select CLK_UNIPHIER select CPU_V7 select SUPPORT_SPL select SPL diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cd7d8803f3..6defdfb190 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -9,7 +9,7 @@ endif # This selects which instruction set is used. arch-$(CONFIG_CPU_ARM720T) =-march=armv4 -arch-$(CONFIG_CPU_ARM920T) =-march=armv4 +arch-$(CONFIG_CPU_ARM920T) =-march=armv4t arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te arch-$(CONFIG_CPU_ARM946ES) =-march=armv4 arch-$(CONFIG_CPU_SA1100) =-march=armv4 diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 6582938db0..1832b9d148 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -13,3 +13,9 @@ obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ obj-$(CONFIG_S3C24X0) += s3c24x0/ + +# some files can only build in ARM mode + +ifdef CONFIG_SYS_THUMB_BUILD +CFLAGS_cpu.o := -marm +endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index bee9318f5a..085649e712 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -46,7 +46,7 @@ void reset_cpu(ulong addr) int arch_cpu_init(void) { /* - * It might be necessary to flush data cache, if U-boot is loaded + * It might be necessary to flush data cache, if U-Boot is loaded * from kickstart bootloader, e.g. from S1L loader */ flush_dcache_all(); diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S index 4b8053e3f9..b21abc3752 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -41,5 +41,5 @@ lowlevel_init: orr r0, #0x00000004 str r0, [r1] - /* Return to U-boot via saved link register */ + /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 31d1c9e348..b7563edbe6 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -37,7 +37,7 @@ _monitor_vectors: /* * secure monitor handler - * U-boot calls this "software interrupt" in start.S + * U-Boot calls this "software interrupt" in start.S * This is executed on a "smc" instruction, we use a "smc #0" to switch * to non-secure state. * r0, r1, r2: passed to the callee diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 4fa72f7835..652d319a08 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -89,6 +89,7 @@ config TARGET_OMAP3_LOGIC select DM select DM_SERIAL select DM_GPIO + select SUPPORT_SPL config TARGET_NOKIA_RX51 bool "Nokia RX51" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4cd84b0311..3d19bbfbe2 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,6 +1,6 @@ if ARM64 config ARMV8_MULTIENTRY - boolean "Enable multiple CPUs to enter into U-boot" + boolean "Enable multiple CPUs to enter into U-Boot" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0fa5796946..b574284262 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -59,7 +59,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ uniphier-ph1-ld6b-ref.dtb \ + uniphier-ph1-pro4-ace.dtb \ uniphier-ph1-pro4-ref.dtb \ + uniphier-ph1-pro4-sanji.dtb \ uniphier-ph1-pro5-4kbox.dtb \ uniphier-ph1-sld3-ref.dtb \ uniphier-ph1-sld8-ref.dtb \ diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts index de50e8f862..0ca36ef39a 100644 --- a/arch/arm/dts/k2g-evm.dts +++ b/arch/arm/dts/k2g-evm.dts @@ -19,3 +19,15 @@ stdout-path = &uart0; }; }; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii-id"; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; +}; diff --git a/arch/arm/dts/k2g-netcp.dtsi b/arch/arm/dts/k2g-netcp.dtsi new file mode 100644 index 0000000000..6f0ff863af --- /dev/null +++ b/arch/arm/dts/k2g-netcp.dtsi @@ -0,0 +1,151 @@ +/* + * Device Tree Source for Keystone 2 Galileo Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@4020000 { + compatible = "ti,keystone-navigator-qmss-l"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 + 0 311 0xf04 0 312 0xf04 0 313 0xf04 + 0 314 0xf04 0 315 0xf04>; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +gbe_subsys: subsys@4200000 { + compatible = "syscon"; + reg = <0x4200000 0x100>; +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ + clock-names = "ethss_clk"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + syscon-subsys = <&gbe_subsys>; + reg = <0x200100 0xe00>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <5>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi index 6b79b163ff..bbc2cf91b9 100644 --- a/arch/arm/dts/k2g.dtsi +++ b/arch/arm/dts/k2g.dtsi @@ -68,5 +68,18 @@ interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; }; + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ + clock-names = "fck"; + reg = <0x04200f00 0x100>; + status = "disabled"; + bus_freq = <2500000>; + }; + + #include "k2g-netcp.dtsi" }; }; diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 51ff266d76..49195c3596 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -18,7 +18,8 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000400"; - usb0 = "/usb@7d008000"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; }; memory { @@ -67,6 +68,12 @@ status = "okay"; }; + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + usb@7d008000 { nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index e7b66d81a4..21ed1aef0b 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -325,6 +325,19 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 8be6adbf07..20e0be30e9 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -1,7 +1,6 @@ /dts-v1/; -#include <dt-bindings/input/input.h> -#include "tegra124.dtsi" +#include "tegra124-nyan.dtsi" / { model = "Acer Chromebook 13 CB5-311"; @@ -9,6 +8,7 @@ aliases { console = &uarta; + stdout-path = &uarta; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; @@ -23,14 +23,13 @@ spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; - }; - - memory { - reg = <0x80000000 0x80000000>; + usb2 = "/usb@7d004000"; }; host1x@50000000 { + u-boot,dm-pre-reloc; dc@54200000 { + u-boot,dm-pre-reloc; display-timings { timing@0 { clock-frequency = <69500000>; @@ -46,372 +45,1337 @@ }; }; - sor@54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - status = "okay"; - }; - }; - - serial@70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - spi-deactivate-delay = <200>; - spi-max-frequency = <3000000>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; - ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - sdhci@700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - non-removable; - }; - - sdhci@700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - }; - - sdhci@700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { /* Rear external USB port. */ - status = "okay"; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d004000 { /* Internal webcam. */ - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - }; - - usb@7d008000 { /* Left external USB port. */ - status = "okay"; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - }; - - usb-phy@7d008000 { - status = "okay"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio@6000d000 { - u-boot,dm-pre-reloc; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = <KEY_RESERVED>; - debounce-interval = <1>; - gpio-key,wakeup; + dc@54240000 { + status = "disabled"; }; - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <30>; - gpio-key,wakeup; - }; }; panel: panel { compatible = "auo,b133xtn01"; backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + sdhci@0,700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; sound { compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", "nvidia,tegra-audio-max98090"; - nvidia,model = "Acer Chromebook 13"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; + nvidia,model = "GoogleNyanBig"; + }; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + pinmux_default: common { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; }; }; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi new file mode 100644 index 0000000000..1b6931fae8 --- /dev/null +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -0,0 +1,718 @@ +#include <dt-bindings/input/input.h> +#include "tegra124.dtsi" + +/ { + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + serial@70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@70030000 { + status = "okay"; + }; + + sdhci0_pwrseq: sdhci0_pwrseq { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + }; + + sdhci@700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&sdhci0_pwrseq>; + vmmc-supply = <&vdd_3v3_lp0>; + vqmmc-supply = <&vddio_1v8>; + keep-power-in-suspend; + }; + + sdhci@700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "disabled"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + usb@7d000000 { /* Rear external USB port. */ + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@7d008000 { /* Left external USB port. */ + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <KEY_RESERVED>; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + nvidia,mic-det-gpios = + <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index 9e93cf90c7..9de86c0143 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -93,4 +93,18 @@ status = "okay"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 43b7f22814..275a509f75 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -1,14 +1,18 @@ #include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra124-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/tegra124-car.h> +#include <dt-bindings/thermal/tegra124-soctherm.h> #include "skeleton.dtsi" / { compatible = "nvidia,tegra124"; - interrupt-parent = <&gic>; + interrupt-parent = <&lic>; + pcie-controller@01003000 { compatible = "nvidia,tegra124-pcie"; @@ -100,6 +104,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; }; @@ -113,6 +119,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; }; @@ -165,49 +173,68 @@ <0x50046000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + gpu@57000000 { + compatible = "nvidia,gk20a"; + reg = <0x57000000 0x01000000>, + <0x58000000 0x01000000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pwr"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + + iommus = <&mc TEGRA_SWGROUP_GPU>; + + status = "disabled"; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + timer@60005000 { + compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; }; tegra_car: clock@60006000 { compatible = "nvidia,tegra124-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x60020000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; + flow-controller@60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x60007000 0x1000>; + }; + + actmon@6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x6000c800 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; }; gpio: gpio@6000d000 { @@ -225,68 +252,73 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + /* + gpio-ranges = <&pinmux 0 0 251>; + */ }; - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 54>; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 67>; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 103>; - status = "disabled"; + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x60020000 0x1400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - status = "disabled"; + apbmisc@70000800 { + compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x7000e864 0x04>; /* Strapping options */ }; - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d100 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - status = "disabled"; + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x70000868 0x164>, /* Pad control registers */ + <0x70003000 0x434>, /* Mux registers */ + <0x70000820 0x008>; /* MIPI pad control */ }; + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the comptible is + * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". + */ uarta: serial@70006000 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; @@ -339,19 +371,6 @@ status = "disabled"; }; - uarte: serial@70006400 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - pwm: pwm@7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; @@ -362,75 +381,254 @@ status = "disabled"; }; + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 54>; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d100 0x100>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&tegra_car 166>; + reset-names = "i2c"; + dmas = <&apbdma 30>, <&apbdma 30>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 41>; }; spi@7000d600 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 44>; }; spi@7000d800 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 46>; }; spi@7000da00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 68>; }; spi@7000dc00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; - nvidia,dma-request-selector = <&apbdma 27>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 104>; }; spi@7000de00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; - nvidia,dma-request-selector = <&apbdma 28>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; - clocks = <&tegra_car 105>; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_RTC>; }; pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra124-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA124_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + mc: memory-controller@70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x70019000 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; + }; + + emc: emc@7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x7001b000 0x1000>; + + nvidia,memory-controller = <&mc>; + }; + + sata@70020000 { + compatible = "nvidia,tegra124-ahci"; + reg = <0x70027000 0x2000>, /* AHCI */ + <0x70020000 0x7000>; /* SATA */ + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "sata", "sata-oob", "cml1", "pll_e"; + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + reset-names = "sata", "sata-oob", "sata-cold"; + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + hda@70030000 { + compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_HDA>, + <&tegra_car TEGRA124_CLK_HDA2HDMI>, + <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; }; padctl: padctl@7009f000 { @@ -445,32 +643,76 @@ sdhci@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; + }; + + soctherm: thermal-sensor@700e2000 { + compatible = "nvidia,tegra124-soctherm"; + reg = <0x700e2000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, + <&tegra_car TEGRA124_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + #thermal-sensor-cells = <1>; + }; + + dfll: clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; status = "disabled"; }; @@ -580,27 +822,206 @@ usb@7d000000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; reg = <0x7d000000 0x4000>; - interrupts = < 52 >; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + clocks = <&tegra_car TEGRA124_CLK_USBD>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; status = "disabled"; }; usb@7d004000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; reg = <0x7d004000 0x4000>; - interrupts = < 53 >; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "hsic"; - clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + clocks = <&tegra_car TEGRA124_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d004000 0x4000>, + <0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; status = "disabled"; }; usb@7d008000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; reg = <0x7d008000 0x4000>; - interrupts = < 129 >; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; status = "disabled"; }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>, + <&{/cpus/cpu@2}>, + <&{/cpus/cpu@3}>; + }; + + thermal-zones { + cpu { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + }; + + mem { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + }; + + gpu { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + }; + + pllx { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + }; }; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index f058d45c5c..2cf24d3ee7 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -20,7 +20,7 @@ sdhci0 = "/sdhci@c8000600"; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { status = "okay"; @@ -32,16 +32,19 @@ }; usb@c5000000 { + statuc = "okay"; dr_mode = "otg"; }; usb@c5004000 { + statuc = "okay"; /* VBUS_LAN */ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; usb@c5008000 { + statuc = "okay"; /* USBH_PEN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; @@ -88,6 +91,23 @@ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + lcd_panel: panel { clock = <25175000>; xres = <640>; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index e6e42295e2..623eb90a8a 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -21,7 +21,7 @@ reg = <0x00000000 0x40000000>; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { status = "okay"; @@ -46,30 +46,15 @@ }; }; - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - usb@c5004000 { + statuc = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; }; + usb@c5008000 { + status = "okay"; + }; + sdhci@c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -86,6 +71,23 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + lcd_panel: panel { clock = <42430000>; xres = <1024>; diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index b6b57abdef..3d37257189 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -19,7 +19,7 @@ reg = <0x00000000 0x20000000>; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { @@ -36,28 +36,12 @@ clock-frequency = <216000000>; }; - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; + usb@c5008000 { + status = "okay"; }; - usb@c5004000 { - status = "disabled"; + pwm: pwm@7000a000 { + status = "okay"; }; lcd_panel: panel { diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 16381c3a4c..5c7e80558d 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -20,7 +20,7 @@ reg = <0x00000000 0x20000000>; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { status = "okay"; @@ -35,28 +35,8 @@ clock-frequency = < 216000000 >; }; - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000000 { @@ -72,6 +52,23 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + lcd_panel: panel { /* PAZ00 has 1024x600 */ clock = <54030000>; diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index e5562a9ca5..7f57f1d4b5 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -38,12 +38,4 @@ i2c@7000d000 { status = "disabled"; }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; - }; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 10f399284a..eada59073e 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -31,7 +31,7 @@ reg = < 0x00000000 0x40000000 >; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { status = "okay"; @@ -40,10 +40,15 @@ nvidia,panel = <&lcd_panel>; }; }; + + dc@54240000 { + status = "disabled"; + }; }; /* This is not used in U-Boot, but is expected to be in kernel .dts */ i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; pmic@34 { compatible = "ti,tps6586x"; @@ -75,18 +80,21 @@ }; i2c@7000c000 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c400 { - status = "disabled"; + status = "okay"; }; i2c@7000c500 { + status = "okay"; clock-frequency = <100000>; }; kbc@7000e200 { + status = "okay"; linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 @@ -114,6 +122,8 @@ }; emc@7000f400 { + #address-cells = <1>; + #size-cells = <0>; emc-table@190000 { reg = < 190000 >; compatible = "nvidia,tegra20-emc-table"; @@ -151,6 +161,7 @@ }; usb@c5000000 { + status = "okay"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; dr_mode = "otg"; }; @@ -159,6 +170,10 @@ status = "disabled"; }; + usb@c5008000 { + status = "okay"; + }; + sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -172,6 +187,23 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + lcd_panel: panel { /* Seaboard has 1366x768 */ clock = <70600000>; diff --git a/arch/arm/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi index 78449e6133..f13ef4d05a 100644 --- a/arch/arm/dts/tegra20-tamonten.dtsi +++ b/arch/arm/dts/tegra20-tamonten.dtsi @@ -8,7 +8,7 @@ reg = <0x00000000 0x20000000>; }; - host1x { + host1x@50000000 { hdmi { vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -483,6 +483,19 @@ status = "okay"; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 94ba6dc2d4..4f68077faf 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -19,7 +19,7 @@ reg = <0x00000000 0x20000000>; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { @@ -52,12 +52,8 @@ status = "disabled"; }; - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; + pwm: pwm@7000a000 { + status = "okay"; }; lcd_panel: panel { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index 27b118f212..db13ff9651 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -26,27 +26,11 @@ clock-frequency = <216000000>; }; - i2c@7000c000 { - status = "disabled"; - }; - spi@7000c380 { status = "okay"; spi-max-frequency = <25000000>; }; - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - pcie-controller@80003000 { status = "okay"; @@ -62,13 +46,10 @@ }; usb@c5000000 { + status = "okay"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; }; - usb@c5004000 { - status = "disabled"; - }; - sdhci@c8000000 { status = "okay"; bus-width = <4>; @@ -81,6 +62,19 @@ bus-width = <4>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 939e567d13..851e0ed8d9 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -20,7 +20,7 @@ reg = <0x00000000 0x40000000>; }; - host1x { + host1x@50000000 { status = "okay"; dc@54200000 { status = "okay"; @@ -35,28 +35,8 @@ clock-frequency = < 216000000 >; }; - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000400 { @@ -72,6 +52,23 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + lcd_panel: panel { clock = <72072000>; xres = <1366>; diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts index c4a28eb427..358c5824f7 100644 --- a/arch/arm/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -26,19 +26,8 @@ clock-frequency = < 216000000 >; }; - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; pmic@3c { @@ -56,12 +45,8 @@ }; }; - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000400 { @@ -74,4 +59,18 @@ status = "okay"; bus-width = <8>; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index e68d7be478..31223e4fc9 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,72 +1,94 @@ #include <dt-bindings/clock/tegra20-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" / { compatible = "nvidia,tegra20"; - interrupt-parent = <&intc>; + interrupt-parent = <&lic>; - host1x { + host1x@50000000 { + u-boot,dm-pre-reloc; compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - status = "disabled"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x04000000>; - /* video-encoding/decoding */ - mpe { + mpe@54040000 { + compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; }; - /* video input */ - vi { + vi@54080000 { + compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; }; - /* EPP */ - epp { + epp@540c0000 { + compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; }; - /* ISP */ - isp { + isp@54100000 { + compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; }; - /* 2D engine */ - gr2d { + gr2d@54140000 { + compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; }; - /* 3D engine */ - gr3d { + gr3d@54180000 { + compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; }; - /* display controllers */ dc@54200000 { + u-boot,dm-pre-reloc; compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_DISP1>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + nvidia,head = <0>; rgb { status = "disabled"; @@ -76,69 +98,138 @@ dc@54240000 { compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - status = "disabled"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_DISP2>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + nvidia,head = <1>; rgb { status = "disabled"; }; }; - /* outputs */ - hdmi { + hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; status = "disabled"; }; - tvo { + tvo@542c0000 { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; }; - dsi { + dsi@54300000 { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_DSI>; + resets = <&tegra_car 48>; + reset-names = "dsi"; status = "disabled"; }; }; + timer@50040600 { + compatible = "arm,cortex-a9-twd-timer"; + interrupt-parent = <&intc>; + reg = <0x50040600 0x20>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA20_CLK_TWD>; + }; + intc: interrupt-controller@50041000 { - compatible = "nvidia,tegra20-gic"; + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; interrupt-controller; - #interrupt-cells = <1>; - reg = < 0x50041000 0x1000 >, - < 0x50040100 0x0100 >; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + timer@60005000 { + compatible = "nvidia,tegra20-timer"; + reg = <0x60005000 0x60>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_TIMER>; }; tegra_car: clock@60006000 { compatible = "nvidia,tegra20-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb@6000c000 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio@6000d000 { @@ -155,41 +246,73 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + /* + gpio-ranges = <&pinmux 0 0 224>; + */ + }; + + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ }; - pinmux: pinmux@70000000 { + pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; - reg = < 0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8 >; /* Pad control registers */ + reg = <0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8>; /* Pad control registers */ }; das@70000c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; - i2s@70002800 { - #address-cells = <1>; - #size-cells = <0>; + tegra_ac97: ac97@70002000 { + compatible = "nvidia,tegra20-ac97"; + reg = <0x70002000 0x200>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_AC97>; + resets = <&tegra_car 3>; + reset-names = "ac97"; + dmas = <&apbdma 12>, <&apbdma 12>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = < 45 >; - dma-channel = < 2 >; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + dmas = <&apbdma 2>, <&apbdma 2>; + dma-names = "rx", "tx"; + status = "disabled"; }; - i2s@70002a00 { - #address-cells = <1>; - #size-cells = <0>; + tegra_i2s2: i2s@70002a00 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = < 35 >; - dma-channel = < 1 >; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + dmas = <&apbdma 1>, <&apbdma 1>; + dma-names = "rx", "tx"; + status = "disabled"; }; + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra20-uart" and to enable the APB DMA based serial + * driver, the comptible is "nvidia,tegra20-hsuart". + */ uarta: serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; @@ -266,58 +389,95 @@ compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; + clocks = <&tegra_car TEGRA20_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_RTC>; }; i2c@7000c000 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C000 0x100>; - interrupts = < 70 >; - /* PERIPH_ID_I2C1, PLL_P_OUT3 */ - clocks = <&tegra_car 12>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C1>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; }; spi@7000c380 { compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; - interrupts = <0 39 0x04>; - nvidia,dma-request-selector = <&apbdma 11>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SPI>; + resets = <&tegra_car 43>; + reset-names = "spi"; + dmas = <&apbdma 11>, <&apbdma 11>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SPI1, PLLP_OUT0 */ - clocks = <&tegra_car 43>; }; i2c@7000c400 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C400 0x100>; - interrupts = < 116 >; - /* PERIPH_ID_I2C2, PLL_P_OUT3 */ - clocks = <&tegra_car 54>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C2>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; }; i2c@7000c500 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C500 0x100>; - interrupts = < 124 >; - /* PERIPH_ID_I2C3, PLL_P_OUT3 */ - clocks = <&tegra_car 67>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; }; i2c@7000d000 { + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000d000 0x200>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000D000 0x200>; - interrupts = < 85 >; - /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ - clocks = <&tegra_car 47>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_DVC>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; }; spi@7000d400 { @@ -376,17 +536,50 @@ status = "disabled"; }; - kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x0078>; + reg = <0x7000e200 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; + status = "disabled"; }; - emc@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; + pmc@7000e400 { + compatible = "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x024 + 0x7000f03c 0x3c4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + }; + + iommu@7000f024 { + compatible = "nvidia,tegra20-gart"; + reg = <0x7000f024 0x00000018 /* controller registers */ + 0x58000000 0x02000000>; /* GART aperture */ + }; + + memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; + #address-cells = <1>; + #size-cells = <0>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; }; pcie-controller@80003000 { @@ -416,9 +609,12 @@ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PCIE_XCLK>, <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + clock-names = "pex", "afi", "pll_e"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -451,57 +647,158 @@ usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; - interrupts = < 52 >; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; - clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ nvidia,has-legacy-mode; + clocks = <&tegra_car TEGRA20_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@c5000000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5000000 0x4000 0xc5000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USBD>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,has-legacy-mode; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; + nvidia,has-utmi-pad-registers; + status = "disabled"; }; usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; - interrupts = < 53 >; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; phy_type = "ulpi"; - clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + status = "disabled"; }; usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; - interrupts = < 129 >; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@c5008000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5008000 0x4000 0xc5000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + clocks = <&tegra_car TEGRA20_CLK_USB3>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + status = "disabled"; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + }; }; diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index 5d4b2cf4c3..59511bde94 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -9,6 +9,13 @@ /include/ "skeleton.dtsi" / { + clocks { + refclk: ref { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -67,6 +74,18 @@ reg = <0x58c00000 0x400>, <0x59800000 0x2000>; }; + mio: mioctrl@59810000 { + /* specify compatible in each SoC DTSI */ + reg = <0x59810000 0x800>; + #clock-cells = <1>; + }; + + peri: perictrl@59820000 { + /* specify compatible in each SoC DTSI */ + reg = <0x59820000 0x200>; + #clock-cells = <1>; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -94,6 +113,14 @@ reg = <0x5f801000 0xe00>; }; + sysctrl: sysctrl@61840000 { + /* specify compatible in each SoC DTSI */ + reg = <0x61840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 469bd05e16..f62916da39 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -59,7 +59,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 856c207b13..7c8759f929 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -115,6 +115,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio 3>, <&mio 6>; }; usb1: usb@5a810100 { @@ -124,6 +125,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio 4>, <&mio 6>; }; usb2: usb@5a820100 { @@ -133,9 +135,14 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio 5>, <&mio 6>; }; }; +&refclk { + clock-frequency = <24576000>; +}; + &serial0 { clock-frequency = <36864000>; }; @@ -153,6 +160,22 @@ clock-frequency = <36864000>; }; +&mio { + compatible = "socionext,ph1-ld4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + +&peri { + compatible = "socionext,ph1-ld4-perictrl"; + clock-names = "uart", "i2c"; + clocks = <&sysctrl 3>, <&sysctrl 4>; +}; + &pinctrl { compatible = "socionext,ph1-ld4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-ld4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index e0a972f4d2..dca408bb70 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -61,7 +61,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts new file mode 100644 index 0000000000..6e741ea45b --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4-ace.dts @@ -0,0 +1,105 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 Ace Board + * + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-ph1-pro4.dtsi" + +/ { + model = "UniPhier PH1-Pro4 Ace Board"; + compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom { + compatible = "24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 02e74a7c3b..202a642a4d 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -66,7 +66,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts new file mode 100644 index 0000000000..91a71ef469 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts @@ -0,0 +1,100 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 Sanji Board + * + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-ph1-pro4.dtsi" + +/ { + model = "UniPhier PH1-Pro4 Sanji Board"; + compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom { + compatible = "24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index 244ccf67e6..cb5b8f1a86 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -147,6 +147,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio 3>, <&mio 6>; }; usb3: usb@5a810100 { @@ -156,6 +157,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio 4>, <&mio 6>; }; usb0: usb@65a00000 { @@ -177,6 +179,10 @@ }; }; +&refclk { + clock-frequency = <25000000>; +}; + &serial0 { clock-frequency = <73728000>; }; @@ -193,6 +199,22 @@ clock-frequency = <73728000>; }; +&mio { + compatible = "socionext,ph1-pro4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + +&peri { + compatible = "socionext,ph1-pro4-perictrl"; + clock-names = "uart", "fi2c"; + clocks = <&sysctrl 3>, <&sysctrl 4>; +}; + &pinctrl { compatible = "socionext,ph1-pro4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index d46e827280..02a3362e74 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -47,7 +47,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 00491062fe..087b25a950 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -171,6 +171,10 @@ }; }; +&refclk { + clock-frequency = <20000000>; +}; + &serial0 { clock-frequency = <73728000>; }; @@ -187,6 +191,22 @@ clock-frequency = <73728000>; }; +&mio { + compatible = "socionext,ph1-pro5-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + +&peri { + compatible = "socionext,ph1-pro5-perictrl"; + clock-names = "uart", "fi2c"; + clocks = <&sysctrl 3>, <&sysctrl 4>; +}; + &pinctrl { compatible = "socionext,ph1-pro5-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro5-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 1f3aee928a..ff17945e90 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -68,7 +68,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ &serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index f481521a0f..85dde66f07 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -30,6 +30,12 @@ }; clocks { + refclk: ref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -172,11 +178,20 @@ reg = <0x59800000 0x2000>; }; + mio: mioctrl@59810000 { + compatible = "socionext,ph1-sld3-mioctrl"; + reg = <0x59810000 0x800>; + #clock-cells = <1>; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; + clocks = <&mio 3>, <&mio 6>; }; usb1: usb@5a810100 { @@ -184,6 +199,7 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; + clocks = <&mio 4>, <&mio 6>; }; usb2: usb@5a820100 { @@ -191,6 +207,7 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; + clocks = <&mio 5>, <&mio 6>; }; usb3: usb@5a830100 { @@ -198,6 +215,15 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; + clocks = <&mio 7>, <&mio 6>; + }; + + sysctrl: sysctrl@f1840000 { + compatible = "socionext,ph1-sld3-sysctrl"; + reg = <0xf1840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; }; nand: nand@f8000000 { diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index b58bf075ac..b5b6f65d36 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -63,7 +63,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index cb28bc4508..f93db83661 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -115,6 +115,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio 3>, <&mio 6>; }; usb1: usb@5a810100 { @@ -124,6 +125,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio 4>, <&mio 6>; }; usb2: usb@5a820100 { @@ -133,9 +135,14 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio 5>, <&mio 6>; }; }; +&refclk { + clock-frequency = <25000000>; +}; + &serial0 { clock-frequency = <80000000>; }; @@ -153,6 +160,22 @@ clock-frequency = <80000000>; }; +&mio { + compatible = "socionext,ph1-sld8-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + +&peri { + compatible = "socionext,ph1-sld8-perictrl"; + clock-names = "uart", "i2c"; + clocks = <&sysctrl 3>, <&sysctrl 4>; +}; + &pinctrl { compatible = "socionext,ph1-sld8-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-sld8-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index a49215edae..dc0def30fd 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -27,6 +27,7 @@ serial1 = &serial1; serial2 = &serial2; i2c0 = &i2c0; + i2c2 = &i2c2; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; @@ -39,6 +40,16 @@ &i2c0 { status = "okay"; + + eeprom { + compatible = "24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c2 { + status = "okay"; }; &usb0 { @@ -49,7 +60,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 63bd3633bd..3703ad36a5 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -45,7 +45,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 3ba6a4ae51..2d324f95a4 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -182,6 +182,10 @@ }; }; +&refclk { + clock-frequency = <25000000>; +}; + &serial0 { clock-frequency = <88900000>; }; @@ -198,6 +202,22 @@ clock-frequency = <88900000>; }; +&mio { + compatible = "socionext,proxstream2-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + +&peri { + compatible = "socionext,proxstream2-perictrl"; + clock-names = "uart", "fi2c"; + clocks = <&sysctrl 3>, <&sysctrl 4>; +}; + &pinctrl { compatible = "socionext,proxstream2-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,proxstream2-sysctrl"; +}; diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h new file mode 100644 index 0000000000..29b98aecf4 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_DEFS_H__ +#define __STM32_DEFS_H__ +#include <asm/arch/stm32_periph.h> + +int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h new file mode 100644 index 0000000000..a1af25cb58 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART1_GPIOA_9_10 = 0, + UART2_GPIOD_5_6, +}; + +enum periph_clock { + USART1_CLOCK_CFG = 0, + USART2_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 3a87f0b956..3a7ee5e77b 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -566,9 +566,4 @@ enum { #define DC_N_WINDOWS 5 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) -struct display_timing; - -int display_init(void *lcdbase, int fb_bits_per_pixel, - struct display_timing *timing); - #endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h index 92dced448a..5a2d9f3a9c 100644 --- a/arch/arm/include/asm/arch-tegra/pwm.h +++ b/arch/arm/include/asm/arch-tegra/pwm.h @@ -27,34 +27,4 @@ struct pwm_ctlr { #define PWM_DIVIDER_SHIFT 0 #define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) -/** - * Program the PWM with the given parameters. - * - * @param channel PWM channel to update - * @param rate Clock rate to use for PWM, or 0 to leave alone - * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, - * n = n/256 pulse high - * @param freq_divider frequency divider value (1 to use rate as is) - */ -void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); - -/** - * Request a pwm channel as referenced by a device tree node. - * - * This channel can then be passed to pwm_enable(). - * - * @param blob Device tree blob - * @param node Node containing reference to pwm - * @param prop_name Property name of pwm reference - * @return channel number, if ok, else -1 - */ -int pwm_request(const void *blob, int node, const char *prop_name); - -/** - * Set up the pwm controller, by looking it up in the fdt. - * - * @return 0 if ok, -1 if the device tree node was not found or invalid. - */ -int pwm_init(const void *blob); - #endif /* __ASM_ARCH_TEGRA_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h index 018c9f9f76..ee5a3f6c91 100644 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ b/arch/arm/include/asm/arch-tegra20/display.h @@ -9,8 +9,6 @@ #define __ASM_ARCH_TEGRA_DISPLAY_H #include <asm/arch-tegra/dc.h> -#include <fdtdec.h> -#include <asm/gpio.h> /* This holds information about a window which can be displayed */ struct disp_ctl_win { @@ -28,110 +26,4 @@ struct disp_ctl_win { unsigned out_h; /* Height of output window in pixels */ }; -#define FDT_LCD_TIMINGS 4 - -enum { - FDT_LCD_TIMING_REF_TO_SYNC, - FDT_LCD_TIMING_SYNC_WIDTH, - FDT_LCD_TIMING_BACK_PORCH, - FDT_LCD_TIMING_FRONT_PORCH, - - FDT_LCD_TIMING_COUNT, -}; - -enum lcd_cache_t { - FDT_LCD_CACHE_OFF = 0, - FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, - FDT_LCD_CACHE_WRITE_BACK = 1 << 1, - FDT_LCD_CACHE_FLUSH = 1 << 2, - FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | - FDT_LCD_CACHE_FLUSH, -}; - -/* Information about the display controller */ -struct fdt_disp_config { - int valid; /* config is valid */ - int width; /* width in pixels */ - int height; /* height in pixels */ - int bpp; /* number of bits per pixel */ - - /* - * log2 of number of bpp, in general, unless it bpp is 24 in which - * case this field holds 24 also! This is a U-Boot thing. - */ - int log2_bpp; - struct disp_ctlr *disp; /* Display controller to use */ - fdt_addr_t frame_buffer; /* Address of frame buffer */ - unsigned pixel_clock; /* Pixel clock in Hz */ - uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ - uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ - int panel_node; /* node offset of panel information */ -}; - -/* Information about the LCD panel */ -struct fdt_panel_config { - int pwm_channel; /* PWM channel to use for backlight */ - enum lcd_cache_t cache_type; - - struct gpio_desc backlight_en; /* GPIO for backlight enable */ - struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ - struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ - struct gpio_desc panel_vdd; /* GPIO for panel vdd */ - /* - * Panel required timings - * Timing 1: delay between panel_vdd-rise and data-rise - * Timing 2: delay between data-rise and backlight_vdd-rise - * Timing 3: delay between backlight_vdd and pwm-rise - * Timing 4: delay between pwm-rise and backlight_en-rise - */ - uint panel_timings[FDT_LCD_TIMINGS]; -}; - -/** - * Register a new display based on device tree configuration. - * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. - * You should pass in the U-Boot address here, and check the contents of - * struct fdt_disp_config to see what was actually chosen. - * - * @param blob Device tree blob - * @param default_lcd_base Default address of LCD frame buffer - * @return 0 if ok, -1 on error (unsupported bits per pixel) - */ -int tegra_display_probe(const void *blob, void *default_lcd_base); - -/** - * Return the current display configuration - * - * @return pointer to display configuration, or NULL if there is no valid - * config - */ -struct fdt_disp_config *tegra_display_get_config(void); - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -int tegra_lcd_check_next_stage(const void *blob, int wait); - -/** - * Set up the maximum LCD size so we can size the frame buffer. - * - * @param blob fdt blob containing LCD information - */ -void tegra_lcd_early_init(const void *blob); - #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 587938249e..e223988b7d 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -19,6 +19,8 @@ #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 +#define ARASAN_NAND_BASEADDR 0xFF100000 + #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 5c5d33f0bd..19c38f4083 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -24,6 +24,7 @@ enum { BOOT_DEVICE_NOR, BOOT_DEVICE_UART, BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 2f4c14e96b..8415f77e1b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -167,8 +167,12 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ mov r0, r9 /* gd_t */ ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ +#if defined(CONFIG_SYS_THUMB_BUILD) + ldr lr, =board_init_r /* this is auto-relocated! */ + bx lr +#else ldr pc, =board_init_r /* this is auto-relocated! */ - +#endif /* we should not return here. */ #endif diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 9426302b38..9ce775e0da 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -96,6 +96,11 @@ config TARGET_SAMA5D4EK select CPU_V7 select SUPPORT_SPL +config TARGET_MA5D4EVK + bool "DENX MA5D4EVK Evaluation Kit" + select CPU_V7 + select SUPPORT_SPL + config TARGET_MEESC bool "Support meesc" select CPU_ARM926EJS @@ -115,6 +120,11 @@ config TARGET_SMARTWEB select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_VINCO + bool "Support VINCO" + select CPU_V7 + select SUPPORT_SPL + endchoice config SYS_SOC @@ -135,8 +145,10 @@ source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/calao/usb_a9263/Kconfig" +source "board/denx/ma5d4evk/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" +source "board/l+g/vinco/Kconfig" source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index abd1d13da7..44245234ee 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o endif +obj-y += clock.o obj-$(CONFIG_CPU_ARM920T) += arm920t/ obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ obj-$(CONFIG_CPU_V7) += armv7/ diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index fc54327c0d..9b9800ad9a 100644 --- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -14,7 +14,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> /* @@ -34,29 +34,23 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index 2813bf7821..8aa21005d0 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -18,6 +18,8 @@ # error You need to define CONFIG_AT91FAMILY in your board config! #endif +#define EN_PLLB_TIMEOUT 500 + DECLARE_GLOBAL_DATA_PTR; static unsigned long at91_css_to_rate(unsigned long css) @@ -155,3 +157,39 @@ int at91_clock_init(unsigned long main_clock) return 0; } + +int at91_pllb_clk_enable(u32 pllbr) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(pllbr, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to enable PLLB\n"); + return -1; + } + } + + return 0; +} + +int at91_pllb_clk_disable(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to disable PLLB\n"); + return -1; + } + } + + return 0; +} diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index 6aa2994723..69ce6f9573 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -19,7 +19,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_tc.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> DECLARE_GLOBAL_DATA_PTR; @@ -29,10 +29,8 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - /* enables TC1.0 clock */ - writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */ + at91_periph_clk_enable(ATMEL_ID_TC0); writel(0, &tc->bcr); writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index 5e0c0f514d..912a966bae 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -11,8 +11,8 @@ #include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> /* @@ -32,51 +32,40 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -106,14 +95,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); @@ -145,9 +131,7 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - /* Enable EMAC clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */ @@ -190,9 +174,7 @@ void at91_macb_hw_init(void) #if defined(CONFIG_GENERIC_ATMEL_MCI) void at91_mci_hw_init(void) { - /* Enable mci clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_MCI, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_MCI); at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */ #if defined(CONFIG_ATMEL_MCI_PORTB) diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index a445c7507e..4bd4e75e0b 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -9,7 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> /* @@ -29,51 +29,40 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 6b51d5f355..f3f480010a 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -13,7 +13,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> /* @@ -33,51 +33,40 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -107,14 +96,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -146,9 +132,7 @@ void at91_spi1_hw_init(unsigned long cs_mask) #if defined(CONFIG_GENERIC_ATMEL_MCI) void at91_mci_hw_init(void) { - /* Enable mci clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_MCI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_MCI1); at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */ @@ -207,12 +191,9 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ - /* Enable clock */ - writel(1 << ATMEL_ID_CAN, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_CAN); } #endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 0e6c0da1bd..0d83426ead 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -8,7 +8,7 @@ #include <common.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> @@ -29,51 +29,40 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); @@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 1); @@ -169,8 +155,6 @@ void at91_macb_hw_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI void at91_mci_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ @@ -178,7 +162,6 @@ void at91_mci_hw_init(void) at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ - /* Enable clock */ - writel(1 << ATMEL_ID_MCI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_MCI0); } #endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 39f17a1e11..a03abfc310 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -8,8 +8,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> unsigned int has_lcdc() { @@ -18,60 +18,47 @@ unsigned int has_lcdc() void at91_serial0_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_serial3_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ - writel(1 << ATMEL_ID_USART3, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART3); } void at91_seriald_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) at91_set_pio_output(AT91_PIO_PORTA, 14, 1); @@ -85,14 +72,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) at91_set_pio_output(AT91_PIO_PORTA, 8, 1); @@ -107,8 +91,6 @@ void at91_spi1_hw_init(unsigned long cs_mask) void at91_mci_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ @@ -116,14 +98,12 @@ void at91_mci_hw_init(void) at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_HSMCI0); } #ifdef CONFIG_LCD void at91_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ @@ -156,6 +136,6 @@ void at91_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); } #endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index 857c864068..dbf9386faa 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -9,7 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> /* @@ -29,51 +29,40 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); @@ -105,8 +94,6 @@ void at91_spi0_hw_init(unsigned long cs_mask) #ifdef CONFIG_GENERIC_ATMEL_MCI void at91_mci_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI CLK */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI CDA */ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI DA0 */ @@ -114,7 +101,6 @@ void at91_mci_hw_init(void) at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI DA2 */ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI DA3 */ - /* Enable clock */ - writel(1 << ATMEL_ID_MCI, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_MCI); } #endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 6d94572237..3e4555a1a1 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> @@ -64,42 +64,34 @@ char *get_cpu_name() void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); } void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_mci_hw_init(void) @@ -112,22 +104,17 @@ void at91_mci_hw_init(void) at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ - /* Enable clock for MCI0 */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_HSMCI0); } #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) at91_set_a_periph(AT91_PIO_PORTA, 14, 0); @@ -149,14 +136,11 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) at91_set_b_periph(AT91_PIO_PORTA, 8, 0); @@ -193,11 +177,9 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - if (has_emac0()) { /* Enable EMAC0 clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); /* EMAC0 pins setup */ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ @@ -213,7 +195,7 @@ void at91_macb_hw_init(void) if (has_emac1()) { /* Enable EMAC1 clock */ - writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC1); /* EMAC1 pins setup */ at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index 8d6934e324..c8d24ae826 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -18,6 +18,8 @@ # error You need to define CONFIG_AT91FAMILY in your board config! #endif +#define EN_PLLB_TIMEOUT 500 + DECLARE_GLOBAL_DATA_PTR; static unsigned long at91_css_to_rate(unsigned long css) @@ -243,9 +245,38 @@ void at91_mck_init(u32 mckr) ; } -void at91_periph_clk_enable(int id) +int at91_pllb_clk_enable(u32 pllbr) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(pllbr, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to enable PLLB\n"); + return -1; + } + } - writel(1 << id, &pmc->pcer); + return 0; +} + +int at91_pllb_clk_disable(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to disable PLLB\n"); + return -1; + } + } + + return 0; } diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 990c689ad7..9b9f8af68c 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -10,7 +10,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index 31ce646260..c49d306295 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -10,7 +10,6 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include <div64.h> @@ -38,11 +37,9 @@ DECLARE_GLOBAL_DATA_PTR; */ int timer_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - /* Enable PITC Clock */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_SYS); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 41dbf16afd..81e9f69c94 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -150,32 +150,6 @@ void at91_mck_init(u32 mckr) ; } -void at91_periph_clk_enable(int id) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 regval; - - if (id > AT91_PMC_PCR_PID_MASK) - return; - - regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id; - - writel(regval, &pmc->pcr); -} - -void at91_periph_clk_disable(int id) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 regval; - - if (id > AT91_PMC_PCR_PID_MASK) - return; - - regval = AT91_PMC_PCR_CMD_WRITE | id; - - writel(regval, &pmc->pcr); -} - int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 7843aed813..18653039fe 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -12,7 +12,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 88f8f2c53d..978eac29bd 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d2.h> @@ -48,9 +47,7 @@ char *get_cpu_name() #ifdef CONFIG_USB_GADGET_ATMEL_USBA void at91_udp_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + at91_upll_clk_enable(); at91_periph_clk_enable(ATMEL_ID_UDPHS); } diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 78ecfc882a..64ac262818 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/arch/sama5d3.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> @@ -208,10 +207,8 @@ void at91_lcd_hw_init(void) #ifdef CONFIG_USB_GADGET_ATMEL_USBA void at91_udp_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable UPLL clock */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + at91_upll_clk_enable(); /* Enable UDPHS clock */ at91_periph_clk_enable(ATMEL_ID_UDPHS); } diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index ce33cd4988..ebb779e473 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include <asm/arch/sama5_sfr.h> #include <asm/arch/sama5d4.h> @@ -37,10 +36,8 @@ char *get_cpu_name() #ifdef CONFIG_USB_GADGET_ATMEL_USBA void at91_udp_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable UPLL clock */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + at91_upll_clk_enable(); /* Enable UDPHS clock */ at91_periph_clk_enable(ATMEL_ID_UDPHS); } diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index a4a3817aa6..6f91e22d0a 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -13,7 +13,6 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include <div64.h> diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 2bccb840c1..adf44c6a94 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -19,3 +19,10 @@ void redirect_int_from_saic_to_aic(void) writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); } } + +void configure_2nd_sram_as_l2_cache(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + writel(1, &sfr->l2cc_hramc); +} diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c new file mode 100644 index 0000000000..06dcbbcbe8 --- /dev/null +++ b/arch/arm/mach-at91/clock.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> + +#define EN_UPLL_TIMEOUT 500 + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + +#ifdef CPU_HAS_PCR + u32 regval; + u32 div_value; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + writel(id, &pmc->pcr); + + div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV; + + regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value; + + writel(regval, &pmc->pcr); +#else + writel(0x01 << id, &pmc->pcer); +#endif +} + +void at91_periph_clk_disable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + +#ifdef CPU_HAS_PCR + u32 regval; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + regval = AT91_PMC_PCR_CMD_WRITE | id; + + writel(regval, &pmc->pcr); +#else + writel(0x01 << id, &pmc->pcdr); +#endif +} + +void at91_system_clk_enable(int sys_clk) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(sys_clk, &pmc->scer); +} + +void at91_system_clk_disable(int sys_clk) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(sys_clk, &pmc->scdr); +} + +int at91_upll_clk_enable(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + if ((readl(&pmc->uckr) & AT91_PMC_UPLLEN) == AT91_PMC_UPLLEN) + return 0; + + start_time = get_timer(0); + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to enable UPLL\n"); + return -1; + } + } + + return 0; +} + +int at91_upll_clk_disable(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to stop UPLL\n"); + return -1; + } + } + + return 0; +} + +void at91_usb_clk_init(u32 value) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(value, &pmc->usb); +} + +void at91_pllicpr_init(u32 icpr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(icpr, &pmc->pllicpr); +} diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index efcd74ed90..0742ffc56f 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -34,5 +34,6 @@ void at91_spl_board_init(void); void at91_disable_wdt(void); void matrix_init(void); void redirect_int_from_saic_to_aic(void); +void configure_2nd_sram_as_l2_cache(void); #endif /* AT91_COMMON_H */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 3f50f7718f..7684f09afc 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -51,19 +51,15 @@ typedef struct at91_pmc { u32 imr; /* 0x6C Interrupt Mask Register */ u32 reserved4[4]; u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ - u32 reserved5[21]; + u32 reserved5[24]; u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ -#ifdef CPU_HAS_PCR - u32 reserved6[8]; + u32 reserved6[5]; u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */ u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */ u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */ u32 pcr; /* 0x10c Periperial Control Register */ u32 ocr; /* 0x110 Oscillator Calibration Register */ -#else - u32 reserved8[5]; -#endif } at91_pmc_t; #endif /* end not assembly */ @@ -250,4 +246,11 @@ typedef struct at91_pmc { #define AT91_PMC_GCKRDY (1 << 24) #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ + +/* PLL Charge Pump Current Register (PMC_PLLICPR) */ +#define AT91_PMC_ICP_PLLA(x) (((x) & 0x3) << 0) +#define AT91_PMC_IPLL_PLLA(x) (((x) & 0x7) << 8) +#define AT91_PMC_ICP_PLLU(x) (((x) & 0x3) << 16) +#define AT91_PMC_IVCO_PLLU(x) (((x) & 0x3) << 24) + #endif diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index ad839275ec..8577c74b47 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -128,5 +128,13 @@ void at91_periph_clk_enable(int id); void at91_periph_clk_disable(int id); int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div); u32 at91_get_periph_generated_clk(u32 id); +void at91_system_clk_enable(int sys_clk); +void at91_system_clk_disable(int sys_clk); +int at91_upll_clk_enable(void); +int at91_upll_clk_disable(void); +void at91_usb_clk_init(u32 value); +int at91_pllb_clk_enable(u32 pllbr); +int at91_pllb_clk_disable(void); +void at91_pllicpr_init(u32 icpr); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index 7b19a20a4e..b040256ba4 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -25,6 +25,7 @@ struct atmel_sfr { u32 sn0; /* 0x4c */ u32 sn1; /* 0x50 */ u32 aicredir; /* 0x54 */ + u32 l2cc_hramc; /* 0x58 */ }; /* Bit field in DDRCFG */ diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c index 2cba7169e4..ddd70f5ff0 100644 --- a/arch/arm/mach-at91/phy.c +++ b/arch/arm/mach-at91/phy.c @@ -15,7 +15,6 @@ #include <common.h> #include <asm/io.h> #include <linux/sizes.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <watchdog.h> diff --git a/arch/arm/mach-at91/sdram.c b/arch/arm/mach-at91/sdram.c index 5758b066e4..1dfc74f2ca 100644 --- a/arch/arm/mach-at91/sdram.c +++ b/arch/arm/mach-at91/sdram.c @@ -13,7 +13,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/gpio.h> diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index b19f95b0d0..cc3341acb5 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -14,7 +14,6 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_wdt.h> #include <asm/arch/clk.h> @@ -77,8 +76,6 @@ void __weak spl_board_init(void) void board_init_f(ulong dummy) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - lowlevel_clock_init(); at91_disable_wdt(); @@ -86,7 +83,7 @@ void board_init_f(ulong dummy) * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ - writel(0x00, &pmc->pllicpr); + at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ at91_plla_init(CONFIG_SYS_AT91_PLLA); diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index b2fb51d0ac..688289e7cf 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -79,6 +79,10 @@ void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); +#ifdef CONFIG_SAMA5D2 + configure_2nd_sram_as_l2_cache(); +#endif + /* disable watchdog */ at91_disable_wdt(); diff --git a/arch/arm/mach-exynos/include/mach/spl.h b/arch/arm/mach-exynos/include/mach/spl.h index 0c480acb1a..a5d13fa7cb 100644 --- a/arch/arm/mach-exynos/include/mach/spl.h +++ b/arch/arm/mach-exynos/include/mach/spl.h @@ -42,10 +42,10 @@ struct spl_machine_param { u32 mem_iv_size; /* Memory channel interleaving size */ enum ddr_mode mem_type; /* Type of on-board memory */ /* - * U-boot size - The iROM mmc copy function used by the SPL takes a - * block count paramter to describe the u-boot size unlike the spi - * boot copy function which just uses the u-boot size directly. Align - * the u-boot size to block size (512 bytes) when populating the SPL + * U-Boot size - The iROM mmc copy function used by the SPL takes a + * block count paramter to describe the U-Boot size unlike the spi + * boot copy function which just uses the U-Boot size directly. Align + * the U-Boot size to block size (512 bytes) when populating the SPL * table only for mmc boot. */ u32 uboot_size; diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index dfc3455929..5dc216dce1 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -30,10 +30,10 @@ relocate_wait_code: * because that comes out to be the last 4KB of the iRAM * (Base Address - 0x02020000, Limit Address - 0x020740000). * - * U-boot and kernel are aware of this code and flags by the simple + * U-Boot and kernel are aware of this code and flags by the simple * fact that we are implementing a workaround in the last 4KB * of the iRAM and we have already defined these flag and address - * values in both kernel and U-boot for our use. + * values in both kernel and U-Boot for our use. */ code_base: b 1f diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index c7f943eb6a..7df01021cd 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -177,7 +177,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) #endif /* -* Copy U-boot from mmc to RAM: +* Copy U-Boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains * Pointer to API (Data transfer from mmc to ram) */ diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 51a8b3c51b..3f38f36ff2 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -283,5 +283,5 @@ lowlevel_init: #endif /* CONFIG_SPL_BUILD */ - /* Return to U-boot via saved link register */ + /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 3deb17aa83..576d3e68ae 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/stm32_periph.h> #define RCC_CR_HSION (1 << 0) #define RCC_CR_HSEON (1 << 16) @@ -50,6 +51,14 @@ #define RCC_APB1ENR_PWREN (1 << 28) +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + #define PWR_CR_VOS0 (1 << 14) #define PWR_CR_VOS1 (1 << 15) #define PWR_CR_VOS_MASK 0xC000 @@ -221,3 +230,14 @@ unsigned long clock_get(enum clock clck) break; } } + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case USART1_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); + break; + default: + break; + } +} diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 0b2852c4da..ba6983f3df 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -9,10 +9,12 @@ config TEGRA_COMMON select DM_KEYBOARD select DM_PCI select DM_PCI_COMPAT + select DM_PWM select DM_SERIAL select DM_SPI select DM_SPI_FLASH select OF_CONTROL + select VIDCONSOLE_AS_LCD if DM_VIDEO config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 2be6ef41ff..b2dbc6999c 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -12,7 +12,6 @@ obj-y += spl.o obj-y += cpu.o else obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o -obj-$(CONFIG_PWM_TEGRA) += pwm.o endif obj-$(CONFIG_ARM64) += arm64-mmu.o diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 60e19c8387..ac274e17e8 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -13,15 +13,9 @@ #include <linux/sizes.h> #include <asm/io.h> #include <asm/arch/clock.h> -#ifdef CONFIG_LCD -#include <asm/arch/display.h> -#endif #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch/pmu.h> -#ifdef CONFIG_PWM_TEGRA -#include <asm/arch/pwm.h> -#endif #include <asm/arch/tegra.h> #include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> @@ -134,13 +128,9 @@ int board_init(void) pin_mux_spi(); #endif -#ifdef CONFIG_PWM_TEGRA - if (pwm_init(gd->fdt_blob)) - debug("%s: Failed to init pwm\n", __func__); -#endif -#ifdef CONFIG_LCD + /* Init is handled automatically in the driver-model case */ +#if defined(CONFIG_DM_VIDEO) pin_mux_display(); - tegra_lcd_check_next_stage(gd->fdt_blob, 0); #endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); @@ -168,12 +158,11 @@ int board_init(void) pin_mux_usb(); #endif -#ifdef CONFIG_LCD +#if defined(CONFIG_DM_VIDEO) board_id = tegra_board_id(); err = tegra_lcd_pmic_init(board_id); if (err) return err; - tegra_lcd_check_next_stage(gd->fdt_blob, 0); #endif #ifdef CONFIG_TEGRA_NAND @@ -221,9 +210,6 @@ int board_early_init_f(void) /* Initialize periph GPIOs */ gpio_early_init(); gpio_early_init_uart(); -#ifdef CONFIG_LCD - tegra_lcd_early_init(gd->fdt_blob); -#endif return 0; } @@ -231,10 +217,6 @@ int board_early_init_f(void) int board_late_init(void) { -#ifdef CONFIG_LCD - /* Make sure we finish initing the LCD */ - tegra_lcd_check_next_stage(gd->fdt_blob, 1); -#endif #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) if (tegra_cpu_is_non_secure()) { printf("CPU is in NS mode\n"); diff --git a/arch/arm/mach-tegra/pwm.c b/arch/arm/mach-tegra/pwm.c deleted file mode 100644 index 1c38fc1784..0000000000 --- a/arch/arm/mach-tegra/pwm.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fdtdec.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/pwm.h> - -struct pwm_info { - struct pwm_ctlr *pwm; /* Registers for our pwm controller */ - int pwm_node; /* PWM device tree node */ -} local; - -void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider) -{ - u32 reg; - - assert(channel < PWM_NUM_CHANNELS); - - /* TODO: Can we use clock_adjust_periph_pll_div() here? */ - if (rate) { - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, - rate); - } - - reg = PWM_ENABLE_MASK; - reg |= pulse_width << PWM_WIDTH_SHIFT; - reg |= freq_divider << PWM_DIVIDER_SHIFT; - writel(reg, &local.pwm[channel].control); - debug("%s: channel=%d, rate=%d\n", __func__, channel, rate); -} - -int pwm_request(const void *blob, int node, const char *prop_name) -{ - int pwm_node; - u32 data[3]; - - if (fdtdec_get_int_array(blob, node, prop_name, data, - ARRAY_SIZE(data))) { - debug("%s: Cannot decode PWM property '%s'\n", __func__, - prop_name); - return -1; - } - - pwm_node = fdt_node_offset_by_phandle(blob, data[0]); - if (pwm_node != local.pwm_node) { - debug("%s: PWM property '%s' phandle %d not recognised" - "- expecting %d\n", __func__, prop_name, data[0], - local.pwm_node); - return -1; - } - if (data[1] >= PWM_NUM_CHANNELS) { - debug("%s: PWM property '%s': invalid channel %u\n", __func__, - prop_name, data[1]); - return -1; - } - - /* - * TODO: We could maintain a list of requests, but it might not be - * worth it for U-Boot. - */ - return data[1]; -} - -int pwm_init(const void *blob) -{ - local.pwm_node = fdtdec_next_compatible(blob, 0, - COMPAT_NVIDIA_TEGRA20_PWM); - if (local.pwm_node < 0) { - debug("%s: Cannot find device tree node\n", __func__); - return -1; - } - - local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node, - "reg"); - if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) { - debug("%s: Cannot find pwm reg address\n", __func__); - return -1; - } - debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node); - - return 0; -} diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index fc3fb4ae4c..17c19900e2 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -6,8 +6,6 @@ ifdef CONFIG_SPL_BUILD obj-y += cpu.o -else -obj-$(CONFIG_VIDEO_TEGRA) += display.o endif # The AVP is ARMv4T architecture so we must use special compiler diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index b7605ff60e..73be9a9cbd 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -14,381 +14,3 @@ #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/timer.h> -static struct fdt_disp_config config; - -static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) -{ - unsigned h_dda, v_dda; - unsigned long val; - - val = readl(&dc->cmd.disp_win_header); - val |= WINDOW_A_SELECT; - writel(val, &dc->cmd.disp_win_header); - - writel(win->fmt, &dc->win.color_depth); - - clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, - BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); - - val = win->out_x << H_POSITION_SHIFT; - val |= win->out_y << V_POSITION_SHIFT; - writel(val, &dc->win.pos); - - val = win->out_w << H_SIZE_SHIFT; - val |= win->out_h << V_SIZE_SHIFT; - writel(val, &dc->win.size); - - val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; - val |= win->h << V_PRESCALED_SIZE_SHIFT; - writel(val, &dc->win.prescaled_size); - - writel(0, &dc->win.h_initial_dda); - writel(0, &dc->win.v_initial_dda); - - h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); - v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); - - val = h_dda << H_DDA_INC_SHIFT; - val |= v_dda << V_DDA_INC_SHIFT; - writel(val, &dc->win.dda_increment); - - writel(win->stride, &dc->win.line_stride); - writel(0, &dc->win.buf_stride); - - val = WIN_ENABLE; - if (win->bpp < 24) - val |= COLOR_EXPAND; - writel(val, &dc->win.win_opt); - - writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); - writel(win->x, &dc->winbuf.addr_h_offset); - writel(win->y, &dc->winbuf.addr_v_offset); - - writel(0xff00, &dc->win.blend_nokey); - writel(0xff00, &dc->win.blend_1win); - - val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; - val |= GENERAL_UPDATE | WIN_A_UPDATE; - writel(val, &dc->cmd.state_ctrl); -} - -static void write_pair(struct fdt_disp_config *config, int item, u32 *reg) -{ - writel(config->horiz_timing[item] | - (config->vert_timing[item] << 16), reg); -} - -static int update_display_mode(struct dc_disp_reg *disp, - struct fdt_disp_config *config) -{ - unsigned long val; - unsigned long rate; - unsigned long div; - - writel(0x0, &disp->disp_timing_opt); - write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync); - write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width); - write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch); - write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch); - - writel(config->width | (config->height << 16), &disp->disp_active); - - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; - writel(val, &disp->data_enable_opt); - - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; - writel(val, &disp->disp_interface_ctrl); - - /* - * The pixel clock divider is in 7.1 format (where the bottom bit - * represents 0.5). Here we calculate the divider needed to get from - * the display clock (typically 600MHz) to the pixel clock. We round - * up or down as requried. - */ - rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); - div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; - debug("Display clock %lu, divider %lu\n", rate, div); - - writel(0x00010001, &disp->shift_clk_opt); - - val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; - val |= div << SHIFT_CLK_DIVIDER_SHIFT; - writel(val, &disp->disp_clk_ctrl); - - return 0; -} - -/* Start up the display and turn on power to PWMs */ -static void basic_init(struct dc_cmd_reg *cmd) -{ - u32 val; - - writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); - writel(0x0000011a, &cmd->cont_syncpt_vsync); - writel(0x00000000, &cmd->int_type); - writel(0x00000000, &cmd->int_polarity); - writel(0x00000000, &cmd->int_mask); - writel(0x00000000, &cmd->int_enb); - - val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; - val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; - val |= PM1_ENABLE; - writel(val, &cmd->disp_pow_ctrl); - - val = readl(&cmd->disp_cmd); - val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; - writel(val, &cmd->disp_cmd); -} - -static void basic_init_timer(struct dc_disp_reg *disp) -{ - writel(0x00000020, &disp->mem_high_pri); - writel(0x00000001, &disp->mem_high_pri_timer); -} - -static const u32 rgb_enb_tab[PIN_REG_COUNT] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { - 0x00000000, - 0x01000000, - 0x00000000, - 0x00000000, -}; - -static const u32 rgb_data_tab[PIN_REG_COUNT] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00210222, - 0x00002200, - 0x00020000, -}; - -static void rgb_enable(struct dc_com_reg *com) -{ - int i; - - for (i = 0; i < PIN_REG_COUNT; i++) { - writel(rgb_enb_tab[i], &com->pin_output_enb[i]); - writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); - writel(rgb_data_tab[i], &com->pin_output_data[i]); - } - - for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) - writel(rgb_sel_tab[i], &com->pin_output_sel[i]); -} - -static int setup_window(struct disp_ctl_win *win, - struct fdt_disp_config *config) -{ - win->x = 0; - win->y = 0; - win->w = config->width; - win->h = config->height; - win->out_x = 0; - win->out_y = 0; - win->out_w = config->width; - win->out_h = config->height; - win->phys_addr = config->frame_buffer; - win->stride = config->width * (1 << config->log2_bpp) / 8; - debug("%s: depth = %d\n", __func__, config->log2_bpp); - switch (config->log2_bpp) { - case 5: - case 24: - win->fmt = COLOR_DEPTH_R8G8B8A8; - win->bpp = 32; - break; - case 4: - win->fmt = COLOR_DEPTH_B5G6R5; - win->bpp = 16; - break; - - default: - debug("Unsupported LCD bit depth"); - return -1; - } - - return 0; -} - -struct fdt_disp_config *tegra_display_get_config(void) -{ - return config.valid ? &config : NULL; -} - -static void debug_timing(const char *name, unsigned int timing[]) -{ -#ifdef DEBUG - int i; - - debug("%s timing: ", name); - for (i = 0; i < FDT_LCD_TIMING_COUNT; i++) - debug("%d ", timing[i]); - debug("\n"); -#endif -} - -/** - * Decode panel information from the fdt, according to a standard binding - * - * @param blob fdt blob - * @param node offset of fdt node to read from - * @param config structure to store fdt config into - * @return 0 if ok, -ve on error - */ -static int tegra_decode_panel(const void *blob, int node, - struct fdt_disp_config *config) -{ - int front, back, ref; - - config->width = fdtdec_get_int(blob, node, "xres", -1); - config->height = fdtdec_get_int(blob, node, "yres", -1); - config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0); - if (!config->pixel_clock || config->width == -1 || - config->height == -1) { - debug("%s: Pixel parameters missing\n", __func__); - return -FDT_ERR_NOTFOUND; - } - - back = fdtdec_get_int(blob, node, "left-margin", -1); - front = fdtdec_get_int(blob, node, "right-margin", -1); - ref = fdtdec_get_int(blob, node, "hsync-len", -1); - if ((back | front | ref) == -1) { - debug("%s: Horizontal parameters missing\n", __func__); - return -FDT_ERR_NOTFOUND; - } - - /* Use a ref-to-sync of 1 always, and take this from the front porch */ - config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; - config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; - config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back; - config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - - config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC]; - debug_timing("horiz", config->horiz_timing); - - back = fdtdec_get_int(blob, node, "upper-margin", -1); - front = fdtdec_get_int(blob, node, "lower-margin", -1); - ref = fdtdec_get_int(blob, node, "vsync-len", -1); - if ((back | front | ref) == -1) { - debug("%s: Vertical parameters missing\n", __func__); - return -FDT_ERR_NOTFOUND; - } - - config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; - config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; - config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; - config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - - config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; - debug_timing("vert", config->vert_timing); - - return 0; -} - -/** - * Decode the display controller information from the fdt. - * - * @param blob fdt blob - * @param config structure to store fdt config into - * @return 0 if ok, -ve on error - */ -static int tegra_display_decode_config(const void *blob, - struct fdt_disp_config *config) -{ - int node, rgb; - int bpp, bit; - - /* TODO: Support multiple controllers */ - node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC); - if (node < 0) { - debug("%s: Cannot find display controller node in fdt\n", - __func__); - return node; - } - config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg"); - if (!config->disp) { - debug("%s: No display controller address\n", __func__); - return -1; - } - - rgb = fdt_subnode_offset(blob, node, "rgb"); - - config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); - if (config->panel_node < 0) { - debug("%s: Cannot find panel information\n", __func__); - return -1; - } - - if (tegra_decode_panel(blob, config->panel_node, config)) { - debug("%s: Failed to decode panel information\n", __func__); - return -1; - } - - bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel", - -1); - bit = ffs(bpp) - 1; - if (bpp == (1 << bit)) - config->log2_bpp = bit; - else - config->log2_bpp = bpp; - if (bpp == -1) { - debug("%s: Pixel bpp parameters missing\n", __func__); - return -FDT_ERR_NOTFOUND; - } - config->bpp = bpp; - - config->valid = 1; /* we have a valid configuration */ - - return 0; -} - -int tegra_display_probe(const void *blob, void *default_lcd_base) -{ - struct disp_ctl_win window; - struct dc_ctlr *dc; - - if (tegra_display_decode_config(blob, &config)) - return -1; - - config.frame_buffer = (u32)default_lcd_base; - - dc = (struct dc_ctlr *)config.disp; - - /* - * A header file for clock constants was NAKed upstream. - * TODO: Put this into the FDT and fdt_lcd struct when we have clock - * support there - */ - clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, - 144 * 1000000); - clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, - 600 * 1000000); - basic_init(&dc->cmd); - basic_init_timer(&dc->disp); - rgb_enable(&dc->com); - - if (config.pixel_clock) - update_display_mode(&dc->disp, &config); - - if (setup_window(&window, &config)) - return -1; - - update_window(dc, &window); - - return 0; -} diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index ea3ae5425e..e65d602350 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -5,9 +5,8 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o -obj-y += init_page_table.o -obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/ +obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ obj-$(CONFIG_DEBUG_LL) += debug_ll.o @@ -33,5 +32,6 @@ obj-y += timer.o obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ +obj-y += dram/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index c2a32618ac..6e2008ccd7 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -11,6 +11,8 @@ #include <linux/io.h> #include <../drivers/mtd/nand/denali.h> +#include "boot-mode/boot-device.h" + static void nand_denali_wp_disable(void) { #ifdef CONFIG_NAND_DENALI @@ -35,7 +37,9 @@ static const struct uniphier_fdt_file uniphier_fdt_files[] = { { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", }, { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", }, { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", }, + { "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", }, { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", }, + { "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", }, { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", }, { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", }, { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", }, @@ -62,7 +66,7 @@ int board_late_init(void) { puts("MODE: "); - switch (spl_boot_device()) { + switch (spl_boot_device_raw()) { case BOOT_DEVICE_MMC1: printf("eMMC Boot\n"); setenv("bootmode", "emmcboot"); @@ -76,6 +80,10 @@ int board_late_init(void) printf("NOR Boot\n"); setenv("bootmode", "norboot"); break; + case BOOT_DEVICE_USB: + printf("USB Boot\n"); + setenv("bootmode", "usbboot"); + break; default: printf("Unsupported Boot Mode\n"); return -1; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index f12415022b..d70c712206 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -40,6 +40,7 @@ static const struct uniphier_board_data ph1_ld4_data = { #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +/* 1GB RAM board */ static const struct uniphier_board_data ph1_pro4_data = { .dram_ch0_base = 0x80000000, .dram_ch0_size = 0x20000000, @@ -49,6 +50,17 @@ static const struct uniphier_board_data ph1_pro4_data = { .dram_ch1_width = 32, .dram_freq = 1600, }; + +/* 2GB RAM board */ +static const struct uniphier_board_data ph1_pro4_2g_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x40000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xc0000000, + .dram_ch1_size = 0x40000000, + .dram_ch1_width = 32, + .dram_freq = 1600, +}; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) @@ -118,6 +130,8 @@ static const struct uniphier_board_id uniphier_boards[] = { { "socionext,ph1-ld4", &ph1_ld4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + { "socionext,ph1-pro4-ace", &ph1_pro4_2g_data, }, + { "socionext,ph1-pro4-sanji", &ph1_pro4_2g_data, }, { "socionext,ph1-pro4", &ph1_pro4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h index 2ab5a535fa..1c59aaa606 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-device.h +++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h @@ -22,4 +22,6 @@ void ph1_ld4_boot_mode_show(void); void ph1_pro5_boot_mode_show(void); void proxstream2_boot_mode_show(void); +u32 spl_boot_device_raw(void); + #endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c index de12953585..1b0c183808 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c @@ -46,7 +46,7 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NONE, "Reserved"}, }; -int get_boot_mode_sel(void) +static int get_boot_mode_sel(void) { return (readl(SG_PINMON0) >> 1) & 0x1f; } @@ -55,6 +55,9 @@ u32 proxstream2_boot_device(void) { int boot_mode; + if (readl(SG_PINMON0) & BIT(6)) + return BOOT_DEVICE_USB; + boot_mode = get_boot_mode_sel(); return boot_device_table[boot_mode].type; diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index 0c5749badb..935e551472 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -11,7 +11,7 @@ #include "../soc-info.h" #include "boot-device.h" -u32 spl_boot_device(void) +u32 spl_boot_device_raw(void) { if (boot_is_swapped()) return BOOT_DEVICE_NOR; @@ -43,3 +43,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } } + +u32 spl_boot_device(void) +{ + u32 ret; + + ret = spl_boot_device_raw(); + + return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret; +} diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c index 4de9bfb102..7a34beea03 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -18,7 +18,7 @@ void ph1_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_RSTCTRL_NRST_STDMAC; #endif #ifdef CONFIG_NAND_DENALI @@ -32,7 +32,7 @@ void ph1_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c index 3df017edd2..c784c314e1 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -22,7 +22,7 @@ void ph1_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_RSTCTRL_NRST_STDMAC; #endif #ifdef CONFIG_NAND_DENALI @@ -47,7 +47,7 @@ void ph1_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index cab7df1653..a0a6003065 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -2,6 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD + obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \ ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ @@ -11,5 +13,9 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o +else + obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o + +endif diff --git a/arch/arm/mach-uniphier/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index c18f099f2c..c18f099f2c 100644 --- a/arch/arm/mach-uniphier/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 4d976e3a97..261f7cfce7 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -13,6 +13,16 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f}; +static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000001, ssif_base + 0x0000b004); @@ -56,19 +66,36 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int width) { + enum dram_size dram_size; + + switch (size / (width / 16)) { + case SZ_128M: + dram_size = DRAM_SZ_128M; + break; + case SZ_256M: + dram_size = DRAM_SZ_256M; + break; + case SZ_512M: + dram_size = DRAM_SZ_512M; + break; + default: + printf("unsupported DRAM size\n"); + return -EINVAL; + } + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); writel(0x18c6aa44, dramcont + UMC_CMDCTLB); writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB); writel(0x00ff00ff, dramcont + UMC_INITCTLC); writel(0x00000d71, dramcont + UMC_DRMMR0); writel(0x00000006, dramcont + UMC_DRMMR1); writel(0x00000298, dramcont + UMC_DRMMR2); writel(0x00000000, dramcont + UMC_DRMMR3); - writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); writel(0x00ff0008, dramcont + UMC_SPCCTLB); writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); @@ -90,9 +117,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00010000, dramcont + UMC_SPCSETD); writel(0x80000020, dramcont + UMC_DFICUPDCTLA); + + return 0; } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -103,6 +132,12 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + int ret; + + if (bd->dram_freq != 1600) { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -111,52 +146,43 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000103, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size); ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size); ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0); writel(0x00000103, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size); ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size, + bd->dram_ch0_width); + if (ret) + return ret; + + ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size, + bd->dram_ch1_width); + if (ret) + return ret; umc_start_ssif(ssif_base); return 0; } - -int ph1_pro4_umc_init(const struct uniphier_board_data *bd) -{ - if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) || - (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) && - ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) || - (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) && - bd->dram_freq == 1600) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; - } -} diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index bb7acdee1e..6e7fa885c4 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -18,6 +18,8 @@ #include "ddrmphy-regs.h" #include "umc-regs.h" +#define CH_NR 3 + enum dram_freq { FREQ_1866M, FREQ_2133M, @@ -43,6 +45,9 @@ static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; +/* dependent on package and board design */ +static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009}; + static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; /* * The ch2 is a different generation UMC core. @@ -150,7 +155,8 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width) return dgsl_max; } -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width, + int ch) { u32 tmp; void __iomem *zq_base, *dx_base; @@ -178,6 +184,8 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3); writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4); + writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0); + writel(0x55555555, phy_base + DMPHY_ACIOCR1); writel(0x00000000, phy_base + DMPHY_ACIOCR2); writel(0x55555555, phy_base + DMPHY_ACIOCR3); @@ -528,7 +536,7 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, umc_dc_base + UMC_DIOCTLA); - ddrphy_init(phy_base, freq, width); + ddrphy_init(phy_base, freq, width, ch); ret = ddrphy_impedance_calibration(phy_base); if (ret) diff --git a/arch/arm/mach-uniphier/include/mach/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h deleted file mode 100644 index 3306934ff7..0000000000 --- a/arch/arm/mach-uniphier/include/mach/mio-regs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * UniPhier MIO (Media I/O) registers - * - * Copyright (C) 2014 Panasonic Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ARCH_MIO_REGS_H -#define ARCH_MIO_REGS_H - -#define MIO_BASE 0x59810000 - -#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) -#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) -#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) - -#define MIO_USB_RSTCTRL_XRST (0x1 << 0) - -#endif /* ARCH_MIO_REGS_H */ diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S deleted file mode 100644 index 2d3ad15c6e..0000000000 --- a/arch/arm/mach-uniphier/init_page_table.S +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> - -/* page table */ -#define NR_SECTIONS 4096 -#define SECTION_SHIFT 20 -#define DEVICE 0x00002002 /* Non-shareable Device */ -#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ - -#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) -#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT)) - - .section ".rodata" - .align 14 -ENTRY(init_page_table) - section = 0 - .rept NR_SECTIONS - .if section == 0 || section == 1 || section == STACK_SECTION - attr = NORMAL - .else - attr = DEVICE - .endif - .word (section << SECTION_SHIFT) | attr - section = section + 1 - .endr -END(init_page_table) diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 291337070e..dd03ad8143 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -29,12 +29,16 @@ ENTRY(lowlevel_init) bl debug_ll_init #endif + bl setup_init_ram @ RAM area for stack and page talbe + /* * Now we are using the page table embedded in the Boot ROM. * It is not handy since it is not a straight mapped table for sLD3. - * What we need to do next is to switch over to the page table in SPL. + * Also, the access to the external bus is prohibited. What we need + * to do next is to create a page table and switch over to it. */ - ldr r3, =init_page_table @ page table must be 16KB aligned + bl create_page_table + bl v7_flush_dcache_all /* Disable MMU and Dcache before switching Page Table */ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) @@ -43,8 +47,6 @@ ENTRY(lowlevel_init) bl enable_mmu - bl setup_init_ram @ RAM area for temporary stack pointer - mov lr, r8 @ restore link mov pc, lr @ back to my caller ENDPROC(lowlevel_init) @@ -55,7 +57,7 @@ ENTRY(enable_mmu) orr r0, r0, #0x20 @ disable TTBR1 mcr p15, 0, r0, c2, c0, 2 - orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA + orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA mcr p15, 0, r0, c2, c0, 0 @ TTBR0 mov r0, #0 @@ -82,8 +84,9 @@ ENDPROC(enable_mmu) * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. * It is large enough for tmp RAM. */ -#define BOOT_RAM_SIZE (SZ_32K) -#define BOOT_WAY_BITS (0x00000100) /* way 8 */ +#define BOOT_RAM_SIZE (SZ_32K) +#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) +#define BOOT_WAY_BITS (0x00000100) /* way 8 */ ENTRY(setup_init_ram) /* @@ -96,7 +99,7 @@ ENTRY(setup_init_ram) ldr r0, = 0x00408006 @ touch to zero with address range ldr r1, = SSCOQM str r0, [r1] - ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address + ldr r0, = BOOT_RAM_BASE ldr r1, = SSCOQAD str r0, [r1] ldr r0, = BOOT_RAM_SIZE @@ -119,3 +122,86 @@ ENTRY(setup_init_ram) mov pc, lr ENDPROC(setup_init_ram) + +#define DEVICE 0x00002002 /* Non-shareable Device */ +#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ + +ENTRY(create_page_table) + ldr r0, = DEVICE + ldr r1, = BOOT_RAM_BASE + mov r12, r1 @ r12 is preserved during D-cache flush +0: str r0, [r1], #4 @ specify all the sections as Device + adds r0, r0, #0x00100000 + bcc 0b + + ldr r0, = NORMAL + str r0, [r12] @ mark the first section as Normal + add r0, r0, #0x00100000 + str r0, [r12, #4] @ mark the second section as Normal + mov pc, lr +ENDPROC(create_page_table) + +/* We don't use Thumb instructions for now */ +#define ARM(x...) x +#define THUMB(x...) + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * + * - mm - mm_struct describing address space + * + * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4 + */ +ENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + mov r3, r0, lsr #23 @ move LoC into position + ands r3, r3, #7 << 1 @ extract LoC*2 from clidr + beq finished @ if loc is 0, then no need to clean +start_flush_levels: + mov r10, #0 @ start clean at cache level 0 +flush_levels: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + movw r4, #0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + movw r7, #0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop1: + mov r9, r7 @ create working copy of max index +loop2: + ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 + THUMB( lsl r6, r4, r5 ) + THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 + ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 + THUMB( lsl r6, r9, r2 ) + THUMB( orr r11, r11, r6 ) @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way + bge loop1 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt flush_levels +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb st + isb + mov pc, lr +ENDPROC(v7_flush_dcache_all) diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c index 8168a63d31..2fe2c7fc80 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -35,15 +35,6 @@ void ph1_ld4_pin_init(void) sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */ - /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */ -#endif - tmp = readl(SG_IECTRL); tmp |= 0x41; writel(tmp, SG_IECTRL); diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c index 23b5f9349a..b08ca1ef31 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -40,12 +40,5 @@ void ph1_pro4_pin_init(void) sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ - sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */ -#endif - writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c index 6fc0dee70e..367d9f3bbc 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -9,7 +9,7 @@ void ph1_sld3_pin_init(void) { -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c index a4e3e7a614..f3fae1d7c6 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -32,13 +32,4 @@ void ph1_sld8_pin_init(void) sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ #endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ - /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */ -#endif } diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 7cd0bbf24e..7ba5f1b848 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 91aa5cc89c..529322a174 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -1,5 +1,5 @@ /* - * U-boot - cpu.c CPU specific functions + * U-Boot - cpu.c CPU specific functions * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h index f6aa1b6539..a5fe02e53c 100644 --- a/arch/blackfin/cpu/cpu.h +++ b/arch/blackfin/cpu/cpu.h @@ -1,5 +1,5 @@ /* - * U-boot - cpu.h + * U-Boot - cpu.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c index 9189816699..45c92c3d3e 100644 --- a/arch/blackfin/cpu/interrupts.c +++ b/arch/blackfin/cpu/interrupts.c @@ -1,5 +1,5 @@ /* - * U-boot - interrupts.c Interrupt related routines + * U-Boot - interrupts.c Interrupt related routines * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index f31abfacf2..823a1dfde8 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -1,5 +1,5 @@ /* - * U-boot - start.S Startup file for Blackfin u-boot + * U-Boot - start.S Startup file for Blackfin U-Boot * * Copyright (c) 2005-2008 Analog Devices Inc. * @@ -51,7 +51,7 @@ ENTRY(_start) #ifdef CONFIG_HW_WATCHDOG /* Program the watchdog with default timeout of ~5 seconds. * That should be long enough to bootstrap ourselves up and - * then the common u-boot code can take over. + * then the common U-Boot code can take over. */ r1 = WDDIS; # ifdef __ADSPBF60x__ diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index 10f72f8246..21760d01a7 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -1,5 +1,5 @@ /* - * U-boot - traps.c Routines related to interrupts and exceptions + * U-Boot - traps.c Routines related to interrupts and exceptions * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds index ae1b813c1f..f407fb2327 100644 --- a/arch/blackfin/cpu/u-boot.lds +++ b/arch/blackfin/cpu/u-boot.lds @@ -1,5 +1,5 @@ /* - * U-boot - u-boot.lds.S + * U-Boot - u-boot.lds.S * * Copyright (c) 2005-2010 Analog Device Inc. * diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 6cde6dbfde..a1462bdecc 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -1,5 +1,5 @@ /* - * U-boot - bitops.h Routines for bit operations + * U-Boot - bitops.h Routines for bit operations * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 868c82ea7d..00556de284 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -1,5 +1,5 @@ /* - * U-boot - blackfin_local.h + * U-Boot - blackfin_local.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h index 98fb7bf744..593ba5a4cf 100644 --- a/arch/blackfin/include/asm/byteorder.h +++ b/arch/blackfin/include/asm/byteorder.h @@ -1,5 +1,5 @@ /* - * U-boot - byteorder.h + * U-Boot - byteorder.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/deferred.h b/arch/blackfin/include/asm/deferred.h index 82ceda3e4d..e75d7e80ad 100644 --- a/arch/blackfin/include/asm/deferred.h +++ b/arch/blackfin/include/asm/deferred.h @@ -1,5 +1,5 @@ /* - * U-boot - deferred register layout + * U-Boot - deferred register layout * * Copyright 2004-2009 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h index f146efd6e7..06c3edd03e 100644 --- a/arch/blackfin/include/asm/delay.h +++ b/arch/blackfin/include/asm/delay.h @@ -1,5 +1,5 @@ /* - * U-boot - delay.h Routines for introducing delays + * U-Boot - delay.h Routines for introducing delays * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index 7aefead402..69a6971dd0 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * U-boot - global_data.h Declarations for global data of u-boot + * U-Boot - global_data.h Declarations for global data of U-Boot * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index aadb0d2d4e..d3337e4fac 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -1,5 +1,5 @@ /* - * U-boot - io.h IO routines + * U-Boot - io.h IO routines * * Copyright 2004-2009 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h index 7e06bc7123..60d5317797 100644 --- a/arch/blackfin/include/asm/linkage.h +++ b/arch/blackfin/include/asm/linkage.h @@ -1,5 +1,5 @@ /* - * U-boot - linkage.h + * U-Boot - linkage.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h index 18be579d26..8535235031 100644 --- a/arch/blackfin/include/asm/posix_types.h +++ b/arch/blackfin/include/asm/posix_types.h @@ -1,5 +1,5 @@ /* - * U-boot - posix_types.h + * U-Boot - posix_types.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h index b79800672e..1daf59bc87 100644 --- a/arch/blackfin/include/asm/processor.h +++ b/arch/blackfin/include/asm/processor.h @@ -1,5 +1,5 @@ /* - * U-boot - processor.h + * U-Boot - processor.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/shared_resources.h b/arch/blackfin/include/asm/shared_resources.h index 1a03392632..42dab9f126 100644 --- a/arch/blackfin/include/asm/shared_resources.h +++ b/arch/blackfin/include/asm/shared_resources.h @@ -1,5 +1,5 @@ /* - * U-boot - setup.h + * U-Boot - setup.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/soft_switch.h b/arch/blackfin/include/asm/soft_switch.h index ff8e44d8be..321b070825 100644 --- a/arch/blackfin/include/asm/soft_switch.h +++ b/arch/blackfin/include/asm/soft_switch.h @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2012 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h index aea4e29c9d..15f50f23cb 100644 --- a/arch/blackfin/include/asm/string.h +++ b/arch/blackfin/include/asm/string.h @@ -1,5 +1,5 @@ /* - * U-boot - string.h String functions + * U-Boot - string.h String functions * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 5a7e8edb6d..f0c4ae2609 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -1,5 +1,5 @@ /* - * U-boot - system.h + * U-Boot - system.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h index 92124f1823..4da64c450e 100644 --- a/arch/blackfin/include/asm/types.h +++ b/arch/blackfin/include/asm/types.h @@ -1,5 +1,5 @@ /* - * U-boot - types.h + * U-Boot - types.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index 7b5cf6a1b6..1ada44edcd 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -1,5 +1,5 @@ /* - * U-boot - u-boot.h Structure declarations for board specific data + * U-Boot - u-boot.h Structure declarations for board specific data * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile index b534a98c9c..de02c69dd2 100644 --- a/arch/blackfin/lib/Makefile +++ b/arch/blackfin/lib/Makefile @@ -1,5 +1,5 @@ # -# U-boot Makefile +# U-Boot Makefile # # Copyright (c) 2005-2008 Analog Devices Inc. # diff --git a/arch/blackfin/lib/boot.c b/arch/blackfin/lib/boot.c index 5644d589e7..fd4c82e9c8 100644 --- a/arch/blackfin/lib/boot.c +++ b/arch/blackfin/lib/boot.c @@ -1,5 +1,5 @@ /* - * U-boot - boot.c - misc boot helper functions + * U-Boot - boot.c - misc boot helper functions * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c index e8a0cb5deb..8d933393b4 100644 --- a/arch/blackfin/lib/cache.c +++ b/arch/blackfin/lib/cache.c @@ -1,5 +1,5 @@ /* - * U-boot - cache.c + * U-Boot - cache.c * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/blackfin/lib/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c index f9f909791e..a4c799acb3 100644 --- a/arch/blackfin/lib/cmd_cache_dump.c +++ b/arch/blackfin/lib/cmd_cache_dump.c @@ -1,5 +1,5 @@ /* - * U-boot - cmd_cache_dump.c + * U-Boot - cmd_cache_dump.c * * Copyright (c) 2007-2008 Analog Devices Inc. * diff --git a/arch/blackfin/lib/kgdb.c b/arch/blackfin/lib/kgdb.c index 4ca3fc7312..2a7c0727f5 100644 --- a/arch/blackfin/lib/kgdb.c +++ b/arch/blackfin/lib/kgdb.c @@ -1,5 +1,5 @@ /* - * U-boot - architecture specific kgdb code + * U-Boot - architecture specific kgdb code * * Copyright 2009 Analog Devices Inc. * diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c index 65f55238f4..9f6f60d05f 100644 --- a/arch/blackfin/lib/muldi3.c +++ b/arch/blackfin/lib/muldi3.c @@ -1,5 +1,5 @@ /* - * U-boot - muldi3.c contains routines for mult and div + * U-Boot - muldi3.c contains routines for mult and div * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/blackfin/lib/sections.c b/arch/blackfin/lib/sections.c index b50f30aa45..86fc4df061 100644 --- a/arch/blackfin/lib/sections.c +++ b/arch/blackfin/lib/sections.c @@ -1,5 +1,5 @@ /* - * U-boot - section.c + * U-Boot - section.c * * Copyright (c) 2014 Analog Devices Inc. * diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c index 211df7b430..c904a88916 100644 --- a/arch/blackfin/lib/string.c +++ b/arch/blackfin/lib/string.c @@ -1,5 +1,5 @@ /* - * U-boot - string.c Contains library routines. + * U-Boot - string.c Contains library routines. * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c index 5c1a1541c8..95b6b3282b 100644 --- a/arch/microblaze/lib/muldi3.c +++ b/arch/microblaze/lib/muldi3.c @@ -1,5 +1,5 @@ /* - * U-boot - muldi3.c contains routines for mult and div + * U-Boot - muldi3.c contains routines for mult and div * * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d2c31ae781..1b56ca350a 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -57,7 +57,7 @@ .set noreorder ENTRY(_start) - /* U-boot entry point */ + /* U-Boot entry point */ b reset nop diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h index 7e06bc7123..60d5317797 100644 --- a/arch/nds32/include/asm/linkage.h +++ b/arch/nds32/include/asm/linkage.h @@ -1,5 +1,5 @@ /* - * U-boot - linkage.h + * U-Boot - linkage.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 204d0cd9d4..3e1b0c9514 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -106,6 +106,13 @@ _reloc: stw r0, 4(sp) mov fp, sp +#ifdef CONFIG_DEBUG_UART + /* Set up the debug UART */ + movhi r2, %hi(debug_uart_init@h) + ori r2, r2, %lo(debug_uart_init@h) + callr r2 +#endif + /* Allocate and initialize reserved area, update SP */ mov r4, sp movhi r2, %hi(board_init_f_alloc_reserve@h) diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c index 2655974a45..577b6d9e79 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -12,7 +12,7 @@ /* * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but - * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in + * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in * this table. This works because most of the SerDes code is for errata * work-arounds, and there are no P5040 errata that effect bank 4. */ diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index af65c969c2..94c785f611 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -268,11 +268,6 @@ smc_putc(const char c) volatile cpm8xx_t *cpmp = &(im->im_cpm); volatile serialbuffer_t *rtx; -#ifdef CONFIG_MODEM_SUPPORT - if (gd->be_quiet) - return; -#endif - if (c == '\n') smc_putc ('\r'); @@ -527,11 +522,6 @@ scc_putc(const char c) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); -#ifdef CONFIG_MODEM_SUPPORT - if (gd->be_quiet) - return; -#endif - if (c == '\n') scc_putc ('\r'); @@ -637,18 +627,6 @@ void mpc8xx_serial_initialize(void) #endif } -#ifdef CONFIG_MODEM_SUPPORT -void disable_putc(void) -{ - gd->be_quiet = 1; -} - -void enable_putc(void) -{ - gd->be_quiet = 0; -} -#endif - #if defined(CONFIG_CMD_KGDB) void diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 9b9a71d553..75ac7dc62a 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -13,7 +13,7 @@ /* Currently, this board information is not passed to * Linux kernel from U-Boot, but may be passed to other - * Operating systems. This is because U-boot emulates + * Operating systems. This is because U-Boot emulates * a SUN PROM loader (from Linux point of view). */ #include <asm-generic/u-boot.h> diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h index 4f68fbda69..916ee9c5a3 100644 --- a/arch/sparc/include/asm/winmacro.h +++ b/arch/sparc/include/asm/winmacro.h @@ -1,5 +1,5 @@ /* - * Added to U-boot, + * Added to U-Boot, * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com * Copyright (C) 2007 * diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a995e32bb9..a0bd344ed1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -93,9 +93,6 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 -config DM_PCI_COMPAT - default y # Until we finish moving over to the new API - config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024 @@ -251,6 +248,16 @@ config FSP_USE_UPD are still some FSPs that might not even have UPD. For such FSPs, override this to n in their platform Kconfig files. +config FSP_BROKEN_HOB + bool + depends on HAVE_FSP + help + Indicate some buggy FSPs that does not report memory used by FSP + itself as reserved in the resource descriptor HOB. Select this to + tell U-Boot to do some additional work to ensure U-Boot relocation + do not overwrite the important boot service data which is used by + FSP, otherwise the subsequent call to fsp_notify() will fail. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 0b36ace091..2950783055 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -16,19 +16,18 @@ DECLARE_GLOBAL_DATA_PTR; -static struct irq_router irq_router; static struct irq_routing_table *pirq_routing_table; -bool pirq_check_irq_routed(int link, u8 irq) +bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { + struct irq_router *priv = dev_get_priv(dev); u8 pirq; - int base = irq_router.link_base; + int base = priv->link_base; - if (irq_router.config == PIRQ_VIA_PCI) - pirq = x86_pci_read_config8(irq_router.bdf, - LINK_N2V(link, base)); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); else - pirq = readb(irq_router.ibase + LINK_N2V(link, base)); + pirq = readb(priv->ibase + LINK_N2V(link, base)); pirq &= 0xf; @@ -39,24 +38,26 @@ bool pirq_check_irq_routed(int link, u8 irq) return pirq == irq ? true : false; } -int pirq_translate_link(int link) +int pirq_translate_link(struct udevice *dev, int link) { - return LINK_V2N(link, irq_router.link_base); + struct irq_router *priv = dev_get_priv(dev); + + return LINK_V2N(link, priv->link_base); } -void pirq_assign_irq(int link, u8 irq) +void pirq_assign_irq(struct udevice *dev, int link, u8 irq) { - int base = irq_router.link_base; + struct irq_router *priv = dev_get_priv(dev); + int base = priv->link_base; /* IRQ# 0/1/2/8/13 are reserved */ if (irq < 3 || irq == 8 || irq == 13) return; - if (irq_router.config == PIRQ_VIA_PCI) - x86_pci_write_config8(irq_router.bdf, - LINK_N2V(link, base), irq); + if (priv->config == PIRQ_VIA_PCI) + dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); else - writeb(irq, irq_router.ibase + LINK_N2V(link, base)); + writeb(irq, priv->ibase + LINK_N2V(link, base)); } static struct irq_info *check_dup_entry(struct irq_info *slot_base, @@ -74,46 +75,40 @@ static struct irq_info *check_dup_entry(struct irq_info *slot_base, return (i == entry_num) ? NULL : slot; } -static inline void fill_irq_info(struct irq_info *slot, int bus, int device, - int pin, int pirq) +static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, + int bus, int device, int pin, int pirq) { slot->bus = bus; slot->devfn = (device << 3) | 0; - slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base); - slot->irq[pin - 1].bitmap = irq_router.irq_mask; + slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); + slot->irq[pin - 1].bitmap = priv->irq_mask; } static int create_pirq_routing_table(struct udevice *dev) { + struct irq_router *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; - struct fdt_pci_addr addr; int node; int len, count; const u32 *cell; struct irq_routing_table *rt; struct irq_info *slot, *slot_base; int irq_entries = 0; - int parent; int i; int ret; node = dev->of_offset; - parent = dev->parent->of_offset; - ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG, - "reg", &addr); - if (ret) - return ret; /* extract the bdf from fdt_pci_addr */ - irq_router.bdf = addr.phys_hi & 0xffff00; + priv->bdf = dm_pci_get_bdf(dev->parent); ret = fdt_find_string(blob, node, "intel,pirq-config", "pci"); if (!ret) { - irq_router.config = PIRQ_VIA_PCI; + priv->config = PIRQ_VIA_PCI; } else { ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase"); if (!ret) - irq_router.config = PIRQ_VIA_IBASE; + priv->config = PIRQ_VIA_IBASE; else return -EINVAL; } @@ -121,12 +116,12 @@ static int create_pirq_routing_table(struct udevice *dev) ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); if (ret == -1) return ret; - irq_router.link_base = ret; + priv->link_base = ret; - irq_router.irq_mask = fdtdec_get_int(blob, node, - "intel,pirq-mask", PIRQ_BITMAP); + priv->irq_mask = fdtdec_get_int(blob, node, + "intel,pirq-mask", PIRQ_BITMAP); - if (irq_router.config == PIRQ_VIA_IBASE) { + if (priv->config == PIRQ_VIA_IBASE) { int ibase_off; ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0); @@ -143,9 +138,8 @@ static int create_pirq_routing_table(struct udevice *dev) * 2) memory range decoding is enabled. * Hence we don't do any santify test here. */ - irq_router.ibase = x86_pci_read_config32(irq_router.bdf, - ibase_off); - irq_router.ibase &= ~0xf; + dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); + priv->ibase &= ~0xf; } cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); @@ -160,9 +154,8 @@ static int create_pirq_routing_table(struct udevice *dev) /* Populate the PIRQ table fields */ rt->signature = PIRQ_SIGNATURE; rt->version = PIRQ_VERSION; - rt->rtr_bus = PCI_BUS(irq_router.bdf); - rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) | - PCI_FUNC(irq_router.bdf); + rt->rtr_bus = PCI_BUS(priv->bdf); + rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf); rt->rtr_vendor = PCI_VENDOR_ID_INTEL; rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; @@ -199,7 +192,7 @@ static int create_pirq_routing_table(struct udevice *dev) * routing information in the device tree. */ if (slot->irq[pr.pin - 1].link != - LINK_N2V(pr.pirq, irq_router.link_base)) + LINK_N2V(pr.pirq, priv->link_base)) debug("WARNING: Inconsistent PIRQ routing information\n"); continue; } @@ -207,8 +200,8 @@ static int create_pirq_routing_table(struct udevice *dev) slot = slot_base + irq_entries++; } debug("writing INT%c\n", 'A' + pr.pin - 1); - fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin, - pr.pirq); + fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), + pr.pin, pr.pirq); } rt->size = irq_entries * sizeof(struct irq_info) + 32; @@ -228,7 +221,7 @@ int irq_router_common_init(struct udevice *dev) return ret; } /* Route PIRQ */ - pirq_route_irqs(pirq_routing_table->slots, + pirq_route_irqs(dev, pirq_routing_table->slots, get_irq_slot_count(pirq_routing_table)); return 0; @@ -257,6 +250,7 @@ U_BOOT_DRIVER(irq_router_drv) = { .id = UCLASS_IRQ, .of_match = irq_router_ids, .probe = irq_router_probe, + .priv_auto_alloc_size = sizeof(struct irq_router), }; UCLASS_DRIVER(irq) = { diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 1768a26a35..0819347b59 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -71,4 +71,16 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly. +config FSP_ADDR + hex + default 0xfff80000 + +config FSP_USE_UPD + bool + default n + +config FSP_BROKEN_HOB + bool + default y + endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 45ef14187e..9203219f31 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -4,7 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += bd82x6x.o +ifdef CONFIG_HAVE_FSP +obj-y += fsp_configs.o ivybridge.o +else obj-y += car.o obj-y += cpu.o obj-y += early_me.o @@ -17,3 +19,5 @@ obj-y += northbridge.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o +endif +obj-y += bd82x6x.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 2b172d49ba..9972b0ae7f 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,8 +19,10 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> +#define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc +#ifndef CONFIG_HAVE_FSP static int pch_revision_id = -1; static int pch_type = -1; @@ -169,8 +171,9 @@ static int bd82x6x_probe(struct udevice *dev) return 0; } +#endif /* CONFIG_HAVE_FSP */ -static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) +static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) { u32 rcba; @@ -182,11 +185,6 @@ static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) return 0; } -static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) -{ - return PCHV_9; -} - static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) { uint8_t bios_cntl; @@ -205,10 +203,41 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops bd82x6x_pch_ops = { - .get_sbase = bd82x6x_pch_get_sbase, - .get_version = bd82x6x_pch_get_version, + .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, + .get_gpio_base = bd82x6x_get_gpio_base, }; static const struct udevice_id bd82x6x_ids[] = { @@ -220,6 +249,8 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .name = "bd82x6x", .id = UCLASS_PCH, .of_match = bd82x6x_ids, +#ifndef CONFIG_HAVE_FSP .probe = bd82x6x_probe, +#endif .ops = &bd82x6x_pch_ops, }; diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c new file mode 100644 index 0000000000..c7f475b5a6 --- /dev/null +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct platform_config *plat_config = &config->plat_config; + struct memory_config *mem_config = &config->mem_config; + const void *blob = gd->fdt_blob; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + plat_config->enable_ht = + fdtdec_get_bool(blob, node, "fsp,enable-ht"); + plat_config->enable_turbo = + fdtdec_get_bool(blob, node, "fsp,enable-turbo"); + plat_config->enable_memory_down = + fdtdec_get_bool(blob, node, "fsp,enable-memory-down"); + plat_config->enable_fast_boot = + fdtdec_get_bool(blob, node, "fsp,enable-fast-boot"); + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->stack_top = config->common.stack_top - 32; + rt_buf->boot_mode = config->common.boot_mode; + rt_buf->plat_config = plat_config; + + if (plat_config->enable_memory_down) + rt_buf->mem_config = mem_config; + else + rt_buf->mem_config = NULL; +} diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c new file mode 100644 index 0000000000..c770b53c08 --- /dev/null +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/post.h> +#include <asm/processor.h> + +int arch_cpu_init(void) +{ + int ret; + + post_code(POST_CPU_INIT); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 7917350bff..fc2fb5bf44 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -243,7 +243,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) params->stack_size = CONFIG_AP_STACK_SIZE; size = params->stack_size * num_cpus; - stack = memalign(size, 4096); + stack = memalign(4096, size); if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 7a312602a0..c9c7637fa7 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -19,59 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pci_controller *get_hose(void) -{ - if (gd->hose) - return gd->hose; - - return pci_bus_to_hose(0); -} - -unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where) -{ - uint8_t value; - - if (pci_hose_read_config_byte(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where) -{ - uint16_t value; - - if (pci_hose_read_config_word(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where) -{ - uint32_t value; - - if (pci_hose_read_config_dword(get_hose(), dev, where, &value)) - return -1U; - - return value; -} - -void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_byte(get_hose(), dev, where, value); -} - -void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_word(get_hose(), dev, where, value); -} - -void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) -{ - pci_hose_write_config_dword(get_hose(), dev, where, value); -} - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { @@ -119,11 +66,11 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) for (func = 0; func < 8; func++) { bdf = PCI_BDF(bus, device, func); - vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID); + pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); if (vendor == 0xffff || vendor == 0x0000) continue; - pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); /* PCI spec says all values except 1..4 are reserved */ if ((pin < 1) || (pin > 4)) @@ -136,6 +83,6 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", line, bus, device, func, 'A' + pin - 1); - x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); } } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index f8af566dea..7ad0ee49a1 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -5,8 +5,8 @@ */ #include <common.h> +#include <pci.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> @@ -21,23 +21,23 @@ static void enable_pm_piix(void) u16 cmd; /* Set the PM I/O base */ - x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); /* Enable access to the PM I/O space */ - cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND); + pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_IO; - x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); + pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); /* PM I/O Space Enable (PMIOSE) */ - en = x86_pci_read_config8(PIIX_PM, PMREGMISC); + pci_read_config8(PIIX_PM, PMREGMISC, &en); en |= PMIOSE; - x86_pci_write_config8(PIIX_PM, PMREGMISC, en); + pci_write_config8(PIIX_PM, PMREGMISC, en); } static void enable_pm_ich9(void) { /* Set the PM I/O base */ - x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); } static void qemu_chipset_init(void) @@ -50,7 +50,7 @@ static void qemu_chipset_init(void) * the same bitfield layout. Here we determine the offset based on its * PCI device ID. */ - device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); i440fx = (device == PCI_DEVICE_ID_INTEL_82441); pam = i440fx ? I440FX_PAM : Q35_PAM; @@ -60,7 +60,7 @@ static void qemu_chipset_init(void) * Configure legacy segments C/D/E/F to system RAM */ for (i = 0; i < PAM_NUM; i++) - x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); if (i440fx) { /* @@ -71,19 +71,19 @@ static void qemu_chipset_init(void) * registers to see whether legacy ports decode is turned on. * This is to make Linux ata_piix driver happy. */ - x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); - x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); /* Enable I/O APIC */ - xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + pci_read_config16(PIIX_ISA, XBCS, &xbcs); xbcs |= APIC_EN; - x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + pci_write_config16(PIIX_ISA, XBCS, xbcs); enable_pm_piix(); } else { /* Configure PCIe ECAM base address */ - x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, - CONFIG_PCIE_ECAM_BASE | BAR_EN); + pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); enable_pm_ich9(); } @@ -136,8 +136,8 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) * connected to I/O APIC INTPIN#16-19. Instead they are routed * to an irq number controled by the PIRQ routing register. */ - irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), - PCI_INTERRUPT_LINE); + pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE, &irq); } else { /* * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 49d803d794..fac2d72e0d 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -12,6 +12,7 @@ #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/arch/quark.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" @@ -106,8 +107,8 @@ void select_hte(void) */ void dram_init_command(uint32_t data) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0); DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data); diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 6e20930a4d..afb3463797 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -20,21 +20,6 @@ static struct pci_device_id mmc_supported[] = { {}, }; -/* - * TODO: - * - * This whole routine should be removed until we fully convert the ICH SPI - * driver to DM and make use of DT to pass the bios control register offset - */ -static void unprotect_spi_flash(void) -{ - u32 bc; - - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); - bc |= 0x1; /* unprotect the flash */ - qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); -} - static void quark_setup_mtrr(void) { u32 base, mask; @@ -259,8 +244,6 @@ int arch_cpu_init(void) /* Turn on legacy segments (A/B/E/F) decode to system RAM */ quark_enable_legacy_seg(); - unprotect_spi_flash(); - return 0; } diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c index 44369f7ec7..63d0f35a29 100644 --- a/arch/x86/cpu/queensbay/irq.c +++ b/arch/x86/cpu/queensbay/irq.c @@ -18,7 +18,7 @@ int queensbay_irq_router_probe(struct udevice *dev) struct tnc_rcba *rcba; u32 base; - base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); + dm_pci_read_config32(dev->parent, LPC_RCBA, &base); base &= ~MEM_BAR_EN; rcba = (struct tnc_rcba *)base; diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 75f7adb74c..b226e4c5fd 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -5,26 +5,34 @@ */ #include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <pci.h> #include <asm/io.h> #include <asm/irq.h> -#include <asm/pci.h> #include <asm/post.h> #include <asm/arch/device.h> #include <asm/arch/tnc.h> #include <asm/fsp/fsp_support.h> #include <asm/processor.h> -static void unprotect_spi_flash(void) +static int __maybe_unused disable_igd(void) { - u32 bc; + struct udevice *igd, *sdvo; + int ret; - bc = x86_pci_read_config32(TNC_LPC, 0xd8); - bc |= 0x1; /* unprotect the flash */ - x86_pci_write_config32(TNC_LPC, 0xd8, bc); -} + ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); + if (ret) + return ret; + if (!igd) + return 0; + + ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); + if (ret) + return ret; + if (!sdvo) + return 0; -static void __maybe_unused disable_igd(void) -{ /* * According to Atom E6xx datasheet, setting VGA Disable (bit17) * of Graphics Controller register (offset 0x50) prevents IGD @@ -43,8 +51,45 @@ static void __maybe_unused disable_igd(void) * two devices will be completely disabled (invisible in the PCI * configuration space) unless a system reset is performed. */ - x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); - x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); + dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); + + /* + * After setting the function disable bit, IGD and SDVO devices will + * disappear in the PCI configuration space. This however creates an + * inconsistent state from a driver model PCI controller point of view, + * as these two PCI devices are still attached to its parent's child + * device list as maintained by the driver model. Some driver model PCI + * APIs like dm_pci_find_class(), are referring to the list to speed up + * the finding process instead of re-enumerating the whole PCI bus, so + * it gets the stale cached data which is wrong. + * + * Note x86 PCI enueration normally happens twice, in pre-relocation + * phase and post-relocation. One option might be to call disable_igd() + * in one of the pre-relocation initialization hooks so that it gets + * disabled in the first round, and when it comes to the second round + * driver model PCI will construct a correct list. Unfortunately this + * does not work as Intel FSP is used on this platform to perform low + * level initialization, and fsp_init_phase_pci() is called only once + * in the post-relocation phase. If we disable IGD and SDVO devices, + * fsp_init_phase_pci() simply hangs and never returns. + * + * So the only option we have is to manually remove these two devices. + */ + ret = device_remove(igd); + if (ret) + return ret; + ret = device_unbind(igd); + if (ret) + return ret; + ret = device_remove(sdvo); + if (ret) + return ret; + ret = device_unbind(sdvo); + if (ret) + return ret; + + return 0; } int arch_cpu_init(void) @@ -62,16 +107,11 @@ int arch_cpu_init(void) int arch_early_init_r(void) { + int ret = 0; + #ifdef CONFIG_DISABLE_IGD - disable_igd(); + ret = disable_igd(); #endif - return 0; -} - -int arch_misc_init(void) -{ - unprotect_spi_flash(); - - return 0; + return ret; } diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 68a5b947d8..183275b9c2 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -1,5 +1,5 @@ /* - * U-boot - x86 Startup Code + * U-Boot - x86 Startup Code * * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 64e569432c..84feb193d7 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -5,6 +5,7 @@ dtb-y += bayleybay.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ + cougarcanyon2.dtb \ crownbay.dtb \ efi.dtb \ galileo.dtb \ diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index fbca46762c..4ea9262251 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,48 +65,6 @@ }; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x20>; - bank-name = "C"; - }; - - gpiod { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x60 0x20>; - bank-name = "D"; - }; - - gpioe { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x80 0x20>; - bank-name = "E"; - }; - - gpiof { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0xA0 0x20>; - bank-name = "F"; - }; - pci { compatible = "pci-x86"; #address-cells = <3>; @@ -119,6 +77,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,irq-router"; @@ -187,7 +147,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -201,6 +161,48 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; }; }; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 7b2c51504b..4bb0a34b5f 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -37,7 +37,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { reg = <0>; compatible = "winbond,w25q128", "spi-flash"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 58072031df..f85e55cd6d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -54,27 +54,6 @@ }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x10>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x30 0x10>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x10>; - bank-name = "C"; - }; - chosen { stdout-path = "/serial"; }; @@ -255,7 +234,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -270,6 +249,27 @@ }; }; + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + lpc { compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 48f0c77d45..480b36658e 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -18,27 +18,6 @@ no-keyboard; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x10>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x30 0x10>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x10>; - bank-name = "C"; - }; - chosen { stdout-path = "/serial"; }; @@ -55,11 +34,13 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -73,6 +54,27 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; }; }; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts new file mode 100644 index 0000000000..d41556638c --- /dev/null +++ b/arch/x86/dts/cougarcanyon2.dts @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Cougar Canyon 2"; + compatible = "intel,cougarcanyon2", "intel,chiefriver"; + + aliases { + spi0 = &spi0; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + microcode { + update@0 { +#include "microcode/m12306a2_00000008.dtsi" + }; + update@1 { +#include "microcode/m12306a4_00000007.dtsi" + }; + update@2 { +#include "microcode/m12306a5_00000007.dtsi" + }; + update@3 { +#include "microcode/m12306a8_00000010.dtsi" + }; + update@4 { +#include "microcode/m12306a9_0000001b.dtsi" + }; + }; + + fsp { + compatible = "intel,ivybridge-fsp"; + fsp,enable-ht; + }; + + pci { + #address-cells = <3>; + #size-cells = <2>; + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,bd82x6x"; + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + spi0: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64bv", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + }; + }; + +}; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 47fab0fda6..337513be57 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -46,20 +46,6 @@ }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - chosen { /* * By default the legacy superio serial port is used as the @@ -162,6 +148,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch7"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,queensbay-irq-router"; @@ -230,7 +218,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich7-spi"; spi-flash@0 { reg = <0>; compatible = "sst,25vf016b", @@ -238,6 +226,20 @@ memory-map = <0xffe00000 0x00200000>; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; }; }; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index dd75fc4dc9..21c36412e2 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -82,6 +82,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch7"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,quark-irq-router"; @@ -118,7 +120,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich7-spi"; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; @@ -132,21 +134,21 @@ }; }; }; - }; - }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 7afdf6c30b..60bd05afb6 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -29,7 +29,6 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; - io-base = <0x4c>; /* GPIO E0 */ soc_gpio_s5_0@0 { @@ -75,48 +74,6 @@ }; }; - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x20>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x20 0x20>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x20>; - bank-name = "C"; - }; - - gpiod { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x60 0x20>; - bank-name = "D"; - }; - - gpioe { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x80 0x20>; - bank-name = "E"; - }; - - gpiof { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0xA0 0x20>; - bank-name = "F"; - }; - chosen { stdout-path = "/serial"; }; @@ -153,6 +110,8 @@ pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; irq-router { compatible = "intel,irq-router"; @@ -221,7 +180,7 @@ spi: spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich-spi"; + compatible = "intel,ich9-spi"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -235,6 +194,48 @@ }; }; }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; }; }; diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h deleted file mode 100644 index 4e8987ce5c..0000000000 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h deleted file mode 100644 index 31edef9623..0000000000 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2014, Google Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-efi/gpio.h b/arch/x86/include/asm/arch-efi/gpio.h deleted file mode 100644 index f044f07537..0000000000 --- a/arch/x86/include/asm/arch-efi/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h new file mode 100644 index 0000000000..9b0613daf5 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct platform_config { + u8 enable_ht; + u8 enable_turbo; + u8 enable_memory_down; + u8 enable_fast_boot; +}; + +/* + * Dummy structure for now as currently only SPD is verified in U-Boot. + * + * We can add the missing parameters when adding support on a board with + * memory down configuration. + */ +struct memory_config { + u8 dummy; +}; + +struct fsp_config_data { + struct fsp_cfg_common common; + struct platform_config plat_config; + struct memory_config mem_config; +}; + +struct fspinit_rtbuf { + u32 stack_top; + u32 boot_mode; + struct platform_config *plat_config; + struct memory_config *mem_config; +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h new file mode 100644 index 0000000000..3b255ccb81 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_VPD_H__ +#define __FSP_VPD_H__ + +/* IvyBridge FSP does not support VPD/UPD */ + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h deleted file mode 100644 index 31edef9623..0000000000 --- a/arch/x86/include/asm/arch-ivybridge/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2014, Google Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-qemu/gpio.h b/arch/x86/include/asm/arch-qemu/gpio.h deleted file mode 100644 index ca8cba4f97..0000000000 --- a/arch/x86/include/asm/arch-qemu/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-quark/gpio.h b/arch/x86/include/asm/arch-quark/gpio.h deleted file mode 100644 index ca8cba4f97..0000000000 --- a/arch/x86/include/asm/arch-quark/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h deleted file mode 100644 index ab4e059131..0000000000 --- a/arch/x86/include/asm/arch-queensbay/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _X86_ARCH_GPIO_H_ -#define _X86_ARCH_GPIO_H_ - -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 - -#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index ed85b08ce7..403851b792 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -7,7 +7,6 @@ #define _X86_GPIO_H_ #include <linux/compiler.h> -#include <asm/arch/gpio.h> #include <asm-generic/gpio.h> struct ich6_bank_platdata { diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index a2945f1aff..f93c840244 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -18,25 +18,6 @@ #ifndef __ASSEMBLY__ -#define DEFINE_PCI_DEVICE_TABLE(_table) \ - const struct pci_device_id _table[] - -struct pci_controller; - -void pci_setup_type1(struct pci_controller *hose); - -/* - * Simple PCI access routines - these work from either the early PCI hose - * or the 'real' one, created after U-Boot has memory available - */ -unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where); -unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where); -unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where); - -void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); -void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); -void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size); diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h index ddc08e11d5..0afcb4615e 100644 --- a/arch/x86/include/asm/pirq_routing.h +++ b/arch/x86/include/asm/pirq_routing.h @@ -72,12 +72,13 @@ static inline int get_irq_slot_count(struct irq_routing_table *rt) * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: link number which represents a PIRQ * @irq: the 8259 IRQ number * @return: true if the irq is already routed to 8259 for a given link, * false elsewise */ -bool pirq_check_irq_routed(int link, u8 irq); +bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq); /** * pirq_translate_link() - Translate a link value @@ -89,10 +90,11 @@ bool pirq_check_irq_routed(int link, u8 irq); * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: platform-specific link value * @return: link number which represents a PIRQ */ -int pirq_translate_link(int link); +int pirq_translate_link(struct udevice *dev, int link); /** * pirq_assign_irq() - Assign an IRQ to a PIRQ link @@ -103,10 +105,11 @@ int pirq_translate_link(int link); * Note: this function should be provided by the platform codes, as the * implementation of interrupt router may be different. * + * @dev: irq router's udevice * @link: link number which represents a PIRQ * @irq: IRQ to which the PIRQ is routed */ -void pirq_assign_irq(int link, u8 irq); +void pirq_assign_irq(struct udevice *dev, int link, u8 irq); /** * pirq_route_irqs() - Route PIRQs to 8259 PIC @@ -117,10 +120,11 @@ void pirq_assign_irq(int link, u8 irq); * The configuration source is taken from a struct irq_info table, the format * of which is defined in PIRQ routing table spec and PCI BIOS spec. * + * @dev: irq router's udevice * @irq: pointer to the base address of the struct irq_info * @num: number of entries in the struct irq_info */ -void pirq_route_irqs(struct irq_info *irq, int num); +void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num); /** * copy_pirq_routing_table() - Copy a PIRQ routing table diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 50bc69a659..4fc19365eb 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,9 +22,6 @@ obj-y += cmd_mtrr.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o -ifndef CONFIG_DM_PCI -obj-$(CONFIG_PCI) += pci_type1.o -endif obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index f441c84df5..783be691af 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -162,7 +162,7 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) * boot_params structure, and then jump to the kernel. We * assume that %cs is 0x10, 4GB flat, and read/execute, and * the data segments are 0x18, 4GB flat, and read/write. - * U-boot is setting them up that way for itself in + * U-Boot is setting them up that way for itself in * arch/i386/cpu/cpu.c. * * Note that we cannot currently boot a kernel while running as diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 29fa06098d..b05dcede0c 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -225,6 +225,10 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) struct hob_res_desc *res_desc; phys_addr_t phys_start; u32 top; +#ifdef CONFIG_FSP_BROKEN_HOB + struct hob_mem_alloc *res_mem; + phys_addr_t mem_base = 0; +#endif /* Get the HOB list for processing */ hdr = hob_list; @@ -242,9 +246,38 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) top += (u32)(res_desc->len); } } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Find out the lowest memory base address allocated by FSP + * for the boot service data + */ + if (hdr->type == HOB_TYPE_MEM_ALLOC) { + res_mem = (struct hob_mem_alloc *)hdr; + if (!mem_base) + mem_base = res_mem->mem_base; + if (res_mem->mem_base < mem_base) + mem_base = res_mem->mem_base; + } +#endif + hdr = get_next_hob(hdr); } +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Check whether the memory top address is below the FSP HOB list. + * If not, use the lowest memory base address allocated by FSP as + * the memory top address. This is to prevent U-Boot relocation + * overwrites the important boot service data which is used by FSP, + * otherwise the subsequent call to fsp_notify() will fail. + */ + if (top > (u32)hob_list) { + debug("Adjust memory top address due to a buggy FSP\n"); + top = (u32)mem_base; + } +#endif + return top; } diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c deleted file mode 100644 index a251adcacd..0000000000 --- a/arch/x86/lib/pci_type1.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Support for type PCI configuration cycles. - * based on pci_indirect.c - */ -#include <common.h> -#include <asm/io.h> -#include <pci.h> -#include <asm/pci.h> - -#define cfg_read(val, addr, op) (*val = op((int)(addr))) -#define cfg_write(val, addr, op) op((val), (int)(addr)) - -#define TYPE1_PCI_OP(rw, size, type, op, mask) \ -static int \ -type1_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), op); \ - return 0; \ -} - -TYPE1_PCI_OP(read, byte, u8 *, inb, 3) -TYPE1_PCI_OP(read, word, u16 *, inw, 2) -TYPE1_PCI_OP(read, dword, u32 *, inl, 0) - -TYPE1_PCI_OP(write, byte, u8, outb, 3) -TYPE1_PCI_OP(write, word, u16, outw, 2) -TYPE1_PCI_OP(write, dword, u32, outl, 0) - -void pci_setup_type1(struct pci_controller *hose) -{ - pci_set_ops(hose, - type1_read_config_byte, - type1_read_config_word, - type1_read_config_dword, - type1_write_config_byte, - type1_write_config_word, - type1_write_config_dword); - - hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; - hose->cfg_data = (unsigned char *)PCI_REG_DATA; -} diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index ba4116908c..3cc6adbbbb 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -14,7 +14,7 @@ static bool irq_already_routed[16]; -static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) +static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap) { int i, link; u8 irq = 0; @@ -33,7 +33,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) continue; for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { - if (pirq_check_irq_routed(link, irq)) { + if (pirq_check_irq_routed(dev, link, irq)) { irq_already_routed[irq] = true; break; } @@ -52,7 +52,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) return irq; } -void pirq_route_irqs(struct irq_info *irq, int num) +void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num) { unsigned char irq_slot[MAX_INTX_ENTRIES]; unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; @@ -80,11 +80,11 @@ void pirq_route_irqs(struct irq_info *irq, int num) } /* translate link value to link number */ - link = pirq_translate_link(link); + link = pirq_translate_link(dev, link); /* yet not routed */ if (!pirq[link]) { - irq = pirq_get_next_free_irq(pirq, bitmap); + irq = pirq_get_next_free_irq(dev, pirq, bitmap); pirq[link] = irq; } else { irq = pirq[link]; @@ -94,7 +94,7 @@ void pirq_route_irqs(struct irq_info *irq, int num) irq_slot[intx] = irq; /* Assign IRQ in the interrupt router */ - pirq_assign_irq(link, irq); + pirq_assign_irq(dev, link, irq); } /* Bus, device, slots IRQs for {A,B,C,D} */ diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index 64ab572619..4ca8106c06 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -14,7 +14,6 @@ #include <netdev.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pio.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_common.h> #include <asm/io.h> diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c index 6761b141fb..fbe8e3d22c 100644 --- a/board/atmel/at91rm9200ek/led.c +++ b/board/atmel/at91rm9200ek/led.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/at91_pio.h> #include <status_led.h> @@ -59,11 +59,9 @@ void red_led_off(void) void coloured_LED_init (void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; - /* Enable PIOB clock */ - writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOB); /* Disable peripherals on LEDs */ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per); diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 7f14af1011..98193bfdc6 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -11,7 +11,7 @@ #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <atmel_mci.h> @@ -70,11 +70,9 @@ static void at91sam9260ek_nand_hw_init(void) #ifdef CONFIG_MACB static void at91sam9260ek_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - /* Enable EMAC clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); /* * Disable pull-up on: @@ -122,12 +120,9 @@ int board_mmc_init(bd_t *bd) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); return 0; } diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 52504742cd..7b7cd2c426 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9261_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> @@ -35,7 +34,6 @@ static void at91sam9261ek_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ @@ -74,7 +72,7 @@ static void at91sam9261ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -161,8 +159,6 @@ void lcd_disable(void) static void at91sam9261ek_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ @@ -186,7 +182,7 @@ static void at91sam9261ek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - writel(AT91_PMC_HCK1, &pmc->scer); + at91_system_clk_enable(AT91_PMC_HCK1); /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */ #ifdef CONFIG_AT91SAM9261EK diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 18a68d8c59..485d7ea81f 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -8,17 +8,15 @@ #include <common.h> #include <asm/arch/at91sam9261.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> #include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> #include <asm/io.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable clock */ - writel(ATMEL_ID_PIOA, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 927adb0d38..af68e10390 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -11,7 +11,6 @@ #include <asm/arch/at91sam9263.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> @@ -39,7 +38,6 @@ static void at91sam9263ek_nand_hw_init(void) unsigned long csa; at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -68,8 +66,8 @@ static void at91sam9263ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -82,11 +80,9 @@ static void at91sam9263ek_nand_hw_init(void) #ifdef CONFIG_MACB static void at91sam9263ek_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: @@ -139,8 +135,6 @@ void lcd_disable(void) static void at91sam9263ek_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ @@ -164,7 +158,7 @@ static void at91sam9263ek_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); gd->fb_base = ATMEL_BASE_SRAM0; } @@ -226,12 +220,9 @@ int board_mmc_init(bd_t *bd) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOCDE), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); at91_seriald_hw_init(); return 0; diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index e317d99831..21d81def5e 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -9,16 +9,13 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/gpio.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91sam9263.h> +#include <asm/arch/clk.h> void coloured_LED_init(void) { - /* Enable clock */ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE, - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOB); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 0a51fcd9aa..4c6431266f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> @@ -36,7 +35,6 @@ void at91sam9m10g45ek_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ @@ -63,7 +61,7 @@ void at91sam9m10g45ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -130,13 +128,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable DDR2 clock */ - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); @@ -146,9 +142,7 @@ void mem_init(void) #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -158,11 +152,9 @@ static void at91sam9m10g45ek_usb_hw_init(void) #ifdef CONFIG_MACB static void at91sam9m10g45ek_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: @@ -222,8 +214,6 @@ void lcd_disable(void) static void at91sam9m10g45ek_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -255,7 +245,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index fe98723962..866052ee1c 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -9,15 +9,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9g45.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 0b0177df2b..d3555bbdf6 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -10,7 +10,6 @@ #include <asm/arch/at91sam9x5_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> @@ -208,9 +207,8 @@ void at91sam9n12ek_usb_hw_init(void) int board_early_init_f(void) { - /* Enable clocks for all PIOs */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOAB); + at91_periph_clk_enable(ATMEL_ID_PIOCD); at91_seriald_hw_init(); return 0; diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f995cef1e2..9ef2864bb1 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9rl_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> @@ -36,7 +35,6 @@ static void at91sam9rlek_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ @@ -64,7 +62,7 @@ static void at91sam9rlek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOD, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOD); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -106,8 +104,6 @@ void lcd_disable(void) } static void at91sam9rlek_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ @@ -130,7 +126,7 @@ static void at91sam9rlek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); } #ifdef CONFIG_LCD_INFO @@ -174,12 +170,10 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); return 0; } diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c index fede59cd32..d593aba6e4 100644 --- a/board/atmel/at91sam9rlek/led.c +++ b/board/atmel/at91sam9rlek/led.c @@ -8,16 +8,13 @@ #include <common.h> #include <asm/arch/at91sam9rl.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(ATMEL_ID_PIOD, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOD); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 833e38335a..c14df303b2 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -9,10 +9,9 @@ #include <asm/arch/at91sam9x5_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/gpio.h> #include <asm/arch/clk.h> +#include <asm/arch/gpio.h> #include <lcd.h> #include <atmel_hlcdc.h> #include <atmel_mci.h> @@ -39,7 +38,6 @@ static void at91sam9x5ek_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ @@ -72,7 +70,7 @@ static void at91sam9x5ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -141,8 +139,6 @@ void lcd_disable(void) static void at91sam9x5ek_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - if (has_lcdc()) { at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ @@ -176,7 +172,7 @@ static void at91sam9x5ek_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); } } diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 8ed01ddbea..10edf28a9b 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -15,7 +15,6 @@ #include <version.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/atmel_pio4.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 7acb8d0974..2b9da91b2d 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -10,7 +10,6 @@ #include <asm/io.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> @@ -184,14 +183,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable MPDDR clock */ + /* Enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); @@ -199,7 +197,6 @@ void mem_init(void) void at91_pmc_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; tmp = AT91_PMC_PLLAR_29 | @@ -208,7 +205,7 @@ void at91_pmc_init(void) AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); - writel(0x3 << 8, &pmc->pllicpr); + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 0d824fc0ba..e8ee612036 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -10,7 +10,6 @@ #include <asm/io.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> @@ -443,14 +442,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable MPDDR clock */ + /* Enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); @@ -458,7 +456,6 @@ void mem_init(void) void at91_pmc_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; tmp = AT91_PMC_PLLAR_29 | @@ -467,7 +464,7 @@ void at91_pmc_init(void) AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); - writel(0x3 << 8, &pmc->pllicpr); + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index e2f33a3e8b..f4eef9609f 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> @@ -383,14 +382,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable MPDDR clock */ + /* Enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); @@ -398,7 +396,6 @@ void mem_init(void) void at91_pmc_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; tmp = AT91_PMC_PLLAR_29 | @@ -407,7 +404,7 @@ void at91_pmc_init(void) AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); - writel(0x0 << 8, &pmc->pllicpr); + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); tmp = AT91_PMC_MCKR_H32MXDIV | AT91_PMC_MCKR_PLLADIV_2 | diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 1799059f87..aee621789e 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -8,7 +8,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> @@ -379,14 +378,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable MPDDR clock */ + /* Enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); @@ -394,7 +392,6 @@ void mem_init(void) void at91_pmc_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; tmp = AT91_PMC_PLLAR_29 | @@ -403,7 +400,7 @@ void at91_pmc_init(void) AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); - writel(0x0 << 8, &pmc->pllicpr); + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); tmp = AT91_PMC_MCKR_H32MXDIV | AT91_PMC_MCKR_PLLADIV_2 | diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile index 12154b625e..28fccc0dcb 100644 --- a/board/bct-brettl2/Makefile +++ b/board/bct-brettl2/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c index bf7cd62954..adb8605bb9 100644 --- a/board/bct-brettl2/bct-brettl2.c +++ b/board/bct-brettl2/bct-brettl2.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file for BCT brettl2 + * U-Boot - main board file for BCT brettl2 * * Copyright (c) 2010 BCT Electronic GmbH * diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile index 0f134f9ac3..7efe1bc20e 100644 --- a/board/bf506f-ezkit/Makefile +++ b/board/bf506f-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf506f-ezkit/bf506f-ezkit.c b/board/bf506f-ezkit/bf506f-ezkit.c index 638500d0c5..77e40ae15d 100644 --- a/board/bf506f-ezkit/bf506f-ezkit.c +++ b/board/bf506f-ezkit/bf506f-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2010 Analog Devices Inc. * diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile index 3a6abaa63b..e9e23ed41f 100644 --- a/board/bf518f-ezbrd/Makefile +++ b/board/bf518f-ezbrd/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index bf4a7db03d..a14e509719 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2009 Analog Devices Inc. * diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile index 8de71a1886..1be1d3117b 100644 --- a/board/bf525-ucr2/Makefile +++ b/board/bf525-ucr2/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf525-ucr2/bf525-ucr2.c b/board/bf525-ucr2/bf525-ucr2.c index 3e6df1fca8..36a725c83b 100644 --- a/board/bf525-ucr2/bf525-ucr2.c +++ b/board/bf525-ucr2/bf525-ucr2.c @@ -1,4 +1,4 @@ -/* U-boot - bf525-ucr2.c board specific routines +/* U-Boot - bf525-ucr2.c board specific routines * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index 34ac56323a..c4882c9346 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c index db1ee283f2..a506d1baff 100644 --- a/board/bf526-ezbrd/bf526-ezbrd.c +++ b/board/bf526-ezbrd/bf526-ezbrd.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile index 9d8ecf118d..c225f7201a 100644 --- a/board/bf527-ad7160-eval/Makefile +++ b/board/bf527-ad7160-eval/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c index ea405b639d..9180630ee7 100644 --- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2010 Analog Devices Inc. * diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile index cedd821b24..53ec9e7aa6 100644 --- a/board/bf527-ezkit/Makefile +++ b/board/bf527-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index b551d4ed7e..c4f58fa3b5 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile index 1ddb026cae..77acb423a5 100644 --- a/board/bf527-sdp/Makefile +++ b/board/bf527-sdp/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c index 504869d72a..0c6094b1e4 100644 --- a/board/bf527-sdp/bf527-sdp.c +++ b/board/bf527-sdp/bf527-sdp.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2010 Analog Devices Inc. * diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 6838cf0451..bf7a2c4477 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 81e390c93f..6879319a70 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index fa322039f7..7822a9dfd7 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -1,5 +1,5 @@ /* - * U-boot - flash-defines.h + * U-Boot - flash-defines.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index fd06b318f3..3180a76fa6 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -1,5 +1,5 @@ /* - * U-boot - flash.c Flash driver for PSD4256GV + * U-Boot - flash.c Flash driver for PSD4256GV * * Copyright (c) 2005-2007 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h index 56c644262a..925669644e 100644 --- a/board/bf533-ezkit/psd4256.h +++ b/board/bf533-ezkit/psd4256.h @@ -1,5 +1,5 @@ /* - * U-boot - psd4256.h + * U-Boot - psd4256.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 244f9e0497..041c98e19c 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 585f5f14d4..eb000a6a88 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile index 66d2f05f44..13ed8bfa22 100644 --- a/board/bf537-minotaur/Makefile +++ b/board/bf537-minotaur/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c index 9312216dc7..34750eca51 100644 --- a/board/bf537-minotaur/bf537-minotaur.c +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile index ffcdf1f0b0..f7af8cd5ae 100644 --- a/board/bf537-pnav/Makefile +++ b/board/bf537-pnav/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c index 6739fe1ed6..c3b06f09fc 100644 --- a/board/bf537-pnav/bf537-pnav.c +++ b/board/bf537-pnav/bf537-pnav.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile index cd0da272a6..1815fc5f8b 100644 --- a/board/bf537-srv1/Makefile +++ b/board/bf537-srv1/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c index b0ffe1aeea..fc22c07102 100644 --- a/board/bf537-srv1/bf537-srv1.c +++ b/board/bf537-srv1/bf537-srv1.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index 234119a52a..4008e3a2d4 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 85d41d0aaa..9b9daf4267 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile index 7c8cda05e9..eb1703e897 100644 --- a/board/bf538f-ezkit/Makefile +++ b/board/bf538f-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c index 49d30e75d0..2dd4c0c4d1 100644 --- a/board/bf538f-ezkit/bf538f-ezkit.c +++ b/board/bf538f-ezkit/bf538f-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008 Analog Devices Inc. * diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile index 6f4200bd46..e4d0caaac4 100644 --- a/board/bf548-ezkit/Makefile +++ b/board/bf548-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index cb9ee863a4..31d6eeec0c 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile index 48bec2884d..08e2fad61e 100644 --- a/board/bf561-acvilon/Makefile +++ b/board/bf561-acvilon/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index 23c7101c20..3d534d2486 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 8441838747..534c39ca89 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile index 3bfd0887bc..e4184ee2b6 100644 --- a/board/bf609-ezkit/Makefile +++ b/board/bf609-ezkit/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index 86da028bce..c993ca6d91 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2011 Analog Devices Inc. * diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c index e0c8d93fe7..7c117ea997 100644 --- a/board/bf609-ezkit/soft_switch.c +++ b/board/bf609-ezkit/soft_switch.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2011 Analog Devices Inc. * diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h index d147fe1378..75d64e279a 100644 --- a/board/bf609-ezkit/soft_switch.h +++ b/board/bf609-ezkit/soft_switch.h @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2011 Analog Devices Inc. * diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile index 38e5da7469..2ae79da071 100644 --- a/board/blackstamp/Makefile +++ b/board/blackstamp/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index 06d004a39e..d233b8a7fc 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -1,5 +1,5 @@ /* - * U-boot - blackstamp.c BlackStamp board specific routines + * U-Boot - blackstamp.c BlackStamp board specific routines * Most code stolen from boards/bf533-stamp/bf533-stamp.c * Edited to the BlackStamp by Ben Matthews for UR LLE * diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile index 4ff989a140..9a617757ea 100644 --- a/board/blackvme/Makefile +++ b/board/blackvme/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c index eccdaf3a48..d8932ed910 100644 --- a/board/blackvme/blackvme.c +++ b/board/blackvme/blackvme.c @@ -1,4 +1,4 @@ -/* U-boot - blackvme.c board specific routines +/* U-Boot - blackvme.c board specific routines * (c) Wojtek Skulski 2010 info@skutek.com * Board info: http://www.skutek.com * Copyright (c) 2005-2009 Analog Devices Inc. diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 95633b0d2e..2d1a89e102 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -15,7 +15,7 @@ #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/atmel_serial.h> #include <net.h> @@ -31,11 +31,9 @@ DECLARE_GLOBAL_DATA_PTR; static void macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); /* Disable pull-ups to prevent PHY going into test mode */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -108,12 +106,9 @@ static void nand_hw_init(void) int board_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable PIO clocks */ - writel((1 << ATMEL_ID_PIOA) | - (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* The mach-type is the same for both Snapper 9260 and 9G20 */ gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; diff --git a/board/br4/Makefile b/board/br4/Makefile index 68e24ab83f..c6c03aba09 100644 --- a/board/br4/Makefile +++ b/board/br4/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) Switchfin Org. <dpn@switchfin.org> # diff --git a/board/br4/br4.c b/board/br4/br4.c index bc034e38d4..6f3f170a32 100644 --- a/board/br4/br4.c +++ b/board/br4/br4.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) Switchfin Org. <dpn@switchfin.org> * diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index 266e9507ef..d627b240d0 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -12,7 +12,7 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_matrix.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm-generic/gpio.h> #include <asm/io.h> @@ -43,7 +43,6 @@ static void usb_a9263_nand_hw_init(void) unsigned long csa; at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0; at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX; - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -66,7 +65,8 @@ static void usb_a9263_nand_hw_init(void) AT91_SMC_MODE_DBW_8 | AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); @@ -81,10 +81,7 @@ static void usb_a9263_nand_hw_init(void) #ifdef CONFIG_MACB static void usb_a9263_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile index ff8ad43d51..1d662c6684 100644 --- a/board/cm-bf527/Makefile +++ b/board/cm-bf527/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index 3186c6717e..0c2138b082 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile index ec99638d0a..41e100da1b 100644 --- a/board/cm-bf533/Makefile +++ b/board/cm-bf533/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c index a863195057..02ef076735 100644 --- a/board/cm-bf533/cm-bf533.c +++ b/board/cm-bf533/cm-bf533.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile index be8056f4ba..317098cf2e 100644 --- a/board/cm-bf537e/Makefile +++ b/board/cm-bf537e/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index 57c72a2c06..7e4cfc2116 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile index 38dd3fbb21..835d5b73f0 100644 --- a/board/cm-bf537u/Makefile +++ b/board/cm-bf537u/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index f365cdbeb7..aad72a9783 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile index 98aca32b1f..1e11b8cdb1 100644 --- a/board/cm-bf548/Makefile +++ b/board/cm-bf548/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 90ce4c3eb7..d9d018bfbc 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile index c8764fb3ce..e0f0c34095 100644 --- a/board/cm-bf561/Makefile +++ b/board/cm-bf561/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c index 5741f64107..99b7eb2612 100644 --- a/board/cm-bf561/cm-bf561.c +++ b/board/cm-bf561/cm-bf561.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index cd992941aa..43931b0653 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -41,7 +41,7 @@ void pin_mux_mmc(void) } #endif -#ifdef CONFIG_LCD +#ifdef CONFIG_DM_VIDEO /* this is a weak define that we are overriding */ void pin_mux_display(void) { diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README index f2c959949c..0777c781c2 100644 --- a/board/congatec/cgtqmx6eval/README +++ b/board/congatec/cgtqmx6eval/README @@ -3,10 +3,10 @@ U-Boot for the Congatec QMX6 boards This file contains information for the port of U-Boot to the Congatec QMX6 boards. -1. Building U-boot +1. Building U-Boot ------------------ -- Build U-boot for Congatec QMX6 boards: +- Build U-Boot for Congatec QMX6 boards: $ make mrproper $ make cgtqmx6eval_defconfig @@ -17,7 +17,7 @@ This will generate the following binaries: - SPL - u-boot.img -2. Flashing U-boot in the SPI NOR +2. Flashing U-Boot in the SPI NOR --------------------------------- Copy SPL and u-boot.img to the exported TFTP directory of the @@ -41,7 +41,7 @@ host PC (/tftpboot , for example). => sf write 0x12000000 0x10000 0x70000 -Reboot the board and the new U-boot should come up. +Reboot the board and the new U-Boot should come up. 3. Booting from the SD card --------------------------- @@ -64,9 +64,9 @@ command: => bmode esdhc4 -And then the U-boot from the big slot will boot. +And then the U-Boot from the big slot will boot. -Note: If the "bmode" command is not available from your pre-installed U-boot, +Note: If the "bmode" command is not available from your pre-installed U-Boot, these instruction will produce the same effect: => mw.l 0x20d8040 0x3850 diff --git a/board/denx/ma5d4evk/Kconfig b/board/denx/ma5d4evk/Kconfig new file mode 100644 index 0000000000..b4ef106532 --- /dev/null +++ b/board/denx/ma5d4evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MA5D4EVK + +config SYS_BOARD + default "ma5d4evk" + +config SYS_VENDOR + default "denx" + +config SYS_CONFIG_NAME + default "ma5d4evk" + +endif diff --git a/board/denx/ma5d4evk/MAINTAINERS b/board/denx/ma5d4evk/MAINTAINERS new file mode 100644 index 0000000000..bb25a9ca94 --- /dev/null +++ b/board/denx/ma5d4evk/MAINTAINERS @@ -0,0 +1,6 @@ +DENX MA5D4EVK BOARD +M: Marek Vasut <marek.vasut@gmail.com> +S: Maintained +F: board/denx/ma5d4evk/ +F: include/configs/ma5d4evk.h +F: configs/ma5d4evk_defconfig diff --git a/board/denx/ma5d4evk/Makefile b/board/denx/ma5d4evk/Makefile new file mode 100644 index 0000000000..b12b5dcbd4 --- /dev/null +++ b/board/denx/ma5d4evk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Marek Vasut <marex@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ma5d4evk.o diff --git a/board/denx/ma5d4evk/ma5d4evk.c b/board/denx/ma5d4evk/ma5d4evk.c new file mode 100644 index 0000000000..ec0fa28f3e --- /dev/null +++ b/board/denx/ma5d4evk/ma5d4evk.c @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <atmel_hlcdc.h> +#include <atmel_mci.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void ma5d4evk_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_CMD_USB +static void ma5d4evk_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 0); + at91_set_pio_output(AT91_PIO_PORTE, 14, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 800, + .vl_row = 480, + .vl_clk = 33500000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 10, + .vl_left_margin = 89, + .vl_right_margin = 164, + .vl_vsync_len = 10, + .vl_upper_margin = 23, + .vl_lower_margin = 10, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void ma5d4evk_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_GENERIC_ATMEL_MCI +/* On-SoM eMMC */ +void ma5d4evk_mci0_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ + at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ + at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ + at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ + at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ + at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ + at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ + at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the internal pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI0); +} + +/* On-board MicroSD slot */ +void ma5d4evk_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the internal pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* Deal with WP pin on the microSD slot. */ + at91_set_pio_output(AT91_PIO_PORTE, 16, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* De-assert reset on On-SoM eMMC */ + at91_set_pio_output(AT91_PIO_PORTE, 15, 1); + at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); + + ret = atmel_mci_init((void *)ATMEL_BASE_MCI0); + if (ret) /* eMMC init failed, skip it. */ + at91_set_pio_output(AT91_PIO_PORTE, 15, 0); + + /* Enable the power supply to On-board MicroSD */ + at91_set_pio_output(AT91_PIO_PORTE, 17, 0); + + ret = atmel_mci_init((void *)ATMEL_BASE_MCI1); + if (ret) /* uSD init failed, power it down. */ + at91_set_pio_output(AT91_PIO_PORTE, 17, 1); + + return 0; +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void ma5d4evk_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +static void ma5d4evk_serial_hw_init(void) +{ + /* USART0 */ + at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ + at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ + at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ + at91_periph_clk_enable(ATMEL_ID_USART0); + + /* USART1 */ + at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ + at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ + at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ + at91_periph_clk_enable(ATMEL_ID_USART1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + /* Configure LEDs as OFF */ + at91_set_pio_output(AT91_PIO_PORTD, 28, 0); + at91_set_pio_output(AT91_PIO_PORTD, 29, 0); + at91_set_pio_output(AT91_PIO_PORTD, 30, 0); + + /* Reset CAN controllers */ + at91_set_pio_output(AT91_PIO_PORTB, 21, 0); + udelay(100); + at91_set_pio_output(AT91_PIO_PORTB, 21, 1); + at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); + + ma5d4evk_serial_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + ma5d4evk_spi0_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + ma5d4evk_mci0_hw_init(); + ma5d4evk_mci1_hw_init(); +#endif +#ifdef CONFIG_MACB + ma5d4evk_macb0_hw_init(); +#endif +#ifdef CONFIG_LCD + ma5d4evk_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + ma5d4evk_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + ma5d4evk_spi0_hw_init(); +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x2b0; + + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(87) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x0 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile index 865522fd6d..c0271da01b 100644 --- a/board/dnp5370/Makefile +++ b/board/dnp5370/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c index ae9ba84dc2..56e3b026af 100644 --- a/board/dnp5370/dnp5370.c +++ b/board/dnp5370/dnp5370.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * (C) Copyright 2010 3ality Digital Systems * diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 67d39844ac..2c8e978eb3 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -67,8 +67,8 @@ #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_spi.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/io.h> #include <asm/gpio.h> @@ -151,12 +151,10 @@ static void ethernut5_nand_hw_init(void) */ int board_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); /* Set adress of boot parameters. */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Initialize UARTs and power management. */ @@ -179,10 +177,9 @@ int board_eth_init(bd_t *bis) { const char *devname; unsigned short mode; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable on-chip EMAC clock. */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); + /* Need to reset PHY via power management. */ ethernut5_phy_reset(); /* Set peripheral pins. */ @@ -211,10 +208,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_GENERIC_ATMEL_MCI int board_mmc_init(bd_t *bd) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_periph_clk_enable(ATMEL_ID_MCI); - /* Enable MCI clock. */ - writel(1 << ATMEL_ID_MCI, &pmc->pcer); /* Initialize MCI hardware. */ at91_mci_hw_init(); /* Register the device. */ @@ -229,6 +224,7 @@ int board_mmc_getcd(struct mmc *mmc) #ifdef CONFIG_ATMEL_SPI /* + * Note, that u-boot uses different code for SPI bus access. While * memory routines use automatic chip select control, the serial * flash support requires 'manual' GPIO control. Thus, we switch diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index f8c746824a..ad7a8cfbb8 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -221,7 +221,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * ** RiOTboard : * mmc0 SDCard slot (bottom) * mmc1 uSDCard slot (top) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index b7f9f90cde..fe781dcc92 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -87,9 +87,8 @@ static void meesc_nand_hw_init(void) #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); + at91_macb_hw_init(); } #endif @@ -244,12 +243,10 @@ int misc_init_r(void) int board_early_init_f(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* enable all clocks */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); + at91_periph_clk_enable(ATMEL_ID_UHP); at91_seriald_hw_init(); diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 4b2303e849..164ec0a47b 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -269,7 +269,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); /* - * XFI does not need a PHY to work, but to make U-boot + * XFI does not need a PHY to work, but to make U-Boot * happy, assign a fake PHY address for a XFI port. */ fm_info_set_phy_address(FM1_10GEC1, 0); diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README index 4902b98ba1..c8405970c1 100644 --- a/board/freescale/bsc9131rdb/README +++ b/board/freescale/bsc9131rdb/README @@ -86,9 +86,9 @@ Default Boot Method -------------------- NAND boot -Building U-boot +Building U-Boot -------------- -To build the u-boot for BSC9131RDB: +To build the U-Boot for BSC9131RDB: 1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default) make BSC9131RDB_NAND 2. NAND Flash with sysclk 100MHz(J16 on RDB open) @@ -123,7 +123,7 @@ DDR Memory map Flashing Images --------------- -To place a new u-boot image in the NAND flash and then boot +To place a new U-Boot image in the NAND flash and then boot with that new image temporarily, use this: tftp 1000000 u-boot-nand.bin nand erase 0 100000 diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README index f8377c9aa4..ede95d41da 100644 --- a/board/freescale/bsc9132qds/README +++ b/board/freescale/bsc9132qds/README @@ -87,9 +87,9 @@ Default Boot Method -------------------- NOR boot -Building U-boot +Building U-Boot -------------- -To build the u-boot for BSC9132QDS: +To build the U-Boot for BSC9132QDS: 1. NOR Flash make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK @@ -122,7 +122,7 @@ Memory map Flashing Images --------------- -To place a new u-boot image in the NAND flash and then boot +To place a new U-Boot image in the NAND flash and then boot with that new image temporarily, use this: tftp 1000000 u-boot-nand.bin nand erase 0 100000 diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README index 3bc396b35a..2e249cbb3a 100644 --- a/board/freescale/c29xpcie/README +++ b/board/freescale/c29xpcie/README @@ -53,7 +53,7 @@ Settings of DIP-switch SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash Note: 1 stands for 'off', 0 stands for 'on' -Build and program u-boot to NOR flash +Build and program U-Boot to NOR flash ================================== 1. Build u-boot.bin image example: export ARCH=powerpc @@ -86,7 +86,7 @@ There are four banks in C29XPCIE board, example to change bank booting: - bank 4 on the flash 0x3000000~0x3ffffff or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. -Build and program u-boot to SPI flash +Build and program U-Boot to SPI flash ================================== 1. Build u-boot-spi.bin image make C29xPCIE_SPIFLASH_config; make diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README index 7e53f1f1e4..646cc02693 100644 --- a/board/freescale/ls2080a/README +++ b/board/freescale/ls2080a/README @@ -12,7 +12,7 @@ Memory map from core's view 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 -Other addresses are either reserved, or not used directly by u-boot. +Other addresses are either reserved, or not used directly by U-Boot. This list should be updated when more addresses are used. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 375e97c9b0..6ddad92f2c 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -103,7 +103,7 @@ Memory map from core's view 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 -Other addresses are either reserved, or not used directly by u-boot. +Other addresses are either reserved, or not used directly by U-Boot. This list should be updated when more addresses are used. IFC region map from core's view diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index ebc9d47468..42ff74317e 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -716,7 +716,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i) switch (serdes1_prtcl) { case 0x2A: /* - * XFI does not need a PHY to work, but to avoid U-boot use + * XFI does not need a PHY to work, but to avoid U-Boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 7fc2569648..6708ca9cc7 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -87,7 +87,7 @@ Memory map from core's view 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 -Other addresses are either reserved, or not used directly by u-boot. +Other addresses are either reserved, or not used directly by U-Boot. This list should be updated when more addresses are used. IFC region map from core's view diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README index 3178d49d0a..92a83849ac 100644 --- a/board/freescale/m52277evb/README +++ b/board/freescale/m52277evb/README @@ -49,7 +49,7 @@ Changed files: - include/asm-m68k/timer.h Timer structure and definition - include/asm-m68k/types.h Data types definition - include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h u-boot structure +- include/asm-m68k/u-boot.h U-Boot structure - include/configs/M52277EVB.h Board specific configuration file @@ -77,7 +77,7 @@ CONFIG_MCFRTC -- define to use common CF RTC driver CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in u-boot +CONFIG_CMD_DATE -- enable to use date feature in U-Boot CONFIG_MCFTMR -- define to use DMA timer CONFIG_MCFPIT -- define to use PIT timer @@ -102,7 +102,7 @@ CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base -CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot, +CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot, update will be provided at later time 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL @@ -113,7 +113,7 @@ update will be provided at later time SRAM: 0x80000000-0x8FFFFFFF (256MB) IP: 0xF0000000-0xFFFFFFFF (256MB) -2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and linux kernel, you can customize it based on your system requirements: Flash0: 0x00000000-0x00FFFFFF (16MB) diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README index f51609f3e0..2ed5c768d5 100644 --- a/board/freescale/m5253evbe/README +++ b/board/freescale/m5253evbe/README @@ -13,7 +13,7 @@ Created 06/05/2007 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== -2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and +2.1. For the initial bringup, we adopted a consistent memory scheme between U-Boot and linux kernel, you can customize it based on your system requirements: SDR: 0x00000000-0x00ffffff SRAM0: 0x20010000-0x20017fff diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 84fc1ecfb1..224e79c46a 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -47,7 +47,7 @@ Changed files: - include/asm-m68k/timer.h Timer structure and definition - include/asm-m68k/types.h Data types definition - include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h u-boot structure +- include/asm-m68k/u-boot.h U-Boot structure - include/configs/M53017EVB.h Board specific configuration file @@ -75,7 +75,7 @@ CONFIG_MCFRTC -- define to use common CF RTC driver CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in u-boot +CONFIG_CMD_DATE -- enable to use date feature in U-Boot CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_MII -- enable to use MII driver @@ -118,7 +118,7 @@ CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base SRAM: 0x80000000-0x8FFFFFFF (256MB) IP: 0xFC000000-0xFFFFFFFF (256MB) -2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and linux kernel, you can customize it based on your system requirements: Flash0: 0x00000000-0x00FFFFFF (16MB) DDR: 0x40000000-0x4FFFFFFF (256MB) diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index 52eac7b2ff..582e0c3d9e 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -46,7 +46,7 @@ Changed files: - include/asm-m68k/timer.h Timer structure and definition - include/asm-m68k/types.h Data types definition - include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h u-boot structure +- include/asm-m68k/u-boot.h U-Boot structure - include/configs/M5373EVB.h Board specific configuration file @@ -74,7 +74,7 @@ CONFIG_MCFRTC -- define to use common CF RTC driver CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in u-boot +CONFIG_CMD_DATE -- enable to use date feature in U-Boot CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_MII -- enable to use MII driver @@ -117,7 +117,7 @@ CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base SRAM: 0x80000000-0x8FFFFFFF (256MB) IP: 0xF0000000-0xFFFFFFFF (256MB) -2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and linux kernel, you can customize it based on your system requirements: Flash0: 0x00000000-0x00FFFFFF (16MB) diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README index c70c4c5c25..c563ad99a7 100644 --- a/board/freescale/m54455evb/README +++ b/board/freescale/m54455evb/README @@ -48,7 +48,7 @@ Changed files: - include/asm-m68k/timer.h Timer structure and definition - include/asm-m68k/types.h Data types definition - include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h u-boot structure +- include/asm-m68k/u-boot.h U-Boot structure - include/configs/M54455EVB.h Board specific configuration file @@ -78,7 +78,7 @@ CONFIG_MCFRTC -- define to use common CF RTC driver CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in u-boot +CONFIG_CMD_DATE -- enable to use date feature in U-Boot CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_MII -- enable to use MII driver @@ -91,7 +91,7 @@ CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop -CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot +CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot CONFIG_ISO_PARTITION -- enable ISO read/write CONFIG_DOS_PARTITION -- enable DOS read/write @@ -136,7 +136,7 @@ CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc CONFIG_SYS_MBAR -- define MBAR offset -CONFIG_SYS_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel +CONFIG_SYS_ATMEL_BOOT -- To determine the U-Boot is booted from Atmel or Intel CONFIG_MONITOR_IS_IN_RAM -- Not support @@ -163,7 +163,7 @@ CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1 FlexBus: 0xC0000000-0xDFFFFFFF (512MB) IP: 0xF0000000-0xFFFFFFFF (256MB) -2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and linux kernel, you can customize it based on your system requirements: Atmel boot: Flash0: 0x00000000-0x0007FFFF (512KB) diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README index ce497c0d2a..30c5dedafe 100644 --- a/board/freescale/m547xevb/README +++ b/board/freescale/m547xevb/README @@ -54,7 +54,7 @@ Changed files: - include/asm-m68k/timer.h Timer structure and definition - include/asm-m68k/types.h Data types definition - include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h u-boot structure +- include/asm-m68k/u-boot.h U-Boot structure - include/configs/M5475EVB.h Board specific configuration file @@ -88,7 +88,7 @@ CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop -CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot +CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot CONFIG_CMD_USB -- enable USB commands CONFIG_USB_OHCI_NEW -- enable USB OHCI driver diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README index be7ef32b45..697cee4c42 100644 --- a/board/freescale/mpc8313erdb/README +++ b/board/freescale/mpc8313erdb/README @@ -70,7 +70,7 @@ Freescale MPC8313ERDB Board 5. Downloading and Flashing Images -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot NOR flash: @@ -81,7 +81,7 @@ Freescale MPC8313ERDB Board first, to make sure that the TFTP load will succeed before it goes ahead and wipes out your current firmware. And of course, have an alternate means of programming the flash available - if the new u-boot doesn't boot. + if the new U-Boot doesn't boot. NAND flash: diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README index b32132d053..8ad6d810c7 100644 --- a/board/freescale/mpc8315erdb/README +++ b/board/freescale/mpc8315erdb/README @@ -63,7 +63,7 @@ Freescale MPC8315ERDB Board 5. Downloading and Flashing Images -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot NOR flash: diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README index 6f89829373..9a46da0781 100644 --- a/board/freescale/mpc8323erdb/README +++ b/board/freescale/mpc8323erdb/README @@ -22,10 +22,10 @@ Freescale MPC8323ERDB Board 3. Downloading and Flashing Images -3.1 Reflash U-boot Image using U-boot +3.1 Reflash U-Boot Image using U-Boot N.b, have an alternate means of programming - the flash available if the new u-boot doesn't boot. + the flash available if the new U-Boot doesn't boot. First try a: @@ -44,7 +44,7 @@ Freescale MPC8323ERDB Board erase fe000000 +$filesize cp.b $loadaddr fe000000 $filesize - To keep your old u-boot's environment variables, do a: + To keep your old U-Boot's environment variables, do a: saveenv diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README index 4142aa9c8d..d141cd33e7 100644 --- a/board/freescale/mpc832xemds/README +++ b/board/freescale/mpc832xemds/README @@ -97,7 +97,7 @@ Freescale MPC832XEMDS Board make MPC832XEMDS_config make - MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: + MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI: 1)Make sure the DIP SW support PCI mode as described in Section 1.1. @@ -113,7 +113,7 @@ Freescale MPC832XEMDS Board tftp 10000 u-boot.bin -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot tftp 20000 u-boot.bin protect off fe000000 fe0fffff diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README index faf21c9ffb..dbb15171e6 100644 --- a/board/freescale/mpc837xemds/README +++ b/board/freescale/mpc837xemds/README @@ -90,7 +90,7 @@ Freescale MPC837xEMDS Board tftp 40000 u-boot.bin -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot tftp 40000 u-boot.bin protect off fe000000 fe1fffff diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README index cfb6efa27e..12df2f2e75 100644 --- a/board/freescale/mpc837xerdb/README +++ b/board/freescale/mpc837xerdb/README @@ -84,7 +84,7 @@ Freescale MPC837xE-RDB Board tftp $loadaddr u-boot.bin -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot tftp $loadaddr u-boot.bin protect off fe000000 fe0fffff diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README index 3d12a964cd..86c3ccde79 100644 --- a/board/freescale/mpc8569mds/README +++ b/board/freescale/mpc8569mds/README @@ -3,7 +3,7 @@ Overview MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform I/O Board). The mpc8569 PowerTM processor is mounted on PB board. -Building U-boot +Building U-Boot ----------- make MPC8569MDS_config make @@ -22,10 +22,10 @@ Memory Map 0xfe00_0000 0xffff_ffff Flash 32MB -Flashing u-boot Images +Flashing U-Boot Images --------------- -Use the following commands to program u-boot image into flash: +Use the following commands to program U-Boot image into flash: => tftp 1000000 u-boot.bin => protect off all diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README index 57fd2ad616..f1ffdd1730 100644 --- a/board/freescale/mpc8572ds/README +++ b/board/freescale/mpc8572ds/README @@ -3,7 +3,7 @@ Overview MPC8572DS is a high-performance computing, evaluation and development platform supporting the mpc8572 PowerTM processor. -Building U-boot +Building U-Boot ----------- make MPC8572DS_config make @@ -22,14 +22,14 @@ Memory Map 0xe800_0000 - 0xebff_ffff Alternate bank 64MB 0xec00_0000 - 0xefff_ffff Boot bank 64MB -0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB +0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB Flashing Images --------------- -To place a new u-boot image in the alternate flash bank and then reset with that +To place a new U-Boot image in the alternate flash bank and then reset with that new image temporarily, use this: tftp 1000000 u-boot.bin @@ -135,7 +135,7 @@ Implementing AMP(Asymmetric MultiProcessing) 5. Bring up two cores separately: - a. Power on the board, under u-boot prompt: + a. Power on the board, under U-Boot prompt: => setenv <serverip> => setenv <ipaddr> => setenv bootargs root=/dev/ram rw console=ttyS0,115200 @@ -154,7 +154,7 @@ Implementing AMP(Asymmetric MultiProcessing) => fdt chosen $initrd_start $initrd_end => bootm prep => cpu 1 release $bootm_low - $fdtaddr - - c. Bring up core0's kernel(on the same u-boot console): + c. Bring up core0's kernel(on the same U-Boot console): => setenv bootm_low 0 => setenv bootm_size 0x20000000 => tftp 1000000 8572/uImage.core0 @@ -162,5 +162,5 @@ Implementing AMP(Asymmetric MultiProcessing) => tftp c00000 8572/mpc8572ds_core0.dtb => bootm 1000000 2000000 c00000 -Please note only core0 will run u-boot, core1 starts kernel directly after +Please note only core0 will run U-Boot, core1 starts kernel directly after "cpu release" command is issued. diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README index 31a9af3fee..066e625d48 100644 --- a/board/freescale/mpc8610hpcd/README +++ b/board/freescale/mpc8610hpcd/README @@ -27,7 +27,7 @@ To Flash U-Boot into the booting bank: cp.b 1000000 fff00000 $filesize -To Flash U-boot into the alternate bank +To Flash U-Boot into the alternate bank tftp 1000000 u-boot.bin erase fbf00000 +$filesize diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README index d8fe0a4a13..77909a8383 100644 --- a/board/freescale/mpc8641hpcn/README +++ b/board/freescale/mpc8641hpcn/README @@ -80,7 +80,7 @@ Switches: 3. Flash U-Boot --------------- The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves. -It is possible to use either half to boot using u-boot. Switch 5 bit 2 +It is possible to use either half to boot using U-Boot. Switch 5 bit 2 is used for this purpose. 0xEF800000 to 0xEFBFFFFF - 4MB @@ -102,7 +102,7 @@ To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF): or use tftpflash command: run tftpflash -To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): +To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): tftp 1000000 u-boot.bin erase efb00000 +$filesize @@ -113,7 +113,7 @@ To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): ------------- NOTE: RIO and PCI are mutually exclusive, so they share an address -For 32-bit u-boot, devices are mapped so that the virtual address == +For 32-bit U-Boot, devices are mapped so that the virtual address == the physical address, and the map looks liks this: Memory Range Device Size @@ -130,7 +130,7 @@ the physical address, and the map looks liks this: 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K 0xef80_0000 0xefff_ffff Flash 8M -For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit. +For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit. However, the physical map is altered to reside in 36-bit space, as follows. Addresses are no longer mapped with VA == PA. All accesses from software use the VA; the PA is only used for setting up windows diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index f9d6324114..a248fb21df 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -1,7 +1,7 @@ FREESCALE MX28EVK ================== -Supported hardware: MX28EVK rev C and D are supported in U-boot. +Supported hardware: MX28EVK rev C and D are supported in U-Boot. Files of the MX28EVK port -------------------------- diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README index 7232b53357..6f6841f099 100644 --- a/board/freescale/mx35pdk/README +++ b/board/freescale/mx35pdk/README @@ -71,7 +71,7 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf Flashing U-Boot -------------------------------- -U-boot should be stored on the NOR flash. +U-Boot should be stored on the NOR flash. The boot storage can be select using the switches on the personality board (SW1-SW2) and on the DEBUG board (SW4-SW10). @@ -96,7 +96,7 @@ Creating 6 MTD partitions on "mxc_nor_flash.0": To erase the whole partition: $ flash_eraseall /dev/mtd0 -Writing u-boot: +Writing U-Boot: dd if=u-boot.bin of=/dev/mtd0 To boot from NOR, you have to select the switches as follows: diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 46b4f3f68e..e9d9664a82 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -268,7 +268,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 SD2 * mmc1 SD3 * mmc2 eMMC diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index df205eac6f..4f816c4c02 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -202,7 +202,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 * mmc2 USDHC3 diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index c9631d2578..a240982975 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -339,7 +339,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC3 * mmc1 USDHC4 */ diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 97e9ed7df6..41319c66d2 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -348,7 +348,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC2 * mmc1 USDHC3 * mmc2 USDHC4 diff --git a/board/freescale/mx6ul_14x14_evk/README b/board/freescale/mx6ul_14x14_evk/README index d48c7ba20f..1edccf688c 100644 --- a/board/freescale/mx6ul_14x14_evk/README +++ b/board/freescale/mx6ul_14x14_evk/README @@ -1,7 +1,7 @@ -How to use U-boot on Freescale MX6UL 14x14 EVK +How to use U-Boot on Freescale MX6UL 14x14 EVK ----------------------------------------------- -- Build U-boot for MX6UL 14x14 EVK: +- Build U-Boot for MX6UL 14x14 EVK: $ make mrproper $ make mx6ul_14x14_evk_defconfig @@ -28,5 +28,5 @@ switch label numbers reference). - Connect the USB cable between the EVK and the PC for the console. (The USB console connector is the one close the push buttons) -- Insert the micro SD card in the board, power it up and U-boot messages should +- Insert the micro SD card in the board, power it up and U-Boot messages should come up. diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index b9b35736cf..98d5675ff1 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -394,7 +394,7 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 782acc6713..4d0b195798 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -375,7 +375,7 @@ int board_mmc_init(bd_t *bis) int i, ret; /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc2 USDHC3 (eMMC) */ diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA index cde246dde2..105942f7a5 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -95,7 +95,7 @@ is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM instead of to CAN/UART1. -Build and burn u-boot to NOR flash +Build and burn U-Boot to NOR flash ================================== 1. Build u-boot.bin image export ARCH=powerpc @@ -131,7 +131,7 @@ CPLD NOR bank selection register address 0xFFB00009 Bit[0]: 1 - boot from lower 4 sectors -Build and burn u-boot to NAND flash +Build and burn U-Boot to NAND flash =================================== 1. Build u-boot.bin image export ARCH=powerpc @@ -146,7 +146,7 @@ Build and burn u-boot to NAND flash 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. -Build and burn u-boot to SPI flash +Build and burn U-Boot to SPI flash ================================== 1. Build u-boot-spi.bin image make P1010RDB_SPIFLASH_config; make diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB index c5d1419445..dc82f0df09 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PB +++ b/board/freescale/p1010rdb/README.P1010RDB-PB @@ -112,14 +112,14 @@ To enable FlexCAN: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system - run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. + run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system - run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. + run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README index bb0f2805dc..c00e3bafbe 100644 --- a/board/freescale/t102xqds/README +++ b/board/freescale/t102xqds/README @@ -172,16 +172,16 @@ Start Address End Address Description Size 128MB NOR Flash memory Map -------------------------- Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB @@ -221,11 +221,11 @@ Software configurations and board settings Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: - via software: run command 'qixis_reset altbank' in u-boot. + via software: run command 'qixis_reset altbank' in U-Boot. via DIP-switch: set SW6[1:4] = '0100' To change boot source to vbank0: - via software: run command 'qixis_reset' in u-boot. + via software: run command 'qixis_reset' in U-Boot. via DIP-Switch: set SW6[1:4] = '0000' 2. NAND Boot: @@ -273,8 +273,8 @@ e) For SDXC: set adaptor=sdxc in hwconfig ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. SPL further initializes DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -294,14 +294,14 @@ Run time view of SPL framework ------------------------------------------------- |STACK | 0xFFFD8000 (22KB) | ------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | +|U-Boot SPL | 0xFFFD8000 (160KB) | ------------------------------------------------- NAND Flash memory Map on T1024QDS ------------------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB -0x100000 0x15FFFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot 1MB +0x100000 0x15FFFF U-Boot env 8KB 0x160000 0x17FFFF FMAN Ucode 128KB 0x180000 0x19FFFF QE Firmware 128KB @@ -309,8 +309,8 @@ Start End Definition Size SD Card memory Map on T1024QDS ---------------------------------------------------- Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB 0x820 0256 FMAN Ucode 128KB 0x920 0256 QE Firmware 128KB @@ -318,8 +318,8 @@ Block #blocks Definition Size SPI Flash memory Map on T1024QDS ---------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x100000 0x101FFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB 0x110000 0x12FFFF FMAN Ucode 128KB 0x130000 0x14FFFF QE Firmware 128KB diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c index ca54e2a4f0..19543c0738 100644 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -310,7 +310,7 @@ int board_eth_init(bd_t *bis) case 0x95: case 0x99: /* - * XFI does not need a PHY to work, but to avoid U-boot use + * XFI does not need a PHY to work, but to avoid U-Boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 7d3794a6d6..a0af25a432 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -145,8 +145,8 @@ Start Address End Address Description Size 128MB NOR Flash Memory Layout ----------------------------- Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB @@ -158,8 +158,8 @@ Start Address End Address Definition Max size 0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB 0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB @@ -198,18 +198,18 @@ Software configurations and board settings Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: on T1024RDB: - via software: run command 'cpld reset altbank' in u-boot. + via software: run command 'cpld reset altbank' in U-Boot. via DIP-switch: set SW3[5:7] = '100' on T1023RDB: - via software: run command 'switch bank4' in u-boot. + via software: run command 'switch bank4' in U-Boot. via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: on T1024RDB: - via software: run command 'cpld reset' in u-boot. + via software: run command 'cpld reset' in U-Boot. via DIP-Switch: set SW3[5:7] = '000' on T1023RDB: - via software: run command 'switch bank0' in u-boot. + via software: run command 'switch bank0' in U-Boot. via DIP-switch: set SW3[5:7] = '000' 2. NAND Boot: @@ -255,8 +255,8 @@ Software configurations and board settings ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. SPL further initializes DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -276,14 +276,14 @@ Run time view of SPL framework ------------------------------------------------- |STACK | 0xFFFD8000 (22KB) | ------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | +|U-Boot SPL | 0xFFFD8000 (160KB) | ------------------------------------------------- NAND Flash memory Map on T1024RDB ------------------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB(2 block) -0x100000 0x17FFFF u-boot env 512KB(1 block) +0x000000 0x0FFFFF U-Boot 1MB(2 block) +0x100000 0x17FFFF U-Boot env 512KB(1 block) 0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) 0x200000 0x27FFFF QE Firmware 512KB(1 block) @@ -291,16 +291,16 @@ Start End Definition Size NAND Flash memory Map on T1023RDB ---------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB -0x100000 0x15FFFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot 1MB +0x100000 0x15FFFF U-Boot env 8KB 0x160000 0x17FFFF FMAN Ucode 128KB SD Card memory Map on T102xRDB ---------------------------------------------------- Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB 0x820 0256 FMAN Ucode 128KB 0x920 0256 QE Firmware 128KB(only T1024RDB) @@ -308,8 +308,8 @@ Block #blocks Definition Size 64MB SPI Flash memory Map on T102xRDB ---------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x100000 0x101FFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB 0x110000 0x12FFFF FMAN Ucode 128KB 0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB) 0x300000 0x3FFFFF device tree 128KB diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index 8160ca0bc0..6c5ffc07f8 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -118,15 +118,15 @@ Start Address End Address Description Size NOR Flash memory Map on T1040QDS -------------------------------- Start End Definition Size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB @@ -138,7 +138,7 @@ Various Software configurations/environment variables/commands -------------------------------------------------------------- The below commands apply to T1040QDS -1. U-boot environment variable hwconfig +1. U-Boot environment variable hwconfig The default hwconfig is: hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: dr_mode=host,phy_type=utmi diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index b9d2212000..98b3f63db2 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -186,15 +186,15 @@ Start Address End Address Description Size NOR Flash memory Map --------------------- Start End Definition Size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB @@ -206,7 +206,7 @@ Various Software configurations/environment variables/commands -------------------------------------------------------------- The below commands apply to the board -1. U-boot environment variable hwconfig +1. U-Boot environment variable hwconfig The default hwconfig is: hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: dr_mode=host,phy_type=utmi @@ -228,8 +228,8 @@ NAND boot with 2 Stage boot loader ---------------------------------- PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. SPL further initialise DDR using SPD and environment variables and copy -u-boot(768 KB) from flash to DDR. -Finally SPL transer control to u-boot for futher booting. +U-Boot(768 KB) from flash to DDR. +Finally SPL transer control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -250,30 +250,30 @@ SPL has following features: ----------------------------------------------- STACK | 0xFFFD8000 (22KB) | ----------------------------------------------- - U-boot SPL | 0xFFFD8000 (160KB) | + U-Boot SPL | 0xFFFD8000 (160KB) | ----------------------------------------------- NAND Flash memory Map on T104xRDB ------------------------------------------ Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB -0x180000 0x19FFFF u-boot env 128KB +0x000000 0x0FFFFF U-Boot 1MB +0x180000 0x19FFFF U-Boot env 128KB 0x280000 0x29FFFF FMAN Ucode 128KB 0x380000 0x39FFFF QE Firmware 128KB SD Card memory Map on T104xRDB ------------------------------------------ Block #blocks Definition Size -0x008 2048 u-boot 1MB -0x800 0024 u-boot env 8KB +0x008 2048 U-Boot 1MB +0x800 0024 U-Boot env 8KB 0x820 0256 FMAN Ucode 128KB 0x920 0256 QE Firmware 128KB SPI Flash memory Map on T104xRDB ------------------------------------------ Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB -0x100000 0x101FFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot 1MB +0x100000 0x101FFF U-Boot env 8KB 0x110000 0x12FFFF FMAN Ucode 128KB 0x130000 0x14FFFF QE Firmware 128KB diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 83060c10f3..2a2a0e514c 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -92,7 +92,7 @@ XFI: 10GBASE-KR scenario. So, for XFI usage, there are two scenarios, one will use fiber cable, another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-boot + introduced to indicate a XFI port will use copper cable, and U-Boot will fixup the dtb accordingly. It's used as: fsl_10gkr_copper:<10g_mac_name> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they @@ -108,7 +108,7 @@ XFI: - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration - Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper + Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper initialization. Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a @@ -142,15 +142,15 @@ Start Address End Address Description Size 128M NOR Flash memory Map ------------------------- Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB @@ -172,11 +172,11 @@ Software configurations and board settings Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: - by software: run command 'qixis_reset altbank' in u-boot. + by software: run command 'qixis_reset altbank' in U-Boot. by DIP-switch: set SW6[1:4] = '0100' To change boot source to vbank0: - by software: run command 'qixis_reset' in u-boot. + by software: run command 'qixis_reset' in U-Boot. by DIP-Switch: set SW6[1:4] = '0000' 2. NAND Boot: @@ -216,8 +216,8 @@ Software configurations and board settings ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. SPL further initializes DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -237,30 +237,30 @@ Run time view of SPL framework ------------------------------------------------- |STACK | 0xFFFD8000 (22KB) | ------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | +|U-Boot SPL | 0xFFFD8000 (160KB) | ------------------------------------------------- NAND Flash memory Map on T2080QDS -------------------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB (2 blocks) -0x100000 0x17FFFF u-boot env 512KB (1 block) +0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) +0x100000 0x17FFFF U-Boot env 512KB (1 block) 0x180000 0x1FFFFF FMAN ucode 512KB (1 block) Micro SD Card memory Map on T2080QDS ---------------------------------------------------- Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB 0x820 0128 FMAN ucode 64KB SPI Flash memory Map on T2080QDS ---------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x100000 0x101FFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB 0x110000 0x11FFFF FMAN ucode 64KB diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index f08cff2654..e92b5d3a05 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -600,7 +600,7 @@ int board_eth_init(bd_t *bis) case 0x66: case 0x67: /* - * XFI does not need a PHY to work, but to avoid U-boot use + * XFI does not need a PHY to work, but to avoid U-Boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 24484cd0ff..42b2b92396 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -107,16 +107,16 @@ Start Address End Address Description Size 128M NOR Flash memory Map ------------------------- Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB @@ -155,11 +155,11 @@ Software configurations and board settings Switching between default bank and alternate bank on NOR flash To change boot source to vbank4: - via software: run command 'cpld reset altbank' in u-boot. + via software: run command 'cpld reset altbank' in U-Boot. via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: - via software: run command 'cpld reset' in u-boot. + via software: run command 'cpld reset' in U-Boot. via DIP-Switch: set SW3[5:7] = '000' 2. NAND Boot: @@ -197,8 +197,8 @@ Software configurations and board settings ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. SPL further initializes DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -218,14 +218,14 @@ Run time view of SPL framework ------------------------------------------------- |STACK | 0xFFFD8000 (22KB) | ------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | +|U-Boot SPL | 0xFFFD8000 (160KB) | ------------------------------------------------- NAND Flash memory Map on T2080RDB -------------------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB (2 blocks) -0x100000 0x17FFFF u-boot env 512KB (1 block) +0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) +0x100000 0x17FFFF U-Boot env 512KB (1 block) 0x180000 0x1FFFFF FMAN ucode 512KB (1 block) 0x200000 0x27FFFF CS4315 ucode 512KB (1 block) @@ -233,8 +233,8 @@ Start End Definition Size Micro SD Card memory Map on T2080RDB ---------------------------------------------------- Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB 0x820 0128 FMAN ucode 64KB 0x8a0 0512 CS4315 ucode 256KB @@ -242,8 +242,8 @@ Block #blocks Definition Size SPI Flash memory Map on T2080RDB ---------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x100000 0x101FFF u-boot env 8KB +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB 0x110000 0x11FFFF FMAN ucode 64KB 0x120000 0x15FFFF CS4315 ucode 256KB diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README index 3962fee7f2..bf238146db 100644 --- a/board/freescale/t4qds/README +++ b/board/freescale/t4qds/README @@ -86,7 +86,7 @@ Board Features 10GBASE-KR scenario. So, for XFI usage, there are two scenarios, one will use fiber cable, another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-boot + introduced to indicate a XFI port will use copper cable, and U-Boot will fixup the dtb accordingly. It's used as: fsl_10gkr_copper:<10g_mac_name> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they @@ -118,7 +118,7 @@ The physical address of the last (boot page translation) varies with the actual Voltage ID and VDD override -------------------- -T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage +T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage accordingly. The voltage can also be override by command vdd_override. The syntax is @@ -144,8 +144,8 @@ Users can set the final voltage directly. ------------------------------- PBL initializes the internal SRAM and copy SPL(160K) in SRAM. SPL further initialise DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. +and copy U-Boot(768 KB) from NAND/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -165,21 +165,21 @@ Run time view of SPL framework ------------------------------------------------- |STACK | 0xFFFD8000 (22KB) | ------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | +|U-Boot SPL | 0xFFFD8000 (160KB) | ------------------------------------------------- NAND Flash memory Map on T4QDS -------------------------------------------------------------- Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x140000 0x15FFFF u-boot env 128KB +0x000000 0x0FFFFF U-Boot img 1MB +0x140000 0x15FFFF U-Boot env 128KB 0x160000 0x17FFFF FMAN Ucode 128KB Micro SD Card memory Map on T4QDS ---------------------------------------------------- Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB 0x820 0128 FMAN ucode 64KB Switch Settings: (ON is 1, OFF is 0) diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 83a3a9bba2..95f8c04e4d 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -658,7 +658,7 @@ int board_eth_init(bd_t *bis) switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { - /* A fake PHY address to make U-boot happy */ + /* A fake PHY address to make U-Boot happy */ fm_info_set_phy_address(i, i); } else { lane = serdes_get_first_lane(FSL_SRDS_1, @@ -839,7 +839,7 @@ int board_eth_init(bd_t *bis) switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { - /* A fake PHY address to make U-boot happy */ + /* A fake PHY address to make U-Boot happy */ fm_info_set_phy_address(i, i); } else { lane = serdes_get_first_lane(FSL_SRDS_2, diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 697e5c8bb4..9418907697 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -16,13 +16,13 @@ The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading an executable image from various boot devices. The Gateworks Ventana board config uses an SPL build configuration. This -will build the following artifacts from u-boot source: +will build the following artifacts from U-Boot source: - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program Loader) boots. This detects CPU/DRAM configuration, configures The DRAM controller, loads u-boot.img from the detected boot device, and jumps to it. As this is booted from the PPL, it has an IVT/DCD table. - - u-boot.img - The main u-boot core which is u-boot.bin with a image header. + - u-boot.img - The main U-Boot core which is u-boot.bin with a image header. 2. Build @@ -71,15 +71,15 @@ kobs-ng init -v -x --search_exponent=1 SPL The kobs-ng application uses an imximage which contains the Image Vector Table (IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and -Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is +Discovered Bad Block Table (DBBT). The SPL build artifact from U-Boot is an imximage. -The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image +The u-boot.img, which is the non SPL U-Boot binary appended to a U-Boot image header must be programmed in the NAND flash boot device at an offset hard coded in the SPL. For the Ventana boards, this has been chosen to be 14MB. -The image can be programmed from either u-boot or Linux: +The image can be programmed from either U-Boot or Linux: -u-boot: +U-Boot: Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs) Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \ nand write ${loadaddr} uboot ${filesize} @@ -104,7 +104,7 @@ More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. When the IMX6 eFUSE settings have been factory programmed to boot from micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is -booted, it will load and execute U-boot (u-boot.img) from offset 69KB +booted, it will load and execute U-Boot (u-boot.img) from offset 69KB on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR). While it is technically possible to enable the SPL to be able to load diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile index 5b05ba8003..cbf16121df 100644 --- a/board/ibf-dsp561/Makefile +++ b/board/ibf-dsp561/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2007 Analog Device Inc. # diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index d2ac7a502b..8475fda1a4 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2009 I-SYST. * diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index e31331aec1..3a9e7807c6 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -93,7 +93,7 @@ int checkboard(void) { enum core_card core; - malta_lcd_puts("U-boot"); + malta_lcd_puts("U-Boot"); puts("Board: MIPS Malta"); core = malta_core_card(); diff --git a/board/intel/Kconfig b/board/intel/Kconfig index f7d71c3612..4d341aa799 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, PCIe and some other sensor interfaces. +config TARGET_COUGARCANYON2 + bool "Cougar Canyon 2" + help + This is the Intel Cougar Canyon 2 Customer Reference Board. It + is built on the Chief River platform with Intel Ivybridge Processor + and Panther Point chipset. The board has 4GB RAM, with some other + peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI. + config TARGET_CROWNBAY bool "Crown Bay" help @@ -54,6 +62,7 @@ config TARGET_MINNOWMAX endchoice source "board/intel/bayleybay/Kconfig" +source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig new file mode 100644 index 0000000000..95a617b725 --- /dev/null +++ b/board/intel/cougarcanyon2/Kconfig @@ -0,0 +1,25 @@ +if TARGET_COUGARCANYON2 + +config SYS_BOARD + default "cougarcanyon2" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "cougarcanyon2" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_FSP + select BOARD_ROMSIZE_KB_2048 + +endif diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS new file mode 100644 index 0000000000..a486739b5e --- /dev/null +++ b/board/intel/cougarcanyon2/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL COUGAR CANYON 2 BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/cougarcanyon2/ +F: include/configs/cougarcanyon2.h +F: configs/cougarcanyon2_defconfig diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile new file mode 100644 index 0000000000..abd924c6b3 --- /dev/null +++ b/board/intel/cougarcanyon2/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cougarcanyon2.o start.o diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c new file mode 100644 index 0000000000..31a480a615 --- /dev/null +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> +#include <smsc_sio1007.h> +#include <asm/ibmpc.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +#define SIO1007_RUNTIME_IOPORT 0x180 + +int board_early_init_f(void) +{ + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + + /* Initialize LPC interface to turn on superio chipset decode range */ + dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE); + dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN); + dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | + (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); + dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | + SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN); + + /* Enable legacy serial port at 0x3f8 */ + sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); + + /* Enable SIO1007 runtime I/O port at 0x180 */ + sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT); + + /* + * On Cougar Canyon 2 board, the RS232 transiver connected to serial + * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. + * Set the pin value to 1 to enable the RS232 transiver. + */ + sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, + GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL); + sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S new file mode 100644 index 0000000000..d8f227c706 --- /dev/null +++ b/board/intel/cougarcanyon2/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index c1087acb69..212c9702d3 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/device.h> -#include <asm/arch/gpio.h> #include <asm/arch/quark.h> int board_early_init_f(void) @@ -30,7 +29,7 @@ void board_assert_perst(void) u32 base, port, val; /* retrieve the GPIO IO base */ - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); base = (base & 0xffff) & ~0x7f; /* enable the pin */ @@ -57,7 +56,7 @@ void board_deassert_perst(void) u32 base, port, val; /* retrieve the GPIO IO base */ - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); base = (base & 0xffff) & ~0x7f; /* pull it up (de-assert) */ diff --git a/board/ip04/Makefile b/board/ip04/Makefile index caba16f199..44fa684729 100644 --- a/board/ip04/Makefile +++ b/board/ip04/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2010 Analog Device Inc. # diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c index 70765bce50..c7bc33434e 100644 --- a/board/ip04/ip04.c +++ b/board/ip04/ip04.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2007 David Rowe, * (c) 2006 Ivan Danov diff --git a/board/keymile/km83xx/README.kmeter1 b/board/keymile/km83xx/README.kmeter1 index 7f4fc999f8..b85d7764bc 100644 --- a/board/keymile/km83xx/README.kmeter1 +++ b/board/keymile/km83xx/README.kmeter1 @@ -60,7 +60,7 @@ Keymile kmeter1 Board Bytes transferred = 204204 (31dac hex) => -4.1 Reflash U-boot Image using U-boot +4.1 Reflash U-Boot Image using U-Boot => run update ..... done diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig new file mode 100644 index 0000000000..229b5ea129 --- /dev/null +++ b/board/l+g/vinco/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VINCO + +config SYS_BOARD + default "vinco" + +config SYS_VENDOR + default "l+g" + +config SYS_CONFIG_NAME + default "vinco" + +endif diff --git a/board/l+g/vinco/MAINTAINERS b/board/l+g/vinco/MAINTAINERS new file mode 100644 index 0000000000..0cd6044172 --- /dev/null +++ b/board/l+g/vinco/MAINTAINERS @@ -0,0 +1,6 @@ +VInCo Platform +M: Gregory CLEMENT <gregory.clement@free-electrons.com> +S: Maintained +F: board/l+g/vinco +F: include/configs/vinco.h +F: configs/vinco_defconfig diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile new file mode 100644 index 0000000000..a2b8a2bc4a --- /dev/null +++ b/board/l+g/vinco/Makefile @@ -0,0 +1 @@ +obj-y += vinco.o diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c new file mode 100644 index 0000000000..3d7af092e8 --- /dev/null +++ b/board/l+g/vinco/vinco.c @@ -0,0 +1,212 @@ +/* + * Board file for the VInCo platform + * Based on the the SAMA5-EK board file + * Configuration settings for the VInCo platform. + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * Copyright (C) 2015 Free Electrons + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <atmel_hlcdc.h> +#include <atmel_mci.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <nand.h> +#include <spi.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void vinco_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + + +#ifdef CONFIG_CMD_USB +static void vinco_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 0); + at91_set_pio_output(AT91_PIO_PORTE, 12, 0); + at91_set_pio_output(AT91_PIO_PORTE, 10, 0); +} +#endif + + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void vinco_mci0_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */ + at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */ + at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */ + at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */ + at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */ + at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */ + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */ + at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */ + at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI0); +} + +int board_mmc_init(bd_t *bis) +{ + /* Enable power for MCI0 interface */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 1); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void vinco_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); + + /* Enable Phy*/ + at91_set_pio_output(AT91_PIO_PORTE, 8, 1); +} +#endif + +static void vinco_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + vinco_serial3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + vinco_spi0_hw_init(); +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI + vinco_mci0_hw_init(); +#endif +#ifdef CONFIG_MACB + vinco_macb0_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + vinco_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/board/lge/sniper/Makefile b/board/lge/sniper/Makefile index 2d216fcaf6..f32a481d0e 100644 --- a/board/lge/sniper/Makefile +++ b/board/lge/sniper/Makefile @@ -1,5 +1,5 @@ # -# LG Optimus Black (P970) codename sniper board +# LG Optimus Black codename sniper board # # Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> # diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index c818c9d4ce..d0e7d66b49 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -1,5 +1,5 @@ /* - * LG Optimus Black (P970) codename sniper board + * LG Optimus Black codename sniper board * * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> * diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h index e5d0774e78..01ab3015d2 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lge/sniper/sniper.h @@ -1,5 +1,5 @@ /* - * LG Optimus Black (P970) codename sniper board + * LG Optimus Black codename sniper board * * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> * diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS index ffe2201b28..68ad3a511c 100644 --- a/board/logicpd/omap3som/MAINTAINERS +++ b/board/logicpd/omap3som/MAINTAINERS @@ -1,5 +1,5 @@ OMAP3SOM BOARD -M: Peter Barada <peter.barada@logicpd.com> +M: Adam Ford <aford173@gmail.com> S: Maintained F: board/logicpd/omap3som/ F: include/configs/omap3_logic.h diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index fb89921e6b..b5c44f915b 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -26,10 +26,20 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> +#include <linux/mtd/nand.h> +#include <asm/omap_musb.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> #include "omap3logic.h" DECLARE_GLOBAL_DATA_PTR; +#define CONTROL_WKUP_CTRL 0x48002a5c +#define GPIO_IO_PWRDNZ (1 << 6) +#define PBIASLITEVMODE1 (1 << 8) + /* * two dimensional array of strucures containining board name and Linux * machine IDs; row it selected based on CPU column is slected based @@ -73,6 +83,89 @@ static struct board_id { }, }; +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#if defined(CONFIG_SPL_BUILD) +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + /* 256MB DDR */ + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; +} +#endif + +#ifdef CONFIG_USB_MUSB_OMAP2PLUS +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" +#endif + .config = &musb_config, + .power = 100, + .platform_ops = &omap2430_ops, + .board_data = &musb_board_data, +}; +#endif + + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ, + CONTROL_WKUP_CTRL); + twl4030_power_init(); + + omap_die_id_display(); + putc('\n'); + +#ifdef CONFIG_USB_MUSB_OMAP2PLUS + musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); +#endif + + return 0; +} + /* * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV */ @@ -188,69 +281,317 @@ int board_eth_init(bd_t *bis) */ void set_muxconf_regs(void) { - /*GPMC*/ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4)); - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); - - /*Expansion card */ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); - - /* Serial Console */ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); - - /* I2C */ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); - - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); - - /*Control and debug */ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ + + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ + + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/ + + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/ + + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/ + + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ + + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/ + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/ + + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/ + + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/ + + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ + + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/ + + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/ + + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/ + + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ + + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ + + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ + + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ + + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/ + + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/ + + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/ + + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/ + + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/ + + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/ + + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ + + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ + + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ } diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c index dc1013ad12..3fb6a7b7cd 100644 --- a/board/mini-box/picosam9g45/led.c +++ b/board/mini-box/picosam9g45/led.c @@ -9,15 +9,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9g45.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c index 193f14d75a..32ba9c6225 100644 --- a/board/mini-box/picosam9g45/picosam9g45.c +++ b/board/mini-box/picosam9g45/picosam9g45.c @@ -17,7 +17,6 @@ #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> @@ -80,15 +79,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct atmel_mpddrc_config ddr2; unsigned long csa; ddr2_conf(&ddr2); - /* enable DDR2 clock */ - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* Chip select 1 is for DDR2/SDRAM */ csa = readl(&mat->ebicsa); @@ -105,9 +102,7 @@ void mem_init(void) #ifdef CONFIG_CMD_USB static void picosam9g45_usb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -117,11 +112,9 @@ static void picosam9g45_usb_hw_init(void) #ifdef CONFIG_MACB static void picosam9g45_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: @@ -181,8 +174,6 @@ void lcd_disable(void) static void picosam9g45_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -214,7 +205,7 @@ static void picosam9g45_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } diff --git a/board/pr1/Makefile b/board/pr1/Makefile index 4f375a8b5c..8caa3601f4 100644 --- a/board/pr1/Makefile +++ b/board/pr1/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) Switchfin Org. <dpn@switchfin.org> # diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c index bb907f3966..3fffabdefb 100644 --- a/board/pr1/pr1.c +++ b/board/pr1/pr1.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) Switchfin Org. <dpn@switchfin.org> * diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 4b80d7b742..7f4fe64385 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -78,6 +78,11 @@ struct msg_get_clock_rate { * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 * http://git.drogon.net/?p=wiringPi;a=blob;f=wiringPi/wiringPi.c;h=503151f61014418b9c42f4476a6086f75cd4e64b;hb=refs/heads/master#l922 + * + * In http://lists.denx.de/pipermail/u-boot/2016-January/243752.html + * ("[U-Boot] [PATCH] rpi: fix up Model B entries") Dom Cobley at the RPi + * Foundation stated that the following source was accurate: + * https://github.com/AndrewFromMelbourne/raspberry_pi_revision */ struct rpi_model { const char *name; @@ -110,28 +115,28 @@ static const struct rpi_model rpi_models_new_scheme[] = { static const struct rpi_model rpi_models_old_scheme[] = { [0x2] = { - "Model B (no P5)", - "bcm2835-rpi-b-i2c0.dtb", + "Model B", + "bcm2835-rpi-b.dtb", true, }, [0x3] = { - "Model B (no P5)", - "bcm2835-rpi-b-i2c0.dtb", + "Model B", + "bcm2835-rpi-b.dtb", true, }, [0x4] = { - "Model B", - "bcm2835-rpi-b.dtb", + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", true, }, [0x5] = { - "Model B", - "bcm2835-rpi-b.dtb", + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", true, }, [0x6] = { - "Model B", - "bcm2835-rpi-b.dtb", + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", true, }, [0x7] = { @@ -254,6 +259,9 @@ static void set_usbethaddr(void) eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac); + if (!getenv("ethaddr")) + setenv("ethaddr", getenv("usbethaddr")); + return; } diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index cc4c2a072b..53e353a75d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -9,15 +9,12 @@ #include <common.h> #include <asm/gpio.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOC); gpio_direction_output(CONFIG_RED_LED, 1); gpio_direction_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index b96f745773..3cc01cb687 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -14,7 +14,6 @@ #include <asm/gpio.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/clk.h> @@ -41,7 +40,6 @@ static void pm9261_nand_hw_init(void) unsigned long csa; struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; @@ -69,9 +67,8 @@ static void pm9261_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOA | - 1 << ATMEL_ID_PIOC, - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); @@ -89,7 +86,6 @@ static void pm9261_nand_hw_init(void) static void pm9261_dm9000_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Configure SMC CS2 for DM9000 */ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | @@ -110,7 +106,7 @@ static void pm9261_dm9000_hw_init(void) &smc->cs[2].mode); /* Configure Interrupt pin as input, no pull-up */ - writel(1 << ATMEL_ID_PIOA, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); at91_set_pio_input(AT91_PIO_PORTA, 24, 0); } #endif @@ -145,8 +141,6 @@ void lcd_disable(void) static void pm9261_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ @@ -170,7 +164,7 @@ static void pm9261_lcd_hw_init(void) at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ - writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ + at91_system_clk_enable(AT91_PMC_HCK1); gd->fb_base = ATMEL_BASE_SRAM; } @@ -224,12 +218,8 @@ void lcd_show_board_info(void) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for some PIOs */ - writel(1 << ATMEL_ID_PIOA | - 1 << ATMEL_ID_PIOC, - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOC); at91_seriald_hw_init(); diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index bfc2310b0e..8025a20a6a 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -9,15 +9,12 @@ #include <common.h> #include <asm/gpio.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> void coloured_LED_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOB); gpio_direction_output(CONFIG_RED_LED, 1); gpio_direction_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 1b00f08835..276ff80943 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -14,7 +14,6 @@ #include <asm/gpio.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/clk.h> @@ -78,8 +77,6 @@ static void pm9263_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9263_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* * PB27 enables the 50MHz oscillator for Ethernet PHY * 1 - enable @@ -88,8 +85,7 @@ static void pm9263_macb_hw_init(void) at91_set_pio_output(AT91_PIO_PORTB, 27, 1); at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: @@ -231,8 +227,6 @@ static int pm9263_lcd_hw_psram_init(void) static void pm9263_lcd_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ @@ -257,7 +251,7 @@ static void pm9263_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_LCDC); /* Power Control */ at91_set_pio_output(AT91_PIO_PORTA, 22, 1); @@ -323,12 +317,9 @@ void lcd_show_board_info(void) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOCDE), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); at91_seriald_hw_init(); diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index efc4133bbf..c2707e0015 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -17,7 +17,6 @@ #include <asm/gpio.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/gpio.h> @@ -39,7 +38,6 @@ static void pm9g45_nand_hw_init(void) unsigned long csa; struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -63,7 +61,7 @@ static void pm9g45_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOC); #ifdef CONFIG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ @@ -78,8 +76,6 @@ static void pm9g45_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9g45_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* * PD2 enables the 50MHz oscillator for Ethernet PHY * 1 - enable @@ -88,8 +84,7 @@ static void pm9g45_macb_hw_init(void) at91_set_pio_output(AT91_PIO_PORTD, 2, 1); at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: @@ -114,13 +109,10 @@ static void pm9g45_macb_hw_init(void) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | - (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC) | - (1 << ATMEL_ID_PIODE), &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_seriald_hw_init(); diff --git a/board/sbc8349/README b/board/sbc8349/README index e2d60cc530..3c142e0407 100644 --- a/board/sbc8349/README +++ b/board/sbc8349/README @@ -30,21 +30,21 @@ image. Restoring a corrupted or missing flash image: ============================================= -Note that U-boot versions up to and including 2009.06 had essentially -two copies of u-boot in flash; one at the very beginning, which set +Note that U-Boot versions up to and including 2009.06 had essentially +two copies of U-Boot in flash; one at the very beginning, which set the HRCW, and one at the very end, which was the image that was run. As of this point in time, the two have been combined into just one at the beginning of flash, which provides both the HRCW, and the image that is executed. This frees up the remainder of flash for other uses. -Use of the u-boot command "fli" will indicate what parts are in use. -Details for storing U-boot to flash using a Wind River ICE can be found +Use of the U-Boot command "fli" will indicate what parts are in use. +Details for storing U-Boot to flash using a Wind River ICE can be found on page 19 of the board manual (request ERG-00328-001). The following is a summary of that information: - Connect ICE and establish connection to it from WorkBench/OCD. - Ensure you have background mode (BKM) in the OCD terminal window. - Select the appropriate flash type (listed above) - - Prepare a u-boot image by using the Wind River Convert utility; + - Prepare a U-Boot image by using the Wind River Convert utility; by using "Convert and Add file" on the ELF file from your build. Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are trying to preserve your old environment settings and user flash). @@ -55,9 +55,9 @@ is a summary of that information: Note that some versions of the register files used with Workbench would zero some TSEC registers, which inhibits ethernet operation -by u-boot when this register file is played to the target. Using +by U-Boot when this register file is played to the target. Using "INN" in the OCD terminal window instead of "IN" before the "GO" -will not play the register file, and allow u-boot to use the TSEC +will not play the register file, and allow U-Boot to use the TSEC interface while executed from the ICE "GO" command. Alternatively, you can locate the register file which will be named @@ -74,7 +74,7 @@ as u-boot.bin. Updating U-Boot with U-Boot: ============================ -This procedure is very similar to other boards that have u-boot installed. +This procedure is very similar to other boards that have U-Boot installed. Assuming that the network has been configured, and that the new u-boot.bin has been copied to the TFTP server, the commands are: @@ -98,7 +98,7 @@ There are three configuration choices: The 1st does not enable CONFIG_PCI, and assumes that the PCI slot will be left empty (M66EN high), and so the board will operate with -a base clock of 66MHz. Note that you need both PCI enabled in u-boot +a base clock of 66MHz. Note that you need both PCI enabled in U-Boot and linux in order to have functional PCI under linux. The only reason for choosing to not enable PCI would be if you had a very early (rev 1.0) CPU with possible PCI issues. diff --git a/board/sbc8548/README b/board/sbc8548/README index feac5e3e63..0def245bd9 100644 --- a/board/sbc8548/README +++ b/board/sbc8548/README @@ -7,10 +7,10 @@ memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC ethernet connections. -U-boot Configuration: +U-Boot Configuration: ===================== -The following possible u-boot configuration targets are available: +The following possible U-Boot configuration targets are available: 1) sbc8548_config 2) sbc8548_PCI_33_config @@ -23,7 +23,7 @@ of each choice are listed below. Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot will be left empty (M66EN high), and so the board will operate with -a base clock of 66MHz. Note that you need both PCI enabled in u-boot +a base clock of 66MHz. Note that you need both PCI enabled in U-Boot and linux in order to have functional PCI under linux. The second enables PCI support and builds for a 33MHz clock rate. Note @@ -100,13 +100,13 @@ from the board's socket to resolve the above i2c address overlap issue and allow SPD autodetection of RAM to work. -Updating U-boot with U-boot: +Updating U-Boot with U-Boot: ============================ -Note that versions of u-boot up to and including 2009.08 had u-boot stored +Note that versions of U-Boot up to and including 2009.08 had U-Boot stored at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to -update u-boot with u-boot and it uses the old address, you will render +update U-Boot with U-Boot and it uses the old address, you will render your board inoperable, and you will require JTAG recovery. The following steps list how to update with the current address: @@ -120,11 +120,11 @@ The following steps list how to update with the current address: protect on all The "md" steps in the above are just a precautionary step that allow -you to confirm the u-boot version that was downloaded, and then confirm +you to confirm the U-Boot version that was downloaded, and then confirm that it was copied to flash. The above assumes that you are using the default board settings which -have u-boot in the 8MB flash, tied to /CS0. +have U-Boot in the 8MB flash, tied to /CS0. If you are running the default 8MB /CS0 settings but want to store an image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, @@ -139,7 +139,7 @@ image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, protect on all Finally, if you are running the alternate 64MB /CS0 settings and want -to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT +to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT enabled) the steps will become: tftp u-boot.bin @@ -155,7 +155,7 @@ Hardware Reference: =================== The following contains some summary information on hardware settings -that are relevant to u-boot, based on the board manual. For the +that are relevant to U-Boot, based on the board manual. For the most up to date and complete details of the board, please request the reference manual ERG-00327-001.pdf from www.windriver.com @@ -166,7 +166,7 @@ Sodimm flash: intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 Note that this address reflects the default setting for the JTAG debugging tools, but since the alignment is - rather inconvenient, u-boot puts it at 0xec00_0000. + rather inconvenient, U-Boot puts it at 0xec00_0000. Jumpers: @@ -193,7 +193,7 @@ is jumpered parallel to the LBC-SDRAM, then /CS0 is for the SODIMM flash and /CS6 is for the boot flash. Note that in this alternate setting, you also need to switch SW2.8 to ON. See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting -and boot u-boot from the 64MB SODIMM +and boot U-Boot from the 64MB SODIMM Switches: @@ -257,7 +257,7 @@ fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) [*] fb80 represents the default programmed by WR JTAG register files, - but u-boot places the flash at either ec00 or fc00 based on JP12. + but U-Boot places the flash at either ec00 or fc00 based on JP12. The EPLD on CS5 demuxes the following devices at the following offsets: diff --git a/board/sbc8641d/README b/board/sbc8641d/README index d07f1ccf7c..4999b7763c 100644 --- a/board/sbc8641d/README +++ b/board/sbc8641d/README @@ -30,15 +30,15 @@ PCI: 4. Reflashing U-Boot -------------------- The board has two independent flash devices which can be used for dual -booting, or for u-boot backup and recovery. A two pin jumper on the +booting, or for U-Boot backup and recovery. A two pin jumper on the three pin JP10 determines which device is attached to /CS0 line. -Assuming one device has a functional u-boot, and the other device has +Assuming one device has a functional U-Boot, and the other device has a recently installed non-functional image, to perform a recovery from that non-functional image goes essentially as follows: a) power down the board and jumper JP10 to select the functional image. -b) power on the board and let it get to u-boot prompt. +b) power on the board and let it get to U-Boot prompt. c) while on, using static precautions, move JP10 back to the failed image. d) use "md fff00000" to confirm you are looking at the failed image e) turn off write protect with "prot off all" diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c index 6be0b987ca..08566fcb8d 100644 --- a/board/seco/mx6quq7/mx6quq7.c +++ b/board/seco/mx6quq7/mx6quq7.c @@ -122,7 +122,7 @@ int board_mmc_init(bd_t *bis) /* * Following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 eMMC on Board * mmc1 Ext SD */ diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 38c0ca3aae..9d5266151b 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -17,7 +17,6 @@ #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> @@ -147,13 +146,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - /* enable DDR2 clock */ - writel(AT91_PMC_DDR, &pmc->scer); + at91_system_clk_enable(AT91_PMC_DDR); /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); @@ -210,10 +207,9 @@ int board_early_init_f(void) /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ void at91_udp_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable UPLL clock */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + at91_upll_clk_enable(); + /* Enable UDPHS clock */ at91_periph_clk_enable(ATMEL_ID_UDPHS); } diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index d82f1b73a7..47a60a72ac 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -22,7 +22,6 @@ #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_spi.h> #include <spi.h> #include <asm/arch/clk.h> @@ -116,17 +115,13 @@ static void smartweb_macb_hw_init(void) void at91_udp_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - /* Enable PLLB */ - writel(get_pllb_init(), &pmc->pllbr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) - ; + at91_pllb_clk_enable(get_pllb_init()); /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ at91_periph_clk_enable(ATMEL_ID_UDP); - writel(AT91SAM926x_PMC_UDP, &pmc->scer); + at91_system_clk_enable(AT91SAM926x_PMC_UDP); } struct at91_udc_data board_udc_data = { diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 72c5e6083d..b0385d8a6e 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -18,7 +18,6 @@ #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/at91sam9_sdramc.h> @@ -290,17 +289,13 @@ void spi_cs_deactivate(struct spi_slave *slave) void at91_udp_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - /* Enable PLLB */ - writel(get_pllb_init(), &pmc->pllbr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) - ; + at91_pllb_clk_enable(get_pllb_init()); /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ at91_periph_clk_enable(ATMEL_ID_UDP); - writel(AT91SAM926x_PMC_UDP, &pmc->scer); + at91_system_clk_enable(AT91SAM926x_PMC_UDP); } struct at91_udc_data board_udc_data = { diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README index b417ff0334..5d0a45d929 100644 --- a/board/solidrun/mx6cuboxi/README +++ b/board/solidrun/mx6cuboxi/README @@ -1,7 +1,7 @@ -How to use U-boot on Solid-run mx6 Hummingboard and Cubox-i +How to use U-Boot on Solid-run mx6 Hummingboard and Cubox-i ----------------------------------------------------------- -- Build U-boot for Hummingboard/Cubox-i: +- Build U-Boot for Hummingboard/Cubox-i: $ make mrproper $ make mx6cuboxi_defconfig @@ -17,5 +17,5 @@ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync -- Insert the SD card in the board, power it up and U-boot messages should +- Insert the SD card in the board, power it up and U-Boot messages should come up. diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 8bc2d9e4c1..fb8475f65f 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -19,6 +19,8 @@ #include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32.h> +#include <asm/arch/stm32_periph.h> +#include <asm/arch/stm32_defs.h> DECLARE_GLOBAL_DATA_PTR; @@ -286,6 +288,7 @@ int board_early_init_f(void) res = uart_setup_gpio(); if (res) return res; + clock_setup(USART1_CLOCK_CFG); return 0; } diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index d302fc23b6..f159af9fbe 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -220,7 +220,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { /* - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 SD2 * mmc1 SD3 * mmc2 eMMC diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile index 2e029f5ce8..1ce8f64a08 100644 --- a/board/tcm-bf518/Makefile +++ b/board/tcm-bf518/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c index 4348678aeb..7923eae5d5 100644 --- a/board/tcm-bf518/tcm-bf518.c +++ b/board/tcm-bf518/tcm-bf518.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2008-2009 Analog Devices Inc. * diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile index 93a01e4a3c..0fe25e80dc 100644 --- a/board/tcm-bf537/Makefile +++ b/board/tcm-bf537/Makefile @@ -1,5 +1,5 @@ # -# U-boot - Makefile +# U-Boot - Makefile # # Copyright (c) 2005-2008 Analog Device Inc. # diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 2cf70cab15..19df51adab 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -1,5 +1,5 @@ /* - * U-boot - main board file + * U-Boot - main board file * * Copyright (c) 2005-2009 Analog Devices Inc. * diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 1bfb36243b..bec3b553bc 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -213,12 +213,12 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ - {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ - {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ - {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ - {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ - {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ - {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ @@ -229,7 +229,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ - {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ @@ -430,6 +430,14 @@ const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */ + {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */ + {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */ + {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */ + {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ }; const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { @@ -486,6 +494,14 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */ + {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */ + {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */ + {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ }; #endif diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index 0fe5c3b9c3..05baff6e33 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -3,7 +3,7 @@ U-Boot port for Texas Instruments Keystone II EVM boards Author: Murali Karicheri <m-karicheri2@ti.com> -This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards. +This README has information on the U-Boot port for K2HK, K2E, and K2L EVM boards. Documentation for this board can be found at http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html @@ -23,7 +23,7 @@ The K2L SoC details are available at Board configuration: ==================== -Some of the peripherals that are configured by u-boot +Some of the peripherals that are configured by U-Boot +------+-------+-------+-----------+-----------+-------+-------+----+ | |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI | +------+-------+-------+-----------+-----------+-------+-------+----+ @@ -37,7 +37,7 @@ There are only 2 eth port installed on the boards. There are separate PLLs to drive clocks to Tetris ARM and Peripherals. To bring up SMP Linux on this board, there is a boot monitor code that will be installed in MSMC SRAM. There is command available -to install this image from u-boot. +to install this image from U-Boot. The port related files can be found at following folders keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ @@ -48,7 +48,7 @@ include/configs/k2hk_evm.h include/configs/k2e_evm.h include/configs/k2l_evm.h -As u-boot is migrating to Kconfig there is also board defconfig files +As U-Boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig configs/k2hk_evm_defconfig configs/k2l_evm_defconfig @@ -80,7 +80,7 @@ Need Code Composer Studio (CCS) installed on a PC to load and run u-boot-dtb.bin on EVM. See instructions at below link for installing CCS on a Windows PC. http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# Installing_Code_Composer_Studio -Use u-boot-dtb.bin from the build folder for loading and running u-boot binary +Use u-boot-dtb.bin from the build folder for loading and running U-Boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup @@ -94,7 +94,7 @@ Start CCS on a Windows machine and Launch Target configuration as instructed at http://processors.wiki.ti.com/index.php/ MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. The instructions provided in the above link uses a script for -loading the u-boot binary on the target EVM. Instead do the following:- +loading the U-Boot binary on the target EVM. Instead do the following:- 1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D is connected: Unknown)" at the debug window (This is created once Target @@ -126,41 +126,41 @@ SPI NOR Flash programming instructions U-Boot image can be flashed to first 512KB of the NOR flash using following instructions: -1. Start CCS and run U-boot as described above. +1. Start CCS and run U-Boot as described above. 2. Suspend Target. Select Run -> Suspend from top level menu CortexA15_1 (Free Running)" 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L EVM using CCS", but using address 0x87000000. -4. Free Run the target as described earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. +4. Free Run the target as described earlier (step 4) to get U-Boot prompt +5. At the U-Boot console type following to setup U-Boot environment variables. setenv addr_uboot 0x87000000 setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000> run burn_uboot_spi - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "SPI Little Endian Boot mode" as per instruction at http://processors.wiki.ti.com/index.php/*_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. +6. Power ON the EVM. The EVM now boots with U-Boot image on the NOR flash. AEMIF NAND Flash programming instructions ====================================== U-Boot image can be flashed to first 1024KB of the NAND flash using following instructions: -1. Start CCS and run U-boot as described above. +1. Start CCS and run U-Boot as described above. 2. Suspend Target. Select Run -> Suspend from top level menu CortexA15_1 (Free Running)" 3. Load MLO binary from build folder on to DDR address 0x87000000 through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM using CCS", but using address 0x87000000. -4. Free Run the target as described earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. +4. Free Run the target as described earlier (step 4) to get U-Boot prompt +5. At the U-Boot console type following to setup U-Boot environment variables. setenv filesize <size in hex of MLO rounded to hex 0x10000> run burn_uboot_nand - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "ARM NAND Boot mode" as per instruction at http://processors.wiki.ti.com/index.php/*_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. +6. Power ON the EVM. The EVM now boots with U-Boot image on the NAND flash. Load and Run U-Boot on keystone EVMs using UART download ======================================================== @@ -171,4 +171,4 @@ Open BMC and regular UART terminals. 2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM BMC> bootmode #4 MBC> reboot -3. When xmodem is complete you should see the u-boot starts on the UART port +3. When xmodem is complete you should see the U-Boot starts on the UART port diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 73d94a6729..7d1709c880 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -56,6 +56,7 @@ int board_init(void) } #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +#ifndef CONFIG_DM_ETH int get_eth_env_param(char *env_name) { char *env; @@ -105,6 +106,7 @@ int board_eth_init(bd_t *bis) return 0; } #endif +#endif #ifdef CONFIG_SPL_BUILD void spl_board_init(void) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 83e1ddc734..879f25a538 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -114,7 +114,7 @@ void pin_mux_usb(void) } #endif -#ifdef CONFIG_VIDEO_TEGRA +#ifdef CONFIG_VIDEO_TEGRA20 /* * Routine: pin_mux_display * Description: setup the pin muxes/tristate values for the LCD interface) diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 8656782d86..7fc57da132 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -77,7 +77,7 @@ static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { /* * According to board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 eMMC (SD3) on TQMa6 * mmc1 .. n optional slots used on baseboard */ diff --git a/board/wandboard/README b/board/wandboard/README index c6c01322b6..6345416b2f 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -9,7 +9,7 @@ SoCs: mx6 quad, mx6 dual lite and mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ -Building U-boot for Wandboard +Building U-Boot for Wandboard ----------------------------- To build U-Boot for the Wandboard: @@ -17,7 +17,7 @@ To build U-Boot for the Wandboard: $ make wandboard_config $ make -Flashing U-boot into the SD card +Flashing U-Boot into the SD card -------------------------------- - After the 'make' command completes, the generated 'SPL' binary must be @@ -36,4 +36,4 @@ as the mx6 processor) - Connect the serial cable to the host PC -- Power up the board and U-boot messages will appear in the serial console. +- Power up the board and U-Boot messages will appear in the serial console. diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index ac001edf3a..4ce74cd971 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -155,7 +155,7 @@ int board_mmc_init(bd_t *bis) /* * Following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 SOM MicroSD * mmc1 Carrier board MicroSD */ diff --git a/board/warp/README b/board/warp/README index 22f9055eb6..3cfd22ec76 100644 --- a/board/warp/README +++ b/board/warp/README @@ -1,4 +1,4 @@ -How to Update U-boot on Warp board +How to Update U-Boot on Warp board ---------------------------------- Required software on the host PC: @@ -7,13 +7,13 @@ Required software on the host PC: - dfu-util: http://dfu-util.sourceforge.net/releases/ -Build U-boot for Warp: +Build U-Boot for Warp: $ make mrproper $ make warp_config $ make -This will generate the U-boot binary called u-boot.imx. +This will generate the U-Boot binary called u-boot.imx. Put warp board in USB download mode @@ -29,7 +29,7 @@ Load u-boot.imx via USB: $ sudo ./imx_usb u-boot.imx -Then U-boot should start and its messages will appear in the console program. +Then U-Boot should start and its messages will appear in the console program. Use the default environment variables: @@ -43,7 +43,7 @@ Transfer u-boot.imx that will be flashed into the eMMC: $ sudo dfu-util -D u-boot.imx -a boot -Then on the U-boot prompt the following message should be seen after a +Then on the U-Boot prompt the following message should be seen after a successful upgrade: #DOWNLOAD ... OK @@ -53,4 +53,4 @@ Remove power from the warp board. Put warp board into normal boot mode -Power up the board and the new updated U-boot should boot from eMMC +Power up the board and the new updated U-Boot should boot from eMMC @@ -259,7 +259,6 @@ int bmp_display(ulong addr, int x, int y) ret = video_bmp_display(dev, addr, x, y, align); } } - return ret ? CMD_RET_FAILURE : 0; #elif defined(CONFIG_LCD) ret = lcd_display_bitmap(addr, x, y); #elif defined(CONFIG_VIDEO) @@ -271,5 +270,5 @@ int bmp_display(ulong addr, int x, int y) if (bmp_alloc_addr) free(bmp_alloc_addr); - return ret; + return ret ? CMD_RET_FAILURE : 0; } diff --git a/cmd/bootldr.c b/cmd/bootldr.c index bc5c1f95ea..38b3b2f8d7 100644 --- a/cmd/bootldr.c +++ b/cmd/bootldr.c @@ -1,5 +1,5 @@ /* - * U-boot - bootldr.c + * U-Boot - bootldr.c * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/cmd/cramfs.c b/cmd/cramfs.c index 1d31326bd6..270701b99d 100644 --- a/cmd/cramfs.c +++ b/cmd/cramfs.c @@ -77,7 +77,7 @@ extern int cramfs_ls (struct part_info *info, char *filename); extern int cramfs_info (struct part_info *info); /***************************************************/ -/* U-boot commands */ +/* U-Boot commands */ /***************************************************/ /** diff --git a/cmd/gpio.c b/cmd/gpio.c index 2b78b16866..693998e8bd 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -141,7 +141,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif if (argc > 0) str_gpio = *argv; - if (!strncmp(str_cmd, "status", 1)) { + if (!strncmp(str_cmd, "status", 2)) { /* Support deprecated gpio_status() */ #ifdef gpio_status gpio_status(); diff --git a/cmd/itest.c b/cmd/itest.c index 91ae5c2704..fb4d797e43 100644 --- a/cmd/itest.c +++ b/cmd/itest.c @@ -59,7 +59,7 @@ static long evalexp(char *s, int w) if (s[0] == '*') { addr = simple_strtoul(&s[1], NULL, 16); buf = map_physmem(addr, w, MAP_WRBACK); - if (!buf) { + if (!buf && addr) { puts("Failed to map physical memory\n"); return 0; } diff --git a/cmd/jffs2.c b/cmd/jffs2.c index bce098315e..0b2eefa195 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -456,7 +456,7 @@ static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int pa } /***************************************************/ -/* U-boot commands */ +/* U-Boot commands */ /***************************************************/ /** diff --git a/cmd/ldrinfo.c b/cmd/ldrinfo.c index 2aa56bdb62..2b49297327 100644 --- a/cmd/ldrinfo.c +++ b/cmd/ldrinfo.c @@ -1,5 +1,5 @@ /* - * U-boot - ldrinfo + * U-Boot - ldrinfo * * Copyright (c) 2010 Analog Devices Inc. * diff --git a/cmd/load.c b/cmd/load.c index 0aa7937fd4..65557e4f9e 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -1081,33 +1081,3 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LOADB */ - -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_HWFLOW) -int do_hwflow(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - extern int hwflow_onoff(int); - - if (argc == 2) { - if (strcmp(argv[1], "off") == 0) - hwflow_onoff(-1); - else - if (strcmp(argv[1], "on") == 0) - hwflow_onoff(1); - else - return CMD_RET_USAGE; - } - printf("RTS/CTS hardware flow control: %s\n", hwflow_onoff(0) ? "on" : "off"); - return 0; -} - -/* -------------------------------------------------------------------- */ - -U_BOOT_CMD( - hwflow, 2, 0, do_hwflow, - "turn RTS/CTS hardware flow control in serial line on/off", - "[on|off]" -); - -#endif /* CONFIG_CMD_HWFLOW */ diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index dab195841a..86a4689616 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -1877,7 +1877,7 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part } /***************************************************/ -/* U-boot commands */ +/* U-Boot commands */ /***************************************************/ /* command line only */ /** @@ -571,7 +571,7 @@ static void label_print(void *data) /* * Boot a label that specified 'localboot'. This requires that the 'localcmd' - * environment variable is defined. Its contents will be executed as U-boot + * environment variable is defined. Its contents will be executed as U-Boot * command. If the label specified an 'append' line, its contents will be * used to overwrite the contents of the 'bootargs' environment variable prior * to running 'localcmd'. @@ -1438,7 +1438,7 @@ static struct pxe_menu *parse_pxefile(cmd_tbl_t *cmdtp, unsigned long menucfg) } /* - * Converts a pxe_menu struct into a menu struct for use with U-boot's generic + * Converts a pxe_menu struct into a menu struct for use with U-Boot's generic * menu code. */ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) diff --git a/cmd/spibootldr.c b/cmd/spibootldr.c index ca76dde1dd..acbb0f6969 100644 --- a/cmd/spibootldr.c +++ b/cmd/spibootldr.c @@ -1,5 +1,5 @@ /* - * U-boot - spibootldr.c + * U-Boot - spibootldr.c * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/common/Makefile b/common/Makefile index 59984111e1..117178ad9b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -82,7 +82,6 @@ obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o obj-$(CONFIG_LYNXKDI) += lynxkdi.o obj-$(CONFIG_MENU) += menu.o -obj-$(CONFIG_MODEM_SUPPORT) += modem.o obj-$(CONFIG_UPDATE_TFTP) += update.o obj-$(CONFIG_DFU_TFTP) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff --git a/common/autoboot.c b/common/autoboot.c index c11fb31236..223e062740 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -287,7 +287,7 @@ static int abortboot(int bootdelay) static void process_fdt_options(const void *blob) { -#if defined(CONFIG_OF_CONTROL) +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_SYS_TEXT_BASE) ulong addr; /* Add an env variable to point to a kernel payload, if available */ @@ -299,7 +299,7 @@ static void process_fdt_options(const void *blob) addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); if (addr) setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); -#endif /* CONFIG_OF_CONTROL */ +#endif /* CONFIG_OF_CONTROL && CONFIG_SYS_TEXT_BASE */ } const char *bootdelay_process(void) diff --git a/common/board_f.c b/common/board_f.c index c470b5921a..a960144b02 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -162,9 +162,6 @@ static int display_text_info(void) text_base, bss_start, bss_end); #endif -#ifdef CONFIG_MODEM_SUPPORT - debug("Modem Support enabled\n"); -#endif #ifdef CONFIG_USE_IRQ debug("IRQ Stack: %08lx\n", IRQ_STACK_START); debug("FIQ Stack: %08lx\n", FIQ_STACK_START); diff --git a/common/board_r.c b/common/board_r.c index 75ee43e2d7..6c23865279 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -456,7 +456,7 @@ static int initr_dataflash(void) /* * Tell if it's OK to load the environment early in boot. * - * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see + * If CONFIG_OF_CONTROL is defined, we'll check with the FDT to see * if this is OK (defaulting to saying it's OK). * * NOTE: Loading the environment early can be a bad idea if security is diff --git a/common/cli_hush.c b/common/cli_hush.c index 2fbfdbe89a..00861e2d9e 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -974,6 +974,30 @@ static inline void setup_prompt_string(int promptmode, char **prompt_str) } #endif +#ifdef __U_BOOT__ +static int uboot_cli_readline(struct in_str *i) +{ + char *prompt; + char __maybe_unused *ps_prompt = NULL; + + if (i->promptmode == 1) + prompt = CONFIG_SYS_PROMPT; + else + prompt = CONFIG_SYS_PROMPT_HUSH_PS2; + +#ifdef CONFIG_CMDLINE_PS_SUPPORT + if (i->promptmode == 1) + ps_prompt = getenv("PS1"); + else + ps_prompt = getenv("PS2"); + if (ps_prompt) + prompt = ps_prompt; +#endif + + return cli_readline(prompt); +} +#endif + static void get_user_input(struct in_str *i) { #ifndef __U_BOOT__ @@ -1003,11 +1027,8 @@ static void get_user_input(struct in_str *i) bootretry_reset_cmd_timeout(); i->__promptme = 1; - if (i->promptmode == 1) { - n = cli_readline(CONFIG_SYS_PROMPT); - } else { - n = cli_readline(CONFIG_SYS_PROMPT_HUSH_PS2); - } + n = uboot_cli_readline(i); + #ifdef CONFIG_BOOT_RETRY_TIME if (n == -2) { puts("\nTimeout waiting for command\n"); diff --git a/common/console.c b/common/console.c index b3f5fdc03a..6a0d11bb04 100644 --- a/common/console.c +++ b/common/console.c @@ -650,6 +650,10 @@ struct stdio_dev *search_device(int flags, const char *name) struct stdio_dev *dev; dev = stdio_get_by_name(name); +#ifdef CONFIG_VIDCONSOLE_AS_LCD + if (!dev && !strcmp(name, "lcd")) + dev = stdio_get_by_name("vidconsole"); +#endif if (dev && (dev->flags & flags)) return dev; @@ -795,6 +799,10 @@ done: #ifndef CONFIG_SYS_CONSOLE_INFO_QUIET stdio_print_current_devices(); #endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */ +#ifdef CONFIG_VIDCONSOLE_AS_LCD + if (strstr(stdoutname, "lcd")) + printf("Warning: Please change 'lcd' to 'vidconsole' in stdout/stderr environment vars\n"); +#endif #ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE /* set the environment variables (will overwrite previous env settings) */ diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 2b964d16b1..5ea37dfb6e 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -2848,7 +2848,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; return m; /* Otherwise, fail */ fREe(m); - return NULL; + m = NULL; } if (m == NULL) return NULL; /* propagate failure */ diff --git a/common/env_flags.c b/common/env_flags.c index 9c3aed1527..921d3770ea 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -15,6 +15,7 @@ #include <env_attr.h> #include <env_flags.h> #define getenv fw_getenv +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #else #include <common.h> #include <environment.h> @@ -373,21 +374,21 @@ int env_flags_validate_varaccess(const char *name, int check_mask) /* * Validate the parameters to "env set" directly */ -int env_flags_validate_env_set_params(int argc, char * const argv[]) +int env_flags_validate_env_set_params(char *name, char * const val[], int count) { - if ((argc >= 3) && argv[2] != NULL) { - enum env_flags_vartype type = env_flags_get_type(argv[1]); + if ((count >= 1) && val[0] != NULL) { + enum env_flags_vartype type = env_flags_get_type(name); /* * we don't currently check types that need more than * one argument */ - if (type != env_flags_vartype_string && argc > 3) { - printf("## Error: too many parameters for setting " - "\"%s\"\n", argv[1]); + if (type != env_flags_vartype_string && count > 1) { + printf("## Error: too many parameters for setting \"%s\"\n", + name); return -1; } - return env_flags_validate_type(argv[1], argv[2]); + return env_flags_validate_type(name, val[0]); } /* ok */ return 0; diff --git a/common/image-fdt.c b/common/image-fdt.c index 5e4e5bd914..79fa65563f 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -450,7 +450,7 @@ error: * addresses of some of the devices in the device tree are compared with the * actual addresses at which U-Boot has placed them. * - * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the + * Returns 1 on success, 0 on failure. If 0 is returned, U-Boot will halt the * boot process. */ __weak int ft_verify_fdt(void *fdt) diff --git a/common/image.c b/common/image.c index f4a1dc8e25..1d7543dd18 100644 --- a/common/image.c +++ b/common/image.c @@ -458,24 +458,29 @@ ulong getenv_bootm_low(void) phys_size_t getenv_bootm_size(void) { - phys_size_t tmp; + phys_size_t tmp, size; + phys_addr_t start; char *s = getenv("bootm_size"); if (s) { tmp = (phys_size_t)simple_strtoull(s, NULL, 16); return tmp; } + +#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS) + start = gd->bd->bi_dram[0].start; + size = gd->bd->bi_dram[0].size; +#else + start = gd->bd->bi_memstart; + size = gd->bd->bi_memsize; +#endif + s = getenv("bootm_low"); if (s) tmp = (phys_size_t)simple_strtoull(s, NULL, 16); else - tmp = 0; - + tmp = start; -#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS) - return gd->bd->bi_dram[0].size - (tmp - gd->bd->bi_dram[0].start); -#else - return gd->bd->bi_memsize - (tmp - gd->bd->bi_memstart); -#endif + return size - (tmp - start); } phys_size_t getenv_bootm_mapsize(void) @@ -1265,7 +1270,7 @@ int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images, * @cmd_end: pointer to a ulong variable, will hold cmdline end * * boot_get_cmdline() allocates space for kernel command line below - * BOOTMAPSZ + getenv_bootm_low() address. If "bootargs" U-boot environemnt + * BOOTMAPSZ + getenv_bootm_low() address. If "bootargs" U-Boot environemnt * variable is present its contents is copied to allocated kernel * command line. * diff --git a/common/kgdb_stubs.c b/common/kgdb_stubs.c index 19b0c1824d..5278209909 100644 --- a/common/kgdb_stubs.c +++ b/common/kgdb_stubs.c @@ -1,5 +1,5 @@ /* - * U-boot - stub functions for common kgdb code, + * U-Boot - stub functions for common kgdb code, * can be overridden in board specific files * * Copyright 2009 Analog Devices Inc. diff --git a/common/main.c b/common/main.c index 5a0318123b..1a2ef39cca 100644 --- a/common/main.c +++ b/common/main.c @@ -20,19 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; */ __weak void show_boot_progress(int val) {} -static void modem_init(void) -{ -#ifdef CONFIG_MODEM_SUPPORT - debug("DEBUG: main_loop: gd->do_mdm_init=%lu\n", gd->do_mdm_init); - if (gd->do_mdm_init) { - char *str = getenv("mdm_cmd"); - - setenv("preboot", str); /* set or delete definition */ - mdm_init(); /* wait for modem connection */ - } -#endif /* CONFIG_MODEM_SUPPORT */ -} - static void run_preboot_environment_command(void) { #ifdef CONFIG_PREBOOT @@ -66,7 +53,6 @@ void main_loop(void) puts("upgraded by the late 2014 may break or be removed.\n"); #endif - modem_init(); #ifdef CONFIG_VERSION_VARIABLE setenv("ver", version_string); /* set version variable */ #endif /* CONFIG_VERSION_VARIABLE */ diff --git a/common/modem.c b/common/modem.c deleted file mode 100644 index 96b10648d8..0000000000 --- a/common/modem.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002-2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - debug("(%c)", c); - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} - -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - debug("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - debug("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - debug("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - debug("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - debug("ini_f: connected"); - return 0; - } - } - - return 0; -} diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index c3931c6c4d..c27a250251 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -284,7 +284,7 @@ int spl_mmc_load_image(u32 boot_device) if (!err) return err; #endif - break; + /* If RAW mode fails, try FS mode. */ case MMCSD_MODE_FS: debug("spl: mmc boot mode: fs\n"); diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a541d9d17f..b79dd3ce5d 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,6 +1,5 @@ CONFIG_ARC=y CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=750000000 CONFIG_SYS_TEXT_BASE=0x81000000 diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index bd8b9649ce..390b2ec9f6 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -57,7 +57,6 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_DM_VIDEO=y CONFIG_I2C_EDID=y CONFIG_DISPLAY=y -CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index e4a3821047..6e851cc1e7 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 982cee4bcc..e8b3e0cb14 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -11,7 +11,13 @@ CONFIG_SYS_PROMPT="Colibri T20 # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig new file mode 100644 index 0000000000..09306bbd30 --- /dev/null +++ b/configs/cougarcanyon2_defconfig @@ -0,0 +1,20 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" +CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index 943ef07638..b4cbd5fc5d 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_EFI=y CONFIG_DEFAULT_DEVICE_TREE="efi" CONFIG_TARGET_EFI=y # CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_IMLS is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set CONFIG_OF_CONTROL=y @@ -13,6 +14,5 @@ CONFIG_DEBUG_EFI_CONSOLE=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 CONFIG_ICH_SPI=y -# CONFIG_X86_SERIAL is not set CONFIG_TIMER=y CONFIG_EFI=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 3b29158f4a..5aa4166757 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -49,7 +49,6 @@ CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y CONFIG_I2C_EDID=y CONFIG_DISPLAY=y -CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index a3f73ccac8..14125b44f3 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 9fb9dac2e7..5616be94d6 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -13,3 +13,4 @@ CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_DM_ETH=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 7bdf7a4550..7cebacd035 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -12,3 +12,4 @@ CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_DM_ETH=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 940d483cbf..f49d820eb8 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -13,3 +13,4 @@ CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_DM_ETH=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 1b21ed05da..6f5ac18a99 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -13,3 +13,4 @@ CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_DM_ETH=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig new file mode 100644 index 0000000000..88102d9329 --- /dev/null +++ b/configs/ma5d4evk_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_MA5D4EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 6c9e41af83..49687cf857 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index ca0f9e067b..1243006598 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -12,6 +12,8 @@ CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_CROS_EC_KEYB=y @@ -20,6 +22,11 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_TPM_TIS_INFINEON=y @@ -27,6 +34,9 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DISPLAY=y CONFIG_I2C_EDID=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA124=y +CONFIG_VIDEO_BRIDGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_TPM=y +CONFIG_ERRNO_STR=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 0ff510edae..53c6913497 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_LOGIC=y +CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_PROMPT="OMAP Logic # " +CONFIG_SYS_EXTRA_OPTIONS="NAND" # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 9d7350ab83..546933171c 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 68e3b367a3..f33daf1b0b 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -47,7 +47,6 @@ CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y CONFIG_I2C_EDID=y CONFIG_DISPLAY=y -CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index ad16a10d5b..7956670f25 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index ee4340fd85..654bb4b385 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -3,4 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SMARTWEB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" -CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 27ea43ff97..053b74ca3d 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,5 +1,4 @@ CONFIG_ARC=y -CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_TB100=y CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=500000000 diff --git a/configs/tec_defconfig b/configs/tec_defconfig index ea3c3696f5..274fc9d8f8 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (TEC) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index ee3cbadf29..535f96fb63 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -27,5 +27,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index 4b871d0ebd..e369c45e82 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -22,5 +22,7 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 3423f24cbd..66c9e264ac 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_TEGRA20=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig new file mode 100644 index 0000000000..7cae79b314 --- /dev/null +++ b/configs/vinco_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_VINCO=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" +CONFIG_SYS_PROMPT="vinco => " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index e7132cd611..85bc3b97ff 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -14,4 +14,4 @@ CONFIG_OF_EMBED=y CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" +CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic" diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index dd2a9edffb..281191809a 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y +CONFIG_NAND_ARASAN=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_FIT=y diff --git a/doc/README.440-DDR-performance b/doc/README.440-DDR-performance index 17bc74764b..66b97bc9b5 100644 --- a/doc/README.440-DDR-performance +++ b/doc/README.440-DDR-performance @@ -9,7 +9,7 @@ performance changes: ---------------------------------------- -SDRAM0_CFG0[PMU] = 1 (U-boot default for Bamboo, Yosemite and Yellowstone) +SDRAM0_CFG0[PMU] = 1 (U-Boot default for Bamboo, Yosemite and Yellowstone) ---------------------------------------- Stream benchmark results ------------------------------------------------------------- diff --git a/doc/README.Modem b/doc/README.Modem deleted file mode 100644 index 1613c11cad..0000000000 --- a/doc/README.Modem +++ /dev/null @@ -1,72 +0,0 @@ -How to configure modem support in U-Boot : - -1. Define modem initialization strings: ---------------------------------------- - -The modem initialization strings have following format: - - mdm_init1=<AT-command> - mdm_init2=<AT-command> - ... - -Turning off modem verbose responses with ATV0 or ATQ1 is not allowed; -U-Boot analyzes only verbose (not numeric) result codes. Modem local -command echo can be turned off (ATE0). - -2. RTS/CTS hardware flow control: ---------------------------------- - -You may wish to enable RTS/CTS hardware flow control, if the board's -UART driver supports it (see CONFIG_HWFLOW compile-time flag in -config/<board>.h). This is controlled by the 'mdm_flow_control' -environment variable: - - 'mdm_flow_control=rts/cts' - to enable RTS/CTS flow control. - 'mdm_flow_control=none ' - to disable. - - -The following are the examples using a Rockwell OEM modem -configuration: - -SAMSUNG # setenv mdm_init1 ATZ - reset the modem to - the factory defaults. -SAMSUNG # setenv mdm_init2 ATS0=1 - set modem into - answer mode. -SAMSUNG # setenv mdm_flow_control rts/cts - enable serial port - flow control -SAMSUNG # saveenv - -The example above initializes modem into answer mode to wait for the -incoming call. RTS/CTS flow control is enabled for the serial port. -(The RTS/CTS flow control is enabled by default on the modem). - - -SAMSUNG # setenv mdm_init1 ATZ -SAMSUNG # setenv mdm_init2 ATS39=0+IFC=0,0 - disable modem - RTS/CTS flow control -SAMSUNG # setenv mdm_init3 ATDT1643973 - dial out the number -SAMSUNG # setenv mdm_flow_control none -SAMSUNG # saveenv - -The example above initializes modem to dial-up connection on the -number 1643973. Flow control is disabled. - -Note that flow control must be turned both off or both on for the -board serial port and for the modem. - - -If the connection was set up successfully, the U-Boot prompt appears -on the terminal console. If not (U-Boot modem was configured for -originating the call and connection was not established) - the board -should be reset for another dial-up try. - - -Note on the SMDK2400 board: ---------------------------- - -Since the board serial ports does not have DTR signal wired, modem -should be told to ignore port DTR setting prior to connection to the -SMDK board, and this setting should be stored in modem NVRAM. For the -Rockwell OEM modem this can to be done with the following command: - -AT&D0&W diff --git a/doc/README.arm64 b/doc/README.arm64 index f32108feb7..de669cb6d7 100644 --- a/doc/README.arm64 +++ b/doc/README.arm64 @@ -1,20 +1,20 @@ -U-boot for arm64 +U-Boot for arm64 Summary ======= -No hardware platform of arm64 is available now. The u-boot is +No hardware platform of arm64 is available now. The U-Boot is simulated on Foundation Model and Fast Model for ARMv8. Notes ===== -1. Currenly, u-boot run at the highest exception level processor +1. Currenly, U-Boot run at the highest exception level processor supported and jump to EL2 or optionally EL1 before enter OS. -2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc +2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc use rela relocation format, a tool(tools/relocate-rela) by Scott Wood is used to encode the initial addend of rela to u-boot.bin. After running, - the u-boot will be relocated to destination again. + the U-Boot will be relocated to destination again. 3. Fdt should be placed at a 2-megabyte boundary and within the first 512 megabytes from the start of the kernel image. So, fdt_high should be diff --git a/doc/README.b4860qds b/doc/README.b4860qds index 6fcc3bd6e8..889c8a9842 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -227,15 +227,15 @@ Start Address End Address Description Size NOR Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB -0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB -0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB +0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB +0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB 0xED300000 0xEDEFFFFF rootfs (current bank) 12MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB @@ -246,7 +246,7 @@ Various Software configurations/environment variables/commands -------------------------------------------------------------- The below commands apply to both B4860QDS and B4420QDS. -1. U-boot environment variable hwconfig +1. U-Boot environment variable hwconfig The default hwconfig is: hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: dr_mode=host,phy_type=ulpi @@ -267,7 +267,7 @@ The below commands apply to both B4860QDS and B4420QDS. 4. To change personality of board For changing personality from B4860 to B4420 1)Boot from vbank0 - 2)Flash vbank2 with b4420 rcw and u-boot + 2)Flash vbank2 with b4420 rcw and U-Boot 3)Give following commands to uboot prompt => mw.b ffdf0040 0x30; => mw.b ffdf0010 0x00; @@ -309,7 +309,7 @@ The below commands apply to both B4860QDS and B4420QDS. When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G SGMII on SGMII riser card. - Under U-boot these network interfaces are recognized as: + Under U-Boot these network interfaces are recognized as: FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6. On Linux the interfaces are renamed as: @@ -322,7 +322,7 @@ The below commands apply to both B4860QDS and B4420QDS. Serdes protocosl tested: 0x18, 0x9e (serdes1, serdes2) - Under U-boot these network interfaces are recognized as: + Under U-Boot these network interfaces are recognized as: FM1@DTSEC3, FM1@DTSEC4 and e1000#0. On Linux the interfaces are renamed as: @@ -333,8 +333,8 @@ NAND boot with 2 Stage boot loader ---------------------------------- PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. SPL further initialise DDR using SPD and environment variables and copy -u-boot(768 KB) from flash to DDR. -Finally SPL transer control to u-boot for futher booting. +U-Boot(768 KB) from flash to DDR. +Finally SPL transer control to U-Boot for futher booting. SPL has following features: - Executes within 256K @@ -355,12 +355,12 @@ SPL has following features: ----------------------------------------------- STACK | 0xFFFD8000 (22KB) | ----------------------------------------------- - U-boot SPL | 0xFFFD8000 (160KB) | + U-Boot SPL | 0xFFFD8000 (160KB) | ----------------------------------------------- NAND Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size -0x000000 0x0FFFFF u-boot 1MB -0x140000 0x15FFFF u-boot env 128KB +0x000000 0x0FFFFF U-Boot 1MB +0x140000 0x15FFFF U-Boot env 128KB 0x1A0000 0x1BFFFF FMAN Ucode 128KB diff --git a/doc/README.clang b/doc/README.clang index fe36909449..7ce5ae4867 100644 --- a/doc/README.clang +++ b/doc/README.clang @@ -1,4 +1,4 @@ -The biggest problem when trying to compile U-boot with clang is that +The biggest problem when trying to compile U-Boot with clang is that almost all archs rely on storing gd in a global register and clang user manual states: "clang does not support global register variables; this is unlikely to be implemented soon because it requires additional LLVM @@ -17,9 +17,9 @@ will also fail to compile, but there is in no strict reason to do so in the ARM world, since crt0.S takes care of this. These assignments can be avoided by changing the init calls but this is not in mainline yet. -NOTE: without the -mllvm -arm-use-movt=0 flags u-boot will compile +NOTE: without the -mllvm -arm-use-movt=0 flags U-Boot will compile fine, but llvm might hardcode addresses in movw / movt pairs, which -cannot be relocated and u-boot will fail at runtime. +cannot be relocated and U-Boot will fail at runtime. Debian (based) -------------- @@ -45,7 +45,7 @@ export CROSS_COMPILE=arm-gnueabi-freebsd- gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8 -Given that u-boot will default to gcc, above commands can be +Given that U-Boot will default to gcc, above commands can be simplified with a simple wrapper script, listed below. /usr/local/bin/arm-gnueabi-freebsd-gcc diff --git a/doc/README.distro b/doc/README.distro index 3715c8c3ba..e1b7216152 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -243,7 +243,7 @@ kernel_addr_r: A size of 16MB for the kernel is likely adequate. -pxe_addr_r: +pxefile_addr_r: Mandatory. The location in RAM where extlinux.conf will be loaded to prior to processing. diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 30e05da574..ed7e47d728 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -1,4 +1,4 @@ -U-boot config options used in fec_mxc.c +U-Boot config options used in fec_mxc.c CONFIG_FEC_MXC Selects fec_mxc.c to be compiled into u-boot. Can read out the diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 1243a12227..cd71ec8e16 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -61,7 +61,7 @@ The ways to configure the ddr interleaving mode "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... -2. Run u-boot "setenv" command to configure the memory interleaving mode. +2. Run U-Boot "setenv" command to configure the memory interleaving mode. Either numerical or string value is accepted. # disable memory controller interleaving @@ -125,7 +125,7 @@ hwconfig=fsl_ddr:ecc=off Memory testing options for mpc85xx ================================== -1. Memory test can be done once U-boot prompt comes up using mtest, or +1. Memory test can be done once U-Boot prompt comes up using mtest, or 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. @@ -267,7 +267,7 @@ For DDR parameter tuning up and debugging, the interactive DDR debugger can be activated by setting the environment variable "ddr_interactive" to any value. (The value of ddr_interactive may have a meaning in the future, but, for now, the presence of the variable will cause the debugger to run.) Once -activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR +activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR controller. The available commands are printed by typing "help". Another way to enter the interactive DDR debugger without setting the @@ -275,7 +275,7 @@ environment variable is to send the 'd' character early during the boot process. To save booting time, no additional delay is added, so the window to send the key press is very short -- basically, it is the time before the memory controller code starts to run. For example, when rebooting from -within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to +within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to initiate a 'reset' command. In case of power on/reset, the user can hold down the 'd' key while applying power or hitting the board's reset button. @@ -341,7 +341,7 @@ help no argument - print a list of all commands go - no argument - program memory controller(s) and continue with U-boot + no argument - program memory controller(s) and continue with U-Boot Examples of debugging flow diff --git a/doc/README.imx6 b/doc/README.imx6 index 7c9a4ac5c6..1823fb2c9d 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -37,7 +37,7 @@ As the fuses are arranged in banks of 8 words: bank = 4 word = 2 -And the U-boot command would be: +And the U-Boot command would be: => fuse read 4 2 Reading bank 4: @@ -58,7 +58,7 @@ As the fuses are arranged in banks of 8 words: bank = 4 word = 3 -And the U-boot command would be: +And the U-Boot command would be: => fuse read 4 3 Reading bank 4: diff --git a/doc/README.m68k b/doc/README.m68k index c85febc1f1..9d5c08f768 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -17,7 +17,7 @@ Motorola M68K series of CPUs. Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola Coldfire architecture. The patches of Bernhard support the MCF5272 and MCF5282. A great disadvantage of these patches was that they needed -a pre-bootloader to start u-boot. Because of this, a new port was +a pre-bootloader to start U-Boot. Because of this, a new port was created which no longer needs a first stage booter. Although this port is intended to cover all M68k processors, only @@ -53,8 +53,8 @@ To configure the board, type: make M5272C3_config U-Boot Memory Map: ------------------ -0xffe00000 - 0xffe3ffff u-boot -0xffe04000 - 0xffe05fff environment (embedded in u-boot!) +0xffe00000 - 0xffe3ffff U-Boot +0xffe04000 - 0xffe05fff environment (embedded in U-Boot!) 0xffe40000 - 0xffffffff free for linux/applications @@ -65,13 +65,13 @@ Board specific code is located in: board/m5282evb To configure the board, type: make M5272C3_config At the moment the code isn't fully implemented and still needs a pre-loader! -The preloader must initialize the processor and then start u-boot. The board +The preloader must initialize the processor and then start U-Boot. The board must be configured for a pre-loader (see 4.1) For the preloader, please see http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html -U-boot is configured to run at 0x20000 at default. This can be configured by +U-Boot is configured to run at 0x20000 at default. This can be configured by change CONFIG_SYS_TEXT_BASE in board/m5282evb/config.mk and CONFIG_SYS_MONITOR_BASE in include/configs/M5282EVB.h. @@ -91,10 +91,10 @@ make EB+MCF-EV123_internal_config for internal FLASH 4.1 Configuration to use a pre-loader ------------------------------------- -If u-boot should be loaded to RAM and started by a pre-loader +If U-Boot should be loaded to RAM and started by a pre-loader CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the initial vector table and basic processor initialization will not -be compiled in. The start address of u-boot must be adjusted in +be compiled in. The start address of U-Boot must be adjusted in the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile (CONFIG_SYS_TEXT_BASE) to the load address. @@ -105,7 +105,7 @@ CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs CONFIG_M5272 -- defined for all Motorola MCF5272 CPUs CONFIG_MONITOR_IS_IN_RAM - -- defined if u-boot is loaded by a pre-loader + -- defined if U-Boot is loaded by a pre-loader CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registers CONFIG_SYS_INIT_RAM_ADDR @@ -130,7 +130,7 @@ CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs CONFIG_M5282 -- defined for all Motorola MCF5282 CPUs CONFIG_MONITOR_IS_IN_RAM - -- defined if u-boot is loaded by a pre-loader + -- defined if U-Boot is loaded by a pre-loader CONFIG_SYS_MBAR -- defines the base address of the MCF5282 internal register space CONFIG_SYS_INIT_RAM_ADDR diff --git a/doc/README.malta b/doc/README.malta index c8db8a0c39..8614696a57 100644 --- a/doc/README.malta +++ b/doc/README.malta @@ -13,4 +13,4 @@ How to flash using a MIPS Navigator Probe: reset flash-boot /path/to/u-boot/u-boot.bin - - You should now be able to reboot your Malta to a U-boot shell. + - You should now be able to reboot your Malta to a U-Boot shell. diff --git a/doc/README.menu b/doc/README.menu index ad520ab3aa..cf142314d3 100644 --- a/doc/README.menu +++ b/doc/README.menu @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -U-boot provides a set of interfaces for creating and using simple, text +U-Boot provides a set of interfaces for creating and using simple, text based menus. Menus are displayed as lists of labeled entries on the console, and an entry can be selected by entering its label. diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads index d4561034b8..7a8b706a78 100644 --- a/doc/README.mpc83xxads +++ b/doc/README.mpc83xxads @@ -80,7 +80,7 @@ Freescale MPC83xx ADS Boards tftp 10000 u-boot.bin -5.1 Reflash U-boot Image using U-boot +5.1 Reflash U-Boot Image using U-Boot tftp 10000 u-boot.bin protect off fe000000 fe09ffff diff --git a/doc/README.mpc85xx-spin-table b/doc/README.mpc85xx-spin-table index 8da768a2a6..72c7bd7b5d 100644 --- a/doc/README.mpc85xx-spin-table +++ b/doc/README.mpc85xx-spin-table @@ -1,7 +1,7 @@ Spin table in cache ===================================== As specified by ePAPR v1.1, the spin table needs to be in cached memory. After -DDR is initialized and U-boot relocates itself into DDR, the spin table is +DDR is initialized and U-Boot relocates itself into DDR, the spin table is accessible for core 0. It is part of release.S, within 4KB range after __secondary_start_page. For other cores to use the spin table, the booting process is described below: diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index 28bbcbe095..ef92739756 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -107,7 +107,7 @@ Updated 13-July-2004 Jon Loeliger 2. MEMORY MAP TO WORK WITH LINUX KERNEL 2.1. For the initial bringup, we adopted a consistent memory scheme - between u-boot and linux kernel, you can customize it based on your + between U-Boot and linux kernel, you can customize it based on your system requirements: 0x0000_0000 0x7fff_ffff DDR 2G @@ -192,7 +192,7 @@ straightforward. and future revisions of 8540/8560. -4.4 Reflash U-boot Image using U-boot +4.4 Reflash U-Boot Image using U-Boot tftp 10000 u-boot.bin protect off fff80000 ffffffff diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds index bc5db0ca8e..79d71cb37f 100644 --- a/doc/README.mpc85xxcds +++ b/doc/README.mpc85xxcds @@ -25,7 +25,7 @@ The 85xx CDS code base is known to compile using: Memory Map ---------- -The memory map for u-boot and linux has been extended w.r.t. the ADS +The memory map for U-Boot and linux has been extended w.r.t. the ADS platform to allow for utilization of all 85xx CDS devices. The memory map is setup for linux to operate properly. The linux source when configured for MPC85xx CDS has been updated to reflect the new memory @@ -55,14 +55,14 @@ The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000). There is a switch which allows the boot-bank to be selected. The switch settings for updating flash are given below. -The u-boot commands for copying the boot-bank into the secondary bank are +The U-Boot commands for copying the boot-bank into the secondary bank are as follows: erase ff780000 ff7fffff cp.b fff80000 ff780000 80000 -U-boot/kermit commands for downloading an image, then copying +U-Boot/kermit commands for downloading an image, then copying it into the secondary bank: loadb @@ -76,7 +76,7 @@ it into the secondary bank: cp.b $loadaddr ff780000 80000 -U-boot commands for downloading an image via tftp and flashing +U-Boot commands for downloading an image via tftp and flashing it into the second bank: tftp 10000 <u-boot.bin.image> @@ -211,7 +211,7 @@ Memory Map: Flash Bank 2 @ 0xff000000 Ram @ 0 -Commands for downloading a u-boot image to memory from edink: +Commands for downloading a U-Boot image to memory from edink: env -c time -s 4/8/2004 4:30p diff --git a/doc/README.mxs b/doc/README.mxs index ed2e568856..6ea73b9d5b 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -1,4 +1,4 @@ -Booting U-boot on a MXS processor +Booting U-Boot on a MXS processor ================================= This document describes the MXS U-Boot port. This document mostly covers topics @@ -23,7 +23,7 @@ Contents 2) Compiling U-Boot for a MXS based board 3) Installation of U-Boot for a MXS based board to SD card 4) Installation of U-Boot into NAND flash on a MX28 based board -5) Installation of U-boot into SPI NOR flash on a MX28 based board +5) Installation of U-Boot into SPI NOR flash on a MX28 based board 1) Prerequisites ---------------- @@ -95,19 +95,19 @@ Next, configure U-Boot for a MXS based board Examples: -1. For building U-boot for Denx M28EVK board: +1. For building U-Boot for Denx M28EVK board: $ make m28evk_config -2. For building U-boot for Freescale MX28EVK board: +2. For building U-Boot for Freescale MX28EVK board: $ make mx28evk_config -3. For building U-boot for Freescale MX23EVK board: +3. For building U-Boot for Freescale MX23EVK board: $ make mx23evk_config -4. For building U-boot for Olimex MX23 Olinuxino board: +4. For building U-Boot for Olimex MX23 Olinuxino board: $ make mx23_olinuxino_config @@ -267,7 +267,7 @@ There are two possibilities when preparing an image writable to NAND flash. 5) Installation of U-Boot into SPI NOR flash on a MX28 based board ------------------------------------------------------------------ -The u-boot.sb file can be directly written to SPI NOR from U-boot prompt. +The u-boot.sb file can be directly written to SPI NOR from U-Boot prompt. Load u-boot.sb into RAM, this can be done in several ways and one way is to use tftp: @@ -278,7 +278,7 @@ Probe the SPI NOR flash: (SPI NOR should be succesfully detected in this step) -Erase the blocks where U-boot binary will be written to: +Erase the blocks where U-Boot binary will be written to: => sf erase 0x0 0x80000 Write u-boot.sb to SPI NOR: @@ -287,4 +287,4 @@ Write u-boot.sb to SPI NOR: Power off the board and set the boot mode DIP switches to boot from the SPI NOR according to MX28 manual section 12.2.1 (Table 12-2) -Last step is to power up the board and U-boot should start from SPI NOR. +Last step is to power up the board and U-Boot should start from SPI NOR. diff --git a/doc/README.odroid b/doc/README.odroid index 8a004ca6ba..ef243d1bde 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -1,4 +1,4 @@ - U-boot for Odroid X2/U3/XU3 + U-Boot for Odroid X2/U3/XU3 ======================== 1. Summary @@ -36,7 +36,7 @@ https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel 4. Boot media layout ==================== -The table below shows SD/eMMC cards layout for U-boot. +The table below shows SD/eMMC cards layout for U-Boot. The block offset is starting from 0 and the block size is 512B. ------------------------------------- | Binary | Block offset| part type | @@ -44,7 +44,7 @@ The block offset is starting from 0 and the block size is 512B. ------------------------------------- | Bl1 | 1 | 0 | 1 (boot) | | Bl2 | 31 | 30 | 1 (boot) | -| U-boot | 63 | 62 | 1 (boot) | +| U-Boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | | Uboot Env | 2560 | 2560 | 0 (user) | ------------------------------------- @@ -62,18 +62,18 @@ From the downloaded files, You can find: without problem) This is all you need to boot this board. But if you want to use your custom -u-boot then you need to change u-boot.bin with your own u-boot binary* +U-Boot then you need to change u-boot.bin with your own U-Boot binary* and run the script "sd_fusing.sh" - this script is valid only for SD card. *note: -The proper binary file of current U-boot is u-boot-dtb.bin. +The proper binary file of current U-Boot is u-boot-dtb.bin. quick steps for Linux: - Download all files from the link at point 3 and extract it if needed. - put any SD card into the SD reader - check the device with "dmesg" - run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) -Check if Hardkernel U-boot is booting, and next do the same with your U-boot. +Check if Hardkernel U-Boot is booting, and next do the same with your U-Boot. 6. Prepare the eMMC boot card with a eMMC card reader (boot from eMMC card slot) @@ -92,19 +92,19 @@ eMMC partition - its size is usually very small, about 1-4 MiB. If you have an eMMC->microSD adapter you can prepare the card as in point 5. But then the device can boot only from the SD card slot. -8. Prepare the boot media using Hardkernel U-boot +8. Prepare the boot media using Hardkernel U-Boot ================================================= -You can update the U-boot to the custom one if you have a working bootloader +You can update the U-Boot to the custom one if you have a working bootloader delivered with the board on the eMMC/SD card. Then follow the steps: - install the android fastboot tool - connect a micro usb cable to the board -- on the U-boot prompt, run command: fastboot (as a root) +- on the U-Boot prompt, run command: fastboot (as a root) - on the host, run command: "fastboot flash bootloader u-boot-dtb.bin" -- the custom U-boot should start after the board resets. +- the custom U-Boot should start after the board resets. 9. Partition layout ==================== -Default U-boot environment is setup for fixed partition layout. +Default U-Boot environment is setup for fixed partition layout. Partition table: MSDOS. Disk layout and files as listed in the table below. ----- ------ ------ ------ -------- --------------------------------- diff --git a/doc/README.pxe b/doc/README.pxe index bd175eb22d..cc182c972d 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -5,8 +5,8 @@ */ The 'pxe' commands provide a near subset of the functionality provided by -the PXELINUX boot loader. This allows U-boot based systems to be controlled -remotely using the same PXE based techniques that many non U-boot based servers +the PXELINUX boot loader. This allows U-Boot based systems to be controlled +remotely using the same PXE based techniques that many non U-Boot based servers use. Commands @@ -99,7 +99,7 @@ with # are treated as comments. White space between and at the beginning of lines is ignored. The size of pxe files and the number of labels is only limited by the amount -of RAM available to U-boot. Memory for labels is dynamically allocated as +of RAM available to U-Boot. Memory for labels is dynamically allocated as they're parsed, and memory for pxe files is statically allocated, and its location is given by the pxefile_addr_r environment variable. The pxe code is not aware of the size of the pxefile memory and will outgrow it if pxe files @@ -206,38 +206,38 @@ to be downloaded, and boot with the command line "root=/dev/sdb1" Differences with PXELINUX ========================= -The biggest difference between U-boot's pxe and PXELINUX is that since -U-boot's pxe support is written entirely in C, it can run on any platform -with network support in U-boot. Here are some other differences between -PXELINUX and U-boot's pxe support. +The biggest difference between U-Boot's pxe and PXELINUX is that since +U-Boot's pxe support is written entirely in C, it can run on any platform +with network support in U-Boot. Here are some other differences between +PXELINUX and U-Boot's pxe support. -- U-boot's pxe does not support the PXELINUX DHCP option codes specified +- U-Boot's pxe does not support the PXELINUX DHCP option codes specified in RFC 5071, but could be extended to do so. -- when U-boot's pxe fails to boot, it will return control to U-boot, - allowing another command to run, other U-boot command, instead of resetting +- when U-Boot's pxe fails to boot, it will return control to U-Boot, + allowing another command to run, other U-Boot command, instead of resetting the machine like PXELINUX. -- U-boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it - only uses U-boot. +- U-Boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it + only uses U-Boot. -- U-boot's pxe doesn't provide the full menu implementation that PXELINUX +- U-Boot's pxe doesn't provide the full menu implementation that PXELINUX does, only a simple text based menu using the commands described in this README. With PXELINUX, it's possible to have a graphical boot - menu, submenus, passwords, etc. U-boot's pxe could be extended to support + menu, submenus, passwords, etc. U-Boot's pxe could be extended to support a more robust menuing system like that of PXELINUX's. -- U-boot's pxe expects U-boot uimg's as kernels. Anything that would work - with the 'bootm' command in U-boot could work with the 'pxe boot' command. +- U-Boot's pxe expects U-Boot uimg's as kernels. Anything that would work + with the 'bootm' command in U-Boot could work with the 'pxe boot' command. -- U-boot's pxe only recognizes a single file on the initrd command line. It +- U-Boot's pxe only recognizes a single file on the initrd command line. It could be extended to support multiple. -- in U-boot's pxe, the localboot command doesn't necessarily cause a local +- in U-Boot's pxe, the localboot command doesn't necessarily cause a local disk boot - it will do whatever is defined in the 'localcmd' env variable. And since it doesn't support a full UNDI/PXE stack, the type field is ignored. -- the interactive prompt in U-boot's pxe only allows you to choose a label +- the interactive prompt in U-Boot's pxe only allows you to choose a label from the menu. If you want to boot something not listed, you can ctrl+c - out of 'pxe boot' and use existing U-boot commands to accomplish it. + out of 'pxe boot' and use existing U-Boot commands to accomplish it. diff --git a/doc/README.qemu-mips b/doc/README.qemu-mips index a192752f4d..3940fac603 100644 --- a/doc/README.qemu-mips +++ b/doc/README.qemu-mips @@ -157,7 +157,7 @@ This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux- (gdb) target remote localhost:1234 Remote debugging using localhost:1234 _start () at start.S:64 -64 RVECENT(reset,0) /* U-boot entry point */ +64 RVECENT(reset,0) /* U-Boot entry point */ Current language: auto; currently asm (gdb) b board.c:289 Breakpoint 1 at 0xbfc00cc8: file board.c, line 289. diff --git a/doc/README.sata b/doc/README.sata index d0ce6673b0..b1104bbd3b 100644 --- a/doc/README.sata +++ b/doc/README.sata @@ -1,4 +1,4 @@ -1. SATA usage in U-boot +1. SATA usage in U-Boot There are two ways to operate the hard disk @@ -45,9 +45,9 @@ SATA device 0: Model: ST3320620AS Firm: 3.AAD Ser#: 4QF01ZTN boot => bootm 200000 1000000 2000000 -1.3 How to load an image from an ext2 file system in U-boot? +1.3 How to load an image from an ext2 file system in U-Boot? - U-boot doesn't support writing to an ext2 file system, so the + U-Boot doesn't support writing to an ext2 file system, so the files must be written by other means (e.g. linux). => ext2ls sata 0:1 / diff --git a/doc/README.uniphier b/doc/README.uniphier index bce70cf5fe..bcf0ac3d4b 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -68,8 +68,8 @@ Burn U-Boot images to NAND -------------------------- Write two files to the NAND device as follows: - - spl/u-boot-spl-dtb.bin at the offset address 0x00000000 - - u-boot-dtb.img at the offset address 0x00010000 + - spl/u-boot-spl.bin at the offset address 0x00000000 + - u-boot.img at the offset address 0x00010000 If a TFTP server is available, the images can be easily updated. Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public @@ -145,4 +145,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada <yamada.masahiro@socionext.com> -Aug. 2015 +Feb. 2016 diff --git a/doc/README.video b/doc/README.video index 62ac17b049..e7ae98aa5d 100644 --- a/doc/README.video +++ b/doc/README.video @@ -32,13 +32,13 @@ The driver has been tested with the following configurations: Example: video-mode=fslfb:1280x1024-32@60,monitor=dvi -U-boot sunxi video controller driver +U-Boot sunxi video controller driver ==================================== -U-boot supports hdmi and lcd output on Allwinner sunxi SoCs, lcd output +U-Boot supports hdmi and lcd output on Allwinner sunxi SoCs, lcd output requires the CONFIG_VIDEO_LCD_MODE Kconfig value to be set. -The sunxi u-boot driver supports the following video-mode options: +The sunxi U-Boot driver supports the following video-mode options: - monitor=[none|dvi|hdmi|lcd|vga|composite-*] - Select the video output to use none: Disable video output. diff --git a/doc/README.x86 b/doc/README.x86 index 6d9cb10edc..d3fea5d56f 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -133,18 +133,49 @@ $ make all --- -Intel Minnowboard Max instructions for bare mode: +Intel Cougar Canyon 2 specific instructions for bare mode: + +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the +time of writing) in the board directory and rename it to fsp.bin. + +Now build U-Boot and obtain u-boot.rom + +$ make cougarcanyon2_defconfig +$ make all + +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program +this image to the SPI-0 flash according to the board manual just once and we are +all set. For programming U-Boot we just need to program SPI-1 flash. + +--- + +Intel Bay Trail based board instructions for bare mode: This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Two boards that use this configuration are Bayley Bay and Minnowboard MAX. Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at -the time of writing). Put it in the board directory: -board/intel/minnowmax/fsp.bin +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same -directory: board/intel/minnowmax/vga.bin +board directory as vga.bin. -You still need two more binary blobs. The first comes from the original -firmware image available from: +You still need two more binary blobs. For Bayley Bay, they can be extracted +from the sample SPI image provided in the FSP (SPI.bin at the time of writing). + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin + $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin + +For Minnowboard MAX, we can reuse the same ME firmware above, but for flash +descriptor, we need get that somewhere else, as the one above does not seem to +work, probably because it is not designed for the Minnowboard MAX. Now download +the original firmware image for this board from: http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip @@ -161,16 +192,8 @@ This will provide the descriptor file - copy this into the correct place: $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin -Then do the same with the sample SPI image provided in the FSP (SPI.bin at -the time of writing) to obtain the last image. Note that this will also -produce a flash descriptor file, but it does not seem to work, probably -because it is not designed for the Minnowmax. That is why you need to get -the flash descriptor from the original firmware as above. - - $ ./tools/ifdtool -x BayleyBay/SPI.bin - $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin - Now you can build U-Boot and obtain u-boot.rom +Note: below are examples/information for Minnowboard MAX. $ make minnowmax_defconfig $ make all @@ -221,7 +244,9 @@ Now you can build U-Boot and obtain u-boot.rom $ make galileo_defconfig $ make all -QEMU x86 target instructions: +--- + +QEMU x86 target instructions for bare mode: To build u-boot.rom for QEMU x86 targets, just simply run diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash index 1b86d01a0e..9064739c3e 100644 --- a/doc/SPI/README.ti_qspi_flash +++ b/doc/SPI/README.ti_qspi_flash @@ -1,4 +1,4 @@ -QSPI U-boot support +QSPI U-Boot support ------------------ Host processor is connected to serial flash device via qpsi @@ -44,4 +44,4 @@ drivers/qspi/ti_qspi.c Testing ------- A seperated file named README.dra_qspi_test has been created which gives all the -details about the commands required to test qspi at u-boot level. +details about the commands required to test qspi at U-Boot level. diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index e5e482e30b..61f2da323e 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -1,23 +1,17 @@ How to port a serial driver to driver model =========================================== -About 16 of 33 serial drivers have been converted as at September 2015. It -is time for maintainers to start converting over the remaining serial drivers: +Almost all of the serial drivers have been converted as at January 2016. These +ones remain: arm_dcc.c - lpc32xx_hsuart.c mcfuart.c - mxs_auart.c - opencores_yanu.c serial_bfin.c - serial_imx.c - serial_max3100.c serial_pxa.c serial_s3c24x0.c - serial_sa1100.c - usbtty.c -You should complete this by the end of January 2016. +The deadline for this work was the end of January 2016. If no one steps +forward to convert these, at some point there may come a patch to remove them! Here is a suggested approach for converting your serial driver over to driver model. Please feel free to update this file with your ideas and suggestions. diff --git a/doc/uImage.FIT/kernel.its b/doc/uImage.FIT/kernel.its index 539cdbfafe..e668c3f6e7 100644 --- a/doc/uImage.FIT/kernel.its +++ b/doc/uImage.FIT/kernel.its @@ -1,5 +1,5 @@ /* - * Simple U-boot uImage source file containing a single kernel + * Simple U-Boot uImage source file containing a single kernel */ /dts-v1/; diff --git a/doc/uImage.FIT/kernel_fdt.its b/doc/uImage.FIT/kernel_fdt.its index 7e940d2af9..7c521486ef 100644 --- a/doc/uImage.FIT/kernel_fdt.its +++ b/doc/uImage.FIT/kernel_fdt.its @@ -1,5 +1,5 @@ /* - * Simple U-boot uImage source file containing a single kernel and FDT blob + * Simple U-Boot uImage source file containing a single kernel and FDT blob */ /dts-v1/; diff --git a/doc/uImage.FIT/multi.its b/doc/uImage.FIT/multi.its index 881b74952d..37369ecc82 100644 --- a/doc/uImage.FIT/multi.its +++ b/doc/uImage.FIT/multi.its @@ -1,5 +1,5 @@ /* - * U-boot uImage source file with multiple kernels, ramdisks and FDT blobs + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs */ /dts-v1/; diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 029f481893..3175c9f0b7 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -1,4 +1,4 @@ -U-boot new uImage source file format (bindings definition) +U-Boot new uImage source file format (bindings definition) ========================================================== Author: Marian Balakowicz <m8@semihalf.com> @@ -14,7 +14,7 @@ Booting with a Flattened Device Tree is much more flexible and is intended to replace direct passing of 'struct bd_info' which was used to boot pre-FDT kernels. -However, U-boot needs to support both techniques to provide backward +However, U-Boot needs to support both techniques to provide backward compatibility for platforms which are not FDT ready. Number of elements playing role in the booting process has increased and now includes the FDT blob. Kernel image, FDT blob and possibly ramdisk image - all must be placed @@ -36,15 +36,15 @@ a) Implementation Libfdt has been selected for the new uImage format implementation as (1) it provides needed functionality, (2) is actively maintained and developed and -(3) increases code reuse as it is already part of the U-boot source tree. +(3) increases code reuse as it is already part of the U-Boot source tree. b) Terminology This document defines new uImage structure by providing FDT bindings for new -uImage internals. Bindings are defined from U-boot perspective, i.e. describe -final form of the uImage at the moment when it reaches U-boot. User +uImage internals. Bindings are defined from U-Boot perspective, i.e. describe +final form of the uImage at the moment when it reaches U-Boot. User perspective may be simpler, as some of the properties (like timestamps and -hashes) will need to be filled in automatically by the U-boot mkimage tool. +hashes) will need to be filled in automatically by the U-Boot mkimage tool. To avoid confusion with the kernel FDT the following naming convention is proposed for the new uImage format related terms: @@ -61,7 +61,7 @@ c) Image building procedure The following picture shows how the new uImage is prepared. Input consists of image source file (.its) and a set of data files. Image is created with the -help of standard U-boot mkimage tool which in turn uses dtc (device tree +help of standard U-Boot mkimage tool which in turn uses dtc (device tree compiler) to produce image tree blob (.itb). Resulting .itb file is the actual binary of a new uImage. diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 2c6d42410c..7b6a1558d2 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -83,7 +83,7 @@ struct mvsata_port_registers { * Status codes to return to client callers. Currently, callers ignore * exact value and only care for zero or nonzero, so no need to make this * public, it is only #define'd for clarity. - * If/when standard negative codes are implemented in U-boot, then these + * If/when standard negative codes are implemented in U-Boot, then these * #defines should be moved to, or replaced by ones from, the common list * of status codes. */ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9fcde39b71..a98b74bbc0 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,4 +20,6 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +source "drivers/clk/uniphier/Kconfig" + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c9144e3e1d..c51db1562b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig new file mode 100644 index 0000000000..0e90c01a9a --- /dev/null +++ b/drivers/clk/uniphier/Kconfig @@ -0,0 +1,13 @@ +config CLK_UNIPHIER + bool + select CLK + select SPL_CLK + +menu "Clock drivers for UniPhier SoCs" + depends on CLK_UNIPHIER + +config CLK_UNIPHIER_MIO + bool "Clock driver for UniPhier Media I/O block" + default y + +endmenu diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile new file mode 100644 index 0000000000..a3168f9bc1 --- /dev/null +++ b/drivers/clk/uniphier/Makefile @@ -0,0 +1,3 @@ +obj-y += clk-uniphier-core.o + +obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c new file mode 100644 index 0000000000..e79e0ff689 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <clk.h> +#include <dm/device.h> + +#include "clk-uniphier.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int uniphier_clk_enable(struct udevice *dev, int index) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_gate_data *gate = priv->socdata->gate; + unsigned int nr_gate = priv->socdata->nr_gate; + void __iomem *reg; + u32 mask, data, tmp; + int i; + + for (i = 0; i < nr_gate; i++) { + if (gate[i].index != index) + continue; + + reg = priv->base + gate[i].reg; + mask = gate[i].mask; + data = gate[i].data & mask; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= data & mask; + debug("%s: %p: %08x\n", __func__, reg, tmp); + writel(tmp, reg); + } + + return 0; +} + +static ulong uniphier_clk_get_rate(struct udevice *dev, int index) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_rate_data *rdata = priv->socdata->rate; + unsigned int nr_rdata = priv->socdata->nr_rate; + void __iomem *reg; + u32 mask, data; + ulong matched_rate = 0; + int i; + + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index) + continue; + + if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) + return rdata[i].rate; + + reg = priv->base + rdata[i].reg; + mask = rdata[i].mask; + data = rdata[i].data & mask; + if ((readl(reg) & mask) == data) { + if (matched_rate && rdata[i].rate != matched_rate) { + printf("failed to get clk rate for insane register values\n"); + return -EINVAL; + } + matched_rate = rdata[i].rate; + } + } + + debug("%s: rate = %lu\n", __func__, matched_rate); + + return matched_rate; +} + +static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_rate_data *rdata = priv->socdata->rate; + unsigned int nr_rdata = priv->socdata->nr_rate; + void __iomem *reg; + u32 mask, data, tmp; + ulong best_rate = 0; + int i; + + /* first, decide the best match rate */ + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index) + continue; + + if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) + return 0; + + if (rdata[i].rate > best_rate && rdata[i].rate <= rate) + best_rate = rdata[i].rate; + } + + if (!best_rate) + return -ENODEV; + + debug("%s: requested rate = %lu, set rate = %lu\n", __func__, + rate, best_rate); + + /* second, really set registers */ + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index || rdata[i].rate != best_rate) + continue; + + reg = priv->base + rdata[i].reg; + mask = rdata[i].mask; + data = rdata[i].data & mask; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= data; + debug("%s: %p: %08x\n", __func__, reg, tmp); + writel(tmp, reg); + } + + return best_rate; +} + +const struct clk_ops uniphier_clk_ops = { + .enable = uniphier_clk_enable, + .get_periph_rate = uniphier_clk_get_rate, + .set_periph_rate = uniphier_clk_set_rate, +}; + +int uniphier_clk_probe(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = map_sysmem(addr, size); + if (!priv->base) + return -ENOMEM; + + priv->socdata = (void *)dev_get_driver_data(dev); + + return 0; +} + +int uniphier_clk_remove(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->base); + + return 0; +} diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c new file mode 100644 index 0000000000..d91ae34da1 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <clk.h> +#include <dm/device.h> + +#include "clk-uniphier.h" + +#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x00000100, \ + .data = 0x00000100, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00000000, \ + .rate = 44444444, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00010000, \ + .rate = 33333333, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 50000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 66666666, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001000, \ + .rate = 100000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001100, \ + .rate = 40000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001200, \ + .rate = 25000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001300, \ + .rate = 22222222, \ + } + +#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x30000000, \ + .data = 0x30000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x01000000, \ + .data = 0x01000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x114 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \ + { \ + .index = (idx), \ + .reg = 0x20, \ + .mask = 0x02000000, \ + .data = 0x02000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110, \ + .mask = 0x00020000, \ + .data = 0x00020000, \ + } + +static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { + UNIPHIER_MIO_CLK_GATE_SD(0, 0), + UNIPHIER_MIO_CLK_GATE_SD(1, 1), + UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_MIO_CLK_GATE_USB(0, 3), + UNIPHIER_MIO_CLK_GATE_USB(1, 4), + UNIPHIER_MIO_CLK_GATE_USB(2, 5), + UNIPHIER_MIO_CLK_GATE_DMAC(6), + UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */ +}; + +static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { + UNIPHIER_MIO_CLK_RATE_SD(0, 0), + UNIPHIER_MIO_CLK_RATE_SD(1, 1), + UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ +}; + +static struct uniphier_clk_soc_data uniphier_mio_clk_data = { + .gate = uniphier_mio_clk_gate, + .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), + .rate = uniphier_mio_clk_rate, + .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), +}; + +static const struct udevice_id uniphier_mio_clk_match[] = { + { + .compatible = "socionext,ph1-sld3-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-sld8-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro5-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,proxstream2-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_mio_clk) = { + .name = "uniphier-mio-clk", + .id = UCLASS_CLK, + .of_match = uniphier_mio_clk_match, + .probe = uniphier_clk_probe, + .remove = uniphier_clk_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), + .ops = &uniphier_clk_ops, +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h new file mode 100644 index 0000000000..560b3f8112 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLK_UNIPHIER_H__ +#define __CLK_UNIPHIER_H__ + +#include <linux/kernel.h> + +struct uniphier_clk_gate_data { + int index; + unsigned int reg; + u32 mask; + u32 data; +}; + +struct uniphier_clk_rate_data { + int index; + unsigned int reg; +#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX + u32 mask; + u32 data; + unsigned long rate; +}; + +struct uniphier_clk_soc_data { + struct uniphier_clk_gate_data *gate; + unsigned int nr_gate; + struct uniphier_clk_rate_data *rate; + unsigned int nr_rate; +}; + +#define UNIPHIER_CLK_FIXED_RATE(i, f) \ + { \ + .index = i, \ + .reg = UNIPHIER_CLK_RATE_IS_FIXED, \ + .rate = f, \ + } + +/** + * struct uniphier_clk_priv - private data for UniPhier clock driver + * + * @base: base address of the clock provider + * @socdata: SoC specific data + */ +struct uniphier_clk_priv { + void __iomem *base; + struct uniphier_clk_soc_data *socdata; +}; + +extern const struct clk_ops uniphier_clk_ops; +int uniphier_clk_probe(struct udevice *dev); +int uniphier_clk_remove(struct udevice *dev); + +#endif /* __CLK_UNIPHIER_H__ */ diff --git a/drivers/ddr/marvell/axp/ddr3_hw_training.c b/drivers/ddr/marvell/axp/ddr3_hw_training.c index a8c5e6a534..c8d7041117 100644 --- a/drivers/ddr/marvell/axp/ddr3_hw_training.c +++ b/drivers/ddr/marvell/axp/ddr3_hw_training.c @@ -450,7 +450,7 @@ int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass, ddr3_set_performance_params(&dram_info); if (dram_info.ecc_ena) { - /* Need to SCRUB the DRAM memory area to load U-boot */ + /* Need to SCRUB the DRAM memory area to load U-Boot */ mv_sys_xor_finish(); dram_info.num_cs = 1; dram_info.cs_ena = 1; diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 431e159e48..4448250f5c 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -269,7 +269,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_gbl); + writel(0, &sysmgr_regs->fpgaintfgrp_module); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c index d5cb383e85..db32db6845 100644 --- a/drivers/gpio/db8500_gpio.c +++ b/drivers/gpio/db8500_gpio.c @@ -1,14 +1,14 @@ /* * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. + * copy-paste it to U-Boot. * * Original Linux authors: * Copyright (C) 2008,2009 STMicroelectronics * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> * - * Ported to U-boot by: + * Ported to U-Boot by: * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> * * This program is free software; you can redistribute it and/or modify diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 67bf0a2dd3..527ed6d0fa 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -30,6 +30,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <pch.h> #include <pci.h> #include <asm/gpio.h> #include <asm/io.h> @@ -62,91 +63,6 @@ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) gd->arch.gpio_map = map; } -static int gpio_ich6_get_base(unsigned long base) -{ - pci_dev_t pci_dev; /* handle for 0:1f:0 */ - u8 tmpbyte; - u16 tmpword; - u32 tmplong; - - /* Where should it be? */ - pci_dev = PCI_BDF(0, 0x1f, 0); - - /* Is the device present? */ - tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID); - if (tmpword != PCI_VENDOR_ID_INTEL) { - debug("%s: wrong VendorID %x\n", __func__, tmpword); - return -ENODEV; - } - - tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID); - debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); - /* - * We'd like to validate the Device ID too, but pretty much any - * value is either a) correct with slight differences, or b) - * correct but undocumented. We'll have to check a bunch of other - * things instead... - */ - - /* I/O should already be enabled (it's a RO bit). */ - tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND); - if (!(tmpword & PCI_COMMAND_IO)) { - debug("%s: device IO not enabled\n", __func__); - return -ENODEV; - } - - /* Header Type must be normal (bits 6-0 only; see spec.) */ - tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE); - if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { - debug("%s: invalid Header type\n", __func__); - return -ENODEV; - } - - /* Base Class must be a bridge device */ - tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE); - if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { - debug("%s: invalid class\n", __func__); - return -ENODEV; - } - /* Sub Class must be ISA */ - tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); - if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { - debug("%s: invalid subclass\n", __func__); - return -ENODEV; - } - - /* Programming Interface must be 0x00 (no others exist) */ - tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG); - if (tmpbyte != 0x00) { - debug("%s: invalid interface type\n", __func__); - return -ENODEV; - } - - /* - * GPIOBASE moved to its current offset with ICH6, but prior to - * that it was unused (or undocumented). Check that it looks - * okay: not all ones or zeros. - * - * Note we don't need check bit0 here, because the Tunnel Creek - * GPIO base address register bit0 is reserved (read returns 0), - * while on the Ivybridge the bit0 is used to indicate it is an - * I/O space. - */ - tmplong = x86_pci_read_config32(pci_dev, base); - if (tmplong == 0x00000000 || tmplong == 0xffffffff) { - debug("%s: unexpected BASE value\n", __func__); - return -ENODEV; - } - - /* - * Okay, I guess we're looking at the right device. The actual - * GPIO registers are in the PCI device's I/O space, starting - * at the offset that we just read. Bit 0 indicates that it's - * an I/O address, not a memory address, so mask that off. - */ - return tmplong & 1 ? tmplong & ~3 : tmplong & ~15; -} - static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value) { u32 val; @@ -288,20 +204,26 @@ static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) int gpio_ich6_pinctrl_init(void) { + struct udevice *pch; int pin_node; int node; int ret; - int gpiobase; - int iobase_offset; - int iobase = -1; + u32 gpiobase; + u32 iobase = -1; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; /* * Get the memory/io base address to configure every pins. * IOBASE is used to configure the mode/pads * GPIOBASE is used to configure the direction and default value */ - gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); - if (gpiobase < 0) { + ret = pch_get_gpio_base(pch, &gpiobase); + if (ret) { debug("%s: invalid GPIOBASE address (%08x)\n", __func__, gpiobase); return -EINVAL; @@ -319,16 +241,11 @@ int gpio_ich6_pinctrl_init(void) * Get the IOBASE, this is not mandatory as this is not * supported by all the CPU */ - iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1); - if (iobase_offset == -1) { - debug("%s: io-base offset not present\n", __func__); - } else { - iobase = gpio_ich6_get_base(iobase_offset); - if (IS_ERR_VALUE(iobase)) { - debug("%s: invalid IOBASE address (%08x)\n", __func__, - iobase); - return -EINVAL; - } + ret = pch_get_io_base(pch, &iobase); + if (ret && ret != -ENOSYS) { + debug("%s: invalid IOBASE address (%08x)\n", __func__, + iobase); + return -EINVAL; } for (pin_node = fdt_first_subnode(gd->fdt_blob, node); @@ -349,10 +266,14 @@ int gpio_ich6_pinctrl_init(void) static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { struct ich6_bank_platdata *plat = dev_get_platdata(dev); - u16 gpiobase; + u32 gpiobase; int offset; + int ret; + + ret = pch_get_gpio_base(dev->parent, &gpiobase); + if (ret) + return ret; - gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); if (offset == -1) { debug("%s: Invalid register offset %d\n", __func__, offset); diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 8e880e276f..5a031159ca 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -177,7 +177,10 @@ static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) debug("%s: pin = %d (port %d:bit %d)\n", __func__, gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); + if (get_direction(gpio) == DIRECTION_INPUT) + val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); + else + val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]); return (val >> GPIO_BIT(gpio)) & 1; } diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index 951cbb4481..c77f610769 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -312,6 +312,7 @@ static int tegra_kbd_probe(struct udevice *dev) __func__, ret); return ret; } + input_add_tables(input, false); if (priv->matrix.fn_keycode) { ret = input_add_table(input, KEY_FN, -1, priv->matrix.fn_keycode, @@ -326,7 +327,6 @@ static int tegra_kbd_probe(struct udevice *dev) priv->input = input; input->dev = dev; input->read_keys = tegra_kbc_check; - input_add_tables(input, false); strcpy(sdev->name, "tegra-kbc"); ret = input_stdio_register(sdev); if (ret) { diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e1e3c6b70f..f2b08abf11 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -32,6 +32,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000000..ec53533bde --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h> + +static inline u8 sio1007_read(int port, int reg) +{ + outb(reg, port); + + return inb(port + 1); +} + +static inline void sio1007_write(int port, int reg, int val) +{ + outb(reg, port); + outb(val, port + 1); +} + +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{ + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); +} + +void sio1007_enable_serial(int port, int num, int iobase, int irq) +{ + if (num < 0 || num > SIO1007_UART_NUM) + return; + + /* enter configuration state */ + outb(0x55, port); + + /* power on serial port and set up its i/o base & irq */ + if (!num) { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON); + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4); + } else { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON); + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq); + } + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_enable_runtime(int port, int iobase) +{ + /* enter configuration state */ + outb(0x55, port); + + /* set i/o base for the runtime register block */ + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); + /* turn on address decoding for this block */ + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN); + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{ + int reg = GPIO0_DIR; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DIR; + gpio -= GPIO_NUM_PER_GROUP; + } + + /* enter configuration state */ + outb(0x55, port); + + /* set gpio pin direction, polority and type */ + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio); + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio); + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio); + + /* exit configuration state */ + outb(0xaa, port); +} + +int sio1007_gpio_get_value(int port, int gpio) +{ + int reg = GPIO0_DATA; + int val; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return -EINVAL; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + val = inb(port + reg); + if (val & (1 << gpio)) + return 1; + else + return 0; +} + +void sio1007_gpio_set_value(int port, int gpio, int val) +{ + int reg = GPIO0_DATA; + u8 data; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + data = inb(port + reg); + data &= ~(1 << gpio); + data |= (val << gpio); + outb(data, port + reg); +} diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index cc62c89a25..30e538cc16 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -526,7 +526,7 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, opc = sh_sdhi_set_cmd(host, data, opc); /* - * U-boot cannot use interrupt. + * U-Boot cannot use interrupt. * So this flag may not be clear by timing */ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END); diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 15848658e1..573819a01e 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -674,7 +674,7 @@ void tegra_mmc_init(void) CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { - printf("%s: Error processing T30 mmc node(s)!\n", __func__); + printf("%s: Error processing T210 mmc node(s)!\n", __func__); return; } @@ -684,7 +684,7 @@ void tegra_mmc_init(void) CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { - printf("%s: Error processing T30 mmc node(s)!\n", __func__); + printf("%s: Error processing T124 mmc node(s)!\n", __func__); return; } diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 9a74064c98..2fc73ef4e5 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -71,6 +71,13 @@ config NAND_SUNXI Enable support for NAND. This option allows SPL to read from sunxi NAND using DMA transfers. +config NAND_ARASAN + bool "Configure Arasan Nand" + help + This enables Nand driver support for Arasan nand flash + controller. This uses the hardware ECC for read and + write operations. + comment "Generic NAND options" # Enhance depends when converting drivers to Kconfig which use this config diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index b4e5376176..6fb37182d5 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -42,6 +42,7 @@ ifdef NORMAL_DRIVERS obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o +obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_NAND_DENALI) += denali.o diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c new file mode 100644 index 0000000000..2d73a05e75 --- /dev/null +++ b/drivers/mtd/nand/arasan_nfc.c @@ -0,0 +1,1154 @@ +/* + * Arasan NAND Flash Controller Driver + * + * Copyright (C) 2014 - 2015 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand_ecc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <nand.h> + +struct arasan_nand_info { + void __iomem *nand_base; + u32 page; +}; + +struct nand_regs { + u32 pkt_reg; + u32 memadr_reg1; + u32 memadr_reg2; + u32 cmd_reg; + u32 pgm_reg; + u32 intsts_enr; + u32 intsig_enr; + u32 intsts_reg; + u32 rdy_busy; + u32 cms_sysadr_reg; + u32 flash_sts_reg; + u32 tmg_reg; + u32 buf_dataport; + u32 ecc_reg; + u32 ecc_errcnt_reg; + u32 ecc_sprcmd_reg; + u32 errcnt_1bitreg; + u32 errcnt_2bitreg; + u32 errcnt_3bitreg; + u32 errcnt_4bitreg; + u32 dma_sysadr0_reg; + u32 dma_bufbdry_reg; + u32 cpu_rls_reg; + u32 errcnt_5bitreg; + u32 errcnt_6bitreg; + u32 errcnt_7bitreg; + u32 errcnt_8bitreg; + u32 data_if_reg; +}; + +#define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR) + +struct arasan_nand_command_format { + u8 cmd1; + u8 cmd2; + u8 addr_cycles; + u32 pgm; +}; + +#define ONDIE_ECC_FEATURE_ADDR 0x90 + +#define ARASAN_PROG_RD_MASK 0x00000001 +#define ARASAN_PROG_BLK_ERS_MASK 0x00000004 +#define ARASAN_PROG_RD_ID_MASK 0x00000040 +#define ARASAN_PROG_RD_STS_MASK 0x00000008 +#define ARASAN_PROG_PG_PROG_MASK 0x00000010 +#define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080 +#define ARASAN_PROG_RST_MASK 0x00000100 +#define ARASAN_PROG_GET_FTRS_MASK 0x00000200 +#define ARASAN_PROG_SET_FTRS_MASK 0x00000400 +#define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000 + +#define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000 +#define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF +#define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000 +#define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23 +#define ARASAN_NAND_CMD_CMD2_SHIFT 8 +#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 +#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 + +#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 +#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF +#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 +#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF +#define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 +#define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 +#define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25 + +#define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10 +#define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08 +#define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02 +#define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01 +#define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04 + +#define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000 +#define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF +#define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12 + +#define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F +#define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0 +#define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4 + +#define ARASAN_NAND_ECC_SIZE_SHIFT 16 +#define ARASAN_NAND_ECC_BCH_SHIFT 27 + +#define ARASAN_NAND_PKTSIZE_1K 1024 +#define ARASAN_NAND_PKTSIZE_512 512 + +#define ARASAN_NAND_POLL_TIMEOUT 1000000 +#define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF + +#define ERR_ADDR_CYCLE -1 +#define READ_BUFF_SIZE 0x4000 + +static struct arasan_nand_command_format *curr_cmd; + +enum addr_cycles { + NAND_ADDR_CYCL_NONE, + NAND_ADDR_CYCL_ONE, + NAND_ADDR_CYCL_ROW, + NAND_ADDR_CYCL_COL, + NAND_ADDR_CYCL_BOTH, +}; + +static struct arasan_nand_command_format arasan_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH, + ARASAN_PROG_RD_MASK}, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL, + ARASAN_PROG_RD_MASK}, + {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_RD_ID_MASK}, + {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, + ARASAN_PROG_RD_STS_MASK}, + {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH, + ARASAN_PROG_PG_PROG_MASK}, + {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL, + ARASAN_PROG_CHNG_ROWADR_END_MASK}, + {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW, + ARASAN_PROG_BLK_ERS_MASK}, + {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, + ARASAN_PROG_RST_MASK}, + {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_RD_PARAM_PG_MASK}, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_GET_FTRS_MASK}, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_SET_FTRS_MASK}, + {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0}, +}; + +struct arasan_ecc_matrix { + u32 pagesize; + u32 ecc_codeword_size; + u8 eccbits; + u8 bch; + u8 bchval; + u16 eccaddr; + u16 eccsize; +}; + +static const struct arasan_ecc_matrix ecc_matrix[] = { + {512, 512, 1, 0, 0, 0x20D, 0x3}, + {512, 512, 4, 1, 3, 0x209, 0x7}, + {512, 512, 8, 1, 2, 0x203, 0xD}, + /* + * 2K byte page + */ + {2048, 512, 1, 0, 0, 0x834, 0xC}, + {2048, 512, 4, 1, 3, 0x826, 0x1A}, + {2048, 512, 8, 1, 2, 0x80c, 0x34}, + {2048, 512, 12, 1, 1, 0x822, 0x4E}, + {2048, 512, 16, 1, 0, 0x808, 0x68}, + {2048, 1024, 24, 1, 4, 0x81c, 0x54}, + /* + * 4K byte page + */ + {4096, 512, 1, 0, 0, 0x1068, 0x18}, + {4096, 512, 4, 1, 3, 0x104c, 0x34}, + {4096, 512, 8, 1, 2, 0x1018, 0x68}, + {4096, 512, 12, 1, 1, 0x1044, 0x9C}, + {4096, 512, 16, 1, 0, 0x1010, 0xD0}, + {4096, 1024, 24, 1, 4, 0x1038, 0xA8}, + /* + * 8K byte page + */ + {8192, 512, 1, 0, 0, 0x20d0, 0x30}, + {8192, 512, 4, 1, 3, 0x2098, 0x68}, + {8192, 512, 8, 1, 2, 0x2030, 0xD0}, + {8192, 512, 12, 1, 1, 0x2088, 0x138}, + {8192, 512, 16, 1, 0, 0x2020, 0x1A0}, + {8192, 1024, 24, 1, 4, 0x2070, 0x150}, + /* + * 16K byte page + */ + {16384, 512, 1, 0, 0, 0x4460, 0x60}, + {16384, 512, 4, 1, 3, 0x43f0, 0xD0}, + {16384, 512, 8, 1, 2, 0x4320, 0x1A0}, + {16384, 512, 12, 1, 1, 0x4250, 0x270}, + {16384, 512, 16, 1, 0, 0x4180, 0x340}, + {16384, 1024, 24, 1, 4, 0x4220, 0x2A0} +}; + +static u8 buf_data[READ_BUFF_SIZE]; +static u32 buf_index; + +static struct nand_ecclayout nand_oob; + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) +{ +} + +static void arasan_nand_enable_ecc(void) +{ + u32 reg_val; + + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; + + writel(reg_val, &arasan_nand_base->cmd_reg); +} + +static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) +{ + u8 addrcycles; + struct nand_chip *chip = mtd->priv; + + switch (curr_cmd->addr_cycles) { + case NAND_ADDR_CYCL_NONE: + addrcycles = 0; + break; + case NAND_ADDR_CYCL_ONE: + addrcycles = 1; + break; + case NAND_ADDR_CYCL_ROW: + addrcycles = chip->onfi_params.addr_cycles & + ARASAN_NAND_ROW_ADDR_CYCL_MASK; + break; + case NAND_ADDR_CYCL_COL: + addrcycles = (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + break; + case NAND_ADDR_CYCL_BOTH: + addrcycles = chip->onfi_params.addr_cycles & + ARASAN_NAND_ROW_ADDR_CYCL_MASK; + addrcycles += (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + break; + default: + addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL; + break; + } + return addrcycles; +} + +static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) +{ + struct nand_chip *chip = mtd->priv; + u32 reg_val, i, pktsize, pktnum; + u32 *bufptr = (u32 *)buf; + u32 timeout; + u32 rdcount = 0; + u8 addr_cycles; + + if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) + pktsize = ARASAN_NAND_PKTSIZE_1K; + else + pktsize = ARASAN_NAND_PKTSIZE_512; + + if (size % pktsize) + pktnum = size/pktsize + 1; + else + pktnum = size/pktsize; + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK | + ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | + pktsize; + writel(reg_val, &arasan_nand_base->pkt_reg); + + arasan_nand_enable_ecc(); + addr_cycles = arasan_nand_get_addrcycle(mtd); + if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) + return ERR_ADDR_CYCLE; + + writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) | + NAND_CMD_RNDOUT | (addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT), + &arasan_nand_base->ecc_sprcmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (rdcount < pktnum) { + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) { + puts("arasan_read_page: timedout:Buff RDY\n"); + return -ETIMEDOUT; + } + + rdcount++; + + if (pktnum == rdcount) { + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + } else { + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_reg); + + for (i = 0; i < pktsize/4; i++) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + + bufptr += pktsize/4; + + if (rdcount >= pktnum) + break; + + writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) { + puts("arasan rd_page timedout:Xfer CMPLT\n"); + return -ETIMEDOUT; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + if (readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) { + printf("arasan rd_page:sbiterror\n"); + return -1; + } + + if (readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_ERR_EN_MASK) { + mtd->ecc_stats.failed++; + printf("arasan rd_page:multibiterror\n"); + return -1; + } + + return 0; +} + +static int arasan_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int status; + + status = arasan_nand_read_page(mtd, buf, (mtd->writesize)); + + if (oob_required) + chip->ecc.read_oob(mtd, chip, page); + + return status; +} + +static void arasan_nand_fill_tx(const u8 *buf, int len) +{ + u32 __iomem *nand = &arasan_nand_base->buf_dataport; + + if (((unsigned long)buf & 0x3) != 0) { + if (((unsigned long)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((unsigned long)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + u32 reg_val, i, pktsize, pktnum; + const u32 *bufptr = (const u32 *)buf; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 size = mtd->writesize; + u32 rdcount = 0; + u8 column_addr_cycles; + struct arasan_nand_info *nand = chip->priv; + + if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) + pktsize = ARASAN_NAND_PKTSIZE_1K; + else + pktsize = ARASAN_NAND_PKTSIZE_512; + + if (size % pktsize) + pktnum = size/pktsize + 1; + else + pktnum = size/pktsize; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; + writel(reg_val, &arasan_nand_base->pkt_reg); + + arasan_nand_enable_ecc(); + column_addr_cycles = (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)), + &arasan_nand_base->ecc_sprcmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (rdcount < pktnum) { + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { + udelay(1); + timeout--; + } + + if (!timeout) { + puts("arasan_write_page: timedout:Buff RDY\n"); + return -ETIMEDOUT; + } + + rdcount++; + + if (pktnum == rdcount) { + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + } else { + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_reg); + + for (i = 0; i < pktsize/4; i++) + writel(bufptr[i], &arasan_nand_base->buf_dataport); + + bufptr += pktsize/4; + + if (rdcount >= pktnum) + break; + + writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) { + puts("arasan write_page timedout:Xfer CMPLT\n"); + return -ETIMEDOUT; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + if (oob_required) + chip->ecc.write_oob(mtd, chip, nand->page); + + return 0; +} + +static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize)); + + return 0; +} + +static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + const u8 *buf = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + chip->write_buf(mtd, buf, mtd->oobsize); + + return status; +} + +static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd) +{ + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 cmd_reg = 0; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + cmd_reg = readl(&arasan_nand_base->cmd_reg); + cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK; + + cmd_reg |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + writel(cmd_reg, &arasan_nand_base->cmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) { + printf("ERROR:%s timedout\n", __func__); + return -ETIMEDOUT; + } + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + return 0; +} + +static u8 arasan_nand_page(struct mtd_info *mtd) +{ + u8 page_val = 0; + + switch (mtd->writesize) { + case 512: + page_val = 0; + break; + case 2048: + page_val = 1; + break; + case 4096: + page_val = 2; + break; + case 8192: + page_val = 3; + break; + case 16384: + page_val = 4; + break; + case 1024: + page_val = 5; + break; + default: + printf("%s:Pagesize>16K\n", __func__); + break; + } + + return page_val; +} + +static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, page; + u8 page_val, addr_cycles; + + writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + if (curr_cmd->cmd1 == NAND_CMD_SEQIN) { + reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; + page_val = arasan_nand_page(mtd); + reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); + } + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + addr_cycles = arasan_nand_get_addrcycle(mtd); + + if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) + return ERR_ADDR_CYCLE; + + reg_val |= (addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + writel(reg_val, &arasan_nand_base->cmd_reg); + + if (page_addr == -1) + page_addr = 0; + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page|column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + + return 0; +} + +static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + u32 reg_val; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len; + writel(reg_val, &arasan_nand_base->pkt_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { + udelay(1); + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_reg); + + arasan_nand_fill_tx(buf, len); + + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) + puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n"); + + writel(readl(&arasan_nand_base->intsts_enr) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + writel(readl(&arasan_nand_base->intsts_reg) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, page; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u8 row_addr_cycles; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + row_addr_cycles = arasan_nand_get_addrcycle(mtd); + + if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) + return ERR_ADDR_CYCLE; + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + reg_val |= (row_addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + + writel(reg_val, &arasan_nand_base->cmd_reg); + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page | column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + if (!timeout) { + printf("ERROR:%s timedout:Xfer CMPLT\n", __func__); + return -ETIMEDOUT; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + return 0; +} + +static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u8 addr_cycles; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + addr_cycles = arasan_nand_get_addrcycle(mtd); + + if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) + return ERR_ADDR_CYCLE; + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + reg_val |= (addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + + writel(reg_val, &arasan_nand_base->cmd_reg); + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; + writel(reg_val, &arasan_nand_base->pkt_reg); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + + if (!timeout) { + printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__); + return -ETIMEDOUT; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + return 0; +} + +static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, addr_cycles, page; + u8 page_val; + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + + if (curr_cmd->cmd1 == NAND_CMD_RNDOUT || + curr_cmd->cmd1 == NAND_CMD_READ0) { + reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; + page_val = arasan_nand_page(mtd); + reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); + } + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + + addr_cycles = arasan_nand_get_addrcycle(mtd); + + if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) + return ERR_ADDR_CYCLE; + + reg_val |= (addr_cycles << 28); + writel(reg_val, &arasan_nand_base->cmd_reg); + + if (page_addr == -1) + page_addr = 0; + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page | column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + buf_index = 0; + + return 0; +} + +static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) +{ + u32 reg_val, i; + u32 *bufptr = (u32 *)buf; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size; + writel(reg_val, &arasan_nand_base->pkt_reg); + + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { + udelay(1); + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_reg); + + buf_index = 0; + for (i = 0; i < size / 4; i++) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + if (size & 0x03) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + udelay(1); + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static u8 arasan_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + u32 size; + u8 val; + struct nand_onfi_params *p; + + if (buf_index == 0) { + p = &chip->onfi_params; + if (curr_cmd->cmd1 == NAND_CMD_READID) + size = 4; + else if (curr_cmd->cmd1 == NAND_CMD_PARAM) + size = sizeof(struct nand_onfi_params); + else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT) + size = le16_to_cpu(p->ext_param_page_length) * 16; + else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) + size = 4; + else if (curr_cmd->cmd1 == NAND_CMD_STATUS) + return readb(&arasan_nand_base->flash_sts_reg); + else + size = 8; + chip->read_buf(mtd, &buf_data[0], size); + } + + val = *(&buf_data[0] + buf_index); + buf_index++; + + return val; +} + +static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + u32 i, ret = 0; + struct nand_chip *chip = mtd->priv; + struct arasan_nand_info *nand = chip->priv; + + curr_cmd = NULL; + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + + if ((command == NAND_CMD_READOOB) && + (mtd->writesize > 512)) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE || + arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) { + if (command == arasan_nand_commands[i].cmd1) { + curr_cmd = &arasan_nand_commands[i]; + break; + } + } + + if (curr_cmd == NULL) { + printf("Unsupported Command; 0x%x\n", command); + return; + } + + if (curr_cmd->cmd1 == NAND_CMD_RESET) + ret = arasan_nand_reset(curr_cmd); + + if ((curr_cmd->cmd1 == NAND_CMD_READID) || + (curr_cmd->cmd1 == NAND_CMD_PARAM) || + (curr_cmd->cmd1 == NAND_CMD_RNDOUT) || + (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) || + (curr_cmd->cmd1 == NAND_CMD_READ0)) + ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd); + + if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) || + (curr_cmd->cmd1 == NAND_CMD_SEQIN)) { + nand->page = page_addr; + ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd); + } + + if (curr_cmd->cmd1 == NAND_CMD_ERASE1) + ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd); + + if (curr_cmd->cmd1 == NAND_CMD_STATUS) + ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd); + + if (ret != 0) + printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1); +} + +static int arasan_nand_ecc_init(struct mtd_info *mtd) +{ + int found = -1; + u32 regval, eccpos_start, i; + struct nand_chip *nand_chip = mtd->priv; + + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.hwctl = NULL; + nand_chip->ecc.read_page = arasan_nand_read_page_hwecc; + nand_chip->ecc.write_page = arasan_nand_write_page_hwecc; + nand_chip->ecc.read_oob = arasan_nand_read_oob; + nand_chip->ecc.write_oob = arasan_nand_write_oob; + + for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) { + if ((ecc_matrix[i].pagesize == mtd->writesize) && + (ecc_matrix[i].ecc_codeword_size >= + nand_chip->ecc_step_ds)) { + if (ecc_matrix[i].eccbits >= + nand_chip->ecc_strength_ds) { + found = i; + break; + } + found = i; + } + } + + if (found < 0) + return 1; + + regval = ecc_matrix[i].eccaddr | + (ecc_matrix[i].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) | + (ecc_matrix[i].bch << ARASAN_NAND_ECC_BCH_SHIFT); + writel(regval, &arasan_nand_base->ecc_reg); + + if (ecc_matrix[i].bch) { + regval = readl(&arasan_nand_base->memadr_reg2); + regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; + regval |= (ecc_matrix[i].bchval << + ARASAN_NAND_MEM_ADDR2_BCH_SHIFT); + writel(regval, &arasan_nand_base->memadr_reg2); + } + + nand_oob.eccbytes = ecc_matrix[i].eccsize; + eccpos_start = mtd->oobsize - nand_oob.eccbytes; + + for (i = 0; i < nand_oob.eccbytes; i++) + nand_oob.eccpos[i] = eccpos_start + i; + + nand_oob.oobfree[0].offset = 2; + nand_oob.oobfree[0].length = eccpos_start - 2; + + nand_chip->ecc.size = ecc_matrix[i].ecc_codeword_size; + nand_chip->ecc.strength = ecc_matrix[i].eccbits; + nand_chip->ecc.bytes = ecc_matrix[i].eccsize; + nand_chip->ecc.layout = &nand_oob; + + return 0; +} + +static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) +{ + struct arasan_nand_info *nand; + struct mtd_info *mtd; + int err = -1; + + nand = calloc(1, sizeof(struct arasan_nand_info)); + if (!nand) { + printf("%s: failed to allocate\n", __func__); + return err; + } + + nand->nand_base = arasan_nand_base; + mtd = &nand_info[0]; + nand_chip->priv = nand; + mtd->priv = nand_chip; + + /* Set the driver entry points for MTD */ + nand_chip->cmdfunc = arasan_nand_cmd_function; + nand_chip->select_chip = arasan_nand_select_chip; + nand_chip->read_byte = arasan_nand_read_byte; + + /* Buffer read/write routines */ + nand_chip->read_buf = arasan_nand_read_buf; + nand_chip->write_buf = arasan_nand_write_buf; + nand_chip->bbt_options = NAND_BBT_USE_FLASH; + + writel(0x0, &arasan_nand_base->cmd_reg); + writel(0x0, &arasan_nand_base->pgm_reg); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + printf("%s: nand_scan_ident failed\n", __func__); + goto fail; + } + + if (arasan_nand_ecc_init(mtd)) { + printf("%s: nand_ecc_init failed\n", __func__); + goto fail; + } + + if (nand_scan_tail(mtd)) { + printf("%s: nand_scan_tail failed\n", __func__); + goto fail; + } + + if (nand_register(devnum)) { + printf("Nand Register Fail\n"); + goto fail; + } + + return 0; +fail: + free(nand); + return err; +} + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (arasan_nand_init(nand, 0)) + puts("NAND init failed\n"); +} diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index fccbfb5129..cbeb74a5bb 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -236,7 +236,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) /* * Main entrypoint for NAND Boot. It's necessary that SDRAM is already - * configured and available since this code loads the main U-boot image + * configured and available since this code loads the main U-Boot image * from NAND into SDRAM and starts from there. */ void nand_boot(void) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 2e5f139606..4e1be36654 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -516,7 +516,7 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, /* * LPC32xx has only one SLC NAND controller, don't utilize * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function - * both in SPL NAND and U-boot images. + * both in SPL NAND and U-Boot images. */ int board_nand_init(struct nand_chip *lpc32xx_chip) { diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c index 69b736a848..6ac2c96eeb 100644 --- a/drivers/mtd/nand/mxc_nand_spl.c +++ b/drivers/mtd/nand/mxc_nand_spl.c @@ -337,7 +337,7 @@ void nand_boot(void) if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { - /* Copy from NAND successful, start U-boot */ + /* Copy from NAND successful, start U-Boot */ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } else { diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index ba019a0763..b5bbd889ff 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -1090,24 +1090,29 @@ int mxs_nand_init(struct mxs_nand_info *info) (struct mxs_gpmi_regs *)MXS_GPMI_BASE; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; - int i = 0, j; + int i = 0, j, ret = 0; info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); - if (!info->desc) + if (!info->desc) { + ret = -ENOMEM; goto err1; + } /* Allocate the DMA descriptors. */ for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { info->desc[i] = mxs_dma_desc_alloc(); - if (!info->desc[i]) + if (!info->desc[i]) { + ret = -ENOMEM; goto err2; + } } /* Init the DMA controller. */ for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { - if (mxs_dma_init_channel(j)) + ret = mxs_dma_init_channel(j); + if (ret) goto err3; } @@ -1127,15 +1132,16 @@ int mxs_nand_init(struct mxs_nand_info *info) return 0; err3: - for (--j; j >= 0; j--) + for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--) mxs_dma_release(j); err2: - free(info->desc); -err1: for (--i; i >= 0; i--) mxs_dma_desc_free(info->desc[i]); - printf("MXS NAND: Unable to allocate DMA descriptors\n"); - return -ENOMEM; + free(info->desc); +err1: + if (ret == -ENOMEM) + printf("MXS NAND: Unable to allocate DMA descriptors\n"); + return ret; } /*! diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index f65b499beb..939274204e 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1486,8 +1486,8 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) info->variant = pxa3xx_nand_get_variant(); for (cs = 0; cs < pdata->num_cs; cs++) { mtd = &nand_info[cs]; - chip = (struct nand_chip *)info + - sizeof(struct pxa3xx_nand_host); + chip = (struct nand_chip *) + ((u8 *)&info[1] + sizeof(*host) * cs); host = (struct pxa3xx_nand_host *)chip; info->host[cs] = host; host->mtd = mtd; @@ -1600,19 +1600,12 @@ void board_nand_init(void) struct pxa3xx_nand_host *host; int ret; - info = kzalloc(sizeof(*info) + (sizeof(struct mtd_info) + - sizeof(*host)) * - CONFIG_SYS_MAX_NAND_DEVICE, GFP_KERNEL); + info = kzalloc(sizeof(*info) + + sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE, + GFP_KERNEL); if (!info) return; - /* - * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible - * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c - * still provides a "struct mtd_info nand_info" instance. - */ - info->host[0]->mtd = &nand_info[0]; - ret = pxa3xx_nand_probe(info); if (ret) return; diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 26595929c5..9151600190 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_emac.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/at91_pio.h> #include <net.h> #include <netdev.h> @@ -321,7 +321,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) emac_device *dev; at91_emac_t *emac; at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; dev = (emac_device *) netdev->priv; @@ -347,7 +346,8 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) writel(value, &pio->piob.pdr); writel(value, &pio->piob.bsr); - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); /* Init Ethernet buffers */ @@ -452,10 +452,10 @@ static int at91emac_recv(struct eth_device *netdev) static int at91emac_write_hwaddr(struct eth_device *netdev) { at91_emac_t *emac; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); + debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 92c3dcae3c..b030498402 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -459,11 +459,11 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; - for(cnt = 0; cnt < 16; cnt++) + for (cnt = 0; cnt < 8; cnt++) writel(0, addr++); addr = &adap_emac->RX0HDP; - for(cnt = 0; cnt < 16; cnt++) + for (cnt = 0; cnt < 8; cnt++) writel(0, addr++); /* Clear Statistics (do this before setting MacControl register) */ @@ -692,8 +692,10 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) davinci_invalidate_rx_descs(); rx_curr_desc = emac_rx_active_head; + if (!rx_curr_desc) + return 0; status = rx_curr_desc->pkt_flag_len; - if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { if (status & EMAC_CPPI_RX_ERROR_FRAME) { /* Error in packet - discard it and requeue desc */ printf ("WARN: emac_rcv_pkt: Error in packet\n"); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 77b98c94c0..ca58f34f13 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -591,11 +591,9 @@ static int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in platdata before we probe the hardware. */ if (device_is_on_pci_bus(dev)) { - pci_dev_t bdf = dm_pci_get_bdf(dev); - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(bdf, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase); pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 70fc02ee5c..196989b386 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -38,8 +38,13 @@ tested on both gig copper and gig fiber boards #define TOUT_LOOP 100000 +#ifdef CONFIG_DM_ETH +#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) +#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a) +#else #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#endif #define E1000_DEFAULT_PCI_PBA 0x00000030 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 @@ -1395,8 +1400,13 @@ e1000_reset_hw(struct e1000_hw *hw) /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif } /* Clear interrupt mask to stop board from generating interrupts */ @@ -1469,7 +1479,11 @@ e1000_reset_hw(struct e1000_hw *hw) /* If MWI was previously enabled, reenable it. */ if (hw->mac_type == e1000_82542_rev2_0) { +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif } if (hw->mac_type != e1000_igb) E1000_WRITE_REG(hw, PBA, pba); @@ -1655,9 +1669,15 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw-> pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); mdelay(5); @@ -1673,7 +1693,11 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); mdelay(1); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif } /* Zero out the Multicast HASH table */ @@ -1696,10 +1720,17 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if (hw->bus_type == e1000_bus_type_pcix) { +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); +#else pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word); pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); +#endif cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; @@ -1711,8 +1742,13 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) if (cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); +#else pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word); +#endif } } break; @@ -4809,6 +4845,16 @@ e1000_sw_init(struct e1000_hw *hw) int result; /* PCI config space info */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#else pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, @@ -4817,6 +4863,7 @@ e1000_sw_init(struct e1000_hw *hw) pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#endif /* identify the MAC */ result = e1000_set_mac_type(hw); @@ -5232,25 +5279,46 @@ void e1000_get_bus_type(struct e1000_hw *hw) static LIST_HEAD(e1000_hw_list); #endif +#ifdef CONFIG_DM_ETH +static int e1000_init_one(struct e1000_hw *hw, int cardnum, + struct udevice *devno, unsigned char enetaddr[6]) +#else static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, unsigned char enetaddr[6]) +#endif { u32 val; /* Assign the passed-in values */ +#ifdef CONFIG_DM_ETH hw->pdev = devno; +#else + hw->pdev = devno; +#endif hw->cardnum = cardnum; /* Print a debug message with the IO base address */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); +#else pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); +#endif E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); /* Try to enable I/O accesses and bus-mastering */ val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; +#ifdef CONFIG_DM_ETH + dm_pci_write_config32(devno, PCI_COMMAND, val); +#else pci_write_config_dword(devno, PCI_COMMAND, val); +#endif /* Make sure it worked */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_COMMAND, &val); +#else pci_read_config_dword(devno, PCI_COMMAND, &val); +#endif if (!(val & PCI_COMMAND_MEMORY)) { E1000_ERR(hw, "Can't enable I/O memory\n"); return -ENOSPC; @@ -5269,8 +5337,13 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM hw->eeprom_semaphore_present = true; #endif +#ifdef CONFIG_DM_ETH + hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); +#else hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); +#endif hw->mac_type = e1000_undefined; /* MAC and Phy settings */ @@ -5380,7 +5453,7 @@ e1000_initialize(bd_t * bis) for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { /* * These will never get freed due to errors, this allows us to - * perform SPI EEPROM programming from U-boot, for example. + * perform SPI EEPROM programming from U-Boot, for example. */ struct eth_device *nic = malloc(sizeof(*nic)); struct e1000_hw *hw = malloc(sizeof(*hw)); @@ -5554,7 +5627,7 @@ static int e1000_eth_probe(struct udevice *dev) hw->name = dev->name; ret = e1000_init_one(hw, trailing_strtol(dev->name), - dm_pci_get_bdf(dev), plat->enetaddr); + dev, plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); return ret; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e46edcd4e1..fcb7df0d83 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1084,7 +1084,11 @@ struct e1000_hw { #endif unsigned int cardnum; +#ifdef CONFIG_DM_ETH + struct udevice *pdev; +#else pci_dev_t pdev; +#endif uint8_t *hw_addr; e1000_mac_type mac_type; e1000_phy_type phy_type; diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index fdbd584186..53c4966c33 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -455,7 +455,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Management Complex cores should be held at reset out of POR. - * U-boot should be the first software to touch MC. To be safe, + * U-Boot should be the first software to touch MC. To be safe, * we reset all cores again by setting GCR1 to 0. It doesn't do * anything if they are held at reset. After we setup the firmware * we kick off MC by deasserting the reset bit for core 0, and diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 209fae94a7..6b28df0f96 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -10,6 +10,8 @@ #include <command.h> #include <console.h> +#include <dm.h> + #include <net.h> #include <phy.h> #include <errno.h> @@ -18,10 +20,15 @@ #include <asm/ti-common/keystone_nav.h> #include <asm/ti-common/keystone_net.h> #include <asm/ti-common/keystone_serdes.h> +#include <asm/arch/psc_defs.h> + +DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_ETH unsigned int emac_open; static struct mii_dev *mdio_bus; static unsigned int sys_has_mdio = 1; +#endif #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) @@ -36,40 +43,74 @@ static unsigned int sys_has_mdio = 1; static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); +#ifndef CONFIG_DM_ETH struct rx_buff_desc net_rx_buffs = { .buff_ptr = rx_buffs, .num_buffs = RX_BUFF_NUMS, .buff_len = RX_BUFF_LEN, .rx_flow = 22, }; - -#ifndef CONFIG_SOC_K2G -static void keystone2_net_serdes_setup(void); #endif -int keystone2_eth_read_mac_addr(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv; - u32 maca = 0; - u32 macb = 0; +#ifdef CONFIG_DM_ETH - eth_priv = (struct eth_priv_t *)dev->priv; +enum link_type { + LINK_TYPE_MAC_TO_MAC_AUTO = 0, + LINK_TYPE_MAC_TO_PHY_MODE = 1, + LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2, + LINK_TYPE_MAC_TO_FIBRE_MODE = 3, + LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4, + LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, + LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, +}; - /* Read the e-fuse mac address */ - if (eth_priv->slave_port == 1) { - maca = __raw_readl(MAC_ID_BASE_ADDR); - macb = __raw_readl(MAC_ID_BASE_ADDR + 4); - } +#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ + ((mac)[2] << 16) | ((mac)[3] << 24)) +#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) - dev->enetaddr[0] = (macb >> 8) & 0xff; - dev->enetaddr[1] = (macb >> 0) & 0xff; - dev->enetaddr[2] = (maca >> 24) & 0xff; - dev->enetaddr[3] = (maca >> 16) & 0xff; - dev->enetaddr[4] = (maca >> 8) & 0xff; - dev->enetaddr[5] = (maca >> 0) & 0xff; +#ifdef CONFIG_KSNET_NETCP_V1_0 - return 0; -} +#define EMAC_EMACSW_BASE_OFS 0x90800 +#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60) + +/* CPSW Switch slave registers */ +#define CPGMACSL_REG_SA_LO 0x10 +#define CPGMACSL_REG_SA_HI 0x14 + +#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ + (x) * 0x30) + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define EMAC_EMACSW_PORT_BASE_OFS 0x222000 + +/* CPSW Switch slave registers */ +#define CPGMACSL_REG_SA_LO 0x308 +#define CPGMACSL_REG_SA_HI 0x30c + +#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ + (x) * 0x1000) + +#endif + + +struct ks2_eth_priv { + struct udevice *dev; + struct phy_device *phydev; + struct mii_dev *mdio_bus; + int phy_addr; + phy_interface_t phy_if; + int sgmii_link_type; + void *mdio_base; + struct rx_buff_desc net_rx_buffs; + struct pktdma_cfg *netcp_pktdma; + void *hd; + int slave_port; + enum link_type link_type; + bool emac_open; + bool has_mdio; +}; +#endif /* MDIO */ @@ -140,6 +181,7 @@ static int keystone2_mdio_write(struct mii_dev *bus, return 0; } +#ifndef CONFIG_DM_ETH static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct eth_device *dev) { @@ -163,6 +205,31 @@ static void __attribute__((unused)) EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); } +#else +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + u_int16_t data; + + if (priv->has_mdio) { + data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, + MDIO_DEVAD_NONE, 0); + /* speed selection MSB */ + if (!(data & (1 << 6))) + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + + CPGMACSL_REG_CTL) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); +} +#endif #ifdef CONFIG_SOC_K2G int keystone_rgmii_config(struct phy_device *phy_dev) @@ -401,6 +468,58 @@ int ethss_stop(void) return 0; } +struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .rate_mode = SERDES_QUARTER_RATE, + .intf = SERDES_PHY_SGMII, + .loopback = 0, +}; + +#ifndef CONFIG_SOC_K2G +static void keystone2_net_serdes_setup(void) +{ + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); + +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + + /* wait till setup */ + udelay(5000); +} +#endif + +#ifndef CONFIG_DM_ETH + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) { if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) @@ -556,6 +675,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) int res; struct eth_device *dev; struct phy_device *phy_dev; + struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; dev = malloc(sizeof(struct eth_device)); if (dev == NULL) @@ -612,28 +732,301 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return 0; } -struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { - .clk = SERDES_CLOCK_156P25M, - .rate = SERDES_RATE_5G, - .rate_mode = SERDES_QUARTER_RATE, - .intf = SERDES_PHY_SGMII, - .loopback = 0, -}; +#else -#ifndef CONFIG_SOC_K2G -static void keystone2_net_serdes_setup(void) +static int ks2_eth_start(struct udevice *dev) { - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, - &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + struct ks2_eth_priv *priv = dev_get_priv(dev); -#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, - &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#ifdef CONFIG_SOC_K2G + keystone_rgmii_config(priv->phydev); +#else + keystone_sgmii_config(priv->phydev, priv->slave_port - 1, + priv->sgmii_link_type); #endif - /* wait till setup */ - udelay(5000); + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + qm_init(); + + if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) { + error("ksnav_init failed\n"); + goto err_knav_init; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (priv->has_mdio) { + phy_startup(priv->phydev); + if (priv->phydev->link == 0) { + error("phy startup failed\n"); + goto err_phy_start; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + priv->emac_open = true; + + return 0; + +err_phy_start: + ksnav_close(priv->netcp_pktdma); +err_knav_init: + qm_close(); + + return -EFAULT; +} + +static int ks2_eth_send(struct udevice *dev, void *packet, int length) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + genphy_update_link(priv->phydev); + if (priv->phydev->link == 0) + return -1; + + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + length = EMAC_MIN_ETHERNET_PKT_SIZE; + + return ksnav_send(priv->netcp_pktdma, (u32 *)packet, + length, (priv->slave_port) << 16); +} + +static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + int pkt_size; + u32 *pkt = NULL; + + priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size); + if (priv->hd == NULL) + return -EAGAIN; + + *packetp = (uchar *)pkt; + + return pkt_size; +} + +static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + ksnav_release_rxhd(priv->netcp_pktdma, priv->hd); + + return 0; +} + +static void ks2_eth_stop(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + if (!priv->emac_open) + return; + ethss_stop(); + + ksnav_close(priv->netcp_pktdma); + qm_close(); + phy_shutdown(priv->phydev); + priv->emac_open = false; +} + +int ks2_eth_read_rom_hwaddr(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + u32 maca = 0; + u32 macb = 0; + + /* Read the e-fuse mac address */ + if (priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + pdata->enetaddr[0] = (macb >> 8) & 0xff; + pdata->enetaddr[1] = (macb >> 0) & 0xff; + pdata->enetaddr[2] = (maca >> 24) & 0xff; + pdata->enetaddr[3] = (maca >> 16) & 0xff; + pdata->enetaddr[4] = (maca >> 8) & 0xff; + pdata->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +int ks2_eth_write_hwaddr(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + writel(mac_hi(pdata->enetaddr), + DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + + CPGMACSL_REG_SA_HI); + writel(mac_lo(pdata->enetaddr), + DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + + CPGMACSL_REG_SA_LO); + + return 0; +} + +static int ks2_eth_probe(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *mdio_bus; + int ret; + + priv->dev = dev; + + /* These clock enables has to be moved to common location */ + if (cpu_is_k2g()) + writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); + + /* By default, select PA PLL clock as PA clock source */ +#ifndef CONFIG_SOC_K2G + if (psc_enable_module(KS2_LPSC_PA)) + return -EACCES; +#endif + if (psc_enable_module(KS2_LPSC_CPGMAC)) + return -EACCES; + if (psc_enable_module(KS2_LPSC_CRYPTO)) + return -EACCES; + + if (cpu_is_k2e() || cpu_is_k2l()) + pll_pa_clk_sel(); + + + priv->net_rx_buffs.buff_ptr = rx_buffs, + priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS, + priv->net_rx_buffs.buff_len = RX_BUFF_LEN, + + /* Register MDIO bus */ + mdio_bus = mdio_alloc(); + if (!mdio_bus) { + error("MDIO alloc failed\n"); + return -ENOMEM; + } + priv->mdio_bus = mdio_bus; + mdio_bus->read = keystone2_mdio_read; + mdio_bus->write = keystone2_mdio_write; + mdio_bus->reset = keystone2_mdio_reset; + mdio_bus->priv = priv->mdio_base; + sprintf(mdio_bus->name, "ethernet-mdio"); + + ret = mdio_register(mdio_bus); + if (ret) { + error("MDIO bus register failed\n"); + return ret; + } + +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif + + priv->netcp_pktdma = &netcp_pktdma; + + priv->phydev = phy_connect(mdio_bus, priv->phy_addr, dev, priv->phy_if); + phy_config(priv->phydev); + + return 0; } + +int ks2_eth_remove(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->mdio_bus); + mdio_free(priv->mdio_bus); + + return 0; +} + +static const struct eth_ops ks2_eth_ops = { + .start = ks2_eth_start, + .send = ks2_eth_send, + .recv = ks2_eth_recv, + .free_pkt = ks2_eth_free_pkt, + .stop = ks2_eth_stop, + .read_rom_hwaddr = ks2_eth_read_rom_hwaddr, + .write_hwaddr = ks2_eth_write_hwaddr, +}; + + +static int ks2_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int interfaces; + int interface_0; + int netcp_gbe_0; + int phy; + int mdio; + u32 dma_channel[6]; + + interfaces = fdt_subnode_offset(fdt, dev->of_offset, + "netcp-interfaces"); + interface_0 = fdt_subnode_offset(fdt, interfaces, "interface-0"); + + netcp_gbe_0 = fdtdec_lookup_phandle(fdt, interface_0, "netcp-gbe"); + priv->link_type = fdtdec_get_int(fdt, netcp_gbe_0, + "link-interface", -1); + priv->slave_port = fdtdec_get_int(fdt, netcp_gbe_0, "slave-port", -1); + /* U-Boot slave port number starts with 1 instead of 0 */ + priv->slave_port += 1; + + phy = fdtdec_lookup_phandle(fdt, netcp_gbe_0, "phy-handle"); + priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1); + + mdio = fdt_parent_offset(fdt, phy); + if (mdio < 0) { + error("mdio dt not found\n"); + return -ENODEV; + } + priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); + + if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) { + priv->phy_if = PHY_INTERFACE_MODE_SGMII; + pdata->phy_interface = priv->phy_if; + priv->sgmii_link_type = SGMII_LINK_MAC_PHY; + priv->has_mdio = true; + } + pdata->iobase = dev_get_addr(dev); + + fdtdec_get_int_array(fdt, dev->of_offset, "ti,navigator-dmas", + dma_channel, 6); + priv->net_rx_buffs.rx_flow = dma_channel[1]; + + return 0; +} + +static const struct udevice_id ks2_eth_ids[] = { + { .compatible = "ti,netcp-1.0" }, + { } +}; + + +U_BOOT_DRIVER(eth_ks2) = { + .name = "eth_ks2", + .id = UCLASS_ETH, + .of_match = ks2_eth_ids, + .ofdata_to_platdata = ks2_eth_ofdata_to_platdata, + .probe = ks2_eth_probe, + .remove = ks2_eth_remove, + .ops = &ks2_eth_ops, + .priv_auto_alloc_size = sizeof(struct ks2_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; #endif diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index c4dd01ec2a..3526876d14 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -1,7 +1,7 @@ /*------------------------------------------------------------------------ * lan91c96.c * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based - * on the SMC91111 driver from U-boot. + * on the SMC91111 driver from U-Boot. * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 887cfd957b..71d133cc8f 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -650,7 +650,7 @@ dp83902a_poll(void) } -/* U-boot specific routines */ +/* U-Boot specific routines */ static u8 *pbuf = NULL; static int pkey = -1; diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 56d29d47af..137818b390 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -117,15 +117,15 @@ static void pch_gbe_rx_descs_init(struct udevice *dev) memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); for (i = 0; i < PCH_GBE_DESC_NUM; i++) - rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)(priv->rx_buff[i])); - writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc), &mac_regs->rx_dsc_base); writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->rx_dsc_size); - writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)), &mac_regs->rx_dsc_sw_p); } @@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev) memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); - writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc), &mac_regs->tx_dsc_base); writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->tx_dsc_size); - writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)), &mac_regs->tx_dsc_sw_p); } @@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (length < 64) frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; - tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet); tx_desc->length = length; tx_desc->tx_words_eob = length + 3; tx_desc->tx_frame_ctrl = frame_ctrl; @@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (++priv->tx_idx >= PCH_GBE_DESC_NUM) priv->tx_idx = 0; - writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)), &mac_regs->tx_dsc_sw_p); start = get_timer(0); @@ -294,7 +294,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) if ((u32)rx_desc == hw_desc) return -EAGAIN; - buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr); *packetp = (uchar *)buffer_addr; length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; @@ -315,7 +315,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length) if (++rx_swp >= PCH_GBE_DESC_NUM) rx_swp = 0; - writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)), &mac_regs->rx_dsc_sw_p); return 0; @@ -421,11 +421,8 @@ int pch_gbe_probe(struct udevice *dev) { struct pch_gbe_priv *priv; struct eth_pdata *plat = dev_get_platdata(dev); - pci_dev_t devno; u32 iobase; - devno = dm_pci_get_bdf(dev); - /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes). This is guaranteed by @@ -433,11 +430,11 @@ int pch_gbe_probe(struct udevice *dev) */ priv = dev_get_priv(dev); - priv->bdf = devno; + priv->dev = dev; - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(devno, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase); plat->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h index afcb03dd36..0ea0c73a4f 100644 --- a/drivers/net/pch_gbe.h +++ b/drivers/net/pch_gbe.h @@ -290,7 +290,7 @@ struct pch_gbe_priv { struct phy_device *phydev; struct mii_dev *bus; struct pch_gbe_regs *mac_regs; - pci_dev_t bdf; + struct udevice *dev; int rx_idx; int tx_idx; }; diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index eab15585c3..b8b1157a0a 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -172,7 +172,6 @@ static int m88e1011s_startup(struct phy_device *phydev) static int m88e1111s_config(struct phy_device *phydev) { int reg; - int timeout; if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || @@ -236,16 +235,7 @@ static int m88e1111s_config(struct phy_device *phydev) MIIM_88E1111_PHY_EXT_SR, reg); /* soft reset */ - timeout = 1000; - phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - while ((reg & BMCR_RESET) && --timeout) { - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - } - if (!timeout) - printf("%s: phy soft reset timeout\n", __func__); + phy_reset(phydev); reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); @@ -258,20 +248,10 @@ static int m88e1111s_config(struct phy_device *phydev) } /* soft reset */ - timeout = 1000; - phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - while ((reg & BMCR_RESET) && --timeout) { - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - } - if (!timeout) - printf("%s: phy soft reset timeout\n", __func__); + phy_reset(phydev); genphy_config_aneg(phydev); - - phy_reset(phydev); + genphy_restart_aneg(phydev); return 0; } diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index c3da1606dc..8fcf737cb8 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -279,7 +279,8 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, #define CTRL1000_CONFIG_MASTER (1 << 11) #define CTRL1000_MANUAL_CONFIG (1 << 12) -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ + defined(CONFIG_PHY_MICREL_KSZ9031)) static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, @@ -385,7 +386,8 @@ static struct phy_driver ksz9021_driver = { #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d #define MII_KSZ9031_MMD_REG_DATA 0x0e -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ + defined(CONFIG_PHY_MICREL_KSZ9031)) static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; static const struct ksz90x1_reg_field ksz9031_clk_grp[] = diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 4579ed12f6..7216660a24 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -12,35 +12,47 @@ DECLARE_GLOBAL_DATA_PTR; -int pch_get_sbase(struct udevice *dev, ulong *sbasep) +int pch_get_spi_base(struct udevice *dev, ulong *sbasep) { struct pch_ops *ops = pch_get_ops(dev); *sbasep = 0; - if (!ops->get_sbase) + if (!ops->get_spi_base) return -ENOSYS; - return ops->get_sbase(dev, sbasep); + return ops->get_spi_base(dev, sbasep); } -enum pch_version pch_get_version(struct udevice *dev) +int pch_set_spi_protect(struct udevice *dev, bool protect) { struct pch_ops *ops = pch_get_ops(dev); - if (!ops->get_version) + if (!ops->set_spi_protect) return -ENOSYS; - return ops->get_version(dev); + return ops->set_spi_protect(dev, protect); } -int pch_set_spi_protect(struct udevice *dev, bool protect) +int pch_get_gpio_base(struct udevice *dev, u32 *gbasep) { struct pch_ops *ops = pch_get_ops(dev); - if (!ops->set_spi_protect) + *gbasep = 0; + if (!ops->get_gpio_base) return -ENOSYS; - return ops->set_spi_protect(dev, protect); + return ops->get_gpio_base(dev, gbasep); +} + +int pch_get_io_base(struct udevice *dev, u32 *iobasep) +{ + struct pch_ops *ops = pch_get_ops(dev); + + *iobasep = 0; + if (!ops->get_io_base) + return -ENOSYS; + + return ops->get_io_base(dev, iobasep); } static int pch_uclass_post_bind(struct udevice *bus) diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c index ef724221c2..302c9299ee 100644 --- a/drivers/pch/pch7.c +++ b/drivers/pch/pch7.c @@ -8,9 +8,10 @@ #include <dm.h> #include <pch.h> +#define GPIO_BASE 0x44 #define BIOS_CTRL 0xd8 -static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep) { u32 rcba; @@ -22,11 +23,6 @@ static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) return 0; } -static enum pch_version pch7_get_version(struct udevice *dev) -{ - return PCHV_7; -} - static int pch7_set_spi_protect(struct udevice *dev, bool protect) { uint8_t bios_cntl; @@ -42,10 +38,41 @@ static int pch7_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops pch7_ops = { - .get_sbase = pch7_get_sbase, - .get_version = pch7_get_version, + .get_spi_base = pch7_get_spi_base, .set_spi_protect = pch7_set_spi_protect, + .get_gpio_base = pch7_get_gpio_base, }; static const struct udevice_id pch7_ids[] = { diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 529cb023e2..910eb61f48 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -8,9 +8,11 @@ #include <dm.h> #include <pch.h> +#define GPIO_BASE 0x48 +#define IO_BASE 0x4c #define SBASE_ADDR 0x54 -static int pch9_get_sbase(struct udevice *dev, ulong *sbasep) +static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep) { uint32_t sbase_addr; @@ -20,14 +22,56 @@ static int pch9_get_sbase(struct udevice *dev, ulong *sbasep) return 0; } -static enum pch_version pch9_get_version(struct udevice *dev) +static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep) { - return PCHV_9; + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + +static int pch9_get_io_base(struct udevice *dev, u32 *iobasep) +{ + u32 base; + + dm_pci_read_config32(dev, IO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + *iobasep = base & 1 ? base & ~3 : base & ~15; + + return 0; } static const struct pch_ops pch9_ops = { - .get_sbase = pch9_get_sbase, - .get_version = pch9_get_version, + .get_spi_base = pch9_get_spi_base, + .get_gpio_base = pch9_get_gpio_base, + .get_io_base = pch9_get_io_base, }; static const struct udevice_id pch9_ids[] = { diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cd8f3570f0..6f0d61e7ab 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -17,3 +17,12 @@ config PWM_ROCKCHIP programmable period and duty cycle. A 32-bit counter is used. Various options provided in the hardware (such as capture mode and continuous/single-shot) are not supported by the driver. + +config PWM_TEGRA + bool "Enable support for the Tegra PWM" + depends on DM_PWM + help + This PWM is found on Tegra 20 and other Nvidia SoCs. It supports + four channels with a programmable period and duty cycle. Only a + 32KHz clock is supported by the driver but the duty cycle is + configurable. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index b6d8c16604..fd414b1893 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -13,3 +13,6 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o +ifdef CONFIG_DM_PWM +obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o +endif diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c new file mode 100644 index 0000000000..10e1fdc9b5 --- /dev/null +++ b/drivers/pwm/tegra_pwm.c @@ -0,0 +1,85 @@ +/* + * Copyright 2016 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pwm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/pwm.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra_pwm_priv { + struct pwm_ctlr *regs; +}; + +static int tegra_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + struct pwm_ctlr *regs = priv->regs; + uint pulse_width; + u32 reg; + + if (channel >= 4) + return -EINVAL; + debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); + /* We ignore the period here and just use 32KHz */ + clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768); + + pulse_width = duty_ns * 255 / period_ns; + + reg = pulse_width << PWM_WIDTH_SHIFT; + reg |= 1 << PWM_DIVIDER_SHIFT; + writel(reg, ®s[channel].control); + debug("%s: pulse_width=%u\n", __func__, pulse_width); + + return 0; +} + +static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + struct pwm_ctlr *regs = priv->regs; + + if (channel >= 4) + return -EINVAL; + debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel); + clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK, + enable ? PWM_ENABLE_MASK : 0); + + return 0; +} + +static int tegra_pwm_ofdata_to_platdata(struct udevice *dev) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + + priv->regs = (struct pwm_ctlr *)dev_get_addr(dev); + + return 0; +} + +static const struct pwm_ops tegra_pwm_ops = { + .set_config = tegra_pwm_set_config, + .set_enable = tegra_pwm_set_enable, +}; + +static const struct udevice_id tegra_pwm_ids[] = { + { .compatible = "nvidia,tegra124-pwm" }, + { .compatible = "nvidia,tegra20-pwm" }, + { } +}; + +U_BOOT_DRIVER(tegra_pwm) = { + .name = "tegra_pwm", + .id = UCLASS_PWM, + .of_match = tegra_pwm_ids, + .ops = &tegra_pwm_ops, + .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv), +}; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 57cd38bf6e..c63999ac41 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -22,14 +22,10 @@ obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o -obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o -obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o -obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o @@ -37,7 +33,6 @@ obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o -obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o diff --git a/drivers/serial/mxs_auart.c b/drivers/serial/mxs_auart.c deleted file mode 100644 index fc0fa96a0e..0000000000 --- a/drivers/serial/mxs_auart.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 AUART driver - * - * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> - * - * Based on the MXC serial driver: - * - * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> - * - * Further based on the Linux mxs-auart.c driver: - * - * Freescale STMP37XX/STMP38X Application UART drkiver - * Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <asm/io.h> -#include <serial.h> -#include <linux/compiler.h> -#include <asm/arch/regs-base.h> -#include <asm/arch/regs-uartapp.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_MXS_AUART_BASE -#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use" -#endif - -/* AUART clock always supplied by XTAL and always 24MHz */ -#define MXS_AUART_CLK 24000000 - -static struct mxs_uartapp_regs *get_uartapp_registers(void) -{ - return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE; -} - -/** - * Sets the baud rate and settings. - * The settings are: 8 data bits, no parit and 1 stop bit. - */ -static void mxs_auart_setbrg(void) -{ - u32 div; - u32 linectrl = 0; - struct mxs_uartapp_regs *regs = get_uartapp_registers(); - - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - /* - * From i.MX28 datasheet: - * div is calculated by calculating UARTCLK*32/baudrate, rounded to int - * div must be between 0xEC and 0x003FFFC0 inclusive - * Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register - * Next 16 bits goes in BAUD_DIVINT part of LINECTRL register - */ - div = (MXS_AUART_CLK * 32) / gd->baudrate; - if (div < 0xEC || div > 0x003FFFC0) - return; - - linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) << - UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) & - UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK; - linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) << - UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) & - UARTAPP_LINECTRL_BAUD_DIVINT_MASK; - - /* Word length: 8 bits */ - linectrl |= UARTAPP_LINECTRL_WLEN_8BITS; - - /* Enable FIFOs. */ - linectrl |= UARTAPP_LINECTRL_FEN_MASK; - - /* Write above settings, no parity, 1 stop bit */ - writel(linectrl, ®s->hw_uartapp_linectrl); -} - -static int mxs_auart_init(void) -{ - struct mxs_uartapp_regs *regs = get_uartapp_registers(); - /* Reset everything */ - mxs_reset_block(®s->hw_uartapp_ctrl0_reg); - /* Disable interrupts */ - writel(0, ®s->hw_uartapp_intr); - /* Set baud rate and settings */ - serial_setbrg(); - /* Disable RTS and CTS, ignore LINECTRL2 register */ - writel(UARTAPP_CTRL2_RTSEN_MASK | - UARTAPP_CTRL2_CTSEN_MASK | - UARTAPP_CTRL2_USE_LCR2_MASK, - ®s->hw_uartapp_ctrl2_clr); - /* Enable receiver, transmitter and UART */ - writel(UARTAPP_CTRL2_RXE_MASK | - UARTAPP_CTRL2_TXE_MASK | - UARTAPP_CTRL2_UARTEN_MASK, - ®s->hw_uartapp_ctrl2_set); - return 0; -} - -static void mxs_auart_putc(const char c) -{ - struct mxs_uartapp_regs *regs = get_uartapp_registers(); - /* Wait in loop while the transmit FIFO is full */ - while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK) - ; - - writel(c, ®s->hw_uartapp_data); - - if (c == '\n') - mxs_auart_putc('\r'); -} - -static int mxs_auart_tstc(void) -{ - struct mxs_uartapp_regs *regs = get_uartapp_registers(); - /* Checks if receive FIFO is empty */ - return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK); -} - -static int mxs_auart_getc(void) -{ - struct mxs_uartapp_regs *regs = get_uartapp_registers(); - /* Wait until a character is available to read */ - while (!mxs_auart_tstc()) - ; - /* Read the character from the data register */ - return readl(®s->hw_uartapp_data) & 0xFF; -} - -static struct serial_device mxs_auart_drv = { - .name = "mxs_auart_serial", - .start = mxs_auart_init, - .stop = NULL, - .setbrg = mxs_auart_setbrg, - .putc = mxs_auart_putc, - .puts = default_serial_puts, - .getc = mxs_auart_getc, - .tstc = mxs_auart_tstc, -}; - -void mxs_auart_initialize(void) -{ - serial_register(&mxs_auart_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mxs_auart_drv; -} diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c deleted file mode 100644 index f68c8d0f04..0000000000 --- a/drivers/serial/opencores_yanu.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Altera NiosII YANU serial interface by Imagos - * please see http://www.opencores.org/project,yanu for - * information/downloads - * - * Copyright 2010, Renato Andreola <renato.andreola@imagos.it> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> -#include <asm/io.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -/*-----------------------------------------------------------------*/ -/* YANU Imagos serial port */ -/*-----------------------------------------------------------------*/ - -#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ -#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ -#define YANU_FIFO_SIZE (16) -#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) -#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) - -#define YANU_RXFIFO_DLY (10*11) -#define YANU_TXFIFO_THR (10) -#define YANU_DATA_CHAR_MASK (0xFF) - -/* data register */ -#define YANU_DATA_OFFSET (0) /* data register offset */ - -#define YANU_CONTROL_OFFSET (4) /* control register offset */ -/* interrupt enable */ -#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ -#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ -#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ -#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ -#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ -#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ -/* control bits */ -#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ -#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */ -#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ -#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */ -#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ -#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ -#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ -#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ -/* tuning part */ -#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */ -#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ -#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ -#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ - -#define YANU_BAUD_OFFSET (8) /* baud register offset */ -#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ -#define YANU_BAUDM_N (12) /* ...its bit filed length */ -#define YANU_BAUDE (1<<12) /* baud exponent lsb */ -#define YANU_BAUDE_N (4) /* ...its bit field length */ - -#define YANU_ACTION_OFFSET (12) /* action register... write only */ -#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ -#define YANU_ACTION_ROE (1<<1) /* reset oe */ -#define YANU_ACTION_RBRK (1<<2) /* reset brk */ -#define YANU_ACTION_RFE (1<<3) /* reset fe */ -#define YANU_ACTION_RPE (1<<4) /* reset pe */ -#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ -#define YANU_ACTION_SOE (1<<6) /* set oe */ -#define YANU_ACTION_SBRK (1<<7) /* set brk */ -#define YANU_ACTION_SFE (1<<8) /* set fe */ -#define YANU_ACTION_SPE (1<<9) /* set pe */ -#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */ -#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ -#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ -#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ -#define YANU_ACTION_STRDY (1<<14) /* set trdy */ - -#define YANU_STATUS_OFFSET (16) -#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ -#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ -#define YANU_STATUS_OE (1<<2) /* rx overrun error */ -#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ -#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ -#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ -#define YANU_RFIFO_CHARS_POS (6) -#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */ -#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ -#define YANU_TFIFO_CHARS_POS (11) -#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */ -#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ - -typedef volatile struct { - volatile unsigned data; - volatile unsigned control; /* control register (RW) 32-bit */ - volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ - volatile unsigned action; /* action register (W) 32-bit */ - volatile unsigned status; /* status register (R) 32-bit */ - volatile unsigned magic; /* magic register (R) 32-bit */ -} yanu_uart_t; - -static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - unsigned baudrate; - -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - /* Everything's already setup for fixed-baud PTF assignment */ - baudrate = CONFIG_BAUDRATE; -#else - baudrate = gd->baudrate; -#endif - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - baudrate) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if (baudrate <= (max_uns >> (15+n-k))) - break; - } - best_m = - (baudrate * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(baud, &uart->baud); - - return; -} - -static int oc_serial_init(void) -{ - unsigned action,control; - - /* status register cleanup */ - action = YANU_ACTION_RRRDY | - YANU_ACTION_RTRDY | - YANU_ACTION_ROE | - YANU_ACTION_RBRK | - YANU_ACTION_RFE | - YANU_ACTION_RPE | - YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; - - writel(action, &uart->action); - - /* - * control register cleanup - * no interrupts enabled - * one stop bit - * hardware flow control disabled - * 8 bits - */ - control = (0x7 << YANU_CONTROL_BITS_POS); - /* enven parity just to be clean */ - control |= YANU_CONTROL_PAREVEN; - /* we set threshold for fifo */ - control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; - control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; - - writel(control, &uart->control); - - /* to set baud rate */ - serial_setbrg(); - - return (0); -} - - -/*----------------------------------------------------------------------- - * YANU CONSOLE - *---------------------------------------------------------------------*/ -static void oc_serial_putc(char c) -{ - int tx_chars; - unsigned status; - - if (c == '\n') - serial_putc ('\r'); - - while (1) { - status = readl(&uart->status); - tx_chars = (status>>YANU_TFIFO_CHARS_POS) - & ((1<<YANU_TFIFO_CHARS_N)-1); - if (tx_chars < YANU_TXFIFO_SIZE-1) - break; - WATCHDOG_RESET (); - } - - writel((unsigned char)c, &uart->data); -} - -static int oc_serial_tstc(void) -{ - unsigned status ; - - status = readl(&uart->status); - return (((status >> YANU_RFIFO_CHARS_POS) & - ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); -} - -static int oc_serial_getc(void) -{ - while (serial_tstc() == 0) - WATCHDOG_RESET (); - - /* first we pull the char */ - writel(YANU_ACTION_RFIFO_PULL, &uart->action); - - return(readl(&uart->data) & YANU_DATA_CHAR_MASK); -} - -static struct serial_device oc_serial_drv = { - .name = "oc_serial", - .start = oc_serial_init, - .stop = NULL, - .setbrg = oc_serial_setbrg, - .putc = oc_serial_putc, - .puts = default_serial_puts, - .getc = oc_serial_getc, - .tstc = oc_serial_tstc, -}; - -void oc_serial_initialize(void) -{ - serial_register(&oc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &oc_serial_drv; -} diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 45dff98d9d..58f882b22a 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * * serial_buf: A buffer that holds keyboard characters for the - * Sandbox U-boot. + * Sandbox U-Boot. * * invariants: * serial_buf_write == serial_buf_read -> empty buffer diff --git a/drivers/serial/serial_bfin.c b/drivers/serial/serial_bfin.c index 0443b8427a..1d5be2a7a2 100644 --- a/drivers/serial/serial_bfin.c +++ b/drivers/serial/serial_bfin.c @@ -1,5 +1,5 @@ /* - * U-boot - serial.c Blackfin Serial Driver + * U-Boot - serial.c Blackfin Serial Driver * * Copyright (c) 2005-2008 Analog Devices Inc. * diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c deleted file mode 100644 index d43a5fedcc..0000000000 --- a/drivers/serial/serial_imx.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> -#include <serial.h> -#include <linux/compiler.h> - -#if defined CONFIG_IMX_SERIAL1 -#define UART_BASE IMX_UART1_BASE -#elif defined CONFIG_IMX_SERIAL2 -#define UART_BASE IMX_UART2_BASE -#else -#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" -#endif - -struct imx_serial { - volatile uint32_t urxd[16]; - volatile uint32_t utxd[16]; - volatile uint32_t ucr1; - volatile uint32_t ucr2; - volatile uint32_t ucr3; - volatile uint32_t ucr4; - volatile uint32_t ufcr; - volatile uint32_t usr1; - volatile uint32_t usr2; - volatile uint32_t uesc; - volatile uint32_t utim; - volatile uint32_t ubir; - volatile uint32_t ubmr; - volatile uint32_t ubrc; - volatile uint32_t bipr[4]; - volatile uint32_t bmpr[4]; - volatile uint32_t uts; -}; - -DECLARE_GLOBAL_DATA_PTR; - -static void imx_serial_setbrg(void) -{ - serial_init(); -} - -extern void imx_gpio_mode(int gpio_mode); - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int imx_serial_init(void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - unsigned int ufcr_rfdiv; - unsigned int refclk; - -#ifdef CONFIG_IMX_SERIAL1 - imx_gpio_mode(PC11_PF_UART1_TXD); - imx_gpio_mode(PC12_PF_UART1_RXD); -#else - imx_gpio_mode(PB30_PF_UART2_TXD); - imx_gpio_mode(PB31_PF_UART2_RXD); -#endif - - /* Disable UART */ - base->ucr1 &= ~UCR1_UARTEN; - - /* Set to default POR state */ - - base->ucr1 = 0x00000004; - base->ucr2 = 0x00000000; - base->ucr3 = 0x00000000; - base->ucr4 = 0x00008040; - base->uesc = 0x0000002B; - base->utim = 0x00000000; - base->ubir = 0x00000000; - base->ubmr = 0x00000000; - base->uts = 0x00000000; - /* Set clocks */ - base->ucr4 |= UCR4_REF16; - - /* Configure FIFOs */ - base->ufcr = 0xa81; - - /* set the baud rate. - * - * baud * 16 x - * --------- = - - * refclk y - * - * x - 1 = UBIR - * y - 1 = UBMR - * - * each register is 16 bits wide. refclk max is 96 MHz - * - */ - - ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7; - if (ufcr_rfdiv == 6) - ufcr_rfdiv = 7; - else - ufcr_rfdiv = 6 - ufcr_rfdiv; - - refclk = get_PERCLK1(); - refclk /= ufcr_rfdiv; - - /* Set the numerator value minus one of the BRM ratio */ - base->ubir = (gd->baudrate / 100) - 1; - - /* Set the denominator value minus one of the BRM ratio */ - base->ubmr = (refclk/(16 * 100)) - 1; - - /* Set to 8N1 */ - base->ucr2 &= ~UCR2_PREN; - base->ucr2 |= UCR2_WS; - base->ucr2 &= ~UCR2_STPB; - - /* Ignore RTS */ - base->ucr2 |= UCR2_IRTS; - - /* Enable UART */ - base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; - - /* Enable FIFOs */ - base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; - - /* Clear status flags */ - base->usr2 |= USR2_ADET | - USR2_DTRF | - USR2_IDLE | - USR2_IRINT | - USR2_WAKE | - USR2_RTSF | - USR2_BRCD | - USR2_ORE; - - /* Clear status flags */ - base->usr1 |= USR1_PARITYERR | - USR1_RTSD | - USR1_ESCF | - USR1_FRAMERR | - USR1_AIRINT | - USR1_AWAKE; - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is successful, the character read is - * written into its argument c. - */ -static int imx_serial_getc(void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - unsigned char ch; - - while(base->uts & UTS_RXEMPTY); - - ch = (char)base->urxd[0]; - - return ch; -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ -} -#endif - -/* - * Output a single byte to the serial port. - */ -static void imx_serial_putc(const char c) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* Wait for Tx FIFO not full */ - while (base->uts & UTS_TXFULL); - - base->utxd[0] = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -static int imx_serial_tstc(void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* If receive fifo is empty, return false */ - if (base->uts & UTS_RXEMPTY) - return 0; - return 1; -} - -static struct serial_device imx_serial_drv = { - .name = "imx_serial", - .start = imx_serial_init, - .stop = NULL, - .setbrg = imx_serial_setbrg, - .putc = imx_serial_putc, - .puts = default_serial_puts, - .getc = imx_serial_getc, - .tstc = imx_serial_tstc, -}; - -void imx_serial_initialize(void) -{ - serial_register(&imx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &imx_serial_drv; -} diff --git a/drivers/serial/serial_max3100.c b/drivers/serial/serial_max3100.c deleted file mode 100644 index 027d9194a7..0000000000 --- a/drivers/serial/serial_max3100.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2003 - * - * Pantelis Antoniou <panto@intracom.gr> - * Intracom S.A. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -/**************************************************************/ - -/* convienient macros */ -#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT) - -#define MAX3100_SPI_TXD(x) \ - do { \ - if (x) \ - MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \ - else \ - MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \ - } while(0) - -#define MAX3100_SPI_CLK(x) \ - do { \ - if (x) \ - MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \ - else \ - MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \ - } while(0) - -#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT) - -#define MAX3100_CS(x) \ - do { \ - if (x) \ - MAX3100_CS_PORT |= MAX3100_CS_BIT; \ - else \ - MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \ - } while(0) - -/**************************************************************/ - -/* MAX3100 definitions */ - -#define MAX3100_WC (3 << 14) /* write configuration */ -#define MAX3100_RC (1 << 14) /* read configuration */ -#define MAX3100_WD (2 << 14) /* write data */ -#define MAX3100_RD (0 << 14) /* read data */ - -/* configuration register bits */ -#define MAX3100_FEN (1 << 13) /* FIFO enable */ -#define MAX3100_SHDN (1 << 12) /* shutdown bit */ -#define MAX3100_TM (1 << 11) /* T bit irq mask */ -#define MAX3100_RM (1 << 10) /* R bit irq mask */ -#define MAX3100_PM (1 << 9) /* P bit irq mask */ -#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */ -#define MAX3100_IR (1 << 7) /* IRDA timing mode */ -#define MAX3100_ST (1 << 6) /* transmit stop bit */ -#define MAX3100_PE (1 << 5) /* parity enable bit */ -#define MAX3100_L (1 << 4) /* Length bit */ -#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */ -#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */ - -/* data register bits (write) */ -#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */ -#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */ - -/* data register bits (read) */ -#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */ -#define MAX3100_FE (1 << 10) /* framing error when in normal mode */ -#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */ - -/* data register bits (both directions) */ -#define MAX3100_R (1 << 15) /* receive bit */ -#define MAX3100_T (1 << 14) /* transmit bit */ -#define MAX3100_P (1 << 8) /* parity bit */ -#define MAX3100_D_MASK 0x00FF /* data bits mask */ -#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */ - -/* these definitions are valid only for fOSC = 3.6864MHz */ -#define MAX3100_B_230400 MAX3100_B(0) -#define MAX3100_B_115200 MAX3100_B(1) -#define MAX3100_B_57600 MAX3100_B(2) -#define MAX3100_B_38400 MAX3100_B(9) -#define MAX3100_B_19200 MAX3100_B(10) -#define MAX3100_B_9600 MAX3100_B(11) -#define MAX3100_B_4800 MAX3100_B(12) -#define MAX3100_B_2400 MAX3100_B(13) -#define MAX3100_B_1200 MAX3100_B(14) -#define MAX3100_B_600 MAX3100_B(15) - -/**************************************************************/ - -static inline unsigned int max3100_transfer(unsigned int val) -{ - unsigned int rx; - int b; - - MAX3100_SPI_CLK(0); - MAX3100_CS(0); - - rx = 0; b = 16; - while (--b >= 0) { - MAX3100_SPI_TXD(val & 0x8000); - val <<= 1; - MAX3100_SPI_CLK_TOGGLE(); - udelay(1); - rx <<= 1; - if (MAX3100_SPI_RXD()) - rx |= 1; - MAX3100_SPI_CLK_TOGGLE(); - udelay(1); - } - - MAX3100_SPI_CLK(1); - MAX3100_CS(1); - - return rx; -} - -/**************************************************************/ - -/* must be power of 2 */ -#define RXFIFO_SZ 16 - -static int rxfifo_cnt; -static int rxfifo_in; -static int rxfifo_out; -static unsigned char rxfifo_buf[16]; - -static void max3100_serial_putc_raw(int c) -{ - unsigned int rx; - - while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0) - WATCHDOG_RESET(); - - rx = max3100_transfer(MAX3100_WD | (c & 0xff)); - if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) { - rxfifo_cnt++; - rxfifo_buf[rxfifo_in++] = rx & 0xff; - rxfifo_in &= RXFIFO_SZ - 1; - } -} - -static int max3100_serial_getc(void) -{ - int c; - unsigned int rx; - - while (rxfifo_cnt == 0) { - rx = max3100_transfer(MAX3100_RD); - if ((rx & MAX3100_R) != 0) { - do { - rxfifo_cnt++; - rxfifo_buf[rxfifo_in++] = rx & 0xff; - rxfifo_in &= RXFIFO_SZ - 1; - - if (rxfifo_cnt >= RXFIFO_SZ) - break; - } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); - } - WATCHDOG_RESET(); - } - - rxfifo_cnt--; - c = rxfifo_buf[rxfifo_out++]; - rxfifo_out &= RXFIFO_SZ - 1; - return c; -} - -static int max3100_serial_tstc(void) -{ - unsigned int rx; - - if (rxfifo_cnt > 0) - return 1; - - rx = max3100_transfer(MAX3100_RD); - if ((rx & MAX3100_R) == 0) - return 0; - - do { - rxfifo_cnt++; - rxfifo_buf[rxfifo_in++] = rx & 0xff; - rxfifo_in &= RXFIFO_SZ - 1; - - if (rxfifo_cnt >= RXFIFO_SZ) - break; - } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); - - return 1; -} - -static int max3100_serial_init(void) -{ - unsigned int wconf, rconf; - int i; - - wconf = 0; - - /* Set baud rate */ - switch (gd->baudrate) { - case 1200: - wconf = MAX3100_B_1200; - break; - case 2400: - wconf = MAX3100_B_2400; - break; - case 4800: - wconf = MAX3100_B_4800; - break; - case 9600: - wconf = MAX3100_B_9600; - break; - case 19200: - wconf = MAX3100_B_19200; - break; - case 38400: - wconf = MAX3100_B_38400; - break; - case 57600: - wconf = MAX3100_B_57600; - break; - default: - case 115200: - wconf = MAX3100_B_115200; - break; - case 230400: - wconf = MAX3100_B_230400; - break; - } - - /* try for 10ms, with a 100us gap */ - for (i = 0; i < 10000; i += 100) { - - max3100_transfer(MAX3100_WC | wconf); - rconf = max3100_transfer(MAX3100_RC) & 0x3fff; - - if (rconf == wconf) - break; - udelay(100); - } - - rxfifo_in = rxfifo_out = rxfifo_cnt = 0; - - return (0); -} - -static void max3100_serial_putc(const char c) -{ - if (c == '\n') - max3100_serial_putc_raw('\r'); - - max3100_serial_putc_raw(c); -} - -static void max3100_serial_puts(const char *s) -{ - while (*s) - max3100_serial_putc_raw(*s++); -} - -static void max3100_serial_setbrg(void) -{ -} - -static struct serial_device max3100_serial_drv = { - .name = "max3100_serial", - .start = max3100_serial_init, - .stop = NULL, - .setbrg = max3100_serial_setbrg, - .putc = max3100_serial_putc, - .puts = max3100_serial_puts, - .getc = max3100_serial_getc, - .tstc = max3100_serial_tstc, -}; - -void max3100_serial_initialize(void) -{ - serial_register(&max3100_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &max3100_serial_drv; -} diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 7afc5044a8..d4e7df27be 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -65,10 +65,6 @@ DECLARE_GLOBAL_DATA_PTR; .puts = s3serial##port##_puts, \ } -#ifdef CONFIG_HWFLOW -static int hwflow; -#endif - static void _serial_setbrg(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); @@ -95,10 +91,6 @@ static int serial_init_dev(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); -#ifdef CONFIG_HWFLOW - hwflow = 0; /* turned off by default */ -#endif - /* FIFO enable, Tx/Rx FIFO clear */ writel(0x07, &uart->ufcon); writel(0x0, &uart->umcon); @@ -111,16 +103,6 @@ static int serial_init_dev(const int dev_index) */ writel(0x245, &uart->ucon); -#ifdef CONFIG_HWFLOW - writel(0x1, &uart->umcon); /* rts up */ -#endif - - /* FIXME: This is sooooooooooooooooooo ugly */ -#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) - /* we need auto hw flow control on the gsm and gps port */ - if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->umcon); -#endif _serial_setbrg(dev_index); return (0); @@ -146,57 +128,16 @@ static inline int serial_getc_dev(unsigned int dev_index) return _serial_getc(dev_index); } -#ifdef CONFIG_HWFLOW -int hwflow_onoff(int on) -{ - switch (on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - /* * Output a single byte to the serial port. */ static void _serial_putc(const char c, const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ; -#ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->umstat) & 0x1)) - /* Wait for CTS up */ ; -#endif - writeb(c, &uart->utxh); /* If \n, also do \r */ diff --git a/drivers/serial/serial_sa1100.c b/drivers/serial/serial_sa1100.c deleted file mode 100644 index 78f241d850..0000000000 --- a/drivers/serial/serial_sa1100.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <SA-1100.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void sa1100_serial_setbrg(void) -{ - unsigned int reg = 0; - - if (gd->baudrate == 1200) - reg = 191; - else if (gd->baudrate == 9600) - reg = 23; - else if (gd->baudrate == 19200) - reg = 11; - else if (gd->baudrate == 38400) - reg = 5; - else if (gd->baudrate == 57600) - reg = 3; - else if (gd->baudrate == 115200) - reg = 1; - else - hang (); - -#ifdef CONFIG_SERIAL1 - /* SA1110 uart function */ - Ser1SDCR0 |= SDCR0_SUS; - - /* Wait until port is ready ... */ - while(Ser1UTSR1 & UTSR1_TBY) {} - - /* init serial serial 1 */ - Ser1UTCR3 = 0x00; - Ser1UTSR0 = 0xff; - Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData ); - Ser1UTCR1 = 0; - Ser1UTCR2 = (u32)reg; - Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE ); -#elif defined(CONFIG_SERIAL3) - /* Wait until port is ready ... */ - while (Ser3UTSR1 & UTSR1_TBY) { - } - - /* init serial serial 3 */ - Ser3UTCR3 = 0x00; - Ser3UTSR0 = 0xff; - Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData); - Ser3UTCR1 = 0; - Ser3UTCR2 = (u32) reg; - Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE); -#else -#error "Bad: you didn't configured serial ..." -#endif -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int sa1100_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void sa1100_serial_putc(const char c) -{ -#ifdef CONFIG_SERIAL1 - /* wait for room in the tx FIFO on SERIAL1 */ - while ((Ser1UTSR0 & UTSR0_TFS) == 0); - - Ser1UTDR = c; -#elif defined(CONFIG_SERIAL3) - /* wait for room in the tx FIFO on SERIAL3 */ - while ((Ser3UTSR0 & UTSR0_TFS) == 0); - - Ser3UTDR = c; -#endif - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int sa1100_serial_tstc(void) -{ -#ifdef CONFIG_SERIAL1 - return Ser1UTSR1 & UTSR1_RNE; -#elif defined(CONFIG_SERIAL3) - return Ser3UTSR1 & UTSR1_RNE; -#endif -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int sa1100_serial_getc(void) -{ -#ifdef CONFIG_SERIAL1 - while (!(Ser1UTSR1 & UTSR1_RNE)); - - return (char) Ser1UTDR & 0xff; -#elif defined(CONFIG_SERIAL3) - while (!(Ser3UTSR1 & UTSR1_RNE)); - - return (char) Ser3UTDR & 0xff; -#endif -} - -static struct serial_device sa1100_serial_drv = { - .name = "sa1100_serial", - .start = sa1100_serial_init, - .stop = NULL, - .setbrg = sa1100_serial_setbrg, - .putc = sa1100_serial_putc, - .puts = default_serial_puts, - .getc = sa1100_serial_getc, - .tstc = sa1100_serial_tstc, -}; - -void sa1100_serial_initialize(void) -{ - serial_register(&sa1100_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &sa1100_serial_drv; -} diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 91a5dde577..c793ba6e90 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -35,24 +35,6 @@ struct stm32_usart { DECLARE_GLOBAL_DATA_PTR; -#define MAX_SERIAL_PORTS 4 - -/* - * RCC USART specific definitions - */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) - -/* Array used to figure out which RCC bit needs to be set */ -static const unsigned long usart_port_rcc_pairs[MAX_SERIAL_PORTS][2] = { - { STM32_USART1_BASE, RCC_ENR_USART1EN }, - { STM32_USART2_BASE, RCC_ENR_USART2EN }, - { STM32_USART3_BASE, RCC_ENR_USART3EN }, - { STM32_USART6_BASE, RCC_ENR_USART6EN } -}; - static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { struct stm32_serial_platdata *plat = dev->platdata; @@ -114,28 +96,6 @@ static int stm32_serial_probe(struct udevice *dev) { struct stm32_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; - int usart_port = -1; - int i; - - for (i = 0; i < MAX_SERIAL_PORTS; i++) { - if ((u32)usart == usart_port_rcc_pairs[i][0]) { - usart_port = i; - break; - } - } - - if (usart_port == -1) - return -EINVAL; - - if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) - setbits_le32(&STM32_RCC->apb1enr, - usart_port_rcc_pairs[usart_port][1]); - else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) - setbits_le32(&STM32_RCC->apb2enr, - usart_port_rcc_pairs[usart_port][1]); - else - return -EINVAL; - setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); return 0; diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 99345eb9a0..69f680cc11 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -1,5 +1,5 @@ # -# Makefile for the U-boot SOC specific device drivers. +# Makefile for the U-Boot SOC specific device drivers. # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index e543b8f0cf..00b2fed7b7 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -5,6 +5,7 @@ * * This file is derived from the flashrom project. */ + #include <common.h> #include <dm.h> #include <errno.h> @@ -17,8 +18,7 @@ #include "ich.h" -#define SPI_OPCODE_WREN 0x06 -#define SPI_OPCODE_FAST_READ 0x0b +DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG_TRACE #define debug_trace(fmt, args...) debug(fmt, ##args) @@ -26,32 +26,6 @@ #define debug_trace(x, args...) #endif -struct ich_spi_platdata { - enum pch_version ich_version; /* Controller version, 7 or 9 */ -}; - -struct ich_spi_priv { - int ichspi_lock; - int locked; - int opmenu; - int menubytes; - void *base; /* Base of register set */ - int preop; - int optype; - int addr; - int data; - unsigned databytes; - int status; - int control; - int bbar; - int bcr; - uint32_t *pr; /* only for ich9 */ - int speed; /* pointer to speed control */ - ulong max_speed; /* Maximum bus speed in MHz */ - ulong cur_speed; /* Current bus speed */ - struct spi_trans trans; /* current transaction in progress */ -}; - static u8 ich_readb(struct ich_spi_priv *priv, int reg) { u8 value = readb(priv->base + reg); @@ -145,11 +119,11 @@ static int ich_init_controller(struct udevice *dev, void *sbase; /* SBASE is similar */ - pch_get_sbase(dev->parent, &sbase_addr); + pch_get_spi_base(dev->parent, &sbase_addr); sbase = (void *)sbase_addr; debug("%s: sbase=%p\n", __func__, sbase); - if (plat->ich_version == PCHV_7) { + if (plat->ich_version == ICHV_7) { struct ich7_spi_regs *ich7_spi = sbase; ich7_spi = (struct ich7_spi_regs *)sbase; @@ -165,7 +139,7 @@ static int ich_init_controller(struct udevice *dev, ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); ctlr->preop = offsetof(struct ich7_spi_regs, preop); ctlr->base = ich7_spi; - } else if (plat->ich_version == PCHV_9) { + } else if (plat->ich_version == ICHV_9) { struct ich9_spi_regs *ich9_spi = sbase; ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; @@ -191,7 +165,7 @@ static int ich_init_controller(struct udevice *dev, /* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; - if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev)) + if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) ctlr->max_speed = 33000000; debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", plat->ich_version, ctlr->base, ctlr->max_speed); @@ -217,7 +191,7 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes) { trans->type = 0xFF; - /* Try to guess spi type from read/write sizes. */ + /* Try to guess spi type from read/write sizes */ if (trans->bytesin == 0) { if (trans->bytesout + data_bytes > 4) /* @@ -301,7 +275,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) static int spi_setup_offset(struct spi_trans *trans) { - /* Separate the SPI address and data. */ + /* Separate the SPI address and data */ switch (trans->type) { case SPI_OPCODE_TYPE_READ_NO_ADDRESS: case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: @@ -410,7 +384,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, trans->in = din; trans->bytesin = din ? bytes : 0; - /* There has to always at least be an opcode. */ + /* There has to always at least be an opcode */ if (!trans->bytesout) { debug("ICH SPI: No opcode for transfer\n"); return -EPROTO; @@ -420,7 +394,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (ret < 0) return ret; - if (plat->ich_version == PCHV_7) + if (plat->ich_version == ICHV_7) ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); else ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); @@ -541,7 +515,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, /* write it */ ich_writew(ctlr, control, ctlr->control); - /* Wait for Cycle Done Status or Flash Cycle Error. */ + /* Wait for Cycle Done Status or Flash Cycle Error */ status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); if (status < 0) return status; @@ -622,9 +596,6 @@ static int ich_spi_probe(struct udevice *dev) uint8_t bios_cntl; int ret; - /* Check the ICH version */ - plat->ich_version = pch_get_version(dev->parent); - ret = ich_init_controller(dev, plat, priv); if (ret) return ret; @@ -678,7 +649,7 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */ - if (plat->ich_version == PCHV_7) { + if (plat->ich_version == ICHV_7) { slave->mode_rx = SPI_RX_SLOW; slave->mode = SPI_TX_BYTE; } @@ -686,6 +657,25 @@ static int ich_spi_child_pre_probe(struct udevice *dev) return 0; } +static int ich_spi_ofdata_to_platdata(struct udevice *dev) +{ + struct ich_spi_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset, + "intel,ich7-spi"); + if (ret == 0) { + plat->ich_version = ICHV_7; + } else { + ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset, + "intel,ich9-spi"); + if (ret == 0) + plat->ich_version = ICHV_9; + } + + return ret; +} + static const struct dm_spi_ops ich_spi_ops = { .xfer = ich_spi_xfer, .set_speed = ich_spi_set_speed, @@ -697,7 +687,8 @@ static const struct dm_spi_ops ich_spi_ops = { }; static const struct udevice_id ich_spi_ids[] = { - { .compatible = "intel,ich-spi" }, + { .compatible = "intel,ich7-spi" }, + { .compatible = "intel,ich9-spi" }, { } }; @@ -706,6 +697,7 @@ U_BOOT_DRIVER(ich_spi) = { .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops, + .ofdata_to_platdata = ich_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), .priv_auto_alloc_size = sizeof(struct ich_spi_priv), .child_pre_probe = ich_spi_child_pre_probe, diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 1419b23e11..bd0a820809 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -6,6 +6,9 @@ * This file is derived from the flashrom project. */ +#ifndef _ICH_H_ +#define _ICH_H_ + struct ich7_spi_regs { uint16_t spis; uint16_t spic; @@ -19,34 +22,34 @@ struct ich7_spi_regs { } __packed; struct ich9_spi_regs { - uint32_t bfpr; /* 0x00 */ + uint32_t bfpr; /* 0x00 */ uint16_t hsfs; uint16_t hsfc; uint32_t faddr; uint32_t _reserved0; - uint32_t fdata[16]; /* 0x10 */ - uint32_t frap; /* 0x50 */ + uint32_t fdata[16]; /* 0x10 */ + uint32_t frap; /* 0x50 */ uint32_t freg[5]; uint32_t _reserved1[3]; - uint32_t pr[5]; /* 0x74 */ + uint32_t pr[5]; /* 0x74 */ uint32_t _reserved2[2]; - uint8_t ssfs; /* 0x90 */ + uint8_t ssfs; /* 0x90 */ uint8_t ssfc[3]; - uint16_t preop; /* 0x94 */ + uint16_t preop; /* 0x94 */ uint16_t optype; - uint8_t opmenu[8]; /* 0x98 */ + uint8_t opmenu[8]; /* 0x98 */ uint32_t bbar; uint8_t _reserved3[12]; - uint32_t fdoc; /* 0xb0 */ + uint32_t fdoc; /* 0xb0 */ uint32_t fdod; uint8_t _reserved4[8]; - uint32_t afc; /* 0xc0 */ + uint32_t afc; /* 0xc0 */ uint32_t lvscc; uint32_t uvscc; uint8_t _reserved5[4]; - uint32_t fpb; /* 0xd0 */ + uint32_t fpb; /* 0xd0 */ uint8_t _reserved6[28]; - uint32_t srdl; /* 0xf0 */ + uint32_t srdl; /* 0xf0 */ uint32_t srdc; uint32_t scs; uint32_t bcr; @@ -121,8 +124,38 @@ struct spi_trans { uint32_t offset; }; -struct ich_spi_slave { - struct spi_slave slave; +#define SPI_OPCODE_WREN 0x06 +#define SPI_OPCODE_FAST_READ 0x0b + +enum ich_version { + ICHV_7, + ICHV_9, +}; + +struct ich_spi_platdata { + enum ich_version ich_version; /* Controller version, 7 or 9 */ +}; + +struct ich_spi_priv { + int ichspi_lock; + int locked; + int opmenu; + int menubytes; + void *base; /* Base of register set */ + int preop; + int optype; + int addr; + int data; + unsigned databytes; + int status; + int control; + int bbar; + int bcr; + uint32_t *pr; /* only for ich9 */ + int speed; /* pointer to speed control */ + ulong max_speed; /* Maximum bus speed in MHz */ + ulong cur_speed; /* Current bus speed */ struct spi_trans trans; /* current transaction in progress */ - int speed; /* SPI speed in Hz */ }; + +#endif /* _ICH_H_ */ diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index a13b21d0a0..60f9272ae6 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -2,7 +2,7 @@ * composite.c - infrastructure for Composite USB Gadgets * * Copyright (C) 2006-2008 David Brownell - * U-boot porting: Lukasz Majewski <l.majewski@samsung.com> + * U-Boot porting: Lukasz Majewski <l.majewski@samsung.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c index 014a6791c1..64284b06f8 100644 --- a/drivers/usb/gadget/config.c +++ b/drivers/usb/gadget/config.c @@ -5,7 +5,7 @@ * * SPDX-License-Identifier: GPL-2.0+ * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index ffe2952f56..cb20b00a56 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -557,8 +557,8 @@ static int dwc2_ep_enable(struct usb_ep *_ep, } /* hardware _could_ do smaller, but driver doesn't */ - if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK - && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) != + if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK && + le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) > ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) { debug("%s: bad %s maxpacket\n", __func__, _ep->name); diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 6ddbe83deb..a53a6dcda3 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -7,7 +7,7 @@ * * SPDX-License-Identifier: GPL-2.0+ * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index cfe9a24e24..9b06f028d6 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -256,7 +256,7 @@ static inline int BITRATE(struct usb_gadget *g) #if defined(CONFIG_USBNET_MANUFACTURER) static char *iManufacturer = CONFIG_USBNET_MANUFACTURER; #else -static char *iManufacturer = "U-boot"; +static char *iManufacturer = "U-Boot"; #endif /* These probably need to be configurable. */ diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e9811c3864..973cd971ad 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -11,7 +11,7 @@ * Some are available on 2.4 kernels; several are available, but not * yet pushed in the 2.6 mainline tree. * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ #ifdef CONFIG_USB_GADGET_NET2280 diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index 8c3ff64fe3..3e24fbf80e 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: LGPL-2.1+ * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 39f7185e86..9332374193 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -74,13 +74,6 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. -config USB_EHCI_UNIPHIER - bool "Support for UniPhier on-chip EHCI USB controller" - depends on ARCH_UNIPHIER && OF_CONTROL - default y - ---help--- - Enables support for the on-chip EHCI controller on UniPhier SoCs. - config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6183b80c75..9a87d2bf62 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o -obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 9a8f004ece..1d7d28048b 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -7,44 +7,21 @@ */ #include <common.h> -#include <watchdog.h> #include <usb.h> #include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> #include "ehci.h" -/* Enable UTMI PLL time out 500us - * 10 times as datasheet specified - */ -#define EN_UPLL_TIMEOUT 500UL - int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - ulong start_time, tmp_time; - - start_time = get_timer(0); /* Enable UTMI PLL */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) { - WATCHDOG_RESET(); - tmp_time = get_timer(0); - if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { - printf("ERROR: failed to enable UPLL\n"); - return -1; - } - } + if (at91_upll_clk_enable()) + return -1; /* Enable USB Host clock */ -#ifdef CPU_HAS_PCR at91_periph_clk_enable(ATMEL_ID_UHPHS); -#else - writel(1 << ATMEL_ID_UHPHS, &pmc->pcer); -#endif *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; *hcor = (struct ehci_hcor *)((uint32_t)*hccr + @@ -55,27 +32,12 @@ int ehci_hcd_init(int index, enum usb_init_type init, int ehci_hcd_stop(int index) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - ulong start_time, tmp_time; - /* Disable USB Host Clock */ -#ifdef CPU_HAS_PCR at91_periph_clk_disable(ATMEL_ID_UHPHS); -#else - writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr); -#endif - start_time = get_timer(0); /* Disable UTMI PLL */ - writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) { - WATCHDOG_RESET(); - tmp_time = get_timer(0); - if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { - printf("ERROR: failed to stop UPLL\n"); - return -1; - } - } + if (at91_upll_clk_disable()) + return -1; return 0; } diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c deleted file mode 100644 index c3f827ca0a..0000000000 --- a/drivers/usb/host/ehci-uniphier.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/err.h> -#include <linux/io.h> -#include <usb.h> -#include <mach/mio-regs.h> -#include <fdtdec.h> -#include "ehci.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define FDT gd->fdt_blob -#define COMPAT "socionext,uniphier-ehci" - -static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) -{ - int offset; - - for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT); - offset >= 0; - offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) { - if (index == 0) { - *base = (struct ehci_hccr *) - fdtdec_get_addr(FDT, offset, "reg"); - return 0; - } - index--; - } - - return -ENODEV; /* not found */ -} - -static void uniphier_ehci_reset(int index, int on) -{ - u32 tmp; - - tmp = readl(MIO_USB_RSTCTRL(index)); - if (on) - tmp &= ~MIO_USB_RSTCTRL_XRST; - else - tmp |= MIO_USB_RSTCTRL_XRST; - writel(tmp, MIO_USB_RSTCTRL(index)); -} - -int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, - struct ehci_hcor **hcor) -{ - int ret; - struct ehci_hccr *cr; - struct ehci_hcor *or; - - uniphier_ehci_reset(index, 0); - - ret = get_uniphier_ehci_base(index, &cr); - if (ret < 0) - return ret; - or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase)); - - *hccr = cr; - *hcor = or; - - return 0; -} - -int ehci_hcd_stop(int index) -{ - uniphier_ehci_reset(index, 1); - - return 0; -} diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 820e2e56ef..e030a0ab14 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -9,45 +9,29 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> int usb_cpu_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB - /* Enable PLLB */ - writel(get_pllb_init(), &pmc->pllbr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) - ; + if (at91_pllb_clk_enable(get_pllb_init())) + return -1; + #ifdef CONFIG_AT91SAM9N12 - writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb); + at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2); #endif #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) - /* Enable UPLL */ - writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, - &pmc->uckr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) - ; - - /* Select PLLA as input clock of OHCI */ - writel(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10, &pmc->usb); + if (at91_upll_clk_enable()) + return -1; + + at91_usb_clk_init(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10); #endif - /* Enable USB host clock. */ -#ifdef CPU_HAS_PCR at91_periph_clk_enable(ATMEL_ID_UHP); -#else - writel(1 << ATMEL_ID_UHP, &pmc->pcer); -#endif + at91_system_clk_enable(ATMEL_PMC_UHP); #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) - writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); -#else - writel(ATMEL_PMC_UHP, &pmc->scer); + at91_system_clk_enable(AT91_PMC_HCK0); #endif return 0; @@ -55,34 +39,24 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - - /* Disable USB host clock. */ -#ifdef CPU_HAS_PCR at91_periph_clk_disable(ATMEL_ID_UHP); -#else - writel(1 << ATMEL_ID_UHP, &pmc->pcdr); -#endif + at91_system_clk_disable(ATMEL_PMC_UHP); #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) - writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); -#else - writel(ATMEL_PMC_UHP, &pmc->scdr); + at91_system_clk_disable(AT91_PMC_HCK0); #endif #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB #ifdef CONFIG_AT91SAM9N12 - writel(0, &pmc->usb); + at91_usb_clk_init(0); #endif - /* Disable PLLB */ - writel(0, &pmc->pllbr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) - ; + + if (at91_pllb_clk_disable()) + return -1; + #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) - /* Disable UPLL */ - writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) - ; + if (at91_upll_clk_disable()) + return -1; #endif return 0; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fbc5d7cfe7..ff4179fcd8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -91,6 +91,16 @@ config CONSOLE_TRUETYPE_SIZE source "drivers/video/fonts/Kconfig" +config VIDCONSOLE_AS_LCD + bool "Use 'vidconsole' when 'lcd' is seen in stdout" + depends on DM_VIDEO + help + This is a work-around for boards which have 'lcd' in their stdout + environment variable, but have moved to use driver model for video. + In this case the console will no-longer work. While it is possible + to update the environment, the breakage may be confusing for users. + This option will be removed around the end of 2016. + config VIDEO_VESA bool "Enable VESA video driver support" default n @@ -371,8 +381,18 @@ config VIDEO_SANDBOX_SDL console device and can display stdout output. Within U-Boot is is a normal bitmap display and can display images as well as text. +config VIDEO_TEGRA20 + bool "Enable LCD support on Tegra20" + depends on OF_CONTROL + help + Tegra20 supports video output to an attached LCD panel as well as + other options such as HDMI. Only the LCD is supported in U-Boot. + This option enables this support which can be used on devices which + have an LCD display connected. + config VIDEO_TEGRA124 bool "Enable video support on Tegra124" + depends on DM_VIDEO help Tegra124 supports many video output options including eDP and HDMI. At present only eDP is supported by U-Boot. This option diff --git a/drivers/video/Makefile b/drivers/video/Makefile index c55e6eda3b..d19a1d9042 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -57,7 +57,7 @@ obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o -obj-$(CONFIG_VIDEO_TEGRA) += tegra.o +obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o obj-$(CONFIG_FORMIKE) += formike.o diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 7867fe3895..bff1fcb9ea 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -7,6 +7,7 @@ #include <common.h> #include <lcd.h> #include <memalign.h> +#include <phys2bus.h> #include <asm/arch/mbox.h> #include <asm/global_data.h> @@ -103,7 +104,8 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_row = h; panel_info.vl_bpix = LCD_COLOR16; - gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address; + gd->fb_base = bus_to_phys( + msg_setup->allocate_buffer.body.resp.fb_address); } void lcd_enable(void) diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index b161517674..c73f24295a 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -85,6 +85,7 @@ static const struct panel_ops simple_panel_ops = { static const struct udevice_id simple_panel_ids[] = { { .compatible = "simple-panel" }, + { .compatible = "auo,b133xtn01" }, { } }; diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 8e8134614e..7fd10e6af3 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -4,11 +4,13 @@ */ #include <common.h> +#include <dm.h> #include <fdtdec.h> -#include <lcd.h> - +#include <pwm.h> +#include <video.h> #include <asm/system.h> #include <asm/gpio.h> +#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> @@ -30,165 +32,347 @@ enum stage_t { STAGE_DONE, }; -static enum stage_t stage; /* Current stage we are at */ -static unsigned long timer_next; /* Time we can move onto next stage */ +#define FDT_LCD_TIMINGS 4 + +enum { + FDT_LCD_TIMING_REF_TO_SYNC, + FDT_LCD_TIMING_SYNC_WIDTH, + FDT_LCD_TIMING_BACK_PORCH, + FDT_LCD_TIMING_FRONT_PORCH, + + FDT_LCD_TIMING_COUNT, +}; + +enum lcd_cache_t { + FDT_LCD_CACHE_OFF = 0, + FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, + FDT_LCD_CACHE_WRITE_BACK = 1 << 1, + FDT_LCD_CACHE_FLUSH = 1 << 2, + FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | + FDT_LCD_CACHE_FLUSH, +}; + +/* Information about the display controller */ +struct tegra_lcd_priv { + enum stage_t stage; /* Current stage we are at */ + unsigned long timer_next; /* Time we can move onto next stage */ + int width; /* width in pixels */ + int height; /* height in pixels */ -/* Our LCD config, set up in handle_stage() */ -static struct fdt_panel_config config; -struct fdt_disp_config *disp_config; /* Display controller config */ + /* + * log2 of number of bpp, in general, unless it bpp is 24 in which + * case this field holds 24 also! This is a U-Boot thing. + */ + int log2_bpp; + struct disp_ctlr *disp; /* Display controller to use */ + fdt_addr_t frame_buffer; /* Address of frame buffer */ + unsigned pixel_clock; /* Pixel clock in Hz */ + uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ + uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ + struct udevice *pwm; + int pwm_channel; /* PWM channel to use for backlight */ + enum lcd_cache_t cache_type; + + struct gpio_desc backlight_en; /* GPIO for backlight enable */ + struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ + struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ + struct gpio_desc panel_vdd; /* GPIO for panel vdd */ + /* + * Panel required timings + * Timing 1: delay between panel_vdd-rise and data-rise + * Timing 2: delay between data-rise and backlight_vdd-rise + * Timing 3: delay between backlight_vdd and pwm-rise + * Timing 4: delay between pwm-rise and backlight_en-rise + */ + uint panel_timings[FDT_LCD_TIMINGS]; +}; enum { /* Maximum LCD size we support */ LCD_MAX_WIDTH = 1366, LCD_MAX_HEIGHT = 768, - LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ + LCD_MAX_LOG2_BPP = VIDEO_BPP16, }; -vidinfo_t panel_info = { - /* Insert a value here so that we don't end up in the BSS */ - .vl_col = -1, -}; +static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) +{ + unsigned h_dda, v_dda; + unsigned long val; -#if !CONFIG_IS_ENABLED(OF_CONTROL) -#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support" -#endif + val = readl(&dc->cmd.disp_win_header); + val |= WINDOW_A_SELECT; + writel(val, &dc->cmd.disp_win_header); -static void update_panel_size(struct fdt_disp_config *config) -{ - panel_info.vl_col = config->width; - panel_info.vl_row = config->height; - panel_info.vl_bpix = config->log2_bpp; + writel(win->fmt, &dc->win.color_depth); + + clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, + BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); + + val = win->out_x << H_POSITION_SHIFT; + val |= win->out_y << V_POSITION_SHIFT; + writel(val, &dc->win.pos); + + val = win->out_w << H_SIZE_SHIFT; + val |= win->out_h << V_SIZE_SHIFT; + writel(val, &dc->win.size); + + val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; + val |= win->h << V_PRESCALED_SIZE_SHIFT; + writel(val, &dc->win.prescaled_size); + + writel(0, &dc->win.h_initial_dda); + writel(0, &dc->win.v_initial_dda); + + h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); + v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); + + val = h_dda << H_DDA_INC_SHIFT; + val |= v_dda << V_DDA_INC_SHIFT; + writel(val, &dc->win.dda_increment); + + writel(win->stride, &dc->win.line_stride); + writel(0, &dc->win.buf_stride); + + val = WIN_ENABLE; + if (win->bpp < 24) + val |= COLOR_EXPAND; + writel(val, &dc->win.win_opt); + + writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); + writel(win->x, &dc->winbuf.addr_h_offset); + writel(win->y, &dc->winbuf.addr_v_offset); + + writel(0xff00, &dc->win.blend_nokey); + writel(0xff00, &dc->win.blend_1win); + + val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; + val |= GENERAL_UPDATE | WIN_A_UPDATE; + writel(val, &dc->cmd.state_ctrl); } -/* - * Main init function called by lcd driver. - * Inits and then prints test pattern if required. - */ +static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg) +{ + writel(priv->horiz_timing[item] | + (priv->vert_timing[item] << 16), reg); +} -void lcd_ctrl_init(void *lcdbase) +static int update_display_mode(struct dc_disp_reg *disp, + struct tegra_lcd_priv *priv) { - int type = DCACHE_OFF; - int size; + unsigned long val; + unsigned long rate; + unsigned long div; - assert(disp_config); + writel(0x0, &disp->disp_timing_opt); + write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync); + write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width); + write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch); + write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch); - /* Make sure that we can acommodate the selected LCD */ - assert(disp_config->width <= LCD_MAX_WIDTH); - assert(disp_config->height <= LCD_MAX_HEIGHT); - assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP); - if (disp_config->width <= LCD_MAX_WIDTH - && disp_config->height <= LCD_MAX_HEIGHT - && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP) - update_panel_size(disp_config); - size = lcd_get_size(&lcd_line_length); + writel(priv->width | (priv->height << 16), &disp->disp_active); - /* Set up the LCD caching as requested */ - if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH) - type = DCACHE_WRITETHROUGH; - else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK) - type = DCACHE_WRITEBACK; - mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type); + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; + writel(val, &disp->data_enable_opt); - /* Enable flushing after LCD writes if requested */ - lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; + writel(val, &disp->disp_interface_ctrl); + + /* + * The pixel clock divider is in 7.1 format (where the bottom bit + * represents 0.5). Here we calculate the divider needed to get from + * the display clock (typically 600MHz) to the pixel clock. We round + * up or down as requried. + */ + rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); + div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; + debug("Display clock %lu, divider %lu\n", rate, div); + + writel(0x00010001, &disp->shift_clk_opt); - debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer); + val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; + val |= div << SHIFT_CLK_DIVIDER_SHIFT; + writel(val, &disp->disp_clk_ctrl); + + return 0; } -ulong calc_fbsize(void) +/* Start up the display and turn on power to PWMs */ +static void basic_init(struct dc_cmd_reg *cmd) { - return (panel_info.vl_col * panel_info.vl_row * - NBITS(panel_info.vl_bpix)) / 8; + u32 val; + + writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); + writel(0x0000011a, &cmd->cont_syncpt_vsync); + writel(0x00000000, &cmd->int_type); + writel(0x00000000, &cmd->int_polarity); + writel(0x00000000, &cmd->int_mask); + writel(0x00000000, &cmd->int_enb); + + val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; + val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; + val |= PM1_ENABLE; + writel(val, &cmd->disp_pow_ctrl); + + val = readl(&cmd->disp_cmd); + val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; + writel(val, &cmd->disp_cmd); } -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +static void basic_init_timer(struct dc_disp_reg *disp) { + writel(0x00000020, &disp->mem_high_pri); + writel(0x00000001, &disp->mem_high_pri_timer); } -void tegra_lcd_early_init(const void *blob) +static const u32 rgb_enb_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x01000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_data_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00210222, + 0x00002200, + 0x00020000, +}; + +static void rgb_enable(struct dc_com_reg *com) { - /* - * Go with the maximum size for now. We will fix this up after - * relocation. These values are only used for memory alocation. - */ - panel_info.vl_col = LCD_MAX_WIDTH; - panel_info.vl_row = LCD_MAX_HEIGHT; - panel_info.vl_bpix = LCD_MAX_LOG2_BPP; + int i; + + for (i = 0; i < PIN_REG_COUNT; i++) { + writel(rgb_enb_tab[i], &com->pin_output_enb[i]); + writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); + writel(rgb_data_tab[i], &com->pin_output_data[i]); + } + + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) + writel(rgb_sel_tab[i], &com->pin_output_sel[i]); +} + +static int setup_window(struct disp_ctl_win *win, + struct tegra_lcd_priv *priv) +{ + win->x = 0; + win->y = 0; + win->w = priv->width; + win->h = priv->height; + win->out_x = 0; + win->out_y = 0; + win->out_w = priv->width; + win->out_h = priv->height; + win->phys_addr = priv->frame_buffer; + win->stride = priv->width * (1 << priv->log2_bpp) / 8; + debug("%s: depth = %d\n", __func__, priv->log2_bpp); + switch (priv->log2_bpp) { + case 5: + case 24: + win->fmt = COLOR_DEPTH_R8G8B8A8; + win->bpp = 32; + break; + case 4: + win->fmt = COLOR_DEPTH_B5G6R5; + win->bpp = 16; + break; + + default: + debug("Unsupported LCD bit depth"); + return -1; + } + + return 0; +} + +static void debug_timing(const char *name, unsigned int timing[]) +{ +#ifdef DEBUG + int i; + + debug("%s timing: ", name); + for (i = 0; i < FDT_LCD_TIMING_COUNT; i++) + debug("%d ", timing[i]); + debug("\n"); +#endif } /** - * Decode the panel information from the fdt. + * Register a new display based on device tree configuration. * - * @param blob fdt blob - * @param config structure to store fdt config into - * @return 0 if ok, -ve on error + * The frame buffer can be positioned by U-Boot or overriden by the fdt. + * You should pass in the U-Boot address here, and check the contents of + * struct tegra_lcd_priv to see what was actually chosen. + * + * @param blob Device tree blob + * @param priv Driver's private data + * @param default_lcd_base Default address of LCD frame buffer + * @return 0 if ok, -1 on error (unsupported bits per pixel) */ -static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config) +static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, + void *default_lcd_base) { - int display_node; + struct disp_ctl_win window; + struct dc_ctlr *dc; - disp_config = tegra_display_get_config(); - if (!disp_config) { - debug("%s: Display controller is not configured\n", __func__); - return -1; - } - display_node = disp_config->panel_node; - if (display_node < 0) { - debug("%s: No panel configuration available\n", __func__); - return -1; - } + priv->frame_buffer = (u32)default_lcd_base; - config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm"); - if (config->pwm_channel < 0) { - debug("%s: Unable to request PWM channel\n", __func__); - return -1; - } + dc = (struct dc_ctlr *)priv->disp; - config->cache_type = fdtdec_get_int(blob, display_node, - "nvidia,cache-type", - FDT_LCD_CACHE_WRITE_BACK_FLUSH); + /* + * A header file for clock constants was NAKed upstream. + * TODO: Put this into the FDT and fdt_lcd struct when we have clock + * support there + */ + clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, + 144 * 1000000); + clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, + 600 * 1000000); + basic_init(&dc->cmd); + basic_init_timer(&dc->disp); + rgb_enable(&dc->com); + + if (priv->pixel_clock) + update_display_mode(&dc->disp, priv); + + if (setup_window(&window, priv)) + return -1; - /* These GPIOs are all optional */ - gpio_request_by_name_nodev(blob, display_node, - "nvidia,backlight-enable-gpios", 0, - &config->backlight_en, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, display_node, - "nvidia,lvds-shutdown-gpios", 0, - &config->lvds_shutdown, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, display_node, - "nvidia,backlight-vdd-gpios", 0, - &config->backlight_vdd, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, display_node, - "nvidia,panel-vdd-gpios", 0, - &config->panel_vdd, GPIOD_IS_OUT); + update_window(dc, &window); - return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings", - config->panel_timings, FDT_LCD_TIMINGS); + return 0; } /** * Handle the next stage of device init */ -static int handle_stage(const void *blob) +static int handle_stage(const void *blob, struct tegra_lcd_priv *priv) { - debug("%s: stage %d\n", __func__, stage); + debug("%s: stage %d\n", __func__, priv->stage); /* do the things for this stage */ - switch (stage) { + switch (priv->stage) { case STAGE_START: - /* Initialize the Tegra display controller */ - if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) { - printf("%s: Failed to probe display driver\n", - __func__); - return -1; - } - - /* get panel details */ - if (fdt_decode_lcd(blob, &config)) { - printf("No valid LCD information in device tree\n"); - return -1; - } - /* * It is possible that the FDT has requested that the LCD be * disabled. We currently don't support this. It would require @@ -202,52 +386,71 @@ static int handle_stage(const void *blob) funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); break; case STAGE_PANEL_VDD: - if (dm_gpio_is_valid(&config.panel_vdd)) - dm_gpio_set_value(&config.panel_vdd, 1); + if (dm_gpio_is_valid(&priv->panel_vdd)) + dm_gpio_set_value(&priv->panel_vdd, 1); break; case STAGE_LVDS: - if (dm_gpio_is_valid(&config.lvds_shutdown)) - dm_gpio_set_value(&config.lvds_shutdown, 1); + if (dm_gpio_is_valid(&priv->lvds_shutdown)) + dm_gpio_set_value(&priv->lvds_shutdown, 1); break; case STAGE_BACKLIGHT_VDD: - if (dm_gpio_is_valid(&config.backlight_vdd)) - dm_gpio_set_value(&config.backlight_vdd, 1); + if (dm_gpio_is_valid(&priv->backlight_vdd)) + dm_gpio_set_value(&priv->backlight_vdd, 1); break; case STAGE_PWM: /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); pinmux_tristate_disable(PMUX_PINGRP_GPU); - pwm_enable(config.pwm_channel, 32768, 0xdf, 1); + pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff); + pwm_set_enable(priv->pwm, priv->pwm_channel, true); break; case STAGE_BACKLIGHT_EN: - if (dm_gpio_is_valid(&config.backlight_en)) - dm_gpio_set_value(&config.backlight_en, 1); + if (dm_gpio_is_valid(&priv->backlight_en)) + dm_gpio_set_value(&priv->backlight_en, 1); break; case STAGE_DONE: break; } /* set up timer for next stage */ - timer_next = timer_get_us(); - if (stage < FDT_LCD_TIMINGS) - timer_next += config.panel_timings[stage] * 1000; + priv->timer_next = timer_get_us(); + if (priv->stage < FDT_LCD_TIMINGS) + priv->timer_next += priv->panel_timings[priv->stage] * 1000; /* move to next stage */ - stage++; + priv->stage++; return 0; } -int tegra_lcd_check_next_stage(const void *blob, int wait) +/** + * Perform the next stage of the LCD init if it is time to do so. + * + * LCD init can be time-consuming because of the number of delays we need + * while waiting for the backlight power supply, etc. This function can + * be called at various times during U-Boot operation to advance the + * initialization of the LCD to the next stage if sufficient time has + * passed since the last stage. It keeps track of what stage it is up to + * and the time that it is permitted to move to the next stage. + * + * The final call should have wait=1 to complete the init. + * + * @param blob fdt blob containing LCD information + * @param wait 1 to wait until all init is complete, and then return + * 0 to return immediately, potentially doing nothing if it is + * not yet time for the next init. + */ +static int tegra_lcd_check_next_stage(const void *blob, + struct tegra_lcd_priv *priv, int wait) { - if (stage == STAGE_DONE) + if (priv->stage == STAGE_DONE) return 0; do { /* wait if we need to */ - debug("%s: stage %d\n", __func__, stage); - if (stage != STAGE_START) { - int delay = timer_next - timer_get_us(); + debug("%s: stage %d\n", __func__, priv->stage); + if (priv->stage != STAGE_START) { + int delay = priv->timer_next - timer_get_us(); if (delay > 0) { if (wait) @@ -257,29 +460,188 @@ int tegra_lcd_check_next_stage(const void *blob, int wait) } } - if (handle_stage(blob)) + if (handle_stage(blob, priv)) return -1; - } while (wait && stage != STAGE_DONE); - if (stage == STAGE_DONE) + } while (wait && priv->stage != STAGE_DONE); + if (priv->stage == STAGE_DONE) debug("%s: LCD init complete\n", __func__); return 0; } -void lcd_enable(void) +static int tegra_lcd_probe(struct udevice *dev) { - /* - * Backlight and power init will be done separately in - * tegra_lcd_check_next_stage(), which should be called in - * board_late_init(). - * - * U-Boot code supports only colour depth, selected at compile time. - * The device tree setting should match this. Otherwise the display - * will not look right, and U-Boot may crash. - */ - if (disp_config->log2_bpp != LCD_BPP) { - printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)" - " must match setting of LCD_BPP (%d)\n", __func__, - disp_config->log2_bpp, disp_config->bpp, LCD_BPP); + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tegra_lcd_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int type = DCACHE_OFF; + + /* Initialize the Tegra display controller */ + if (tegra_display_probe(blob, priv, (void *)plat->base)) { + printf("%s: Failed to probe display driver\n", __func__); + return -1; } + + tegra_lcd_check_next_stage(blob, priv, 1); + + /* Set up the LCD caching as requested */ + if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH) + type = DCACHE_WRITETHROUGH; + else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK) + type = DCACHE_WRITEBACK; + mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type); + + /* Enable flushing after LCD writes if requested */ + video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH); + + uc_priv->xsize = priv->width; + uc_priv->ysize = priv->height; + uc_priv->bpix = priv->log2_bpp; + debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer, + plat->size); + + return 0; } + +static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) +{ + struct tegra_lcd_priv *priv = dev_get_priv(dev); + struct fdtdec_phandle_args args; + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + int front, back, ref; + int panel_node; + int rgb; + int bpp, bit; + int ret; + + priv->disp = (struct disp_ctlr *)dev_get_addr(dev); + if (!priv->disp) { + debug("%s: No display controller address\n", __func__); + return -EINVAL; + } + + rgb = fdt_subnode_offset(blob, node, "rgb"); + + panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); + if (panel_node < 0) { + debug("%s: Cannot find panel information\n", __func__); + return -EINVAL; + } + + priv->width = fdtdec_get_int(blob, panel_node, "xres", -1); + priv->height = fdtdec_get_int(blob, panel_node, "yres", -1); + priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0); + if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) { + debug("%s: Pixel parameters missing\n", __func__); + return -EINVAL; + } + + back = fdtdec_get_int(blob, panel_node, "left-margin", -1); + front = fdtdec_get_int(blob, panel_node, "right-margin", -1); + ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1); + if ((back | front | ref) == -1) { + debug("%s: Horizontal parameters missing\n", __func__); + return -EINVAL; + } + + /* Use a ref-to-sync of 1 always, and take this from the front porch */ + priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; + priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; + priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back; + priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - + priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC]; + debug_timing("horiz", priv->horiz_timing); + + back = fdtdec_get_int(blob, panel_node, "upper-margin", -1); + front = fdtdec_get_int(blob, panel_node, "lower-margin", -1); + ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1); + if ((back | front | ref) == -1) { + debug("%s: Vertical parameters missing\n", __func__); + return -EINVAL; + } + + priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; + priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; + priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; + priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - + priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; + debug_timing("vert", priv->vert_timing); + + bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1); + bit = ffs(bpp) - 1; + if (bpp == (1 << bit)) + priv->log2_bpp = bit; + else + priv->log2_bpp = bpp; + if (bpp == -1) { + debug("%s: Pixel bpp parameters missing\n", __func__); + return -EINVAL; + } + + if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm", + "#pwm-cells", 0, 0, &args)) { + debug("%s: Unable to decode PWM\n", __func__); + return -EINVAL; + } + + ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm); + if (ret) { + debug("%s: Unable to find PWM\n", __func__); + return -EINVAL; + } + priv->pwm_channel = args.args[0]; + + priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type", + FDT_LCD_CACHE_WRITE_BACK_FLUSH); + + /* These GPIOs are all optional */ + gpio_request_by_name_nodev(blob, panel_node, + "nvidia,backlight-enable-gpios", 0, + &priv->backlight_en, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, panel_node, + "nvidia,lvds-shutdown-gpios", 0, + &priv->lvds_shutdown, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, panel_node, + "nvidia,backlight-vdd-gpios", 0, + &priv->backlight_vdd, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, panel_node, + "nvidia,panel-vdd-gpios", 0, + &priv->panel_vdd, GPIOD_IS_OUT); + + if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings", + priv->panel_timings, FDT_LCD_TIMINGS)) + return -EINVAL; + + return 0; +} + +static int tegra_lcd_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + return 0; +} + +static const struct video_ops tegra_lcd_ops = { +}; + +static const struct udevice_id tegra_lcd_ids[] = { + { .compatible = "nvidia,tegra20-dc" }, + { } +}; + +U_BOOT_DRIVER(tegra_lcd) = { + .name = "tegra_lcd", + .id = UCLASS_VIDEO, + .of_match = tegra_lcd_ids, + .ops = &tegra_lcd_ops, + .bind = tegra_lcd_bind, + .probe = tegra_lcd_probe, + .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv), +}; diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile index 52eedb0f08..4287b9a25f 100644 --- a/drivers/video/tegra124/Makefile +++ b/drivers/video/tegra124/Makefile @@ -7,4 +7,3 @@ obj-y += display.o obj-y += dp.o obj-y += sor.o -obj-y += tegra124-lcd.o diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index 610ffa9684..2f1f0df20e 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -14,11 +14,13 @@ #include <edid.h> #include <fdtdec.h> #include <lcd.h> +#include <video.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/pwm.h> #include <asm/arch-tegra/dc.h> +#include <dm/uclass-internal.h> #include "displayport.h" DECLARE_GLOBAL_DATA_PTR; @@ -333,73 +335,46 @@ static int display_update_config_from_edid(struct udevice *dp_dev, return 0; } -/* Somewhat torturous method */ -static int get_backlight_info(const void *blob, struct gpio_desc *vdd, - struct gpio_desc *enable, int *pwmp) -{ - int sor, panel, backlight, power; - const u32 *prop; - int len; - int ret; - - *pwmp = 0; - sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); - if (sor < 0) - return -ENOENT; - panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel"); - if (panel < 0) - return -ENOENT; - backlight = fdtdec_lookup_phandle(blob, panel, "backlight"); - if (backlight < 0) - return -ENOENT; - ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0, - enable, GPIOD_IS_OUT); - if (ret) - return ret; - prop = fdt_getprop(blob, backlight, "pwms", &len); - if (!prop || len != 3 * sizeof(u32)) - return -EINVAL; - *pwmp = fdt32_to_cpu(prop[1]); - - power = fdtdec_lookup_phandle(blob, backlight, "power-supply"); - if (power < 0) - return -ENOENT; - ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd, - GPIOD_IS_OUT); - if (ret) - goto err; - - return 0; - -err: - dm_gpio_free(NULL, enable); - return ret; -} - -int display_init(void *lcdbase, int fb_bits_per_pixel, - struct display_timing *timing) +static int display_init(struct udevice *dev, void *lcdbase, + int fb_bits_per_pixel, struct display_timing *timing) { + struct display_plat *disp_uc_plat; struct dc_ctlr *dc_ctlr; const void *blob = gd->fdt_blob; struct udevice *dp_dev; const int href_to_sync = 1, vref_to_sync = 1; int panel_bpp = 18; /* default 18 bits per pixel */ u32 plld_rate; - struct gpio_desc vdd_gpio, enable_gpio; - int pwm; - int node; int ret; + /* + * Before we probe the display device (eDP), tell it that this device + * is are the source of the display data. + */ + ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev); + if (ret) { + debug("%s: device '%s' display not found (ret=%d)\n", __func__, + dev->name, ret); + return ret; + } + + disp_uc_plat = dev_get_uclass_platdata(dp_dev); + debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name, + disp_uc_plat); + disp_uc_plat->src_dev = dev; + ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); - if (ret) + if (ret) { + debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret); return ret; + } - node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); - if (node < 0) - return -ENOENT; - dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); - if (fdtdec_decode_display_timing(blob, node, 0, timing)) + dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev->of_offset, + "reg"); + if (fdtdec_decode_display_timing(blob, dev->of_offset, 0, timing)) { + debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; + } ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); if (ret) { @@ -407,12 +382,6 @@ int display_init(void *lcdbase, int fb_bits_per_pixel, dump_config(panel_bpp, timing); } - if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { - dm_gpio_set_value(&vdd_gpio, 1); - debug("%s: backlight vdd setting gpio %08x to %d\n", - __func__, gpio_get_number(&vdd_gpio), 1); - } - /* * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the @@ -443,22 +412,99 @@ int display_init(void *lcdbase, int fb_bits_per_pixel, /* Enable dp */ ret = display_enable(dp_dev, panel_bpp, timing); - if (ret) + if (ret) { + debug("dc: failed to enable display: ret=%d\n", ret); return ret; + } ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); + if (ret) { + debug("dc: failed to update window\n"); + return ret; + } + + return 0; +} + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1200, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +static int tegra124_lcd_init(struct udevice *dev, void *lcdbase, + enum video_log2_bpp l2bpp) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct display_timing timing; + int ret; + + clock_set_up_plldp(); + clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000); + + clock_enable(PERIPH_ID_HOST1X); + clock_enable(PERIPH_ID_DISP1); + clock_enable(PERIPH_ID_PWM); + clock_enable(PERIPH_ID_DPAUX); + clock_enable(PERIPH_ID_SOR0); + udelay(2); + + reset_set_enable(PERIPH_ID_HOST1X, 0); + reset_set_enable(PERIPH_ID_DISP1, 0); + reset_set_enable(PERIPH_ID_PWM, 0); + reset_set_enable(PERIPH_ID_DPAUX, 0); + reset_set_enable(PERIPH_ID_SOR0, 0); + + ret = display_init(dev, lcdbase, 1 << l2bpp, &timing); if (ret) return ret; - /* Set up Tegra PWM to drive the panel backlight */ - pwm_enable(pwm, 0, 220, 0x2e); - udelay(10 * 1000); + uc_priv->xsize = roundup(timing.hactive.typ, 16); + uc_priv->ysize = timing.vactive.typ; + uc_priv->bpix = l2bpp; - if (dm_gpio_is_valid(&enable_gpio)) { - dm_gpio_set_value(&enable_gpio, 1); - debug("%s: backlight enable setting gpio %08x to %d\n", - __func__, gpio_get_number(&enable_gpio), 1); - } + video_set_flush_dcache(dev, 1); + debug("%s: done\n", __func__); return 0; } + +static int tegra124_lcd_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + ulong start; + int ret; + + start = get_timer(0); + ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16); + debug("LCD init took %lu ms\n", get_timer(start)); + if (ret) + printf("%s: Error %d\n", __func__, ret); + + return 0; +} + +static int tegra124_lcd_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << VIDEO_BPP16) / 8; + debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + +static const struct udevice_id tegra124_lcd_ids[] = { + { .compatible = "nvidia,tegra124-dc" }, + { } +}; + +U_BOOT_DRIVER(tegra124_dc) = { + .name = "tegra124-dc", + .id = UCLASS_VIDEO, + .of_match = tegra124_lcd_ids, + .bind = tegra124_lcd_bind, + .probe = tegra124_lcd_probe, +}; diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c index bb1805a248..5bf8524a5e 100644 --- a/drivers/video/tegra124/dp.c +++ b/drivers/video/tegra124/dp.c @@ -11,6 +11,7 @@ #include <div64.h> #include <errno.h> #include <fdtdec.h> +#include <video_bridge.h> #include <asm/io.h> #include <asm/arch-tegra/dc.h> #include "display.h" @@ -26,9 +27,15 @@ struct tegra_dp_plat { ulong base; }; +/** + * struct tegra_dp_priv - private displayport driver info + * + * @dc_dev: Display controller device that is sending the video feed + */ struct tegra_dp_priv { + struct udevice *sor; + struct udevice *dc_dev; struct dpaux_ctlr *regs; - struct tegra_dc_sor_data *sor; u8 revision; int enabled; }; @@ -710,8 +717,8 @@ static int tegra_dc_dp_init_max_link_cfg( return 0; } -static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp, - struct tegra_dc_sor_data *sor, int ena) +static int tegra_dc_dp_set_assr(struct tegra_dp_priv *priv, + struct udevice *sor, int ena) { int ret; @@ -719,7 +726,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp, DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE : DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE; - ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET, + ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET, dpcd_data); if (ret) return ret; @@ -730,7 +737,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp, } static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, - struct tegra_dc_sor_data *sor, + struct udevice *sor, u8 link_bw) { tegra_dc_sor_set_link_bandwidth(sor, link_bw); @@ -741,7 +748,7 @@ static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp, const struct tegra_dp_link_config *link_cfg, - struct tegra_dc_sor_data *sor) + struct udevice *sor) { u8 dpcd_data; int ret; @@ -1002,7 +1009,7 @@ fail: static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], u32 pc[4], const struct tegra_dp_link_config *cfg) { - struct tegra_dc_sor_data *sor = dp->sor; + struct udevice *sor = dp->sor; u32 n_lanes = cfg->lane_count; u8 pc_supported = cfg->tps3_supported; u32 cnt; @@ -1186,7 +1193,7 @@ static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp, const struct display_timing *timing, struct tegra_dp_link_config *cfg) { - struct tegra_dc_sor_data *sor = dp->sor; + struct udevice *sor = dp->sor; int err; u32 pe[4], vs[4], pc[4]; @@ -1229,7 +1236,7 @@ fail: */ static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, const struct tegra_dp_link_config *link_cfg, - struct tegra_dc_sor_data *sor) + struct udevice *sor) { u8 link_bw; u8 lane_count; @@ -1301,7 +1308,7 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, static int tegra_dp_do_link_training(struct tegra_dp_priv *dp, struct tegra_dp_link_config *link_cfg, const struct display_timing *timing, - struct tegra_dc_sor_data *sor) + struct udevice *sor) { u8 link_bw; u8 lane_count; @@ -1344,7 +1351,7 @@ static int tegra_dp_do_link_training(struct tegra_dp_priv *dp, static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp, struct tegra_dp_link_config *link_cfg, - struct tegra_dc_sor_data *sor, + struct udevice *sor, const struct display_timing *timing) { struct tegra_dp_link_config temp_cfg; @@ -1444,7 +1451,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp, printf("DP: Out of sync after %d retries\n", max_retry); return -EIO; } - ret = tegra_dc_sor_detach(dp->sor); + ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor); if (ret) return ret; if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor, @@ -1454,7 +1461,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp, } tegra_dc_sor_set_power_state(dp->sor, 1); - tegra_dc_sor_attach(dp->sor, link_cfg, timing); + tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing); /* Increase delay_frame for next try in case the sink is skipping more frames */ @@ -1467,7 +1474,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp, { struct tegra_dp_priv *priv = dev_get_priv(dev); struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg; - struct tegra_dc_sor_data *sor; + struct udevice *sor; int data; int retry; int ret; @@ -1489,9 +1496,11 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp, return -ENOLINK; } - ret = tegra_dc_sor_init(&sor); - if (ret) + ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor); + if (ret || !sor) { + debug("dp: failed to find SOR device: ret=%d\n", ret); return ret; + } priv->sor = sor; ret = tegra_dc_sor_enable_dp(sor, link_cfg); if (ret) @@ -1531,7 +1540,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp, } tegra_dc_sor_set_power_state(sor, 1); - ret = tegra_dc_sor_attach(sor, link_cfg, timing); + ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing); if (ret && ret != -EEXIST) return ret; @@ -1548,6 +1557,12 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp, /* Power down the unused lanes to save power - a few hundred mW */ tegra_dc_sor_power_down_unused_lanes(sor, link_cfg); + ret = video_bridge_set_backlight(sor, 80); + if (ret) { + debug("dp: failed to set backlight\n"); + return ret; + } + priv->enabled = true; error_enable: return 0; @@ -1583,10 +1598,14 @@ static int dp_tegra_probe(struct udevice *dev) { struct tegra_dp_plat *plat = dev_get_platdata(dev); struct tegra_dp_priv *priv = dev_get_priv(dev); + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); priv->regs = (struct dpaux_ctlr *)plat->base; priv->enabled = false; + /* Remember the display controller that is sending us video */ + priv->dc_dev = disp_uc_plat->src_dev; + return 0; } diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index aa3d80c4c0..e5cea51d48 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -5,9 +5,12 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <panel.h> +#include <video_bridge.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/dc.h> @@ -37,6 +40,14 @@ DECLARE_GLOBAL_DATA_PTR; #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25) #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25) +struct tegra_dc_sor_data { + void *base; + void *pmc_base; + u8 portnum; /* 0 or 1 */ + int power_is_up; + struct udevice *panel; +}; + static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) { return readl((u32 *)sor->base + reg); @@ -57,15 +68,19 @@ static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, reg, reg_val); } -void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor) +void tegra_dp_disable_tx_pu(struct udevice *dev) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE); } -void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg, +void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); + tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); if (pc_supported) { @@ -95,8 +110,9 @@ static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, return -ETIMEDOUT; } -int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) +int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; u32 orig_val; @@ -123,10 +139,11 @@ int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) return 0; } -void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, +void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena, u8 training_pattern, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); @@ -194,9 +211,10 @@ static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, return 0; } -static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, +static int tegra_dc_sor_power_dplanes(struct udevice *dev, u32 lane_count, int pu) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); @@ -218,15 +236,15 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, } tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); - tegra_dc_sor_set_lane_count(sor, lane_count); + tegra_dc_sor_set_lane_count(dev, lane_count); } return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); } -void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, - int power_up) +void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); @@ -255,14 +273,15 @@ static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, } } -static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, +static void tegra_dc_sor_set_dp_mode(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; - tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); + tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); - tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg); + tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg); reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); reg_val &= ~DP_CONFIG_WATERMARK_MASK; reg_val |= link_cfg->watermark; @@ -351,8 +370,9 @@ static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) return 0; } -void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int) +void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); @@ -366,9 +386,10 @@ void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int) tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); } -void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, +void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw, u8 *lane_count) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, CLK_CNTRL); @@ -395,15 +416,18 @@ void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, } } -void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw) +void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); + tegra_sor_write_field(sor, CLK_CNTRL, CLK_CNTRL_DP_LINK_SPEED_MASK, link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT); } -void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count) +void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); @@ -439,15 +463,16 @@ void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count) * 4 1 0 0 0 0 0 1 * 5 0 0 0 0 0 0 1 */ -static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds) +static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); int ret; if (sor->power_is_up) return 0; /* Set link bw */ - tegra_dc_sor_set_link_bandwidth(sor, is_lvds ? + tegra_dc_sor_set_link_bandwidth(dev, is_lvds ? CLK_CNTRL_DP_LINK_SPEED_LVDS : CLK_CNTRL_DP_LINK_SPEED_G1_62); @@ -655,9 +680,10 @@ static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl) writel(reg_val, &disp_ctrl->cmd.state_access); } -int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_enable_dp(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); int ret; tegra_sor_write_field(sor, CLK_CNTRL, @@ -701,7 +727,7 @@ int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, PLL2_AUX2_OVERRIDE_POWERDOWN | PLL2_AUX7_PORT_POWERDOWN_DISABLE); - ret = tegra_dc_sor_power_up(sor, 0); + ret = tegra_dc_sor_power_up(dev, 0); if (ret) { debug("DP failed to power up\n"); return ret; @@ -711,18 +737,19 @@ int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, clock_sor_enable_edp_clock(); /* Power up lanes */ - tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); + tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1); - tegra_dc_sor_set_dp_mode(sor, link_cfg); + tegra_dc_sor_set_dp_mode(dev, link_cfg); debug("%s ret\n", __func__); return 0; } -int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); const void *blob = gd->fdt_blob; struct dc_ctlr *disp_ctrl; u32 reg_val; @@ -730,9 +757,7 @@ int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, /* Use the first display controller */ debug("%s\n", __func__); - node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); - if (node < 0) - return -ENOENT; + node = dc_dev->of_offset; disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); tegra_dc_sor_enable_dc(disp_ctrl); @@ -798,9 +823,11 @@ int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, return 0; } -void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, +void tegra_dc_sor_set_lane_parm(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); + tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), link_cfg->drive_current); tegra_sor_writel(sor, PR(sor->portnum), @@ -809,8 +836,8 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, link_cfg->postcursor); tegra_sor_writel(sor, LVDS, 0); - tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); - tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); + tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); + tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count); tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), DP_PADCTL_TX_PU_ENABLE | @@ -825,9 +852,10 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); } -int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_set_voltage_swing(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 drive_current = 0; u32 pre_emphasis = 0; @@ -851,9 +879,10 @@ int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, return 0; } -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, +void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 pad_ctrl = 0; int err = 0; @@ -891,9 +920,10 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, } } -int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, +int tegra_sor_precharge_lanes(struct udevice *dev, const struct tegra_dp_link_config *cfg) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 val = 0; switch (cfg->lane_count) { @@ -931,8 +961,9 @@ static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable) writel(reg_val, &disp_ctrl->disp.disp_win_opt); } -int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor) +int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev) { + struct tegra_dc_sor_data *sor = dev_get_priv(dev); int dc_reg_ctx[DC_REG_SAVE_SPACE]; const void *blob = gd->fdt_blob; struct dc_ctlr *disp_ctrl; @@ -942,11 +973,7 @@ int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor) debug("%s\n", __func__); /* Use the first display controller */ - node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); - if (node < 0) { - ret = -ENOENT; - goto err; - } + node = dc_dev->of_offset; disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); /* Sleep mode */ @@ -997,28 +1024,61 @@ err: return ret; } -int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp) +static int tegra_sor_set_backlight(struct udevice *dev, int percent) { + struct tegra_dc_sor_data *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + debug("sor: Cannot enable panel backlight\n"); + return ret; + } + + return 0; +} + +static int tegra_sor_ofdata_to_platdata(struct udevice *dev) +{ + struct tegra_dc_sor_data *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; - struct tegra_dc_sor_data *sor; int node; + int ret; - node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); - if (node < 0) - return -ENOENT; - sor = calloc(1, sizeof(*sor)); - if (!sor) - return -ENOMEM; - sor->base = (void *)fdtdec_get_addr(blob, node, "reg"); + priv->base = (void *)fdtdec_get_addr(blob, dev->of_offset, "reg"); node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC); - if (node < 0) + if (node < 0) { + debug("%s: Cannot find PMC\n", __func__); return -ENOENT; - sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg"); + } + priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg"); - sor->power_is_up = 0; - sor->portnum = 0; - *sorp = sor; + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel", + &priv->panel); + if (ret) { + debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, + dev->name, ret); + return ret; + } return 0; } + +static const struct video_bridge_ops tegra_sor_ops = { + .set_backlight = tegra_sor_set_backlight, +}; + +static const struct udevice_id tegra_sor_ids[] = { + { .compatible = "nvidia,tegra124-sor" }, + { } +}; + +U_BOOT_DRIVER(sor_tegra) = { + .name = "sor_tegra", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = tegra_sor_ids, + .ofdata_to_platdata = tegra_sor_ofdata_to_platdata, + .ops = &tegra_sor_ops, + .priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data), +}; diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra124/sor.h index dc8fd03d80..e854bef17d 100644 --- a/drivers/video/tegra124/sor.h +++ b/drivers/video/tegra124/sor.h @@ -873,44 +873,37 @@ struct tegra_dp_link_config { u8 tps3_supported; }; -struct tegra_dc_sor_data { - void *base; - void *pmc_base; - u8 portnum; /* 0 or 1 */ - int power_is_up; -}; - #define TEGRA_SOR_TIMEOUT_MS 1000 #define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000 -int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_enable_dp(struct udevice *sor, const struct tegra_dp_link_config *link_cfg); -int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd); -void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, +int tegra_dc_sor_set_power_state(struct udevice *sor, int pu_pd); +void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena, u8 training_pattern, const struct tegra_dp_link_config *link_cfg); -void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw); -void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count); -void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, +void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw); +void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count); +void tegra_dc_sor_set_panel_power(struct udevice *sor, int power_up); -void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int); -void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, +void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int); +void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw, u8 *lane_count); -void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, - const struct tegra_dp_link_config *link_cfg); -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, +void tegra_dc_sor_set_lane_parm(struct udevice *dev, + const struct tegra_dp_link_config *link_cfg); +void tegra_dc_sor_power_down_unused_lanes(struct udevice *sor, const struct tegra_dp_link_config *link_cfg); -int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_set_voltage_swing(struct udevice *sor, const struct tegra_dp_link_config *link_cfg); -int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, +int tegra_sor_precharge_lanes(struct udevice *dev, const struct tegra_dp_link_config *cfg); -void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); -void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, - u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); +void tegra_dp_disable_tx_pu(struct udevice *sor); +void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg, + u32 vs_reg, u32 pc_reg, u8 pc_supported); -int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, +int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *sor, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing); -int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor); +int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *sor); void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, int *dc_reg_ctx); @@ -918,5 +911,5 @@ int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl); void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, int *dc_reg_ctx); -int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp); +int tegra_dc_sor_init(struct udevice **sorp); #endif diff --git a/drivers/video/tegra124/tegra124-lcd.c b/drivers/video/tegra124/tegra124-lcd.c deleted file mode 100644 index cfdc77ffe3..0000000000 --- a/drivers/video/tegra124/tegra124-lcd.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#include <common.h> -#include <errno.h> -#include <fdtdec.h> -#include <lcd.h> -#include <asm/gpio.h> -#include <asm/arch-tegra/clk_rst.h> -#include <asm/arch/clock.h> -#include <asm/arch-tegra/dc.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -enum { - /* Maximum LCD size we support */ - LCD_MAX_WIDTH = 1920, - LCD_MAX_HEIGHT = 1200, - LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ -}; - -vidinfo_t panel_info = { - /* Insert a value here so that we don't end up in the BSS */ - .vl_col = -1, -}; - -int tegra_lcd_check_next_stage(const void *blob, int wait) -{ - return 0; -} - -void tegra_lcd_early_init(const void *blob) -{ - /* - * Go with the maximum size for now. We will fix this up after - * relocation. These values are only used for memory alocation. - */ - panel_info.vl_col = LCD_MAX_WIDTH; - panel_info.vl_row = LCD_MAX_HEIGHT; - panel_info.vl_bpix = LCD_MAX_LOG2_BPP; -} - -static int tegra124_lcd_init(void *lcdbase) -{ - struct display_timing timing; - int ret; - - clock_set_up_plldp(); - clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000); - - clock_enable(PERIPH_ID_HOST1X); - clock_enable(PERIPH_ID_DISP1); - clock_enable(PERIPH_ID_PWM); - clock_enable(PERIPH_ID_DPAUX); - clock_enable(PERIPH_ID_SOR0); - udelay(2); - - reset_set_enable(PERIPH_ID_HOST1X, 0); - reset_set_enable(PERIPH_ID_DISP1, 0); - reset_set_enable(PERIPH_ID_PWM, 0); - reset_set_enable(PERIPH_ID_DPAUX, 0); - reset_set_enable(PERIPH_ID_SOR0, 0); - - ret = display_init(lcdbase, 1 << LCD_BPP, &timing); - if (ret) - return ret; - - panel_info.vl_col = roundup(timing.hactive.typ, 16); - panel_info.vl_row = timing.vactive.typ; - - lcd_set_flush_dcache(1); - - return 0; -} - -void lcd_ctrl_init(void *lcdbase) -{ - ulong start; - int ret; - - start = get_timer(0); - ret = tegra124_lcd_init(lcdbase); - debug("LCD init took %lu ms\n", get_timer(start)); - if (ret) - printf("%s: Error %d\n", __func__, ret); -} - -void lcd_enable(void) -{ -} diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index f6326b6e07..832e90aea2 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -170,6 +170,7 @@ static void vidconsole_puts(struct stdio_dev *sdev, const char *s) while (*s) vidconsole_put_char(dev, *s++); + video_sync(dev->parent); } /* Set up the number of rows and colours (rotated drivers override this) */ diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index c9075d62dd..fb7943e06d 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -194,7 +194,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, { struct video_priv *priv = dev_get_uclass_priv(dev); ushort *cmap_base = NULL; - ushort i, j; + int i, j; uchar *fb; struct bmp_image *bmp = map_sysmem(bmp_image, 0); uchar *bmap; diff --git a/examples/api/Makefile b/examples/api/Makefile index 6cf23d10ac..4e9b8ea17d 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -10,6 +10,9 @@ endif ifeq ($(ARCH),arm) LOAD_ADDR = 0x1000000 endif +ifeq ($(ARCH),mips) +LOAD_ADDR = 0x80200000 +endif # Resulting ELF and binary exectuables will be named demo and demo.bin extra-y = demo diff --git a/examples/api/crt0.S b/examples/api/crt0.S index 78d35a2893..ced2c82e5f 100644 --- a/examples/api/crt0.S +++ b/examples/api/crt0.S @@ -40,6 +40,30 @@ syscall: ldr ip, =syscall_ptr ldr pc, [ip] +#elif defined(CONFIG_MIPS) + .text + .globl __start + .ent __start +__start: + sw $sp, search_hint + b main + .end __start + + .globl syscall + .ent syscall +syscall: + sw $ra, return_addr + lw $t9, syscall_ptr + jalr $t9 + nop + lw $ra, return_addr + jr $ra + nop + .end syscall + +return_addr: + .align 4 + .long 0 #else #error No support for this arch! #endif diff --git a/examples/standalone/README.smc91111_eeprom b/examples/standalone/README.smc91111_eeprom index f73a8d3a58..0d8bc63f32 100644 --- a/examples/standalone/README.smc91111_eeprom +++ b/examples/standalone/README.smc91111_eeprom @@ -7,14 +7,14 @@ EEPROMs. Contents: ------------------------ -1. Ensuring U-boot's MAC address can be set in hardware +1. Ensuring U-Boot's MAC address can be set in hardware 2. Running the smc91111_eeprom program 3. Setting MAC addresses 4. Other things you can do with this 5. Things to be done. -1. Ensuring U-boot's MAC address can be set in hardware +1. Ensuring U-Boot's MAC address can be set in hardware -------------------------------------------------------------------------- On the Internet - MAC addresses are very important. Short for Media @@ -130,14 +130,14 @@ SMC91111> The MAC address can be stored in four locations: -Boot environmental variable in Flash <- can not change, without - re-flashing U-boot. + re-flashing U-Boot. U-Boot environmental variable <- can not change, without resetting board/U-Boot LAN91C111 Registers <- volatile LAN91C111 EEPROM <- Non-volatile If you have not activated the network, and do not have a hardcoded -or pre-assigned MAC address in U-boot, the environmental variables +or pre-assigned MAC address in U-Boot, the environmental variables should be blank, and allow you to set things one time. To set the EEPROM MAC address to 12:34:56:78:9A:BC diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c index afecbb1277..38fadede1e 100644 --- a/examples/standalone/smc91111_eeprom.c +++ b/examples/standalone/smc91111_eeprom.c @@ -6,7 +6,7 @@ * * Heavily borrowed from the following peoples GPL'ed software: * - Wolfgang Denk, DENX Software Engineering, wd@denx.de - * Das U-boot + * Das U-Boot * - Ladislav Michl ladis@linux-mips.org * A rejected patch on the U-Boot mailing list */ diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c index 364ad2d2d5..2c05ed902d 100644 --- a/examples/standalone/smc911x_eeprom.c +++ b/examples/standalone/smc911x_eeprom.c @@ -9,7 +9,7 @@ * Based on smc91111_eeprom.c which: * Heavily borrowed from the following peoples GPL'ed software: * - Wolfgang Denk, DENX Software Engineering, wd@denx.de - * Das U-boot + * Das U-Boot * - Ladislav Michl ladis@linux-mips.org * A rejected patch on the U-Boot mailing list */ diff --git a/include/asm-generic/errno.h b/include/asm-generic/errno.h index 523defbab9..464cfb715c 100644 --- a/include/asm-generic/errno.h +++ b/include/asm-generic/errno.h @@ -1,5 +1,5 @@ /* - * U-boot - errno.h Error number defines + * U-Boot - errno.h Error number defines * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index a587d3c203..f2810a1bd7 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -48,10 +48,6 @@ typedef struct global_data { #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ #endif -#ifdef CONFIG_MODEM_SUPPORT - unsigned long do_mdm_init; - unsigned long be_quiet; -#endif unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 424721b7e7..e858e55837 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -34,7 +34,6 @@ #define CONFIG_CMD_FUSE /* Device fuse support */ #define CONFIG_CMD_GETTIME /* Get time since boot */ #define CONFIG_CMD_HASH /* calculate hash / digest */ -#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_IDE /* IDE harddisk support */ #define CONFIG_CMD_IMMAP /* IMMR dump support */ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 9d1de5508f..0f85cd0e14 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -24,15 +24,15 @@ #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) #if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7" #endif #elif defined(__aarch64__) #if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8" #endif #else #if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-boot.arm" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.arm" #endif #endif #elif defined(__i386__) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 342fdfe24a..535dc6eceb 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -334,7 +334,7 @@ * * Please notice, that the resulting clock frequency could differ from the * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot + * clock over a frequency divider with only a few divider values. U-Boot * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated * approximation allways lies below the configured value, never above. */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 42af34fdc6..de7d5c2243 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -20,6 +20,8 @@ * High Level Configuration Options * (easy to change) */ +#define CONFIG_SYS_THUMB_BUILD + #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 2499b39c16..f6c0147dd9 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -271,7 +271,7 @@ /* * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. + * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. */ #define CONFIG_SYS_LOAD_ADDR 0x300000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 4547d7f4aa..4d662ad3c2 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -132,6 +132,10 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ @@ -184,19 +188,34 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdtfile=am3517-evm.dtb\0" \ + "fdtaddr=0x82C00000\0" \ + "vram=16M\0" \ + "bootenv=uEnv.txt\0" \ + "cmdline=\0" \ + "optargs=\0" \ "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw rootwait\0" \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${cmdline}\0" \ "nandargs=setenv bootargs console=${console} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ @@ -204,13 +223,20 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ + "echo SD/MMC found on device $mmcdev; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "echo Running default loadimage ...; " \ + "setenv bootfile zImage; " \ + "if run loadimage; then " \ + "run loadfdt; " \ + "run mmcboot; " \ "fi; " \ "else run nandboot; fi" diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index c3867efe9a..1428aa97b6 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -227,7 +227,7 @@ #define CONFIG_TI_SPI_MMAP #define CONFIG_QSPI_SEL_GPIO 48 #define CONFIG_SF_DEFAULT_SPEED 48000000 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #define CONFIG_QSPI_QUAD_SUPPORT #define CONFIG_TI_EDMA3 diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index e1eb700404..32e9ba38d9 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -43,7 +43,6 @@ /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index 36637aef95..658b16d3ae 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF536 brettl2 board + * U-Boot - Configuration file for BF536 brettl2 board */ #ifndef __CONFIG_BCT_BRETTL2_H__ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 89c7446d26..c672a8e40c 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -51,7 +51,6 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h index 597f1cd5d1..68a91a6b5a 100644 --- a/include/configs/bf506f-ezkit.h +++ b/include/configs/bf506f-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF506F EZ-Kit board + * U-Boot - Configuration file for BF506F EZ-Kit board */ #ifndef __CONFIG_BF506F_EZKIT_H__ diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 84bb044421..9f44ebdb0b 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF518F EZBrd board + * U-Boot - Configuration file for BF518F EZBrd board */ #ifndef __CONFIG_BF518F_EZBRD_H__ diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index d12963a5f0..5a6067e5e2 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for bf525-ucr2 board + * U-Boot - Configuration file for bf525-ucr2 board * The board includes ADSP-BF525 rev. 0.2, * 32-bit SDRAM (SAMSUNG K4S561632H-UC75), * USB 2.0 High Speed OTG USB WIFI, diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 35a2228a6b..e9d900ef01 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF526 EZBrd board + * U-Boot - Configuration file for BF526 EZBrd board */ #ifndef __CONFIG_BF526_EZBRD_H__ diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index 2f3dec5b09..dd62e7e0fe 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF527 AD7160-EVAL board + * U-Boot - Configuration file for BF527 AD7160-EVAL board */ #ifndef __CONFIG_BF527_AD7160_EVAL_H__ diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index aee776132c..44de44f8f5 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF537 STAMP board + * U-Boot - Configuration file for BF537 STAMP board */ #ifndef __CONFIG_BF527_EZKIT_H__ diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h index 51814a677f..6b51201629 100644 --- a/include/configs/bf527-sdp.h +++ b/include/configs/bf527-sdp.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF527 SDP board + * U-Boot - Configuration file for BF527 SDP board */ #ifndef __CONFIG_BF527_SDP_H__ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 1b7290e8d7..95811018cf 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF533 EZKIT board + * U-Boot - Configuration file for BF533 EZKIT board */ #ifndef __CONFIG_BF533_EZKIT_H__ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 4876169104..c8c48aeac4 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF533 STAMP board + * U-Boot - Configuration file for BF533 STAMP board */ #ifndef __CONFIG_BF533_STAMP_H__ diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 4fbdca7239..be474ad1ba 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CSP Minotaur board + * U-Boot - Configuration file for CSP Minotaur board * * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> * Minotaur config, brushed up for official uClinux dist. diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 2474adb555..5794f471eb 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF537 PNAV board + * U-Boot - Configuration file for BF537 PNAV board */ #ifndef __CONFIG_BF537_PNAV_H__ diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 89d26043da..6d4a93b324 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CSP Minotaur board + * U-Boot - Configuration file for CSP Minotaur board * * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> * Minotaur config, brushed up for official uClinux dist. diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index f250cdbf0a..b1787132ab 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF537 STAMP board + * U-Boot - Configuration file for BF537 STAMP board */ #ifndef __CONFIG_BF537_STAMP_H__ diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index b1d4f263ae..55becdc5a1 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF538F EZ-Kit Lite board + * U-Boot - Configuration file for BF538F EZ-Kit Lite board */ #ifndef __CONFIG_BF538F_EZKIT_H__ diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 65009c6f28..8198cb862a 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF548 STAMP board + * U-Boot - Configuration file for BF548 STAMP board */ #ifndef __CONFIG_BF548_EZKIT_H__ diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 92251fc0bd..31862daf31 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF561 Acvilon System On Module + * U-Boot - Configuration file for BF561 Acvilon System On Module * For more information please go to http://www.niistt.ru/ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index efbc6c21d9..1a3b33f395 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF561 EZKIT board + * U-Boot - Configuration file for BF561 EZKIT board */ #ifndef __CONFIG_BF561_EZKIT_H__ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index b5d4847523..3e0bff56dd 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BF609 EZ-Kit board + * U-Boot - Configuration file for BF609 EZ-Kit board */ #ifndef __CONFIG_BF609_EZKIT_H__ diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 60650aa77b..b9e859c07b 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BlackStamp board + * U-Boot - Configuration file for BlackStamp board * Configuration by Ben Matthews for UR LLE using bf533-stamp.h * as a template * See http://blackfin.uclinux.org/gf/project/blackstamp/ diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 16949aa929..a262e7914f 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -1,4 +1,4 @@ -/* U-boot for BlackVME. (C) Wojtek Skulski 2010. +/* U-Boot for BlackVME. (C) Wojtek Skulski 2010. * The board includes ADSP-BF561 rev. 0.5, * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), diff --git a/include/configs/br4.h b/include/configs/br4.h index 7dda472fe7..85f31a46a4 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for BR4 Appliance + * U-Boot - Configuration file for BR4 Appliance * * based on bf537-stamp.h * Copyright (c) Switchfin Org. <dpn@switchfin.org> diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h index 00fe26da29..d5b33902cc 100644 --- a/include/configs/chromebox_panther.h +++ b/include/configs/chromebox_panther.h @@ -11,7 +11,5 @@ #include <configs/x86-chromebook.h> #define CONFIG_RTL8169 -/* Avoid a warning in the Realtek Ethernet driver */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #endif /* __CONFIG_H */ diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index e9e4e1414a..761e2c5f43 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CM-BF527 board + * U-Boot - Configuration file for CM-BF527 board */ #ifndef __CONFIG_CM_BF527_H__ diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index a4647858dd..d06333dc41 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CM-BF533 board + * U-Boot - Configuration file for CM-BF533 board */ #ifndef __CONFIG_CM_BF533_H__ diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 0eebe56503..746a5bd417 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CM-BF537E board + * U-Boot - Configuration file for CM-BF537E board */ #ifndef __CONFIG_CM_BF537E_H__ diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 3a2d72626c..71008aaa06 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CM-BF537U board + * U-Boot - Configuration file for CM-BF537U board */ #ifndef __CONFIG_CM_BF537U_H__ diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index cde23ada40..37205a9c5b 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for cm-bf548 board + * U-Boot - Configuration file for cm-bf548 board */ #ifndef __CONFIG_CM_BF548_H__ diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 9d8a2c613f..284ec83391 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for CM-BF561 board + * U-Boot - Configuration file for CM-BF561 board */ #ifndef __CONFIG_CM_BF561_H__ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 8e70d8c94c..67a143f8f6 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -7,7 +7,7 @@ */ /* --- - * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board + * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board * Date: 2004-03-29 * Author: Florian Schlote * diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 7611fc5004..b7ad189af3 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -38,7 +38,6 @@ #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -53,10 +52,6 @@ #define CONFIG_TFTP_TSIZE /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 #define CONFIG_CMD_BMP diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index ef743b0d33..47914c7679 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -43,7 +43,6 @@ /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h new file mode 100644 index 0000000000..88845dc068 --- /dev/null +++ b/include/configs/cougarcanyon2.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (2 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SMSC_SIO1007 + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +/* Environment configuration */ +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x5ff000 + +/* Video is not supported for now */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index ffd65d5439..fc1a8baf89 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_ARCH_MISC_INIT #define CONFIG_SMSC_LPC47M diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index fdfda6b903..f74ced1b43 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -58,6 +58,7 @@ /* General networking support */ #define CONFIG_CMD_DHCP +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h index 3b2da0ddd4..c46e60d2e5 100644 --- a/include/configs/dnp5370.h +++ b/include/configs/dnp5370.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for SSV DNP5370 board + * U-Boot - Configuration file for SSV DNP5370 board */ #ifndef __CONFIG_DNP5370_H__ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 9d62421050..4658283014 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -138,8 +138,8 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP -#define CONFIG_SF_DEFAULT_SPEED 48000000 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_SF_DEFAULT_SPEED 64000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_QSPI_QUAD_SUPPORT #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 18a63d7ec7..33ebb7c7af 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -44,7 +44,6 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 9fce1cda6b..7bc58dc414 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for Cirrus Logic EDB93xx boards + * U-Boot - Configuration file for Cirrus Logic EDB93xx boards */ #ifndef __CONFIG_H diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 258a83f9de..6dd0b32dae 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -13,9 +13,6 @@ #undef CONFIG_TPM_TIS_BASE_ADDRESS -#undef CONFIG_CMD_IMLS - -#undef CONFIG_X86_SERIAL #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE #undef CONFIG_VIDEO @@ -23,6 +20,7 @@ #undef CONFIG_SCSI_AHCI #undef CONFIG_CMD_SCSI #undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_USB_EHCI_PCI #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ diff --git a/include/configs/espt.h b/include/configs/espt.h index d854341b07..4896498c46 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS (1) #define CONFIG_SYS_MAX_FLASH_SECT (150) -/* U-boot setting */ +/* U-Boot setting */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_MONITOR_LEN (128 * 1024) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 9c3ea883ff..834a22f7a5 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -113,7 +113,7 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -/* U-boot copy size from boot Media to DRAM.*/ +/* U-Boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) diff --git a/include/configs/harmony.h b/include/configs/harmony.h index e0bc7c0d73..f66ac7087e 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -42,7 +42,6 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_ULPI @@ -60,10 +59,6 @@ #define CONFIG_CMD_DHCP /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 4757929618..7cb23466fb 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for IBF-DSP561 board + * U-Boot - Configuration file for IBF-DSP561 board */ #ifndef __CONFIG_IBF_DSP561__H__ diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 0993ffa444..3638648713 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for IP04 board (having BF532 processor) + * U-Boot - Configuration file for IP04 board (having BF532 processor) * * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com * diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 23b2e43616..763d2ec71e 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -48,7 +48,6 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 4a7ba2477b..534ebb6735 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -11,12 +11,12 @@ #ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU" #endif #ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU" #endif #define CONFIG_SYS_CLK_FREQ 100000000 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 876ee30517..2c2ce7bfec 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -11,12 +11,12 @@ #ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-SIMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU" #endif #ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-SIMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-SIMU" #endif #define CONFIG_SYS_CLK_FREQ 100000000 diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h new file mode 100644 index 0000000000..f0d5e9d3c5 --- /dev/null +++ b/include/configs/ma5d4evk.h @@ -0,0 +1,255 @@ +/* + * DENX MA5D4 configuration + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MA5D4EVK_CONFIG_H__ +#define __MA5D4EVK_CONFIG_H__ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_FIT + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#include "at91-sama5_common.h" +#undef CONFIG_BOOTARGS +#define CONFIG_SYS_USE_SERIALFLASH 1 + +/* + * U-Boot Commands + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +/*#define CONFIG_LCD*/ + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_USB + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE 0x1000 + +/* + * U-Boot general configurations + */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ + +/* + * Serial Driver + */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART0 +#define CONFIG_USART_ID ATMEL_ID_USART0 + +/* + * Ethernet + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_IP_DEFRAG +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_ATMEL_HLCD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +/* + * SD/MMC + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* + * SPI NOR (boot memory) + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "DENX" +#endif + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200" +#define CONFIG_LOADADDR 0x20800000 +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT + +/* + * Extra Environments + */ +#define CONFIG_PREBOOT "run try_bootscript" +#define CONFIG_HOSTNAME ma5d4evk + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttyS3\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "bootdev=/dev/mmcblk1p1\0" \ + "bootpart=1:1\0" \ + "rootdev=/dev/mmcblk1p2\0" \ + "netdev=eth0\0" \ + "kernel_addr_r=0x22000000\0" \ + "update_spi_firmware_spl_addr=0x21000000\0" \ + "update_spi_firmware_spl_filename=boot.bin\0" \ + "update_spi_firmware_addr=0x22000000\0" \ + "update_spi_firmware_filename=u-boot.img\0" \ + "update_spi_firmware=" /* Update the SPI flash firmware */ \ + "if sf probe ; then " \ + "if tftp ${update_spi_firmware_spl_addr} " \ + "${update_spi_firmware_spl_filename} ; then " \ + "setenv update_spi_firmware_spl_filesize ${filesize} ; "\ + "if tftp ${update_spi_firmware_addr} " \ + "${update_spi_firmware_filename} ; then " \ + "setenv update_spi_firmware_filesize ${filesize} ; " \ + "sf update ${update_spi_firmware_spl_addr} 0x0 " \ + "${update_spi_firmware_spl_filesize} ; " \ + "sf update ${update_spi_firmware_addr} 0x10000 " \ + "${update_spi_firmware_filesize} ; " \ + "fi ; " \ + "fi ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc ${bootpart} ${bootscript} ; then " \ + "if load mmc ${bootpart} ${kernel_addr_r} ${bootscript};"\ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 + +#endif /* __MA5D4EVK_CONFIG_H__ */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 6dfd5e2c40..cd89fa537b 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -48,10 +48,6 @@ #define CONFIG_CMD_DHCP /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK /* support the new (FDT-based) image format */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 863b032042..3813e25d2f 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -165,7 +165,7 @@ /* NAND configuration for the NAND_SPL */ -/* Start copying real U-boot from the second page */ +/* Start copying real U-Boot from the second page */ #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 /* Load U-Boot to this address */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 63fdf9e4e7..4c490ae54e 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -121,12 +121,10 @@ * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. */ -#ifndef CONFIG_MXS_AUART #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 -#endif /* Default baudrate can be overriden by board! */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/novena.h b/include/configs/novena.h index d5f517c76d..a5416131ba 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -1,5 +1,5 @@ /* - * Configuration settings for the Novena U-boot. + * Configuration settings for the Novena U-Boot. * * Copyright (C) 2014 Marek Vasut <marex@denx.de> * diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 176f6e902b..d528fac8c8 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -38,10 +38,7 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA #define CONFIG_AS3722_POWER -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CMD_BMP @@ -58,7 +55,6 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 1dd71a8eb6..996f772a28 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -21,7 +21,7 @@ #include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- - * Supported U-boot commands + * Supported U-Boot commands * ---------------------------------------------------------------------------- */ #define CONFIG_CMD_ASKENV @@ -37,7 +37,7 @@ #define CONFIG_CMD_PING /* ---------------------------------------------------------------------------- - * Supported U-boot features + * Supported U-Boot features * ---------------------------------------------------------------------------- */ #define CONFIG_SYS_LONGHELP diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 2004d148c6..0f16a6e19d 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -175,7 +175,7 @@ #endif /* CONFIG_USB_OMAP3 */ /* ---------------------------------------------------------------------------- - * U-boot features + * U-Boot features * ---------------------------------------------------------------------------- */ #define CONFIG_SYS_MAXARGS 16 /* max args for a command */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 27cd9bed5c..23a8a07132 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -16,7 +16,7 @@ #include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- - * Supported U-boot commands + * Supported U-Boot commands * ---------------------------------------------------------------------------- */ #define CONFIG_CMD_MMC @@ -30,7 +30,7 @@ */ /* ---------------------------------------------------------------------------- - * Supported U-boot features + * Supported U-Boot features * ---------------------------------------------------------------------------- */ #define CONFIG_SILENT_CONSOLE diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 124e8c6641..bb908fad3e 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -16,7 +16,7 @@ #include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- - * Supported U-boot commands + * Supported U-Boot commands * ---------------------------------------------------------------------------- */ #define CONFIG_CMD_NAND @@ -29,7 +29,7 @@ */ /* ---------------------------------------------------------------------------- - * Supported U-boot features + * Supported U-Boot features * ---------------------------------------------------------------------------- */ #define CONFIG_SILENT_CONSOLE diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index e9ce3f6d1c..fba2a1256b 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -11,112 +11,138 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ +/* High Level Configuration Options */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define CONFIG_SYS_TEXT_BASE 0x80400000 -#include <configs/ti_omap3_common.h> -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ /* - * Display CPU and Board information + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#include <configs/ti_omap3_common.h> + +/* Override default SPL info to minimize empty space and allow BCH8 in SPL */ +#undef CONFIG_SPL_TEXT_BASE +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_TEXT_BASE 0x40200000 +#define CONFIG_SPL_MAX_SIZE (64 * 1024) + +/* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */ -#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */ - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -/* - * Hardware drivers - */ +/* Hardware drivers */ /* GPIO banks */ #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ -/* - * select serial console configuration - */ +#define CONFIG_USB_OMAP3 + +/* select serial console configuration */ #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - /* commands to include */ +#define CONFIG_CMD_NAND #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\ - "1920k(u-boot),128k(u-boot-env),"\ - "4m(kernel),-(fs)" - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -#define CONFIG_SYS_NO_FLASH - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +/* I2C */ #define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ - - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#define EXPANSION_EEPROM_I2C_BUS 2 /* I2C Bus for AT24C64 */ +#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID + +/* USB */ +#define CONFIG_USB_MUSB_GADGET +#define CONFIG_USB_MUSB_OMAP2PLUS +#define CONFIG_USB_MUSB_PIO_ONLY +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 0 +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xd022 +#define CONFIG_G_DNL_MANUFACTURER "TI" +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* TWL4030 */ +#define CONFIG_TWL4030_PWM +#define CONFIG_TWL4030_USB + +/* Board NAND Info. */ +#ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT - +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_BCH +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" +#endif /* Environment information */ @@ -142,15 +168,20 @@ "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \ "setenv display 15;" \ "setenv preboot;" \ + "nand unlock;" \ "saveenv;" - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ - "bootfile=uImage\0" \ + "uimage=uImage\0" \ + "zimage=zImage\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ + "nandrootfstype=ubifs rootwait\0" \ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ @@ -168,79 +199,81 @@ "setenv bootargs ${bootargs} omapfb.vrfb=y " \ "omapfb.rotate=${rotation}; " \ "fi\0" \ - "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \ + "optargs=ignore_loglevel early_printk no_console_suspend\0" \ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \ - "${otherbootargs};" \ + "${optargs};" \ "run addmtdparts; " \ "run vrfb_arg\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo 'Running bootscript from mmc ...'; " \ "source ${loadaddr}\0" \ - "loaduimage=mmc rescan ${mmcdev}; " \ - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \ + "loadzimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \ "ramdisksize=64000\0" \ "ramdiskaddr=0x82000000\0" \ "ramdiskimage=rootfs.ext2.gz.uboot\0" \ + "loadramdisk=mmc rescan; " \ + "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \ "ramargs=run setconsole; setenv bootargs console=${console} " \ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \ + "mmcargs=run setconsole; setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=run setconsole; setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "fdtaddr=0x86000000\0" \ + "loadfdtimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ + "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loadzimage; " \ + "run loadfdtimage; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \ "run ramargs; " \ "run common_bootargs; " \ "run dump_bootargs; " \ "run loaduimage; " \ - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\ + "run loadramdisk; " \ "bootm ${loadaddr} ${ramdiskaddr}\0" \ - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ + "mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \ "run ramargs; " \ "run common_bootargs; " \ "run dump_bootargs; " \ - "tftpboot ${loadaddr} ${bootfile}; "\ - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\ + "run loadzimage; " \ + "run loadramdisk; " \ + "run loadfdtimage; " \ + "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \ + "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "tftpboot ${loadaddr} ${uimage}; " \ + "tftpboot ${ramdiskaddr} ${ramdiskimage}; " \ "bootm ${loadaddr} ${ramdiskaddr}\0" #define CONFIG_BOOTCOMMAND \ "run autoboot" +/* Miscellaneous configurable options */ #define CONFIG_AUTO_COMPLETE -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ +/* FLASH and environment organization */ /* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE #elif defined(CONFIG_CMD_ONENAND) @@ -250,29 +283,32 @@ /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#endif - #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -/* - * SMSC922x Ethernet - */ +/* SMSC922x Ethernet */ #if defined(CONFIG_CMD_NET) - #define CONFIG_SMC911X -#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x08000000 - #endif /* (CONFIG_CMD_NET) */ +/* Defines for SPL */ + +#define CONFIG_SPL_OMAP3_ID_NAND + +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index ef80bf60ca..fa71874f8a 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -111,7 +111,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 -/* U-boot copy size from boot Media to DRAM.*/ +/* U-Boot copy size from boot Media to DRAM.*/ #define COPY_BL2_SIZE 0x80000 #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index fffe5c9df8..9ca29f8b4e 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -44,7 +44,6 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 7dbf4221f4..01fd743d82 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -44,7 +44,6 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/p2571.h b/include/configs/p2571.h index f3357d1e0d..d35e25524f 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -45,7 +45,6 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/paz00.h b/include/configs/paz00.h index d9dd9bdcd4..6acecb1e27 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -48,10 +48,6 @@ #define CONFIG_CMD_DHCP /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 2e5ce75629..1af9ef7cad 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for PR1 Appliance + * U-Boot - Configuration file for PR1 Appliance * * based on bf537-stamp.h * Copyright (c) Switchfin Org. <dpn@switchfin.org> diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h index 927bae78eb..97e5d2c795 100644 --- a/include/configs/rpi-common.h +++ b/include/configs/rpi-common.h @@ -144,8 +144,14 @@ /* * Memory layout for where various images get loaded by boot scripts: * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it low in memory to avoid conflicts. + * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this. + * + * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's + * binary firmware loads a DT to address 0x100, so we choose this address to + * match it. This allows custom boot scripts to pass this DT on to Linux + * simply by not over-writing the data at this address. When using U-Boot, + * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW + * and loads its own DT from disk (triggered by boot.scr or extlinux.conf). * * pxefile_addr_r can be pretty much anywhere that doesn't conflict with * something else. Put it low in memory to avoid conflicts. @@ -159,13 +165,15 @@ * this up to 16M allows for a sizable kernel to be decompressed below the * compressed load address. * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Choosing 32M allows for the compressed kernel to be up to 16M. * * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. + * for any boot script to be up to 1M, which is hopefully plenty. */ #define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=ffffffff\0" \ + "initrd_high=ffffffff\0" \ "fdt_addr_r=0x00000100\0" \ "pxefile_addr_r=0x00100000\0" \ "kernel_addr_r=0x01000000\0" \ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 3e904746f2..06112139ea 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_STORAGE @@ -66,10 +65,6 @@ #define CONFIG_USB_KEYBOARD /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 7148f1da95..0fd2caf161 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS (1) #define CONFIG_SYS_MAX_FLASH_SECT (520) -/* U-boot setting */ +/* U-Boot setting */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_MONITOR_LEN (128 * 1024) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 44d1d5a171..de7b6bca1d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -49,10 +49,18 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + /* setting board specific options */ -# define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB -#define CONFIG_CMDLINE_EDITING +#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB +#define CONFIG_AUTO_COMPLETE +#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_AUTOLOAD "yes" +#define CONFIG_RESET_TO_RETRY /* The LED PINs */ #define CONFIG_RED_LED AT91_PIN_PA9 @@ -184,9 +192,7 @@ /* General Boot Parameter */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 2492f99269..b7ac402f98 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -92,7 +92,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 -/* U-boot copy size from boot Media to DRAM.*/ +/* U-Boot copy size from boot Media to DRAM.*/ #define COPY_BL2_SIZE 0x80000 #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) diff --git a/include/configs/sniper.h b/include/configs/sniper.h index a995415432..4152ecde26 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -1,5 +1,5 @@ /* - * LG Optimus Black (P970) codename sniper config + * LG Optimus Black codename sniper config * * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> * diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index d2630f4be1..a309448ecf 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -12,7 +12,7 @@ */ -/* U-boot Load Address */ +/* U-Boot Load Address */ #define CONFIG_SYS_TEXT_BASE 0x00700000 /* Ethernet driver configuration */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index f4213217bb..6db628a052 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -45,7 +45,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* U-boot Load Address */ +/* U-Boot Load Address */ #define CONFIG_SYS_TEXT_BASE 0x00010000 #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 1e74535b5c..0f4d959e67 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for Bluetechnix TCM-BF518 board + * U-Boot - Configuration file for Bluetechnix TCM-BF518 board */ #ifndef __CONFIG_TCM_BF518_H__ diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index a8947c5934..fc98d242fb 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -1,5 +1,5 @@ /* - * U-boot - Configuration file for TCM-BF537 board + * U-Boot - Configuration file for TCM-BF537 board */ #ifndef __CONFIG_TCM_BF537_H__ diff --git a/include/configs/tec.h b/include/configs/tec.h index 4b8ca5e8da..50b9e97fe7 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -48,10 +48,6 @@ #define CONFIG_CMD_DHCP /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK /* support the new (FDT-based) image format */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 68da23e8b7..b6b8ffc08f 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -53,6 +53,12 @@ #define STDOUT_LCD "" #endif +#ifdef CONFIG_DM_VIDEO +#define STDOUT_VIDEO ",vidconsole" +#else +#define STDOUT_VIDEO "" +#endif + #ifdef CONFIG_CROS_EC_KEYB #define STDOUT_CROS_EC ",cros-ec-keyb" #else @@ -61,8 +67,8 @@ #define TEGRA_DEVICE_SETTINGS \ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ - "stdout=serial" STDOUT_LCD "\0" \ - "stderr=serial" STDOUT_LCD "\0" \ + "stdout=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ + "stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ "" #ifndef BOARD_EXTRA_ENV_SETTINGS diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 8761f8de09..92ebb6aa4c 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -44,7 +44,6 @@ #define CONFIG_ENV_OFFSET (512 * 1024) /* USB Host support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_STORAGE diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index 2f6c97cf58..50e1abb0e5 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -20,7 +20,7 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_NO_FLASH /* No NOR Flash */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-boot is a 2nd stage bootloader */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ #define CONFIG_HW_WATCHDOG diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 599b26959e..fcec0c0ae2 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* U-boot - Common settings for UniPhier Family */ +/* U-Boot - Common settings for UniPhier Family */ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ @@ -173,7 +173,7 @@ "setenv bootargs $bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ - "tftpboot; bootm;" + "run __nfsboot" #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" @@ -186,7 +186,8 @@ "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ "bootm $fit_addr_r\0" \ "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ - "bootm $fit_addr_r\0" + "bootm $fit_addr_r\0" \ + "__nfsboot=run tftpboot\0" #else #define CONFIG_CMD_BOOTZ #define CONFIG_BOOTFILE "zImage" @@ -201,31 +202,36 @@ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ - "norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ - "setexpr kernel_addr $nor_base + $kernel_addr &&" \ - "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ - "setexpr fdt_addr $nor_base + $fdt_addr &&" \ - "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ - "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \ + "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ + "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ + "run boot_common\0" \ + "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ - "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ - "tftpboot $kernel_addr_r $bootfile &&" \ + "run boot_common\0" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" + "run boot_common\0" \ + "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot $fdt_addr_r $fdt_file &&" \ + "tftpboot $fdt_addr_r $fdt_file &&" \ + "setenv ramdisk_addr_r - &&" \ + "run boot_common\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "verify=n\0" \ - "norbase=0x42000000\0" \ + "nor_base=0x42000000\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ - "tftpboot u-boot-spl-dtb.bin &&" \ + "tftpboot u-boot-spl.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ - "tftpboot u-boot-dtb.img &&" \ + "tftpboot u-boot.img &&" \ "nand write $loadaddr 0x00010000 0x000f0000\0" \ LINUXBOOT_ENV_SETTINGS @@ -245,7 +251,7 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#define CONFIG_SPL_STACK (0x0ff08000) +#define CONFIG_SPL_STACK (0x00100000) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) #define CONFIG_PANIC_HANG diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 4a0b448332..75f7268d10 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -45,7 +45,6 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB diff --git a/include/configs/ventana.h b/include/configs/ventana.h index e9c3500109..7f970d011d 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -49,10 +49,6 @@ #define CONFIG_USB_KEYBOARD /* LCD support */ -#define CONFIG_LCD -#define CONFIG_PWM_TEGRA -#define CONFIG_VIDEO_TEGRA -#define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 814934aa92..133041bca5 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -24,7 +24,7 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_IDENT_STRING " vexpress_aemv8a" -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8.vexpress_aemv8a" /* Link Definitions */ #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 59b6310b57..883e58e660 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -12,7 +12,7 @@ #define __VEXPRESS_CA15X2_TC2_h #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca15x2_tc2" #include "vexpress_common.h" #define CONFIG_SYSFLAGS_ADDR 0x1c010030 diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h index a4ffdf54db..43850272a6 100644 --- a/include/configs/vexpress_ca5x2.h +++ b/include/configs/vexpress_ca5x2.h @@ -12,7 +12,7 @@ #define __VEXPRESS_CA5X2_h #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca5x2" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca5x2" #include "vexpress_common.h" #endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h index 71233d8c3f..99be50a5bd 100644 --- a/include/configs/vexpress_ca9x4.h +++ b/include/configs/vexpress_ca9x4.h @@ -12,7 +12,7 @@ #define __VEXPRESS_CA9X4_H #define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca9x4" +#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca9x4" #include "vexpress_common.h" #endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/vinco.h b/include/configs/vinco.h new file mode 100644 index 0000000000..92b1b4bca7 --- /dev/null +++ b/include/configs/vinco.h @@ -0,0 +1,167 @@ +/* + * Configuration settings for the VInCo platform. + * + * Based on the settings for the SAMA5-EK board + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * Copyright (C) 2015 Free Electrons + * Gregory CLEMENT gregory.clement@free-electrons.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should be put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* The value in the common file is too far away for the VInCo platform */ +#ifdef CONFIG_SYS_TEXT_BASE +#undef CONFIG_SYS_TEXT_BASE +#endif +#define CONFIG_SYS_TEXT_BASE 0x20f00000 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x4000000 + + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_ENV_SPI_MODE (SPI_MODE_0) +#endif + + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#define CONFIG_SYS_MMC_CLK_OD 500000 + +/* For generating MMC partitions */ +#define CONFIG_PARTITION_UUIDS +#define CONFIG_RANDOM_UUID +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "L+G VInCo" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_CMD_MII +#define CONFIG_PHY_SMSC +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RNDIS + + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +/* Use our own mapping for the VInCo platform */ +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE + +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* Update the bootcommand according to our mapping for the VInCo platform */ +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \ + "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \ + "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \ + "bootz ${loadaddr} - ${oftaddr}" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_start=0x20000\0" \ + "kernel_size=0x800000\0" \ + "mmcblksize=0x200\0" \ + "oftaddr=0x21000000\0" \ + "loadaddr=0x22000000\0" \ + "update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \ + "sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \ + "create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \ + "setexpr rootfs_start ${kernel_start} + ${kernel_size};" \ + "setenv partitions 'name=kernel,size=${kernel_size}," \ + "start=${kernel_start};name=rootfs,size=-';" \ + "gpt write mmc 0 ${partitions} \0"\ + "f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \ + "setexpr fileblksize ${fileblksize} + 1\0" \ + "store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \ + "setexpr k_blksize ${fileblksize};" \ + "setexpr k_offset ${kernel_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \ + "store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \ + "setexpr dtb_blksize ${fileblksize};" \ + "setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \ + "store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \ + "setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \ + "bootdelay=0\0" + +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index dc7b227d25..3ae4366bfa 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -236,4 +236,6 @@ "tftpboot $loadaddr $bootfile;" \ "zboot $loadaddr" +#define CONFIG_BOOTDELAY 2 + #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 27ef74daf5..28622dec18 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -105,6 +105,15 @@ # define CONFIG_CMD_EXT4_WRITE #endif +#ifdef CONFIG_NAND_ARASAN +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR 0x8000000 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h new file mode 100644 index 0000000000..a215609056 --- /dev/null +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -0,0 +1,345 @@ +/* + * This header provides constants for binding nvidia,tegra124-car or + * nvidia,tegra132-car. + * + * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 185 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 185 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H +#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA124_CLK_ISPB 3 +#define TEGRA124_CLK_RTC 4 +#define TEGRA124_CLK_TIMER 5 +#define TEGRA124_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA124_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA124_CLK_I2S1 11 +#define TEGRA124_CLK_I2C1 12 +/* 13 */ +#define TEGRA124_CLK_SDMMC1 14 +#define TEGRA124_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA124_CLK_PWM 17 +#define TEGRA124_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA124_CLK_USBD 22 +#define TEGRA124_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA124_CLK_DISP2 26 +#define TEGRA124_CLK_DISP1 27 +#define TEGRA124_CLK_HOST1X 28 +#define TEGRA124_CLK_VCP 29 +#define TEGRA124_CLK_I2S0 30 +/* 31 */ + +#define TEGRA124_CLK_MC 32 +/* 33 */ +#define TEGRA124_CLK_APBDMA 34 +/* 35 */ +#define TEGRA124_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA124_CLK_KFUSE 40 +#define TEGRA124_CLK_SBC1 41 +#define TEGRA124_CLK_NOR 42 +/* 43 */ +#define TEGRA124_CLK_SBC2 44 +/* 45 */ +#define TEGRA124_CLK_SBC3 46 +#define TEGRA124_CLK_I2C5 47 +#define TEGRA124_CLK_DSIA 48 +/* 49 */ +#define TEGRA124_CLK_MIPI 50 +#define TEGRA124_CLK_HDMI 51 +#define TEGRA124_CLK_CSI 52 +/* 53 */ +#define TEGRA124_CLK_I2C2 54 +#define TEGRA124_CLK_UARTC 55 +#define TEGRA124_CLK_MIPI_CAL 56 +#define TEGRA124_CLK_EMC 57 +#define TEGRA124_CLK_USB2 58 +#define TEGRA124_CLK_USB3 59 +/* 60 */ +#define TEGRA124_CLK_VDE 61 +#define TEGRA124_CLK_BSEA 62 +#define TEGRA124_CLK_BSEV 63 + +/* 64 */ +#define TEGRA124_CLK_UARTD 65 +/* 66 */ +#define TEGRA124_CLK_I2C3 67 +#define TEGRA124_CLK_SBC4 68 +#define TEGRA124_CLK_SDMMC3 69 +#define TEGRA124_CLK_PCIE 70 +#define TEGRA124_CLK_OWR 71 +#define TEGRA124_CLK_AFI 72 +#define TEGRA124_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA124_CLK_LA 76 +#define TEGRA124_CLK_TRACE 77 +#define TEGRA124_CLK_SOC_THERM 78 +#define TEGRA124_CLK_DTV 79 +/* 80 */ +#define TEGRA124_CLK_I2CSLOW 81 +#define TEGRA124_CLK_DSIB 82 +#define TEGRA124_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA124_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA124_CLK_MSENC 91 +#define TEGRA124_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA124_CLK_MSELECT 99 +#define TEGRA124_CLK_TSENSOR 100 +#define TEGRA124_CLK_I2S3 101 +#define TEGRA124_CLK_I2S4 102 +#define TEGRA124_CLK_I2C4 103 +#define TEGRA124_CLK_SBC5 104 +#define TEGRA124_CLK_SBC6 105 +#define TEGRA124_CLK_D_AUDIO 106 +#define TEGRA124_CLK_APBIF 107 +#define TEGRA124_CLK_DAM0 108 +#define TEGRA124_CLK_DAM1 109 +#define TEGRA124_CLK_DAM2 110 +#define TEGRA124_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA124_CLK_AUDIO0_2X 113 +#define TEGRA124_CLK_AUDIO1_2X 114 +#define TEGRA124_CLK_AUDIO2_2X 115 +#define TEGRA124_CLK_AUDIO3_2X 116 +#define TEGRA124_CLK_AUDIO4_2X 117 +#define TEGRA124_CLK_SPDIF_2X 118 +#define TEGRA124_CLK_ACTMON 119 +#define TEGRA124_CLK_EXTERN1 120 +#define TEGRA124_CLK_EXTERN2 121 +#define TEGRA124_CLK_EXTERN3 122 +#define TEGRA124_CLK_SATA_OOB 123 +#define TEGRA124_CLK_SATA 124 +#define TEGRA124_CLK_HDA 125 +/* 126 */ +#define TEGRA124_CLK_SE 127 + +#define TEGRA124_CLK_HDA2HDMI 128 +#define TEGRA124_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA124_CLK_CILAB 144 +#define TEGRA124_CLK_CILCD 145 +#define TEGRA124_CLK_CILE 146 +#define TEGRA124_CLK_DSIALP 147 +#define TEGRA124_CLK_DSIBLP 148 +#define TEGRA124_CLK_ENTROPY 149 +#define TEGRA124_CLK_DDS 150 +/* 151 */ +#define TEGRA124_CLK_DP2 152 +#define TEGRA124_CLK_AMX 153 +#define TEGRA124_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA124_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA124_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA124_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA124_CLK_HDMI_AUDIO 176 +#define TEGRA124_CLK_CLK72MHZ 177 +#define TEGRA124_CLK_VIC03 178 +/* 179 */ +#define TEGRA124_CLK_ADX1 180 +#define TEGRA124_CLK_DPAUX 181 +#define TEGRA124_CLK_SOR0 182 +/* 183 */ +#define TEGRA124_CLK_GPU 184 +#define TEGRA124_CLK_AMX1 185 +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ +#define TEGRA124_CLK_UARTB 192 +#define TEGRA124_CLK_VFIR 193 +#define TEGRA124_CLK_SPDIF_IN 194 +#define TEGRA124_CLK_SPDIF_OUT 195 +#define TEGRA124_CLK_VI 196 +#define TEGRA124_CLK_VI_SENSOR 197 +#define TEGRA124_CLK_FUSE 198 +#define TEGRA124_CLK_FUSE_BURN 199 +#define TEGRA124_CLK_CLK_32K 200 +#define TEGRA124_CLK_CLK_M 201 +#define TEGRA124_CLK_CLK_M_DIV2 202 +#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_PLL_REF 204 +#define TEGRA124_CLK_PLL_C 205 +#define TEGRA124_CLK_PLL_C_OUT1 206 +#define TEGRA124_CLK_PLL_C2 207 +#define TEGRA124_CLK_PLL_C3 208 +#define TEGRA124_CLK_PLL_M 209 +#define TEGRA124_CLK_PLL_M_OUT1 210 +#define TEGRA124_CLK_PLL_P 211 +#define TEGRA124_CLK_PLL_P_OUT1 212 +#define TEGRA124_CLK_PLL_P_OUT2 213 +#define TEGRA124_CLK_PLL_P_OUT3 214 +#define TEGRA124_CLK_PLL_P_OUT4 215 +#define TEGRA124_CLK_PLL_A 216 +#define TEGRA124_CLK_PLL_A_OUT0 217 +#define TEGRA124_CLK_PLL_D 218 +#define TEGRA124_CLK_PLL_D_OUT0 219 +#define TEGRA124_CLK_PLL_D2 220 +#define TEGRA124_CLK_PLL_D2_OUT0 221 +#define TEGRA124_CLK_PLL_U 222 +#define TEGRA124_CLK_PLL_U_480M 223 + +#define TEGRA124_CLK_PLL_U_60M 224 +#define TEGRA124_CLK_PLL_U_48M 225 +#define TEGRA124_CLK_PLL_U_12M 226 +/* 227 */ +/* 228 */ +#define TEGRA124_CLK_PLL_RE_VCO 229 +#define TEGRA124_CLK_PLL_RE_OUT 230 +#define TEGRA124_CLK_PLL_E 231 +#define TEGRA124_CLK_SPDIF_IN_SYNC 232 +#define TEGRA124_CLK_I2S0_SYNC 233 +#define TEGRA124_CLK_I2S1_SYNC 234 +#define TEGRA124_CLK_I2S2_SYNC 235 +#define TEGRA124_CLK_I2S3_SYNC 236 +#define TEGRA124_CLK_I2S4_SYNC 237 +#define TEGRA124_CLK_VIMCLK_SYNC 238 +#define TEGRA124_CLK_AUDIO0 239 +#define TEGRA124_CLK_AUDIO1 240 +#define TEGRA124_CLK_AUDIO2 241 +#define TEGRA124_CLK_AUDIO3 242 +#define TEGRA124_CLK_AUDIO4 243 +#define TEGRA124_CLK_SPDIF 244 +#define TEGRA124_CLK_CLK_OUT_1 245 +#define TEGRA124_CLK_CLK_OUT_2 246 +#define TEGRA124_CLK_CLK_OUT_3 247 +#define TEGRA124_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA124_CLK_XUSB_HOST_SRC 252 +#define TEGRA124_CLK_XUSB_FALCON_SRC 253 +#define TEGRA124_CLK_XUSB_FS_SRC 254 +#define TEGRA124_CLK_XUSB_SS_SRC 255 + +#define TEGRA124_CLK_XUSB_DEV_SRC 256 +#define TEGRA124_CLK_XUSB_DEV 257 +#define TEGRA124_CLK_XUSB_HS_SRC 258 +#define TEGRA124_CLK_SCLK 259 +#define TEGRA124_CLK_HCLK 260 +#define TEGRA124_CLK_PCLK 261 +/* 262 */ +/* 263 */ +#define TEGRA124_CLK_DFLL_REF 264 +#define TEGRA124_CLK_DFLL_SOC 265 +#define TEGRA124_CLK_VI_SENSOR2 266 +#define TEGRA124_CLK_PLL_P_OUT5 267 +#define TEGRA124_CLK_CML0 268 +#define TEGRA124_CLK_CML1 269 +#define TEGRA124_CLK_PLL_C4 270 +#define TEGRA124_CLK_PLL_DP 271 +#define TEGRA124_CLK_PLL_E_MUX 272 +#define TEGRA124_CLK_PLL_D_DSI_OUT 273 +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA124_CLK_AUDIO0_MUX 300 +#define TEGRA124_CLK_AUDIO1_MUX 301 +#define TEGRA124_CLK_AUDIO2_MUX 302 +#define TEGRA124_CLK_AUDIO3_MUX 303 +#define TEGRA124_CLK_AUDIO4_MUX 304 +#define TEGRA124_CLK_SPDIF_MUX 305 +#define TEGRA124_CLK_CLK_OUT_1_MUX 306 +#define TEGRA124_CLK_CLK_OUT_2_MUX 307 +#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +/* 309 */ +/* 310 */ +#define TEGRA124_CLK_SOR0_LVDS 311 +#define TEGRA124_CLK_XUSB_SS_DIV2 312 + +#define TEGRA124_CLK_PLL_M_UD 313 +#define TEGRA124_CLK_PLL_C_UD 314 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h index fd8d62ac7f..2860737f04 100644 --- a/include/dt-bindings/clock/tegra124-car.h +++ b/include/dt-bindings/clock/tegra124-car.h @@ -1,342 +1,19 @@ /* - * This header provides constants for binding nvidia,tegra124-car. - * - * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 185 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 185 and - * above. + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. */ +#include <dt-bindings/clock/tegra124-car-common.h> + #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA124_CLK_ISPB 3 -#define TEGRA124_CLK_RTC 4 -#define TEGRA124_CLK_TIMER 5 -#define TEGRA124_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA124_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA124_CLK_I2S1 11 -#define TEGRA124_CLK_I2C1 12 -#define TEGRA124_CLK_NDFLASH 13 -#define TEGRA124_CLK_SDMMC1 14 -#define TEGRA124_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA124_CLK_PWM 17 -#define TEGRA124_CLK_I2S2 18 -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA124_CLK_USBD 22 -#define TEGRA124_CLK_ISP 23 -/* 26 */ -/* 25 */ -#define TEGRA124_CLK_DISP2 26 -#define TEGRA124_CLK_DISP1 27 -#define TEGRA124_CLK_HOST1X 28 -#define TEGRA124_CLK_VCP 29 -#define TEGRA124_CLK_I2S0 30 -/* 31 */ - -/* 32 */ -/* 33 */ -#define TEGRA124_CLK_APBDMA 34 -/* 35 */ -#define TEGRA124_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA124_CLK_KFUSE 40 -#define TEGRA124_CLK_SBC1 41 -#define TEGRA124_CLK_NOR 42 -/* 43 */ -#define TEGRA124_CLK_SBC2 44 -/* 45 */ -#define TEGRA124_CLK_SBC3 46 -#define TEGRA124_CLK_I2C5 47 -#define TEGRA124_CLK_DSIA 48 -/* 49 */ -#define TEGRA124_CLK_MIPI 50 -#define TEGRA124_CLK_HDMI 51 -#define TEGRA124_CLK_CSI 52 -/* 53 */ -#define TEGRA124_CLK_I2C2 54 -#define TEGRA124_CLK_UARTC 55 -#define TEGRA124_CLK_MIPI_CAL 56 -#define TEGRA124_CLK_EMC 57 -#define TEGRA124_CLK_USB2 58 -#define TEGRA124_CLK_USB3 59 -/* 60 */ -#define TEGRA124_CLK_VDE 61 -#define TEGRA124_CLK_BSEA 62 -#define TEGRA124_CLK_BSEV 63 - -/* 64 */ -#define TEGRA124_CLK_UARTD 65 -#define TEGRA124_CLK_UARTE 66 -#define TEGRA124_CLK_I2C3 67 -#define TEGRA124_CLK_SBC4 68 -#define TEGRA124_CLK_SDMMC3 69 -#define TEGRA124_CLK_PCIE 70 -#define TEGRA124_CLK_OWR 71 -#define TEGRA124_CLK_AFI 72 -#define TEGRA124_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA124_CLK_LA 76 -#define TEGRA124_CLK_TRACE 77 -#define TEGRA124_CLK_SOC_THERM 78 -#define TEGRA124_CLK_DTV 79 -#define TEGRA124_CLK_NDSPEED 80 -#define TEGRA124_CLK_I2CSLOW 81 -#define TEGRA124_CLK_DSIB 82 -#define TEGRA124_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA124_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA124_CLK_MSENC 91 -#define TEGRA124_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA124_CLK_MSELECT 99 -#define TEGRA124_CLK_TSENSOR 100 -#define TEGRA124_CLK_I2S3 101 -#define TEGRA124_CLK_I2S4 102 -#define TEGRA124_CLK_I2C4 103 -#define TEGRA124_CLK_SBC5 104 -#define TEGRA124_CLK_SBC6 105 -#define TEGRA124_CLK_D_AUDIO 106 -#define TEGRA124_CLK_APBIF 107 -#define TEGRA124_CLK_DAM0 108 -#define TEGRA124_CLK_DAM1 109 -#define TEGRA124_CLK_DAM2 110 -#define TEGRA124_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA124_CLK_AUDIO0_2X 113 -#define TEGRA124_CLK_AUDIO1_2X 114 -#define TEGRA124_CLK_AUDIO2_2X 115 -#define TEGRA124_CLK_AUDIO3_2X 116 -#define TEGRA124_CLK_AUDIO4_2X 117 -#define TEGRA124_CLK_SPDIF_2X 118 -#define TEGRA124_CLK_ACTMON 119 -#define TEGRA124_CLK_EXTERN1 120 -#define TEGRA124_CLK_EXTERN2 121 -#define TEGRA124_CLK_EXTERN3 122 -#define TEGRA124_CLK_SATA_OOB 123 -#define TEGRA124_CLK_SATA 124 -#define TEGRA124_CLK_HDA 125 -/* 126 */ -#define TEGRA124_CLK_SE 127 - -#define TEGRA124_CLK_HDA2HDMI 128 -#define TEGRA124_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA124_CLK_CILAB 144 -#define TEGRA124_CLK_CILCD 145 -#define TEGRA124_CLK_CILE 146 -#define TEGRA124_CLK_DSIALP 147 -#define TEGRA124_CLK_DSIBLP 148 -#define TEGRA124_CLK_ENTROPY 149 -#define TEGRA124_CLK_DDS 150 -/* 151 */ -#define TEGRA124_CLK_DP2 152 -#define TEGRA124_CLK_AMX 153 -#define TEGRA124_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA124_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA124_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA124_CLK_VIM2_CLK 171 -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -#define TEGRA124_CLK_HDMI_AUDIO 176 -#define TEGRA124_CLK_CLK72MHZ 177 -#define TEGRA124_CLK_VIC03 178 -/* 179 */ -#define TEGRA124_CLK_ADX1 180 -#define TEGRA124_CLK_DPAUX 181 -#define TEGRA124_CLK_SOR0 182 -/* 183 */ -#define TEGRA124_CLK_GPU 184 -#define TEGRA124_CLK_AMX1 185 -#define TEGRA124_CLK_AFC0 186 -#define TEGRA124_CLK_AFC1 187 -#define TEGRA124_CLK_AFC2 188 -#define TEGRA124_CLK_AFC3 189 -#define TEGRA124_CLK_AFC4 190 -#define TEGRA124_CLK_AFC5 191 -#define TEGRA124_CLK_UARTB 192 -#define TEGRA124_CLK_VFIR 193 -#define TEGRA124_CLK_SPDIF_IN 194 -#define TEGRA124_CLK_SPDIF_OUT 195 -#define TEGRA124_CLK_VI 196 -#define TEGRA124_CLK_VI_SENSOR 197 -#define TEGRA124_CLK_FUSE 198 -#define TEGRA124_CLK_FUSE_BURN 199 -#define TEGRA124_CLK_CLK_32K 200 -#define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 -#define TEGRA124_CLK_PLL_REF 204 -#define TEGRA124_CLK_PLL_C 205 -#define TEGRA124_CLK_PLL_C_OUT1 206 -#define TEGRA124_CLK_PLL_C2 207 -#define TEGRA124_CLK_PLL_C3 208 -#define TEGRA124_CLK_PLL_M 209 -#define TEGRA124_CLK_PLL_M_OUT1 210 -#define TEGRA124_CLK_PLL_P 211 -#define TEGRA124_CLK_PLL_P_OUT1 212 -#define TEGRA124_CLK_PLL_P_OUT2 213 -#define TEGRA124_CLK_PLL_P_OUT3 214 -#define TEGRA124_CLK_PLL_P_OUT4 215 -#define TEGRA124_CLK_PLL_A 216 -#define TEGRA124_CLK_PLL_A_OUT0 217 -#define TEGRA124_CLK_PLL_D 218 -#define TEGRA124_CLK_PLL_D_OUT0 219 -#define TEGRA124_CLK_PLL_D2 220 -#define TEGRA124_CLK_PLL_D2_OUT0 221 -#define TEGRA124_CLK_PLL_U 222 -#define TEGRA124_CLK_PLL_U_480M 223 - -#define TEGRA124_CLK_PLL_U_60M 224 -#define TEGRA124_CLK_PLL_U_48M 225 -#define TEGRA124_CLK_PLL_U_12M 226 -#define TEGRA124_CLK_PLL_X 227 -#define TEGRA124_CLK_PLL_X_OUT0 228 -#define TEGRA124_CLK_PLL_RE_VCO 229 -#define TEGRA124_CLK_PLL_RE_OUT 230 -#define TEGRA124_CLK_PLL_E 231 -#define TEGRA124_CLK_SPDIF_IN_SYNC 232 -#define TEGRA124_CLK_I2S0_SYNC 233 -#define TEGRA124_CLK_I2S1_SYNC 234 -#define TEGRA124_CLK_I2S2_SYNC 235 -#define TEGRA124_CLK_I2S3_SYNC 236 -#define TEGRA124_CLK_I2S4_SYNC 237 -#define TEGRA124_CLK_VIMCLK_SYNC 238 -#define TEGRA124_CLK_AUDIO0 239 -#define TEGRA124_CLK_AUDIO1 240 -#define TEGRA124_CLK_AUDIO2 241 -#define TEGRA124_CLK_AUDIO3 242 -#define TEGRA124_CLK_AUDIO4 243 -#define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA124_CLK_XUSB_HOST_SRC 252 -#define TEGRA124_CLK_XUSB_FALCON_SRC 253 -#define TEGRA124_CLK_XUSB_FS_SRC 254 -#define TEGRA124_CLK_XUSB_SS_SRC 255 +#define TEGRA124_CLK_PLL_X 227 +#define TEGRA124_CLK_PLL_X_OUT0 228 -#define TEGRA124_CLK_XUSB_DEV_SRC 256 -#define TEGRA124_CLK_XUSB_DEV 257 -#define TEGRA124_CLK_XUSB_HS_SRC 258 -#define TEGRA124_CLK_SCLK 259 -#define TEGRA124_CLK_HCLK 260 -#define TEGRA124_CLK_PCLK 261 -#define TEGRA124_CLK_CCLK_G 262 -#define TEGRA124_CLK_CCLK_LP 263 -#define TEGRA124_CLK_DFLL_REF 264 -#define TEGRA124_CLK_DFLL_SOC 265 -#define TEGRA124_CLK_VI_SENSOR2 266 -#define TEGRA124_CLK_PLL_P_OUT5 267 -#define TEGRA124_CLK_CML0 268 -#define TEGRA124_CLK_CML1 269 -#define TEGRA124_CLK_PLL_C4 270 -#define TEGRA124_CLK_PLL_DP 271 -#define TEGRA124_CLK_PLL_E_MUX 272 -/* 273 */ -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ +#define TEGRA124_CLK_CCLK_G 262 +#define TEGRA124_CLK_CCLK_LP 263 -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA124_CLK_AUDIO0_MUX 300 -#define TEGRA124_CLK_AUDIO1_MUX 301 -#define TEGRA124_CLK_AUDIO2_MUX 302 -#define TEGRA124_CLK_AUDIO3_MUX 303 -#define TEGRA124_CLK_AUDIO4_MUX 304 -#define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 -#define TEGRA124_CLK_DSIA_MUX 309 -#define TEGRA124_CLK_DSIB_MUX 310 -#define TEGRA124_CLK_SOR0_LVDS 311 -#define TEGRA124_CLK_PLL_M_UD 311 -#define TEGRA124_CLK_CLK_MAX 312 +#define TEGRA124_CLK_CLK_MAX 315 #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h new file mode 100644 index 0000000000..7d8ee798f3 --- /dev/null +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -0,0 +1,31 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H +#define DT_BINDINGS_MEMORY_TEGRA124_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_AFI 3 +#define TEGRA_SWGROUP_AVPC 4 +#define TEGRA_SWGROUP_HDA 5 +#define TEGRA_SWGROUP_HC 6 +#define TEGRA_SWGROUP_MSENC 7 +#define TEGRA_SWGROUP_PPCS 8 +#define TEGRA_SWGROUP_SATA 9 +#define TEGRA_SWGROUP_VDE 10 +#define TEGRA_SWGROUP_MPCORELP 11 +#define TEGRA_SWGROUP_MPCORE 12 +#define TEGRA_SWGROUP_ISP2 13 +#define TEGRA_SWGROUP_XUSB_HOST 14 +#define TEGRA_SWGROUP_XUSB_DEV 15 +#define TEGRA_SWGROUP_ISP2B 16 +#define TEGRA_SWGROUP_TSEC 17 +#define TEGRA_SWGROUP_A9AVP 18 +#define TEGRA_SWGROUP_GPU 19 +#define TEGRA_SWGROUP_SDMMC1A 20 +#define TEGRA_SWGROUP_SDMMC2A 21 +#define TEGRA_SWGROUP_SDMMC3A 22 +#define TEGRA_SWGROUP_SDMMC4A 23 +#define TEGRA_SWGROUP_VIC 24 +#define TEGRA_SWGROUP_VI 25 + +#endif diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h new file mode 100644 index 0000000000..070e4f6e74 --- /dev/null +++ b/include/dt-bindings/reset/tegra124-car.h @@ -0,0 +1,12 @@ +/* + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H +#define _DT_BINDINGS_RESET_TEGRA124_CAR_H + +#define TEGRA124_RESET(x) (6 * 32 + (x)) +#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h new file mode 100644 index 0000000000..85aaf66690 --- /dev/null +++ b/include/dt-bindings/thermal/tegra124-soctherm.h @@ -0,0 +1,13 @@ +/* + * This header provides constants for binding nvidia,tegra124-soctherm. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H + +#define TEGRA124_SOCTHERM_SENSOR_CPU 0 +#define TEGRA124_SOCTHERM_SENSOR_MEM 1 +#define TEGRA124_SOCTHERM_SENSOR_GPU 2 +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 + +#endif diff --git a/include/env_flags.h b/include/env_flags.h index 8823fb9602..9e87e1b7db 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -143,7 +143,7 @@ int env_flags_validate_varaccess(const char *name, int check_mask); /* * Validate the parameters passed to "env set" for type compliance */ -int env_flags_validate_env_set_params(int argc, char * const argv[]); +int env_flags_validate_env_set_params(char *name, char *const val[], int count); #else /* !USE_HOSTCC */ diff --git a/include/fdtdec.h b/include/fdtdec.h index dd82916dc0..4caf3b6cbd 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -120,7 +120,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ - COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */ COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ @@ -722,6 +721,15 @@ const u32 *fdtdec_locate_array(const void *blob, int node, */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); +/* + * Count child nodes of one parent node. + * + * @param blob FDT blob + * @param node parent node + * @return number of child node; 0 if there is not child node + */ +int fdtdec_get_child_count(const void *blob, int node); + /** * Look in the FDT for a config item with the given name and return its value * as a 32-bit integer. The property must have at least 4 bytes of data. The diff --git a/include/linux/linkage.h b/include/linux/linkage.h index efb04eeed4..8e2f15a635 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -1,5 +1,5 @@ /* - * U-boot - linkage.h + * U-Boot - linkage.h * * Copyright (c) 2005-2007 Analog Devices Inc. * diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h index c1d039cb85..442316b4e2 100644 --- a/include/linux/usb/cdc.h +++ b/include/linux/usb/cdc.h @@ -5,7 +5,7 @@ * notably ethernet adapters and various modems. It's used mostly with * firmware based USB peripherals. * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 4adf35e3ae..b824f13477 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -11,7 +11,7 @@ * * This software is licensed under the GNU GPL version 2. * - * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and * Remy Bohmer <linux@bohmer.net> */ diff --git a/include/pch.h b/include/pch.h index 79f49bd5f6..222e9081c3 100644 --- a/include/pch.h +++ b/include/pch.h @@ -8,12 +8,6 @@ #ifndef __pch_h #define __pch_h -enum pch_version { - PCHV_UNKNOWN, - PCHV_7, - PCHV_9, -}; - #define PCH_RCBA 0xf0 #define BIOS_CTRL_BIOSWE BIT(0) @@ -21,20 +15,13 @@ enum pch_version { /* Operations for the Platform Controller Hub */ struct pch_ops { /** - * get_sbase() - get the address of SPI base + * get_spi_base() - get the address of SPI base * * @dev: PCH device to check * @sbasep: Returns address of SPI base if available, else 0 * @return 0 if OK, -ve on error (e.g. there is no SPI base) */ - int (*get_sbase)(struct udevice *dev, ulong *sbasep); - - /** - * get_version() - get the PCH version - * - * @return version, or -ENOSYS if unknown - */ - enum pch_version (*get_version)(struct udevice *dev); + int (*get_spi_base)(struct udevice *dev, ulong *sbasep); /** * set_spi_protect() - set whether SPI flash is protected or not @@ -45,25 +32,36 @@ struct pch_ops { * @return 0 on success, -ENOSYS if not implemented */ int (*set_spi_protect)(struct udevice *dev, bool protect); + + /** + * get_gpio_base() - get the address of GPIO base + * + * @dev: PCH device to check + * @gbasep: Returns address of GPIO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no GPIO base) + */ + int (*get_gpio_base)(struct udevice *dev, u32 *gbasep); + + /** + * get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ + int (*get_io_base)(struct udevice *dev, u32 *iobasep); }; #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) /** - * pch_get_sbase() - get the address of SPI base + * pch_get_spi_base() - get the address of SPI base * * @dev: PCH device to check * @sbasep: Returns address of SPI base if available, else 0 * @return 0 if OK, -ve on error (e.g. there is no SPI base) */ -int pch_get_sbase(struct udevice *dev, ulong *sbasep); - -/** - * pch_get_version() - get the PCH version - * - * @return version, or -ENOSYS if unknown - */ -enum pch_version pch_get_version(struct udevice *dev); +int pch_get_spi_base(struct udevice *dev, ulong *sbasep); /** * set_spi_protect() - set whether SPI flash is protected or not @@ -75,4 +73,22 @@ enum pch_version pch_get_version(struct udevice *dev); */ int pch_set_spi_protect(struct udevice *dev, bool protect); +/** + * pch_get_gpio_base() - get the address of GPIO base + * + * @dev: PCH device to check + * @gbasep: Returns address of GPIO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no GPIO base) + */ +int pch_get_gpio_base(struct udevice *dev, u32 *gbasep); + +/** + * pch_get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ +int pch_get_io_base(struct udevice *dev, u32 *iobasep); + #endif diff --git a/include/pci.h b/include/pci.h index d0d152c00b..68548b00d9 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1050,6 +1050,11 @@ int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); * functions, rather than byte/word/dword. But both are supported. */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); +int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); +int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); +int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); +int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); #ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ @@ -1059,8 +1064,6 @@ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, return pci_write_config32(pcidev, offset, value); } -int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); - /* Compatibility with old naming */ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, u16 value) @@ -1068,8 +1071,6 @@ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, return pci_write_config16(pcidev, offset, value); } -int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); - /* Compatibility with old naming */ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, u8 value) @@ -1077,8 +1078,6 @@ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, return pci_write_config8(pcidev, offset, value); } -int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, u32 *valuep) @@ -1086,8 +1085,6 @@ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, return pci_read_config32(pcidev, offset, valuep); } -int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, u16 *valuep) @@ -1095,15 +1092,12 @@ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, return pci_read_config16(pcidev, offset, valuep); } -int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, u8 *valuep) { return pci_read_config8(pcidev, offset, valuep); } - #endif /* CONFIG_DM_PCI_COMPAT */ /** diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000000..805fa0ebb1 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_ + +/* + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0 + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of + * SYSOPT0 and SYSOPT1 determines one of the following addresses. + */ +#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e + +/* SIO1007 registers */ + +#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7) + +#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28 + +#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30 + +#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1 + +#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1 + +#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1 + +#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1) + +/* Runtime register offset */ + +#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe + +/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2 + +/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM) + +/** + * Configure the I/O port address of the specified serial device and + * enable the serial device. + * + * @port: SIO1007 I/O port address + * @num: serial device number (0 or 1) + * @iobase: processor I/O port address to assign to this serial device + * @irq: processor IRQ number to assign to this serial device + */ +void sio1007_enable_serial(int port, int num, int iobase, int irq); + +/** + * Configure the I/O port address of the runtime register block and + * enable the address decoding. + * + * @port: SIO1007 I/O port address + * @iobase: processor I/O port address to assign to the runtime registers + */ +void sio1007_enable_runtime(int port, int iobase); + +/** + * Configure the direction/polority/type of a specified GPIO pin + * + * @port: SIO1007 I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN + */ +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type); + +/** + * Get a GPIO pin value. + * This will work whether the GPIO is an input or an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid + */ +int sio1007_gpio_get_value(int port, int gpio); + +/** + * Set a GPIO pin value. + * This will only work when the GPIO is configured as an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @val: 0 if low, 1 if high + */ +void sio1007_gpio_set_value(int port, int gpio, int val); + +#endif /* _SMSC_SIO1007_H_ */ diff --git a/lib/Kconfig b/lib/Kconfig index 46d7034397..c7eab46516 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -16,7 +16,7 @@ config USE_PRIVATE_LIBGCC depends on HAVE_PRIVATE_LIBGCC help This option allows you to use the built-in libgcc implementation - of U-boot instead of the one privided by the compiler. + of U-Boot instead of the one privided by the compiler. If unsure, say N. config SYS_HZ diff --git a/lib/Makefile b/lib/Makefile index dd36f25b2a..1e21bcc4c7 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_ADDR_MAP) += addr_map.o obj-y += hashtable.o obj-y += errno.o obj-y += display_options.o +CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"') obj-$(CONFIG_BCH) += bch.o obj-y += crc32.o obj-y += ctype.o diff --git a/lib/bzip2/bzlib_compress.c b/lib/bzip2/bzlib_compress.c index c8da1c72e9..68d948b427 100644 --- a/lib/bzip2/bzlib_compress.c +++ b/lib/bzip2/bzlib_compress.c @@ -67,7 +67,7 @@ */ #include "bzlib_private.h" - +#include <compiler.h> /*---------------------------------------------------*/ /*--- Bit stream I/O ---*/ @@ -280,7 +280,8 @@ void sendMTFValues ( EState* s ) { Int32 v, t, i, j, gs, ge, totc, bt, bc, iter; Int32 nSelectors, alphaSize, minLen, maxLen, selCtr; - Int32 nGroups, nBytes; + Int32 nGroups; + Int32 nBytes __maybe_unused; /*-- UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; @@ -635,8 +636,6 @@ void sendMTFValues ( EState* s ) if (s->verbosity >= 3) VPrintf1( "codes %d\n", s->numZ-nBytes ); - else /* squash compiler 'used but not set' warning */ - nBytes = nBytes; } diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0eb56af4d6..b361a2579f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -27,7 +27,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), - COMPAT(NVIDIA_TEGRA124_DC, "nvidia,tegra124-dc"), COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"), COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), @@ -831,6 +830,17 @@ int fdtdec_parse_phandle_with_args(const void *blob, int src_node, return rc; } +int fdtdec_get_child_count(const void *blob, int node) +{ + int subnode; + int num = 0; + + fdt_for_each_subnode(blob, subnode, node) + num++; + + return num; +} + int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, u8 *array, int count) { diff --git a/lib/gunzip.c b/lib/gunzip.c index 80b157f99e..da0c76c500 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -286,12 +286,11 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, do { r = inflate(&s, Z_FINISH); if (stoponerr == 1 && r != Z_STREAM_END && - (s.avail_out == 0 || r != Z_BUF_ERROR)) { + (s.avail_in == 0 || s.avail_out == 0 || r != Z_BUF_ERROR)) { printf("Error: inflate() returned %d\n", r); err = -1; break; } - s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned char*)dst); } while (r == Z_BUF_ERROR); *lenp = s.next_out - (unsigned char *) dst; inflateEnd(&s); diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index 0700e04cb9..e3c7f3b892 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c @@ -3,7 +3,7 @@ * For conditions of distribution and use, see copyright notice in zlib.h */ -/* U-boot: we already included these +/* U-Boot: we already included these #include "zutil.h" #include "inftrees.h" #include "inflate.h" diff --git a/lib/zlib/inftrees.c b/lib/zlib/inftrees.c index 7474a52e7f..b71b9695a8 100644 --- a/lib/zlib/inftrees.c +++ b/lib/zlib/inftrees.c @@ -3,7 +3,7 @@ * For conditions of distribution and use, see copyright notice in zlib.h */ -/* U-boot: we already included these +/* U-Boot: we already included these #include "zutil.h" #include "inftrees.h" */ diff --git a/lib/zlib/zutil.h b/lib/zlib/zutil.h index 7e05c3b564..e63bf68653 100644 --- a/lib/zlib/zutil.h +++ b/lib/zlib/zutil.h @@ -95,7 +95,7 @@ extern const char * const z_errmsg[10]; /* indexed by 2-zlib_error */ /* Diagnostic functions */ #ifdef DEBUG -/* Not valid for U-boot +/* Not valid for U-Boot # include <stdio.h> */ extern int z_verbose; extern void z_error OF((char *m)); diff --git a/net/eth-uclass.c b/net/eth-uclass.c index a356a08826..c15cc4d90b 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -14,6 +14,8 @@ #include <dm/uclass-internal.h> #include "eth_internal.h" +DECLARE_GLOBAL_DATA_PTR; + /** * struct eth_device_priv - private structure for each Ethernet device * diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index f486feb0d0..44242842db 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -114,7 +114,7 @@ MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE) MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE) -MLO MLO.byteswap: $(obj)/u-boot-spl.bin +MLO MLO.byteswap: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) ifeq ($(CONFIG_SYS_SOC),"at91") @@ -126,12 +126,12 @@ MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params) boot.bin: $(obj)/../tools/atmel_pmecc_params endif -boot.bin: $(obj)/u-boot-spl.bin +boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) else MKIMAGEFLAGS_boot.bin = -T zynqimage -spl/boot.bin: $(obj)/u-boot-spl.bin +spl/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) endif @@ -193,14 +193,14 @@ quiet_cmd_fdtgrep = FDTGREP $@ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) -$(obj)/$(SPL_BIN).dtb: dts/dt.dtb - $(call cmd,fdtgrep) +$(obj)/$(SPL_BIN).dtb: dts/dt.dtb $(objtree)/tools/fdtgrep FORCE + $(call if_changed,fdtgrep) quiet_cmd_cpp_cfg = CFG $@ cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ -DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $< -$(obj)/$(SPL_BIN).cfg: include/config.h +$(obj)/$(SPL_BIN).cfg: include/config.h FORCE $(call if_changed,cpp_cfg) ifdef CONFIG_SAMSUNG @@ -228,18 +228,14 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif -ifdef CONFIG_ARCH_SOCFPGA MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) -endif -ifdef CONFIG_SUNXI quiet_cmd_mksunxiboot = MKSUNXI $@ cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@ -$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mksunxiboot) -endif quiet_cmd_u-boot-spl = LD $@ cmd_u-boot-spl = (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c index 074234fd5d..e8e8c7756d 100644 --- a/scripts/basic/fixdep.c +++ b/scripts/basic/fixdep.c @@ -123,7 +123,7 @@ char *target; char *depfile; char *cmdline; -int is_spl_build = 0; /* hack for U-boot */ +int is_spl_build = 0; /* hack for U-Boot */ static void usage(void) { @@ -459,7 +459,7 @@ int main(int argc, char *argv[]) target = argv[2]; cmdline = argv[3]; - /* hack for U-boot */ + /* hack for U-Boot */ if (!strncmp(target, "spl/", 4) || !strncmp(target, "tpl/", 4)) is_spl_build = 1; diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh deleted file mode 100755 index 1a0f1509b4..0000000000 --- a/test/dm/test-dm.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -die() { - echo $1 - exit 1 -} - -NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) -make O=sandbox sandbox_config || die "Cannot configure U-Boot" -make O=sandbox -s -j${NUM_CPUS} || die "Cannot build U-Boot" -dd if=/dev/zero of=spi.bin bs=1M count=2 -echo -n "this is a test" > testflash.bin -dd if=/dev/zero bs=1M count=4 >>testflash.bin -./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb -c "ut dm" -rm spi.bin -rm testflash.bin diff --git a/test/dm/video.c b/test/dm/video.c index de223281b4..4d000fa1be 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -249,9 +249,9 @@ static int read_file(struct unit_test_state *uts, const char *fname, fd = os_open(fname, OS_O_RDONLY); ut_assert(fd >= 0); size = os_read(fd, buf, buf_size); + os_close(fd); ut_assert(size >= 0); ut_assert(size < buf_size); - os_close(fd); *addrp = addr; return 0; diff --git a/test/py/README.md b/test/py/README.md index 8036299d07..ba1674cb1d 100644 --- a/test/py/README.md +++ b/test/py/README.md @@ -76,6 +76,43 @@ will be written to `${build_dir}/test-log.html`. This is best viewed in a web browser, but may be read directly as plain text, perhaps with the aid of the `html2text` utility. +### Testing under a debugger + +If you need to run sandbox under a debugger, you may pass the command-line +option `--gdbserver COMM`. This causes two things to happens: + +- Instead of running U-Boot directly, it will be run under gdbserver, with + debug communication via the channel `COMM`. You can attach a debugger to the + sandbox process in order to debug it. See `man gdbserver` and the example + below for details of valid values for `COMM`. +- All timeouts in tests are disabled, allowing U-Boot an arbitrary amount of + time to execute commands. This is useful if U-Boot is stopped at a breakpoint + during debugging. + +A usage example is: + +Window 1: +```shell +./test/py/test.py --bd sandbox --gdbserver localhost:1234 +``` + +Window 2: +```shell +gdb ./build-sandbox/u-boot -ex 'target remote localhost:1234' +``` + +Alternatively, you could leave off the `-ex` option and type the command +manually into gdb once it starts. + +You can use any debugger you wish, so long as it speaks the gdb remote +protocol, or any graphical wrapper around gdb. + +Some tests deliberately cause the sandbox process to exit, e.g. to test the +reset command, or sandbox's CTRL-C handling. When this happens, you will need +to attach the debugger to the new sandbox instance. If these tests are not +relevant to your debugging session, you can skip them using pytest's -k +command-line option; see the next section. + ## Command-line options - `--board-type`, `--bd`, `-B` set the type of the board to be tested. For @@ -98,10 +135,25 @@ browser, but may be read directly as plain text, perhaps with the aid of the data. This is test data that may be re-used across test runs, such as file- system images. -`pytest` also implements a number of its own command-line options. Please see -`pytest` documentation for complete details. Execute `py.test --version` for -a brief summary. Note that U-Boot's test.py script passes all command-line -arguments directly to `pytest` for processing. +`pytest` also implements a number of its own command-line options. Commonly used +options are mentioned below. Please see `pytest` documentation for complete +details. Execute `py.test --version` for a brief summary. Note that U-Boot's +test.py script passes all command-line arguments directly to `pytest` for +processing. + +- `-k` selects which tests to run. The default is to run all known tests. This + option takes a single argument which is used to filter test names. Simple + logical operators are supported. For example: + - `'ums'` runs only tests with "ums" in their name. + - ``ut_dm'` runs only tests with "ut_dm" in their name. Note that in this + case, "ut_dm" is a parameter to a test rather than the test name. The full + test name is e.g. "test_ut[ut_dm_leak]". + - `'not reset'` runs everything except tests with "reset" in their name. + - `'ut or hush'` runs only tests with "ut" or "hush" in their name. + - `'not (ut or hush)'` runs everything except tests with "ut" or "hush" in + their name. +- `-s` prevents pytest from hiding a test's stdout. This allows you to see + U-Boot's console log in real time on pytest's stdout. ## Testing real hardware diff --git a/test/py/conftest.py b/test/py/conftest.py index 3e162cafcc..449f98bee3 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -17,10 +17,10 @@ import atexit import errno import os import os.path -import pexpect import pytest from _pytest.runner import runtestprotocol import ConfigParser +import re import StringIO import sys @@ -71,6 +71,9 @@ def pytest_addoption(parser): help='U-Boot board identity/instance') parser.addoption('--build', default=False, action='store_true', help='Compile U-Boot before running tests') + parser.addoption('--gdbserver', default=None, + help='Run sandbox under gdbserver. The argument is the channel '+ + 'over which gdbserver should communicate, e.g. localhost:1234') def pytest_configure(config): """pytest hook: Perform custom initialization at startup time. @@ -110,6 +113,10 @@ def pytest_configure(config): persistent_data_dir = build_dir + '/persistent-data' mkdir_p(persistent_data_dir) + gdbserver = config.getoption('gdbserver') + if gdbserver and board_type != 'sandbox': + raise Exception('--gdbserver only supported with sandbox') + import multiplexed_log log = multiplexed_log.Logfile(result_dir + '/test-log.html') @@ -122,10 +129,12 @@ def pytest_configure(config): ['make', o_opt, '-s', board_type + '_defconfig'], ['make', o_opt, '-s', '-j8'], ) - runner = log.get_runner('make', sys.stdout) - for cmd in cmds: - runner.run(cmd, cwd=source_dir) - runner.close() + with log.section('make'): + runner = log.get_runner('make', sys.stdout) + for cmd in cmds: + runner.run(cmd, cwd=source_dir) + runner.close() + log.status_pass('OK') class ArbitraryAttributeContainer(object): pass @@ -169,6 +178,7 @@ def pytest_configure(config): ubconfig.persistent_data_dir = persistent_data_dir ubconfig.board_type = board_type ubconfig.board_identity = board_identity + ubconfig.gdbserver = gdbserver env_vars = ( 'board_type', @@ -189,8 +199,42 @@ def pytest_configure(config): import u_boot_console_exec_attach console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) -def pytest_generate_tests(metafunc): - """pytest hook: parameterize test functions based on custom rules. +re_ut_test_list = re.compile(r'_u_boot_list_2_(dm|env)_test_2_\1_test_(.*)\s*$') +def generate_ut_subtest(metafunc, fixture_name): + """Provide parametrization for a ut_subtest fixture. + + Determines the set of unit tests built into a U-Boot binary by parsing the + list of symbols generated by the build process. Provides this information + to test functions by parameterizing their ut_subtest fixture parameter. + + Args: + metafunc: The pytest test function. + fixture_name: The fixture name to test. + + Returns: + Nothing. + """ + + fn = console.config.build_dir + '/u-boot.sym' + try: + with open(fn, 'rt') as f: + lines = f.readlines() + except: + lines = [] + lines.sort() + + vals = [] + for l in lines: + m = re_ut_test_list.search(l) + if not m: + continue + vals.append(m.group(1) + ' ' + m.group(2)) + + ids = ['ut_' + s.replace(' ', '_') for s in vals] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def generate_config(metafunc, fixture_name): + """Provide parametrization for {env,brd}__ fixtures. If a test function takes parameter(s) (fixture names) of the form brd__xxx or env__xxx, the brd and env configuration dictionaries are consulted to @@ -199,6 +243,7 @@ def pytest_generate_tests(metafunc): Args: metafunc: The pytest test function. + fixture_name: The fixture name to test. Returns: Nothing. @@ -208,30 +253,49 @@ def pytest_generate_tests(metafunc): 'brd': console.config.brd, 'env': console.config.env, } + parts = fixture_name.split('__') + if len(parts) < 2: + return + if parts[0] not in subconfigs: + return + subconfig = subconfigs[parts[0]] + vals = [] + val = subconfig.get(fixture_name, []) + # If that exact name is a key in the data source: + if val: + # ... use the dict value as a single parameter value. + vals = (val, ) + else: + # ... otherwise, see if there's a key that contains a list of + # values to use instead. + vals = subconfig.get(fixture_name+ 's', []) + def fixture_id(index, val): + try: + return val['fixture_id'] + except: + return fixture_name + str(index) + ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def pytest_generate_tests(metafunc): + """pytest hook: parameterize test functions based on custom rules. + + Check each test function parameter (fixture name) to see if it is one of + our custom names, and if so, provide the correct parametrization for that + parameter. + + Args: + metafunc: The pytest test function. + + Returns: + Nothing. + """ + for fn in metafunc.fixturenames: - parts = fn.split('__') - if len(parts) < 2: + if fn == 'ut_subtest': + generate_ut_subtest(metafunc, fn) continue - if parts[0] not in subconfigs: - continue - subconfig = subconfigs[parts[0]] - vals = [] - val = subconfig.get(fn, []) - # If that exact name is a key in the data source: - if val: - # ... use the dict value as a single parameter value. - vals = (val, ) - else: - # ... otherwise, see if there's a key that contains a list of - # values to use instead. - vals = subconfig.get(fn + 's', []) - def fixture_id(index, val): - try: - return val["fixture_id"] - except: - return fn + str(index) - ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] - metafunc.parametrize(fn, vals, ids=ids) + generate_config(metafunc, fn) @pytest.fixture(scope='function') def u_boot_console(request): @@ -247,12 +311,13 @@ def u_boot_console(request): console.ensure_spawned() return console -tests_not_run = set() -tests_failed = set() -tests_xpassed = set() -tests_xfailed = set() -tests_skipped = set() -tests_passed = set() +anchors = {} +tests_not_run = [] +tests_failed = [] +tests_xpassed = [] +tests_xfailed = [] +tests_skipped = [] +tests_passed = [] def pytest_itemcollected(item): """pytest hook: Called once for each test found during collection. @@ -267,7 +332,7 @@ def pytest_itemcollected(item): Nothing. """ - tests_not_run.add(item.name) + tests_not_run.append(item.name) def cleanup(): """Clean up all global state. @@ -286,27 +351,33 @@ def cleanup(): if console: console.close() if log: - log.status_pass('%d passed' % len(tests_passed)) - if tests_skipped: - log.status_skipped('%d skipped' % len(tests_skipped)) - for test in tests_skipped: - log.status_skipped('... ' + test) - if tests_xpassed: - log.status_xpass('%d xpass' % len(tests_xpassed)) - for test in tests_xpassed: - log.status_xpass('... ' + test) - if tests_xfailed: - log.status_xfail('%d xfail' % len(tests_xfailed)) - for test in tests_xfailed: - log.status_xfail('... ' + test) - if tests_failed: - log.status_fail('%d failed' % len(tests_failed)) - for test in tests_failed: - log.status_fail('... ' + test) - if tests_not_run: - log.status_fail('%d not run' % len(tests_not_run)) - for test in tests_not_run: - log.status_fail('... ' + test) + with log.section('Status Report', 'status_report'): + log.status_pass('%d passed' % len(tests_passed)) + if tests_skipped: + log.status_skipped('%d skipped' % len(tests_skipped)) + for test in tests_skipped: + anchor = anchors.get(test, None) + log.status_skipped('... ' + test, anchor) + if tests_xpassed: + log.status_xpass('%d xpass' % len(tests_xpassed)) + for test in tests_xpassed: + anchor = anchors.get(test, None) + log.status_xpass('... ' + test, anchor) + if tests_xfailed: + log.status_xfail('%d xfail' % len(tests_xfailed)) + for test in tests_xfailed: + anchor = anchors.get(test, None) + log.status_xfail('... ' + test, anchor) + if tests_failed: + log.status_fail('%d failed' % len(tests_failed)) + for test in tests_failed: + anchor = anchors.get(test, None) + log.status_fail('... ' + test, anchor) + if tests_not_run: + log.status_fail('%d not run' % len(tests_not_run)) + for test in tests_not_run: + anchor = anchors.get(test, None) + log.status_fail('... ' + test, anchor) log.close() atexit.register(cleanup) @@ -372,7 +443,7 @@ def pytest_runtest_setup(item): Nothing. """ - log.start_section(item.name) + anchors[item.name] = log.start_section(item.name) setup_boardspec(item) setup_buildconfigspec(item) @@ -422,7 +493,7 @@ def pytest_runtest_protocol(item, nextitem): if failure_cleanup: console.drain_console() - test_list.add(item.name) + test_list.append(item.name) tests_not_run.remove(item.name) try: diff --git a/test/py/multiplexed_log.css b/test/py/multiplexed_log.css index f6240d52da..f135b10a24 100644 --- a/test/py/multiplexed_log.css +++ b/test/py/multiplexed_log.css @@ -25,37 +25,24 @@ pre { color: #808080; } -.section { +.block { border-style: solid; border-color: #303030; border-width: 0px 0px 0px 5px; padding-left: 5px } -.section-header { +.block-header { background-color: #303030; margin-left: -5px; margin-top: 5px; } -.section-trailer { - display: none; +.block-header:hover { + text-decoration: underline; } -.stream { - border-style: solid; - border-color: #303030; - border-width: 0px 0px 0px 5px; - padding-left: 5px -} - -.stream-header { - background-color: #303030; - margin-left: -5px; - margin-top: 5px; -} - -.stream-trailer { +.block-trailer { display: none; } @@ -94,3 +81,21 @@ pre { .status-fail { color: #ff0000 } + +.hidden { + display: none; +} + +a:link { + text-decoration: inherit; + color: inherit; +} + +a:visited { + text-decoration: inherit; + color: inherit; +} + +a:hover { + text-decoration: underline; +} diff --git a/test/py/multiplexed_log.py b/test/py/multiplexed_log.py index 69a577e577..68917eb0ea 100644 --- a/test/py/multiplexed_log.py +++ b/test/py/multiplexed_log.py @@ -168,12 +168,13 @@ class SectionCtxMgr(object): Objects of this type should be created by factory functions in the Logfile class rather than directly.""" - def __init__(self, log, marker): + def __init__(self, log, marker, anchor): """Initialize a new object. Args: log: The Logfile object to log to. marker: The name of the nested log section. + anchor: The anchor value to pass to start_section(). Returns: Nothing. @@ -181,9 +182,10 @@ class SectionCtxMgr(object): self.log = log self.marker = marker + self.anchor = anchor def __enter__(self): - self.log.start_section(self.marker) + self.anchor = self.log.start_section(self.marker, self.anchor) def __exit__(self, extype, value, traceback): self.log.end_section(self.marker) @@ -206,11 +208,70 @@ class Logfile(object): self.last_stream = None self.blocks = [] self.cur_evt = 1 + self.anchor = 0 + shutil.copy(mod_dir + '/multiplexed_log.css', os.path.dirname(fn)) self.f.write('''\ <html> <head> <link rel="stylesheet" type="text/css" href="multiplexed_log.css"> +<script src="http://code.jquery.com/jquery.min.js"></script> +<script> +$(document).ready(function () { + // Copy status report HTML to start of log for easy access + sts = $(".block#status_report")[0].outerHTML; + $("tt").prepend(sts); + + // Add expand/contract buttons to all block headers + btns = "<span class=\\\"block-expand hidden\\\">[+] </span>" + + "<span class=\\\"block-contract\\\">[-] </span>"; + $(".block-header").prepend(btns); + + // Pre-contract all blocks which passed, leaving only problem cases + // expanded, to highlight issues the user should look at. + // Only top-level blocks (sections) should have any status + passed_bcs = $(".block-content:has(.status-pass)"); + // Some blocks might have multiple status entries (e.g. the status + // report), so take care not to hide blocks with partial success. + passed_bcs = passed_bcs.not(":has(.status-fail)"); + passed_bcs = passed_bcs.not(":has(.status-xfail)"); + passed_bcs = passed_bcs.not(":has(.status-xpass)"); + passed_bcs = passed_bcs.not(":has(.status-skipped)"); + // Hide the passed blocks + passed_bcs.addClass("hidden"); + // Flip the expand/contract button hiding for those blocks. + bhs = passed_bcs.parent().children(".block-header") + bhs.children(".block-expand").removeClass("hidden"); + bhs.children(".block-contract").addClass("hidden"); + + // Add click handler to block headers. + // The handler expands/contracts the block. + $(".block-header").on("click", function (e) { + var header = $(this); + var content = header.next(".block-content"); + var expanded = !content.hasClass("hidden"); + if (expanded) { + content.addClass("hidden"); + header.children(".block-expand").first().removeClass("hidden"); + header.children(".block-contract").first().addClass("hidden"); + } else { + header.children(".block-contract").first().removeClass("hidden"); + header.children(".block-expand").first().addClass("hidden"); + content.removeClass("hidden"); + } + }); + + // When clicking on a link, expand the target block + $("a").on("click", function (e) { + var block = $($(this).attr("href")); + var header = block.children(".block-header"); + var content = block.children(".block-content").first(); + header.children(".block-contract").first().removeClass("hidden"); + header.children(".block-expand").first().addClass("hidden"); + content.removeClass("hidden"); + }); +}); +</script> </head> <body> <tt> @@ -273,45 +334,60 @@ class Logfile(object): if not self.last_stream: return self.f.write('</pre>\n') - self.f.write('<div class="stream-trailer" id="' + - self.last_stream.name + '">End stream: ' + + self.f.write('<div class="stream-trailer block-trailer">End stream: ' + self.last_stream.name + '</div>\n') self.f.write('</div>\n') + self.f.write('</div>\n') self.last_stream = None - def _note(self, note_type, msg): + def _note(self, note_type, msg, anchor=None): """Write a note or one-off message to the log file. Args: note_type: The type of note. This must be a value supported by the accompanying multiplexed_log.css. msg: The note/message to log. + anchor: Optional internal link target. Returns: Nothing. """ self._terminate_stream() - self.f.write('<div class="' + note_type + '">\n<pre>') + self.f.write('<div class="' + note_type + '">\n') + if anchor: + self.f.write('<a href="#%s">\n' % anchor) + self.f.write('<pre>') self.f.write(self._escape(msg)) - self.f.write('\n</pre></div>\n') + self.f.write('\n</pre>\n') + if anchor: + self.f.write('</a>\n') + self.f.write('</div>\n') - def start_section(self, marker): + def start_section(self, marker, anchor=None): """Begin a new nested section in the log file. Args: marker: The name of the section that is starting. + anchor: The value to use for the anchor. If None, a unique value + will be calculated and used Returns: - Nothing. + Name of the HTML anchor emitted before section. """ self._terminate_stream() self.blocks.append(marker) + if not anchor: + self.anchor += 1 + anchor = str(self.anchor) blk_path = '/'.join(self.blocks) - self.f.write('<div class="section" id="' + blk_path + '">\n') - self.f.write('<div class="section-header" id="' + blk_path + - '">Section: ' + blk_path + '</div>\n') + self.f.write('<div class="section block" id="' + anchor + '">\n') + self.f.write('<div class="section-header block-header">Section: ' + + blk_path + '</div>\n') + self.f.write('<div class="section-content block-content">\n') + + return anchor def end_section(self, marker): """Terminate the current nested section in the log file. @@ -331,12 +407,13 @@ class Logfile(object): (marker, '/'.join(self.blocks))) self._terminate_stream() blk_path = '/'.join(self.blocks) - self.f.write('<div class="section-trailer" id="section-trailer-' + - blk_path + '">End section: ' + blk_path + '</div>\n') + self.f.write('<div class="section-trailer block-trailer">' + + 'End section: ' + blk_path + '</div>\n') + self.f.write('</div>\n') self.f.write('</div>\n') self.blocks.pop() - def section(self, marker): + def section(self, marker, anchor=None): """Create a temporary section in the log file. This function creates a context manager for Python's "with" statement, @@ -349,12 +426,13 @@ class Logfile(object): Args: marker: The name of the nested section. + anchor: The anchor value to pass to start_section(). Returns: A context manager object. """ - return SectionCtxMgr(self, marker) + return SectionCtxMgr(self, marker, anchor) def error(self, msg): """Write an error note to the log file. @@ -404,65 +482,70 @@ class Logfile(object): self._note("action", msg) - def status_pass(self, msg): + def status_pass(self, msg, anchor=None): """Write a note to the log file describing test(s) which passed. Args: msg: A message describing the passed test(s). + anchor: Optional internal link target. Returns: Nothing. """ - self._note("status-pass", msg) + self._note("status-pass", msg, anchor) - def status_skipped(self, msg): + def status_skipped(self, msg, anchor=None): """Write a note to the log file describing skipped test(s). Args: msg: A message describing the skipped test(s). + anchor: Optional internal link target. Returns: Nothing. """ - self._note("status-skipped", msg) + self._note("status-skipped", msg, anchor) - def status_xfail(self, msg): + def status_xfail(self, msg, anchor=None): """Write a note to the log file describing xfailed test(s). Args: msg: A message describing the xfailed test(s). + anchor: Optional internal link target. Returns: Nothing. """ - self._note("status-xfail", msg) + self._note("status-xfail", msg, anchor) - def status_xpass(self, msg): + def status_xpass(self, msg, anchor=None): """Write a note to the log file describing xpassed test(s). Args: msg: A message describing the xpassed test(s). + anchor: Optional internal link target. Returns: Nothing. """ - self._note("status-xpass", msg) + self._note("status-xpass", msg, anchor) - def status_fail(self, msg): + def status_fail(self, msg, anchor=None): """Write a note to the log file describing failed test(s). Args: msg: A message describing the failed test(s). + anchor: Optional internal link target. Returns: Nothing. """ - self._note("status-fail", msg) + self._note("status-fail", msg, anchor) def get_stream(self, name, chained_file=None): """Create an object to log a single stream's data into the log file. @@ -519,9 +602,10 @@ class Logfile(object): if stream != self.last_stream: self._terminate_stream() - self.f.write('<div class="stream" id="%s">\n' % stream.name) - self.f.write('<div class="stream-header" id="' + stream.name + - '">Stream: ' + stream.name + '</div>\n') + self.f.write('<div class="stream block">\n') + self.f.write('<div class="stream-header block-header">Stream: ' + + stream.name + '</div>\n') + self.f.write('<div class="stream-content block-content">\n') self.f.write('<pre>') if implicit: self.f.write('<span class="implicit">') diff --git a/test/py/test.py b/test/py/test.py index 95671d4737..74e560a4d3 100755 --- a/test/py/test.py +++ b/test/py/test.py @@ -30,3 +30,4 @@ except: print >>sys.stderr, ''' exec(py.test) failed; perhaps you are missing some dependencies? See test/py/README.md for the list.''' + sys.exit(1) diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py index 74add891c3..5c1a2623fe 100644 --- a/test/py/tests/test_sleep.py +++ b/test/py/tests/test_sleep.py @@ -15,6 +15,7 @@ def test_sleep(u_boot_console): u_boot_console.run_command('sleep %d' % sleep_time) tend = time.time() elapsed = tend - tstart - delta_to_expected = abs(elapsed - sleep_time) - # 0.25s margin is hopefully enough to account for any system overhead. - assert delta_to_expected < 0.25 + assert elapsed >= sleep_time + if not u_boot_console.config.gdbserver: + # 0.25s margin is hopefully enough to account for any system overhead. + assert elapsed < (sleep_time + 0.25) diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py new file mode 100644 index 0000000000..5c25a2d465 --- /dev/null +++ b/test/py/tests/test_ut.py @@ -0,0 +1,29 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +import os.path +import pytest + +@pytest.mark.buildconfigspec('ut_dm') +def test_ut_dm_init(u_boot_console): + """Initialize data for ut dm tests.""" + + fn = u_boot_console.config.source_dir + '/testflash.bin' + if not os.path.exists(fn): + data = 'this is a test' + data += '\x00' * ((4 * 1024 * 1024) - len(data)) + with open(fn, 'wb') as fh: + fh.write(data) + + fn = u_boot_console.config.source_dir + '/spi.bin' + if not os.path.exists(fn): + data = '\x00' * (2 * 1024 * 1024) + with open(fn, 'wb') as fh: + fh.write(data) + +def test_ut(u_boot_console, ut_subtest): + """Execute a "ut" subtest.""" + + output = u_boot_console.run_command('ut ' + ut_subtest) + assert output.endswith('Failures: 0') diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 392f8cb885..bc2bd767e4 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -17,8 +17,8 @@ import sys import u_boot_spawn # Regexes for text we expect U-Boot to send to the console. -pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}-[^\r\n]*)') -pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}-[^\r\n]*)') +pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))') +pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))') pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ') pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'') pattern_error_notification = re.compile('## Error: ') @@ -293,16 +293,17 @@ class ConsoleBase(object): if self.p: return try: + self.log.start_section('Starting U-Boot') self.at_prompt = False - self.log.action('Starting U-Boot') self.p = self.get_spawn() # Real targets can take a long time to scroll large amounts of # text if LCD is enabled. This value may need tweaking in the # future, possibly per-test to be optimal. This works for 'help' # on board 'seaboard'. - self.p.timeout = 30000 + if not self.config.gdbserver: + self.p.timeout = 30000 self.p.logfile_read = self.logstream - if self.config.buildconfig.get('CONFIG_SPL', False) == 'y': + if self.config.buildconfig.get('config_spl', False) == 'y': m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on console: ' + @@ -311,12 +312,7 @@ class ConsoleBase(object): if m != 0: raise Exception('Bad pattern found on console: ' + self.bad_pattern_ids[m - 1]) - signon = self.p.after - build_idx = signon.find(', Build:') - if build_idx == -1: - self.u_boot_version_string = signon - else: - self.u_boot_version_string = signon[:build_idx] + self.u_boot_version_string = self.p.after while True: m = self.p.expect([self.prompt_escaped, pattern_stop_autoboot_prompt] + self.bad_patterns) @@ -333,6 +329,8 @@ class ConsoleBase(object): self.log.error(str(ex)) self.cleanup_spawn() raise + finally: + self.log.end_section('Starting U-Boot') def cleanup_spawn(self): """Shut down all interaction with the U-Boot instance. diff --git a/test/py/u_boot_console_exec_attach.py b/test/py/u_boot_console_exec_attach.py index 19520cb3b9..445b58dda6 100644 --- a/test/py/u_boot_console_exec_attach.py +++ b/test/py/u_boot_console_exec_attach.py @@ -35,11 +35,13 @@ class ConsoleExecAttach(ConsoleBase): # HW flow control would mean this could be infinite. super(ConsoleExecAttach, self).__init__(log, config, max_fifo_fill=16) - self.log.action('Flashing U-Boot') - cmd = ['u-boot-test-flash', config.board_type, config.board_identity] - runner = self.log.get_runner(cmd[0], sys.stdout) - runner.run(cmd) - runner.close() + with self.log.section('flash'): + self.log.action('Flashing U-Boot') + cmd = ['u-boot-test-flash', config.board_type, config.board_identity] + runner = self.log.get_runner(cmd[0], sys.stdout) + runner.run(cmd) + runner.close() + self.log.status_pass('OK') def get_spawn(self): """Connect to a fresh U-Boot instance. @@ -56,10 +58,14 @@ class ConsoleExecAttach(ConsoleBase): args = [self.config.board_type, self.config.board_identity] s = Spawn(['u-boot-test-console'] + args) - self.log.action('Resetting board') - cmd = ['u-boot-test-reset'] + args - runner = self.log.get_runner(cmd[0], sys.stdout) - runner.run(cmd) - runner.close() + try: + self.log.action('Resetting board') + cmd = ['u-boot-test-reset'] + args + runner = self.log.get_runner(cmd[0], sys.stdout) + runner.run(cmd) + runner.close() + except: + s.close() + raise return s diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py index a7263f30b8..3de0fe4a3b 100644 --- a/test/py/u_boot_console_sandbox.py +++ b/test/py/u_boot_console_sandbox.py @@ -39,7 +39,10 @@ class ConsoleSandbox(ConsoleBase): A u_boot_spawn.Spawn object that is attached to U-Boot. """ - cmd = [ + cmd = [] + if self.config.gdbserver: + cmd += ['gdbserver', self.config.gdbserver] + cmd += [ self.config.build_dir + '/u-boot', '-d', self.config.build_dir + '/arch/sandbox/dts/test.dtb' diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py index 0f52d3e945..a5f4a8e91b 100644 --- a/test/py/u_boot_spawn.py +++ b/test/py/u_boot_spawn.py @@ -56,8 +56,12 @@ class Spawn(object): finally: os._exit(255) - self.poll = select.poll() - self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR | select.POLLHUP | select.POLLNVAL) + try: + self.poll = select.poll() + self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR | select.POLLHUP | select.POLLNVAL) + except: + self.close() + raise def kill(self, sig): """Send unix signal "sig" to the child process. @@ -142,16 +146,20 @@ class Spawn(object): earliest_pi = pi if earliest_m: pos = earliest_m.start() - posafter = earliest_m.end() + 1 + posafter = earliest_m.end() self.before = self.buf[:pos] self.after = self.buf[pos:posafter] self.buf = self.buf[posafter:] return earliest_pi tnow_s = time.time() - tdelta_ms = (tnow_s - tstart_s) * 1000 - if tdelta_ms > self.timeout: - raise Timeout() - events = self.poll.poll(self.timeout - tdelta_ms) + if self.timeout: + tdelta_ms = (tnow_s - tstart_s) * 1000 + poll_maxwait = self.timeout - tdelta_ms + if tdelta_ms > self.timeout: + raise Timeout() + else: + poll_maxwait = None + events = self.poll.poll(poll_maxwait) if not events: raise Timeout() c = os.read(self.fd, 1024) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 39f733376e..ee17a69016 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -34,8 +34,6 @@ #include "fw_env.h" -#include <aes.h> - #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) #define WHITESPACE(c) ((c == '\t') || (c == ' ')) @@ -105,9 +103,6 @@ static struct environment environment = { .flag_scheme = FLAG_NONE, }; -/* Is AES encryption used? */ -static int aes_flag; -static uint8_t aes_key[AES_KEY_LENGTH] = { 0 }; static int env_aes_cbc_crypt(char *data, const int enc); static int HaveRedundEnv = 0; @@ -125,7 +120,6 @@ static int parse_config (void); #if defined(CONFIG_FILE) static int get_config (char *); -static char *config_file = CONFIG_FILE; #endif static inline ulong getenvsize (void) { @@ -134,7 +128,7 @@ static inline ulong getenvsize (void) if (HaveRedundEnv) rc -= sizeof (char); - if (aes_flag) + if (common_args.aes_flag) rc &= ~(AES_KEY_LENGTH - 1); return rc; @@ -208,7 +202,7 @@ char *fw_getdefenv(char *name) return NULL; } -static int parse_aes_key(char *key) +int parse_aes_key(char *key, uint8_t *bin_key) { char tmp[5] = { '0', 'x', 0, 0, 0 }; unsigned long ul; @@ -230,11 +224,9 @@ static int parse_aes_key(char *key) "## Error: '-a' option requires valid AES key\n"); return -1; } - aes_key[i] = ul & 0xff; + bin_key[i] = ul & 0xff; key += 2; } - aes_flag = 1; - return 0; } @@ -245,39 +237,12 @@ static int parse_aes_key(char *key) int fw_printenv (int argc, char *argv[]) { char *env, *nxt; - int i, n_flag; - int rc = 0; - -#ifdef CONFIG_FILE - if (argc >= 2 && strcmp(argv[1], "-c") == 0) { - if (argc < 3) { - fprintf(stderr, - "## Error: '-c' option requires the config file to use\n"); - return -1; - } - config_file = argv[2]; - argv += 2; - argc -= 2; - } -#endif - - if (argc >= 2 && strcmp(argv[1], "-a") == 0) { - if (argc < 3) { - fprintf(stderr, - "## Error: '-a' option requires AES key\n"); - return -1; - } - rc = parse_aes_key(argv[2]); - if (rc) - return rc; - argv += 2; - argc -= 2; - } + int i, rc = 0; if (fw_env_open()) return -1; - if (argc == 1) { /* Print all env variables */ + if (argc == 0) { /* Print all env variables */ for (env = environment.data; *env; env = nxt + 1) { for (nxt = env; *nxt; ++nxt) { if (nxt >= &environment.data[ENV_SIZE]) { @@ -292,20 +257,13 @@ int fw_printenv (int argc, char *argv[]) return 0; } - if (strcmp (argv[1], "-n") == 0) { - n_flag = 1; - ++argv; - --argc; - if (argc != 2) { - fprintf (stderr, "## Error: " - "`-n' option requires exactly one argument\n"); - return -1; - } - } else { - n_flag = 0; + if (printenv_args.name_suppress && argc != 1) { + fprintf(stderr, + "## Error: `-n' option requires exactly one argument\n"); + return -1; } - for (i = 1; i < argc; ++i) { /* print single env variables */ + for (i = 0; i < argc; ++i) { /* print single env variables */ char *name = argv[i]; char *val = NULL; @@ -320,7 +278,7 @@ int fw_printenv (int argc, char *argv[]) } val = envmatch (name, env); if (val) { - if (!n_flag) { + if (!printenv_args.name_suppress) { fputs (name, stdout); putc ('=', stdout); } @@ -340,7 +298,7 @@ int fw_printenv (int argc, char *argv[]) int fw_env_close(void) { int ret; - if (aes_flag) { + if (common_args.aes_flag) { ret = env_aes_cbc_crypt(environment.data, 1); if (ret) { fprintf(stderr, @@ -496,43 +454,14 @@ int fw_env_write(char *name, char *value) */ int fw_setenv(int argc, char *argv[]) { - int i, rc; + int i; size_t len; - char *name; + char *name, **valv; char *value = NULL; + int valc; -#ifdef CONFIG_FILE - if (argc >= 2 && strcmp(argv[1], "-c") == 0) { - if (argc < 3) { - fprintf(stderr, - "## Error: '-c' option requires the config file to use\n"); - return -1; - } - config_file = argv[2]; - argv += 2; - argc -= 2; - } -#endif - - if (argc < 2) { - errno = EINVAL; - return -1; - } - - if (strcmp(argv[1], "-a") == 0) { - if (argc < 3) { - fprintf(stderr, - "## Error: '-a' option requires AES key\n"); - return -1; - } - rc = parse_aes_key(argv[2]); - if (rc) - return rc; - argv += 2; - argc -= 2; - } - - if (argc < 2) { + if (argc < 1) { + fprintf(stderr, "## Error: variable name missing\n"); errno = EINVAL; return -1; } @@ -542,14 +471,16 @@ int fw_setenv(int argc, char *argv[]) return -1; } - name = argv[1]; + name = argv[0]; + valv = argv + 1; + valc = argc - 1; - if (env_flags_validate_env_set_params(argc, argv) < 0) + if (env_flags_validate_env_set_params(name, valv, valc) < 0) return 1; len = 0; - for (i = 2; i < argc; ++i) { - char *val = argv[i]; + for (i = 0; i < valc; ++i) { + char *val = valv[i]; size_t val_len = strlen(val); if (value) @@ -1023,7 +954,7 @@ static int env_aes_cbc_crypt(char *payload, const int enc) uint32_t aes_blocks; /* First we expand the key. */ - aes_expand_key(aes_key, key_exp); + aes_expand_key(common_args.aes_key, key_exp); /* Calculate the number of AES blocks to encrypt. */ aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH); @@ -1251,7 +1182,7 @@ int fw_env_open(void) crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE); - if (aes_flag) { + if (common_args.aes_flag) { ret = env_aes_cbc_crypt(environment.data, 0); if (ret) return ret; @@ -1308,7 +1239,7 @@ int fw_env_open(void) crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE); - if (aes_flag) { + if (common_args.aes_flag) { ret = env_aes_cbc_crypt(redundant->data, 0); if (ret) return ret; @@ -1392,9 +1323,9 @@ static int parse_config () #if defined(CONFIG_FILE) /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ - if (get_config (config_file)) { - fprintf (stderr, - "Cannot parse config file '%s': %s\n", config_file, strerror (errno)); + if (get_config(common_args.config_file)) { + fprintf(stderr, "Cannot parse config file '%s': %m\n", + common_args.config_file); return -1; } #else diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h index 60c05177ff..57149e733b 100644 --- a/tools/env/fw_env.h +++ b/tools/env/fw_env.h @@ -5,6 +5,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <aes.h> +#include <stdint.h> + /* Pull in the current config to define the default environment */ #include <linux/kconfig.h> @@ -54,6 +57,27 @@ "bootm" #endif +struct common_args { +#ifdef CONFIG_FILE + char *config_file; +#endif + uint8_t aes_key[AES_KEY_LENGTH]; + int aes_flag; /* Is AES encryption used? */ +}; +extern struct common_args common_args; + +struct printenv_args { + int name_suppress; +}; +extern struct printenv_args printenv_args; + +struct setenv_args { + char *script_file; +}; +extern struct setenv_args setenv_args; + +int parse_aes_key(char *key, uint8_t *bin_key); + extern int fw_printenv(int argc, char *argv[]); extern char *fw_getenv (char *name); extern int fw_setenv (int argc, char *argv[]); diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 234c061544..4bd4216625 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -36,119 +36,226 @@ #include <unistd.h> #include "fw_env.h" -#define CMD_PRINTENV "fw_printenv" +#define CMD_PRINTENV "fw_printenv" #define CMD_SETENV "fw_setenv" +static int do_printenv; static struct option long_options[] = { - {"script", required_argument, NULL, 's'}, + {"aes", required_argument, NULL, 'a'}, + {"config", required_argument, NULL, 'c'}, {"help", no_argument, NULL, 'h'}, + {"script", required_argument, NULL, 's'}, + {"noheader", required_argument, NULL, 'n'}, {NULL, 0, NULL, 0} }; -void usage(void) +struct common_args common_args; +struct printenv_args printenv_args; +struct setenv_args setenv_args; + +void usage_printenv(void) { - fprintf(stderr, "fw_printenv/fw_setenv, " - "a command line interface to U-Boot environment\n\n" -#ifndef CONFIG_FILE - "usage:\tfw_printenv [-a key] [-n] [variable name]\n" - "\tfw_setenv [-a key] [variable name] [variable value]\n" -#else - "usage:\tfw_printenv [-c /my/fw_env.config] [-a key] [-n] [variable name]\n" - "\tfw_setenv [-c /my/fw_env.config] [-a key] [variable name] [variable value]\n" + fprintf(stderr, + "Usage: fw_printenv [OPTIONS]... [VARIABLE]...\n" + "Print variables from U-Boot environment\n" + "\n" + " -h, --help print this help.\n" +#ifdef CONFIG_ENV_AES + " -a, --aes aes key to access environment\n" +#endif +#ifdef CONFIG_FILE + " -c, --config configuration file, default:" CONFIG_FILE "\n" +#endif + " -n, --noheader do not repeat variable name in output\n" + "\n"); +} + +void usage_setenv(void) +{ + fprintf(stderr, + "Usage: fw_setenv [OPTIONS]... [VARIABLE]...\n" + "Modify variables in U-Boot environment\n" + "\n" + " -h, --help print this help.\n" +#ifdef CONFIG_ENV_AES + " -a, --aes aes key to access environment\n" +#endif +#ifdef CONFIG_FILE + " -c, --config configuration file, default:" CONFIG_FILE "\n" #endif - "\tfw_setenv -s [ file ]\n" - "\tfw_setenv -s - < [ file ]\n\n" - "The file passed as argument contains only pairs " - "name / value\n" - "Example:\n" - "# Any line starting with # is treated as comment\n" + " -s, --script batch mode to minimize writes\n" + "\n" + "Examples:\n" + " fw_setenv foo bar set variable foo equal bar\n" + " fw_setenv foo clear variable foo\n" + " fw_setenv --script file run batch script\n" "\n" - "\t netdev eth0\n" - "\t kernel_addr 400000\n" - "\t var1\n" - "\t var2 The quick brown fox jumps over the " - "lazy dog\n" + "Script Syntax:\n" + " key [space] value\n" + " lines starting with '#' are treated as commment\n" "\n" - "A variable without value will be dropped. It is possible\n" - "to put any number of spaces between the fields, but any\n" - "space inside the value is treated as part of the value " - "itself.\n\n" - ); + " A variable without value will be deleted. Any number of spaces are\n" + " allowed between key and value. Space inside of the value is treated\n" + " as part of the value itself.\n" + "\n" + "Script Example:\n" + " netdev eth0\n" + " kernel_addr 400000\n" + " foo empty empty empty empty empty empty\n" + " bar\n" + "\n"); } -int main(int argc, char *argv[]) +static void parse_common_args(int argc, char *argv[]) { - char *p; - char *cmdname = *argv; - char *script_file = NULL; int c; - const char *lockname = "/var/lock/" CMD_PRINTENV ".lock"; - int lockfd = -1; - int retval = EXIT_SUCCESS; - lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666); - if (-1 == lockfd) { - fprintf(stderr, "Error opening lock file %s\n", lockname); - return EXIT_FAILURE; - } +#ifdef CONFIG_FILE + common_args.config_file = CONFIG_FILE; +#endif - if (-1 == flock(lockfd, LOCK_EX)) { - fprintf(stderr, "Error locking file %s\n", lockname); - close(lockfd); - return EXIT_FAILURE; + while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) != + EOF) { + switch (c) { + case 'a': + if (parse_aes_key(optarg, common_args.aes_key)) { + fprintf(stderr, "AES key parse error\n"); + exit(EXIT_FAILURE); + } + common_args.aes_flag = 1; + break; +#ifdef CONFIG_FILE + case 'c': + common_args.config_file = optarg; + break; +#endif + case 'h': + do_printenv ? usage_printenv() : usage_setenv(); + exit(EXIT_SUCCESS); + break; + default: + /* ignore unknown options */ + break; + } } - if ((p = strrchr (cmdname, '/')) != NULL) { - cmdname = p + 1; - } + /* Reset getopt for the next pass. */ + opterr = 1; + optind = 1; +} + +int parse_printenv_args(int argc, char *argv[]) +{ + int c; - while ((c = getopt_long (argc, argv, "a:c:ns:h", - long_options, NULL)) != EOF) { + parse_common_args(argc, argv); + + while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) != + EOF) { switch (c) { - case 'a': - /* AES key, handled later */ + case 'n': + printenv_args.name_suppress = 1; break; + case 'a': case 'c': - /* handled later */ + case 'h': + /* ignore common options */ break; - case 'n': - /* handled in fw_printenv */ + default: /* '?' */ + usage_printenv(); + exit(EXIT_FAILURE); break; + } + } + return 0; +} + +int parse_setenv_args(int argc, char *argv[]) +{ + int c; + + parse_common_args(argc, argv); + + while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) != + EOF) { + switch (c) { case 's': - script_file = optarg; + setenv_args.script_file = optarg; break; + case 'a': + case 'c': case 'h': - usage(); - goto exit; + /* ignore common options */ + break; default: /* '?' */ - fprintf(stderr, "Try `%s --help' for more information." - "\n", cmdname); - retval = EXIT_FAILURE; - goto exit; + usage_setenv(); + exit(EXIT_FAILURE); + break; } } + return 0; +} + +int main(int argc, char *argv[]) +{ + const char *lockname = "/var/lock/" CMD_PRINTENV ".lock"; + int lockfd = -1; + int retval = EXIT_SUCCESS; + char *_cmdname; + + _cmdname = *argv; + if (strrchr(_cmdname, '/') != NULL) + _cmdname = strrchr(_cmdname, '/') + 1; - if (strcmp(cmdname, CMD_PRINTENV) == 0) { + if (strcmp(_cmdname, CMD_PRINTENV) == 0) { + do_printenv = 1; + } else if (strcmp(_cmdname, CMD_SETENV) == 0) { + do_printenv = 0; + } else { + fprintf(stderr, + "Identity crisis - may be called as `%s' or as `%s' but not as `%s'\n", + CMD_PRINTENV, CMD_SETENV, _cmdname); + exit(EXIT_FAILURE); + } + + if (do_printenv) { + if (parse_printenv_args(argc, argv)) + exit(EXIT_FAILURE); + } else { + if (parse_setenv_args(argc, argv)) + exit(EXIT_FAILURE); + } + + /* shift parsed flags, jump to non-option arguments */ + argc -= optind; + argv += optind; + + lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666); + if (-1 == lockfd) { + fprintf(stderr, "Error opening lock file %s\n", lockname); + return EXIT_FAILURE; + } + + if (-1 == flock(lockfd, LOCK_EX)) { + fprintf(stderr, "Error locking file %s\n", lockname); + close(lockfd); + return EXIT_FAILURE; + } + + if (do_printenv) { if (fw_printenv(argc, argv) != 0) retval = EXIT_FAILURE; - } else if (strcmp(cmdname, CMD_SETENV) == 0) { - if (!script_file) { + } else { + if (!setenv_args.script_file) { if (fw_setenv(argc, argv) != 0) retval = EXIT_FAILURE; } else { - if (fw_parse_script(script_file) != 0) + if (fw_parse_script(setenv_args.script_file) != 0) retval = EXIT_FAILURE; } - } else { - fprintf(stderr, - "Identity crisis - may be called as `" CMD_PRINTENV - "' or as `" CMD_SETENV "' but not as `%s'\n", - cmdname); - retval = EXIT_FAILURE; } -exit: flock(lockfd, LOCK_UN); close(lockfd); return retval; diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c index 3d8296fc6b..832d3fef7b 100644 --- a/tools/palmtreo680/flash_u-boot.c +++ b/tools/palmtreo680/flash_u-boot.c @@ -97,7 +97,7 @@ int main(int argc, char * const argv[]) return -errsv; } printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt); - printf("U-boot will occupy %d blocks\n", num_blocks); + printf("U-Boot will occupy %d blocks\n", num_blocks); if (num_blocks > devinfo.eb_cnt) { fprintf(stderr, "Insufficient blocks on partition\n"); return -EINVAL; diff --git a/tools/patman/README b/tools/patman/README index 5bd74c4f83..e36857dede 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -138,7 +138,7 @@ is useful if your top commit is for setting up testing. How to install it ================= -The most up to date version of patman can be found in the U-boot sources. +The most up to date version of patman can be found in the U-Boot sources. However to use it on other projects it may be more convenient to install it as a standalone application. A distutils installer is included, this can be used to install patman: diff --git a/tools/tbot/README b/tools/tbot/README new file mode 100644 index 0000000000..a637a63d32 --- /dev/null +++ b/tools/tbot/README @@ -0,0 +1,185 @@ +# Copyright (c) 2016 DENX Software Engineering GmbH +# Heiko Schocher <hs@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +What is tbot ? +============== + +tbot is a tool for executing testcases on boards. +Source code found on [1] +Based on DUTS [2] +written in python + +Basic Ideas of tbot +=================== +(see also the figure: +https://github.com/hsdenx/tbot/blob/master/doc/tbot_structure.png ) + +- Virtual laboratory (VL) + VL is the basic environment that groups: + - [a number of] boards - target devices on which tbot executes testcases. + - one Lab PC + +- Test case (TC): + A piece of python code, which uses the tbot class from [1]. + Tbot provides functions for sending shell commands and parsing the + shell commands output. + Tbot waits endless for a shell commands end (detected through reading + the consoles prompt). + A TC can also call other TC-es. + + remark: + Tbot not really waits endless, for a shell commands end, instead + tbot starts a watchdog in the background, and if it triggers, tbot + ends the TC as failed. In the tbot beginning there was a lot of + timeouts / retry cases, but it turned out, that waiting endless + is robust and easy ... + +- Host PC (where tbot runs, currently only linux host tested) + must not a powerful machine (For example [3], I use a + raspberry pi for running tbot and buildbot) + +- Lab PC: + - Host PC connects through ssh to the Lab PC + -> so it is possible to test boards, which + are not at the same place as the Host PC. + (Lab PC and Host PC can be the same of course) + -> maybe we can setup a Testsystem, which does nightly + U-Boot/Linux builds and test from current mainline U-Boot + on boards wherever they are accessible. + + - necessary tasks a Lab PC must deliver: + - connect to boards console through a shell command. + - power on/off boards through a shell command + - detect the current power state of a board through + a shell command + + - optional tasks: + - tftp server (for example loading images) + - nfs server (used as rootfs for linux kernels) + - Internet access for example for downloading + U-Boot source with git. + - toolchains installed for compiling source code + + -> a linux machine is preffered. + + - currently only Lab PC with an installed linux supported/tested. + +- Boards(s): + the boards on which shell commands are executed. + +- Board state: + equals to the software, the board is currently running. + + Currently tbot supports 2 board states: + - "u-boot", if the board is running U-Boot + - "linux", if the board is running a linux kernel + + It should be easy to add other board states to tbot, see + https://github.com/hsdenx/tbot/tree/master/src/lab_api/state_[u-boot/linux].py + + A board state is detected through analysing the boards + shell prompt. In linux, tbot sets a special tbot prompt, + in U-Boot the prompt is static, and configurable in tbot through + a board config file. + + A TC can say in which board state it want to send shell commands. + Tbot tries to detect the current board state, if board is not in + the requested board state, tbot tries to switch into the correct + state. If this fails, the TC fails. + + It is possible to switch in a single TC between board states. + +- tbot cmdline parameters: + +$ python2.7 src/common/tbot.py --help +Usage: tbot.py [options] + +Options: + -h, --help show this help message and exit + -c CFGFILE, --cfgfile=CFGFILE + the tbot common configfilename + -l LOGFILE, --logfile=LOGFILE + the tbot logfilename, if default, tbot creates a + defaultnamelogfile + -t TC, --testcase=TC the testcase which should be run + -v, --verbose be verbose, print all read/write to stdout + -w WORKDIR, --workdir=WORKDIR + set workdir, default os.getcwd() +$ + +tbot needs the following files for proper execution: + + - tbot board configuration file (option -c): + A board configuration file contains settings tbot needs to + connect to the Lab PC and board specific variable settings + for testcases. + + - name of the logfile tbot creates (option -l) + defaultname: 'log/' + now.strftime("%Y-%m-%d-%H-%M") + '.log' + + - tbots working directory (option -w) + + - the testcasename tbot executes (option -t) + +You are interested and want to use tbot? +If so, please read on the file: +tools/tbot/README.install + +If not read [3] ;-) + +Heiko Schocher <hs@denx.de> +v1 2016.01.22 + +-------------- +[1] https://github.com/hsdenx/tbot +[2] http://www.denx.de/wiki/DUTS/DUTSDocs +[3] automated Testsetup with buildbot and tbot doing cyclic tests + (buildbot used for starting tbot TC and web presentation of the + results, all testing done through tbot): + http://xeidos.ddns.net/buildbot/tgrid + Host PC in Letkes/hungary + VL in munich/germany + + Fancy things are done here, for example: + - http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/43/steps/shell/logs/tbotlog + (I try to cleanup the logfile soon, so it is not so filled with crap ;-) + A first step see here: + http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/45/steps/shell/logs/tbotlog + (same TC now with the new loglevel = 'CON' ... not yet perfect) + Executed steps: + - clone u-boot.git + - set toolchain + - get a list of patchwork patches from my U-Boots ToDo list + - download all of them, and check them with checkpatch + and apply them to u-boot.git + - compile U-Boot for the smartweb board + - install the resulting images on the smartweb board + - boot U-boot + - test DFU + - more TC should be added here for testing U-Boot + + - automatic "git bisect" + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_board_git_bisect.py + http://xeidos.ddns.net/buildbot/builders/tqm5200s/builds/3/steps/shell/logs/tbotlog + + If a current U-Boot image not works on the tqm5200 board + this TC can be started. It starts a "git bisect" session, + and compiles for each step U-Boot, install it on the tqm5200 + board, and tests if U-Boot works ! + + At the end, it detects the commit, which breaks the board + + This TC is not dependend on U-Boot nor on a special board. It + needs only 3 variables: + tb.board_git_bisect_get_source_tc: TC which gets the source tree, in which + "git bisect" should be executed + tb.board_git_bisect_call_tc: TC which gets called every "git bisect" step, + which executes commands for detecting if current source code is OK or not. + This could be a TC which compiles U-Boot, install it on the board and + executes TC on the new booted U-Boot image. ! Board maybe gets borken, + as not all U-Boot images work, so you must have a TC which install U-Boot + image for example through a debugger. + tb.board_git_bisect_good_commit: last nown good commit id diff --git a/tools/tbot/README-ToDo b/tools/tbot/README-ToDo new file mode 100644 index 0000000000..daf1af1323 --- /dev/null +++ b/tools/tbot/README-ToDo @@ -0,0 +1,62 @@ +# Copyright (c) 2016 DENX Software Engineering GmbH +# Heiko Schocher <hs@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ToDo list for tbot +================== + +please look also into the tbot ToDo list. +https://github.com/hsdenx/tbot/blob/master/ToDo + +- cleanup tbot code: + - remove all retry / timeout pieces of code + - clean up tbot function names, as I am not good in + giving function a understandable name ;-) + - as I am not a python programmer, cleanup whole tbot code + +- introduce a "layering" like yocto do, so U-Boot TC can integrated + into U-Boot source code. + + Proposal: + introduce subdirs in "src/tc" + + lab: all lab specific stuff + lab/common: common lab stuff (for example ssh handling) + lab/ssh_std: ssh_std specific stuff + + u-boot: all u-boot tests + u-boot/common: common u-boot tc + u-boot/duts: DUTS tc + u-boot-dxr2: all u-boot dxr2 board specific tc + + board: board tc + board/common: common board tc + board/dxr2: all tc for dxr2 board + + linux: all linux tc + linux/common: common linux tc + linux/dxr2 + + - move U-Boot special TC to U-Boot source + -> need a mechanism in tbot, how it gets automatically for example + U-Boot TC from U-Boot source... + -> add a consistency checker + +- simplify tbot log output (seperate a lot of output which is currently + in INFO logging level, to another logging level) + started (new loglevel "CON", whih prints read/write from console only), see: + https://github.com/hsdenx/tbot/commit/b4ab2567ad8c19ad53f785203159d3c8465a21c6 + - make the timestamp configurable + +- Open more than 2 filehandles ? + Do we need for more complex TC more than 2 filehandles? + +- Find a way to document all TC and document all variables they use in an + automated way. + +- write a lot of more TC + +- get U-Boot configuration settings from current U-Boot code and use + them in U-Boot TC-es diff --git a/tools/tbot/README.create_a_new_testcase b/tools/tbot/README.create_a_new_testcase new file mode 100644 index 0000000000..fbf8ae8329 --- /dev/null +++ b/tools/tbot/README.create_a_new_testcase @@ -0,0 +1,117 @@ +# Copyright (c) 2016 DENX Software Engineering GmbH +# Heiko Schocher <hs@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +write a new testcase +===================== + +A TC is written in python, so you can use python as usual. For accessing +the boards console, use functions from the tbotlib, therefore + +First import the tbotlib with the line: + + from tbotlib import tbot + +If your TC uses variables, please add a line which adds them to +the log file (for debugging purposes): + + logging.info("args: %s ...", tb.varname, ...) + +Say tbot, for which board state your TC is valid with: + + tb.set_board_state("u-boot") + +Then you are ready ... and you can use the tbotlib funtions +for writting/reading to the boards console. + +Big fat warning: + +A TC must worry about to end only if a board has finished the shell +command! + +Not following this rule, will end in unpredictable behaviour. + +(hopefully) useful tbotlib functions +==================================== +- set the board state, you want to test + tb.set_board_state(state) + states are: "u-boot" or "linux" + If tbot could not set the board state, tbot ends with failure. + +- write a command to the boards console: + tb.eof_write_con(command): + write the command to the boards console. If this + fails, tbot ends with failure + +- write a command to boards console and wait for prompt: + tb.eof_write_cmd(fd, command): + fd: filedescriptor which is used, use tb.channel_con for boards console + command: command which is written to fd + + Wait endless for board prompt + +- write a list of commands to boards console: + tb.eof_write_cmd_list(fd, cmdlist): + fd: filedescriptor which is used, use tb.channel_con for boards console + cmdlist: python list of commandstrings which is written to fd + +- wait for boards prompt: + tb.eof_read_end_state_con(retry): + retry: deprecated, not used anymore, cleanup needed here... + tbot waits endless for the boards prompt + +- write a command, wait for prompt and check, if a string is read + tb.write_cmd_check(fd, cmd, string): + fd: filedescriptor which is used, use tb.channel_con for boards console + cmd: command, which is send to fd + string: string which should be read from fd + + return value: + True, if string is read and tbot got back boards prompt + False, else + + tb.eof_write_cmd_check(fd, cmd, string): + same as tb.write_cmd_check(fd, cmd, string) except, that tbot + ends immediately with Failure, if string is not read. + +- read until prompt and search strings: + tb.readline_and_search_strings(fd, strings): + fd: filedescriptor which is used, use tb.channel_con for boards console + strings: python list of strings, which can be read + If one of this strings is read, this function return the index, which + string is read. This function shoud be called in a while loop, + until this function returns 'prompt' + +- read a line from filedescriptor: + not recommended to use, as the TC must check, if tprompt is read for every + readen line. Also TC must ensure, that it ends only, if prompt is read. + tb.read_line(fd, retry) + fd: filedescriptor which is used, use tb.channel_con for boards console + retry: retry of trying to reead a line + + return values: + True, if a line is read. Readen line in tb.buf[fd] + False, if something read, but not a complete line + None, if nothing is read + + check if string contains prompt with: + tb.is_end_fd(fd, string) + fd: filedescriptor which is used, use tb.channel_con for boards console + string: buffer, in which a prompt gets searched. + +- calling other TC: + eof_call_tc(name): + call another TC from "src/tc" + if the called TC fails with failure, tbot ends with failure + + call_tc(name): + call another TC from "src/tc" + if the TC which call_tc calls fails, call_tc() returns False, else True + +There are more functions, but for writting TC this should be enough. But +its software, so new useful functions can always pop up. + +Heiko Schocher <hs@denx.de> +v1 2016.01.23 diff --git a/tools/tbot/README.install b/tools/tbot/README.install new file mode 100644 index 0000000000..24c67bc661 --- /dev/null +++ b/tools/tbot/README.install @@ -0,0 +1,370 @@ +# Copyright (c) 2016 DENX Software Engineering GmbH +# Heiko Schocher <hs@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +install tbot on your PC (linux only tested): +============================================ + +- get the source code: + +$ git clone https://github.com/hsdenx/tbot.git +[...] +$ + + cd into the tbot directory. + +- you need the for running tbot the python paramiko module, see: + http://www.paramiko.org/installing.html + + paramiko is used for handling ssh sessions, and open filedescriptors + on a ssh connection. Tbot open a ssh connection to a "lab PC" and + opens on that connection 2 filehandles, one for control functions + and one for the connection to the boards console. May it is worth + to think about to open more filehandles and use them in tbot, but + thats a point in the Todo list ... + + See [1] for more infos about tbot principles. + +- prepare a directory for storing the logfiles + and pass it with the commandline option "-l" + to tbot. Default is the directory "log" in the tbot + root (don;t forget to create it, if you want to use it) + +- If your VL is not yet in tbot source, integrate it + (This task has only to be done once for your VL): + + A VL has, as described in [2] "necessary tasks for a Lab PC" explained, + 3 tasks: + + a) power on/off the board + b) get power state of the board + c) connect to the boards console + + As tbot sends only shell commands (also to the Lab PC) + this tasks must be executable through shell commands on your + Lab PC: + + Task a) power on/off board: + default TC for this task is: + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_power.py + + - now copy this file to for example + cp src/tc/tc_lab_denx_power.py src/tc/tc_lab_denx_power_XXX.py + (replace XXX to a proper value) + and adapt the "remote_power" command from the denx lab to your needs. + + As this TC powers on the board for all your boards in your VL, + you can differ between the boards through the tbot class + variable "tb.boardlabpowername" (which is in the default case the + same as "tb.boardname"), but you may need to name the power target + with an other name than boardname, so you can configure this case. + The power state "tb.power_state" which the TC has to set + is "on" for power on, or "off" for power off. + + If switching on the power is successful, call "tb.end_tc(True)" + else "tb.end_tc(False)" + + - set in your board config file: + self.tc_lab_denx_power_tc = 'tc_lab_denx_power_XXX.py' + + Task b) power on/off board: + default TC for this task is: + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_get_power_state.py + + - now copy this file to for example + (replace XXX to a proper value) + cp src/tc/tc_lab_denx_get_power_state.py src/tc/tc_lab_denx_get_power_state_XXX.py + and adapt the commands to your needs. + + If the power of the board is on, call "tb.end_tc(True)" + else "tb.end_tc(False)" + + - set in your board config file: + self.tc_lab_denx_get_power_state_tc = 'tc_lab_denx_get_power_state_XXX.py' + + Task c) connect to the boards console: + default TC for this task is: + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_connect_to_board.py + + - now copy this file to for example + (replace XXX to a proper value) + cp src/tc/tc_lab_denx_connect_to_board.py src/tc/tc_lab_denx_connect_to_board_XXX.py + and adapt the commands to your needs. + + As this TC powers on the board for all your boards in your VL, + you can differ between the boards through the tbot class + variable "tb.boardlabname" (which is in the default case the + same as "tb.boardname"), but you may need to name the power target + with an other name than boardname, so you can configure this case. + + If connect fails end this TC with "tb.end_tc(False)" + else call "tb.end_tc(True)" + + If you want to use kermit for connecting to the boards console, you + can use: + + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_workfd_connect_with_kermit.py + + Example for such a board in the VL from denx: + self.tc_lab_denx_connect_to_board_tc = 'tc_workfd_connect_with_kermit.py' + https://github.com/hsdenx/tbot/blob/master/tbot_dxr2.cfg#L24 + + Hopefully this works for you too. + + - set in your board config file: + self.tc_lab_denx_connect_to_board_tc = 'tc_lab_denx_connect_to_board_XXX.py' + + remarks while writting this: + - Currently there is only the denx VL. Original idea was to include + other VL through a seperate class/file in + https://github.com/hsdenx/tbot/tree/master/src/lab_api + but it turned out, that if we say "ssh" is the standard way to connect + to a VL, we can integrate the VL specific tasks through testcases, see + above, so we should do: + - rename the "denx" API to a more general name. + This is a point on my ToDo list ... done, renamed to 'ssh_std' + + - the VL specific configuration may moved from the board config files + and should be collected in VL specific config files, which boards + config file simple include. + +- prepare password.py file: + This file contains all passwords tbot needs (for example for + linux login on the boards) + tbot searches this file in the tbot root directory. + It is a simple python file, for example: + + # passwords for the lab + if (board == 'lab'): + if (user == 'hs'): + password = 'passwordforuserhs' + if (user == 'root'): + password = 'passwordforrootuser' + # passwords for the boards + elif (board == 'mcx'): + if (user == 'root'): + password = 'passwordformcxrootfs' + else: + if (user == 'root'): + password = '' + + In the above example passwords for logging into the Lab PC tbot finds + through: + if (board == 'lab'): + user = 'name': + password = 'gnlmpf' # password 'gnlmpf' for login of user 'name' + +- prepare board config file + Each board which is found in the VL needs a tbot configuration file + pass the config file name with the option '-c' to tbot, tbot searches + in the root dir for them. + + board Example (dxr2 board): + https://github.com/hsdenx/tbot/blob/master/tbot_dxr2.cfg + + Necessary variables: + + line 3: boardname, here it is the "etamin" board + no default value, must be set. + line 4: boardlabname: name used for connecting to the board + may differ from tb.boardname, default tb.boardname + line 5: boardlabpowername: name used for power on/off + may differ from tb.boardname, default tb.boardname + line 6: tftpboardname: name used for tftp subdir (from where + U-Boot loads images for example). + may differ from tb.boardname, default tb.boardname + line 7: labprompt: linux prompt tbot sets + no defaultvalue, must be set (maybe we should introduce + "ttbott" as default ... + line 8: debug: If True, adds debug output on the tbot shell + line 9: debugstatus: enable status debug output on the shell + line 10: ip: Where tbot finds the Lab PC + line 11: user: As which user does tbot logs into the Lab PC + line 12: accept_all: passed to paramiko, accept all connections + line 13: keepalivetimout: passed to paramiko, timeout for sending + keepalive message. + line 14: channel_timeout: passed to paramiko + line 15: loglevel: tbots loglevel for adding entries into the logfile. + line 16: lap_api: used lap API (currently only 'ssh_std') + Should be declared as standard -> this line would be not needed + longer. + line 17: wdt_timeout: timeout in seconds for tbots watchdog. + Watchdog gets triggered if prompt get read. + line 20,21: include 'ssh_std' api + should be removed. + line 24: tc_lab_denx_connect_to_board_tc: Which TC is used for + connecting to the boards console the TC, here: + https://github.com/hsdenx/tbot/blob/master/src/tc/tc_workfd_connect_with_kermit.py + line 27: uboot_prompt: boards U-Boot prompt + line 28: linux_prompt: boards linux prompt + + Now comes a list of variables TC needs, this vary from which TC + you start on the board. + +Thats it ... you now can call tbot and hopefully, it works ;-) +Find an example log [3] for calling simple U-Boot TC for setting +an U-Boot Environmentvariable. + +If you have problems in setting tbot up, please contact me +(and may give me ssh access to your Lab PC ;-) + +If you have running your first TC [3], you may want to write now your own +TC (and hopefully share them), so continue with: +u-boot:tools/tbot/README.create_a_new_testcase + +Heiko Schocher <hs@denx.de> +v1 2016.01.22 + +-------------- + +[1] tbot Dokumentation: + [2] u-boot:/tools/tbot/README + https://github.com/hsdenx/tbot/blob/master/README.md + +[3] Example for a first U-Boot TC which should always work: + (with commandline option "-v" for verbose output): + +hs@localhost:tbot [master] $ python2.7 src/common/tbot.py -c tbot_dxr2.cfg -t tc_ub_setenv.py -v -l log/tbot.log +**** option cfg: tbot_dxr2.cfg log: log/tbot.log tc: tc_ub_setenv.py v 1 +('CUR WORK PATH: ', '/home/hs/data/Entwicklung/tbot') +('CFGFILE ', 'tbot_dxr2.cfg') +('LOGFILE ', '/home/hs/data/Entwicklung/tbot/log/tbot.log') +(<denx.tbot_lab_api object at 0x7f53ac1808d0>, <tbotlib.tbot object at 0x7f53a45fd410>, True) +(<denx.tbot_lab_api object at 0x7f53ac1808d0>, <tbotlib.tbot object at 0x7f53a45fd410>, True) +read 0: Last login: Fri Jan 22 12:20:12 2016 from 87.97.28.177 +read 0: +read 0: ************************************************************* +read 0: BDI2000 Assignment: (last updated: 2015-11-20 12:30 MET) +read 0: bdi1 => techem bdi2 => cetec_mx25 bdi3 => lpc3250 +read 0: bdi4 => - bdi5 => --Rev.B!-- bdi6 => tqm5200s +read 0: bdi7 => [stefano] bdi8 => smartweb bdi9 => sigmatek-nand +read 0: bdi10 => pcm052 bdi11 => socrates bdi12 => aristainetos +read 0: bdi13 => imx53 bdi14 => ib8315 bdi15 => cairo +read 0: bdi16 => g2c1 bdi17 => lwe090 bdi18 => symphony +read 0: bdi19 => dxr2 bdi20 => ima3-mx6 bdi21 => sama5d3 +read 0: bdi98 => - bdi99 => - bdi0 => - +read 0: Please power off unused systems when you leave! Thanks, wd. +read 0: ************************************************************* +read no ret 0: +pollux:~ hs $ +write 0: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 0: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 0: hs@pollux [12:21:00] ttbott > +read 1: Last login: Fri Jan 22 12:20:59 2016 from 87.97.28.177 +read 1: +read 1: ************************************************************* +read 1: BDI2000 Assignment: (last updated: 2015-11-20 12:30 MET) +read 1: bdi1 => techem bdi2 => cetec_mx25 bdi3 => lpc3250 +read 1: bdi4 => - bdi5 => --Rev.B!-- bdi6 => tqm5200s +read 1: bdi7 => [stefano] bdi8 => smartweb bdi9 => sigmatek-nand +read 1: bdi10 => pcm052 bdi11 => socrates bdi12 => aristainetos +read 1: bdi13 => imx53 bdi14 => ib8315 bdi15 => cairo +read 1: bdi16 => g2c1 bdi17 => lwe090 bdi18 => symphony +read 1: bdi19 => dxr2 bdi20 => ima3-mx6 bdi21 => sama5d3 +read 1: bdi98 => - bdi99 => - bdi0 => - +read 1: Please power off unused systems when you leave! Thanks, wd. +read 1: ************************************************************* +read no ret 1: +pollux:~ hs $ +write 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 1: hs@pollux [12:21:02] ttbott > +write 0: remote_power dxr2 -l +read 0: hs@pollux [12:21:00] ttbott >remote_power dxr2 -l +read 0: dxr2 ON +read 0: hs@pollux [12:21:02] ttbott > +read no ret 1: +hs@pollux [12:21:02] ttbott > +write 1: ssh hs@lena +read 1: ssh hs@lena +read no ret 1: +hs@lena's password: +read 1: +read 1: Last login: Fri Jan 22 12:20:17 2016 from 192.168.1.1 +read 1: +read no ret 1: +[hs@lena ~]$ +write 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >" +read 1: hs@lena [12:21:07] ttbott > +read no ret 1: +hs@lena [12:21:07] ttbott > +write 1: stty cols 200 +read 1: stty cols 200 +read 1: hs@lena [12:21:08] ttbott > +write 1: export TERM=vt200 +read 1: hs@lena [12:21:08] ttbott >export TERM=vt200 +read 1: hs@lena [12:21:08] ttbott > +write 1: echo $COLUMNS +read 1: hs@lena [12:21:08] ttbott >echo $COLUMNS +read 1: 200 +read 1: hs@lena [12:21:08] ttbott > +write 1: kermit +read 1: hs@lena [12:21:08] ttbott >kermit +read 1: C-Kermit 8.0.211, 10 Apr 2004, for Linux +read 1: +read 1: Copyright (C) 1985, 2004, +read 1: Trustees of Columbia University in the City of New York. +read 1: Type ? or HELP for help. +read 1: +read 1: (/home/hs/) C-Kermit> +read 1: +read no ret 1: (/home/hs/) C-Kermit> +write 1: set line /dev/ttyUSB0 +read 1: set line /dev/ttyUSB0 +read 1: +read 1: (/home/hs/) C-Kermit> +write 1: set speed 115200 +read 1: +read 1: (/home/hs/) C-Kermit>set speed 115200 +read 1: /dev/ttyUSB0, 115200 bps +read 1: +read 1: (/home/hs/) C-Kermit> +write 1: set flow-control none +read 1: +read 1: (/home/hs/) C-Kermit>set flow-control none +read 1: +read 1: (/home/hs/) C-Kermit> +write 1: set carrier-watch off +read 1: +read 1: (/home/hs/) C-Kermit>set carrier-watch off +read 1: +read 1: (/home/hs/) C-Kermit> +write 1: connect +read 1: +read 1: (/home/hs/) C-Kermit>connect +read 1: Connecting to /dev/ttyUSB0, speed 115200 +read 1: +read 1: Escape character: Ctrl-\ (ASCII 28, FS): enabled +read 1: +read 1: Type the escape character followed by C to get back, +read 1: +read 1: or followed by ? to see other options. +read 1: +read 1: ---------------------------------------------------- +read no ret 1: + +write no ret 1: + +read 1: +read 1: Heiko=Schocher +read no ret 1: +U-Boot# +write no ret 1: +write no ret 1: + +read 1: <INTERRUPT> +read 1: U-Boot# +write 1: setenv Heiko Schocher +read 1: U-Boot# setenv Heiko Schocher +read no ret 1: +U-Boot# +write 1: printenv Heiko +read 1: printenv Heiko +read 1: Heiko=Schocher +read no ret 1: +U-Boot# +End of TBOT: success +hs@localhost:tbot [master] $ |
