diff options
| -rw-r--r-- | drivers/usb/host/xhci-exynos5.c | 78 | ||||
| -rw-r--r-- | include/configs/exynos5-common.h | 1 |
2 files changed, 1 insertions, 78 deletions
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index a27a79632b..251885b28b 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -179,84 +179,6 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); } -static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) -{ - clrsetbits_le32(&dwc3_reg->g_ctl, - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), - DWC3_GCTL_PRTCAPDIR(mode)); -} - -static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) -{ - /* Before Resetting PHY, put Core in Reset */ - setbits_le32(&dwc3_reg->g_ctl, - DWC3_GCTL_CORESOFTRESET); - - /* Assert USB3 PHY reset */ - setbits_le32(&dwc3_reg->g_usb3pipectl[0], - DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Assert USB2 PHY reset */ - setbits_le32(&dwc3_reg->g_usb2phycfg, - DWC3_GUSB2PHYCFG_PHYSOFTRST); - - mdelay(100); - - /* Clear USB3 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb3pipectl[0], - DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Clear USB2 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb2phycfg, - DWC3_GUSB2PHYCFG_PHYSOFTRST); - - /* After PHYs are stable we can take Core out of reset state */ - clrbits_le32(&dwc3_reg->g_ctl, - DWC3_GCTL_CORESOFTRESET); -} - -static int dwc3_core_init(struct dwc3 *dwc3_reg) -{ - u32 reg; - u32 revision; - unsigned int dwc3_hwparams1; - - revision = readl(&dwc3_reg->g_snpsid); - /* This should read as U3 followed by revision number */ - if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { - puts("this is not a DesignWare USB3 DRD Core\n"); - return -EINVAL; - } - - dwc3_core_soft_reset(dwc3_reg); - - dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); - - reg = readl(&dwc3_reg->g_ctl); - reg &= ~DWC3_GCTL_SCALEDOWN_MASK; - reg &= ~DWC3_GCTL_DISSCRAMBLE; - switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { - case DWC3_GHWPARAMS1_EN_PWROPT_CLK: - reg &= ~DWC3_GCTL_DSBLCLKGTNG; - break; - default: - debug("No power optimization available\n"); - } - - /* - * WORKAROUND: DWC3 revisions <1.90a have a bug - * where the device can fail to connect at SuperSpeed - * and falls back to high-speed mode which causes - * the device to enter a Connect/Disconnect loop - */ - if ((revision & DWC3_REVISION_MASK) < 0x190a) - reg |= DWC3_GCTL_U2RSTECN; - - writel(reg, &dwc3_reg->g_ctl); - - return 0; -} - static int exynos_xhci_core_init(struct exynos_xhci *exynos) { int ret; diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 5476248d88..e04dec7411 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -182,6 +182,7 @@ /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE +#define CONFIG_USB_XHCI_DWC3 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
