diff options
126 files changed, 3212 insertions, 2085 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1922fb0d2c..bd073ebd28 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,6 +49,7 @@ config SYS_CPU default "armv7" if CPU_V7 default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 + default "armv8" if ARM64 choice prompt "Target select" @@ -225,9 +226,11 @@ config KIRKWOOD config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select CPU_V7 config TARGET_MAXBCM bool "Support maxbcm" + select CPU_V7 config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -630,6 +633,8 @@ config TARGET_HUMMINGBOARD config TARGET_KOSAGI_NOVENA bool "Support Kosagi Novena" + select CPU_V7 + select SUPPORT_SPL config TARGET_TBS2910 bool "Support tbs2910" @@ -779,8 +784,6 @@ config ARCH_UNIPHIER endchoice -source "arch/arm/cpu/armv8/Kconfig" - source "arch/arm/cpu/arm926ejs/davinci/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" diff --git a/arch/arm/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile deleted file mode 100644 index 3279f125f6..0000000000 --- a/arch/arm/cpu/arm_intcm/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk deleted file mode 100644 index 438668d6ff..0000000000 --- a/arch/arm/cpu/arm_intcm/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm_intcm/cpu.c b/arch/arm/cpu/arm_intcm/cpu.c deleted file mode 100644 index 0d00e4b7ae..0000000000 --- a/arch/arm/cpu/arm_intcm/cpu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for an unknown cpu - * - hence fairly empty...... - */ - -#include <common.h> -#include <command.h> - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* Since the CM has unknown processor we do not support - * cache operations - */ - - return (0); -} diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S deleted file mode 100644 index c0c07b6a11..0000000000 --- a/arch/arm/cpu/arm_intcm/start.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex ZĂĽpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <version.h> - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - - .globl reset - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - mov pc, lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* arm_int_generic assumes the ARM boot monitor, or user software, - * has initialized the platform - */ - mov pc, lr /* back to my caller */ -#endif diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a2c4032fed..0f9d8377ed 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -21,7 +21,8 @@ * to get size details from Current Cache Size ID Register(CCSIDR) */ static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; +{ + u32 csselr = level << 1 | type; /* Write to Cache Size Selection Register(CSSELR) */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) static void v7_maint_dcache_all(u32 operation) { u32 level, cache_type, level_start_bit = 0; - u32 clidr = get_clidr(); for (level = 0; level < 7; level++) { @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) } } -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; @@ -256,7 +257,6 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d869f47c88..fa3b93a257 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return clock; } +unsigned int cm_get_spi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); @@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void) printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); } int set_cpu_clk_info(void) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7cd4..73cffd3a8d 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d0c8..af9db850fe 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 82dbf764e4..3b6ae47329 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -13,6 +13,7 @@ obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o +obj-$(CONFIG_MACH_SUN6I) += p2wi.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o @@ -27,9 +28,10 @@ endif endif ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_MACH_SUN4I) += dram.o -obj-$(CONFIG_MACH_SUN5I) += dram.o -obj-$(CONFIG_MACH_SUN7I) += dram.o +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o ifdef CONFIG_SPL_FEL obj-y += start.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6c812fc6e9..9b3e80c24a 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -114,6 +114,11 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { +#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I + /* Magic (undocmented) value taken from boot0, without this DRAM + * access gets messed up (seems cache related) */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#endif #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 1eae9767d0..16ab6f3729 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -16,6 +16,33 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* Set PLL ldo voltage without this PLL6 does not work properly */ + clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_KEY); + clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); + clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); + + clock_set_pll1(408000000); + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + + writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); + writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); +} +#endif + void clock_init_uart(void) { struct sunxi_ccm_reg *const ccm = @@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state) return 0; } +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int k = 1; + int m = 1; + + if (clk > 1152000000) { + k = 2; + } else if (clk > 768000000) { + k = 3; + m = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* PLL1 rate = 24000000 * n * k / m */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll5(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int k = 2; + const int m = 1; + + /* PLL5 rate = 24000000 * n * k / m */ + writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); + + udelay(5500); +} + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index dc9fdb930b..dc9fdb930b 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file mode 100644 index 0000000000..10a62416d2 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -0,0 +1,435 @@ +/* + * Sun6i platform dram controller init. + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/prcm.h> + +/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */ +#define DRAM_CLK_DEFAULT 312000000 +#define DRAM_ZQ_DEFAULT 0x78 + +struct dram_sun6i_para { + u8 bus_width; + u8 chan; + u8 rank; + u8 rows; + u16 page_size; +}; + +/* + * Wait up to 1s for value to be set in given part of reg. + */ +static void await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int dram_clk_div = 2; + + clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, + CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | + CCM_DRAMCLK_CFG_UPD); + await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); + + /* deassert mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + else + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + + /* disable + reset dlls */ + writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); + } + udelay(2); + + /* enable + reset dlls */ + writel(0, &mctl_phy->acdllcr); + writel(0, &mctl_phy->dx0dllcr); + writel(0, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(0, &mctl_phy->dx2dllcr); + writel(0, &mctl_phy->dx3dllcr); + } + udelay(22); + + /* enable and release reset of dlls */ + writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); + } + udelay(22); +} + +static bool mctl_rank_detect(u32 *gsr0, int rank) +{ + const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; + const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; + + await_completion(gsr0, done, done); + await_completion(gsr0 + 0x10, done, done); + + return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); +} + +static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl; + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + } else { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + } + + writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); + await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); + + /* PHY initialization */ + writel(MCTL_PGCR, &mctl_phy->pgcr); + writel(MCTL_MR0, &mctl_phy->mr0); + writel(MCTL_MR1, &mctl_phy->mr1); + writel(MCTL_MR2, &mctl_phy->mr2); + writel(MCTL_MR3, &mctl_phy->mr3); + + writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, + &mctl_phy->ptr0); + /* Unknown magic performed by boot0 */ + if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2) + setbits_le32(&mctl_phy->ptr0, 1 << 18); + + writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); + writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); + + writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | + (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | + (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), + &mctl_phy->dtpr0); + + writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | + (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | + ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | + (MCTL_TAOND << 0), &mctl_phy->dtpr1); + + writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | + (MCTL_TEXSR << 0), &mctl_phy->dtpr2); + + writel(1, &mctl_ctl->dfitphyupdtype0); + writel(MCTL_DCR_DDR3, &mctl_phy->dcr); + writel(MCTL_DSGCR, &mctl_phy->dsgcr); + writel(MCTL_DXCCR, &mctl_phy->dxccr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); + + await_completion(&mctl_phy->pgsr, 0x03, 0x03); + + writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1); + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP1, &mctl_phy->pir); + udelay(10); + await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); + + /* rank detect */ + if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { + para->rank = 1; + clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); + } + + /* + * channel detect, check channel 1 dx0 and dx1 have rank 0, if not + * assume nothing is connected to channel 1. + */ + if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { + para->chan = 1; + clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + return; + } + + /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ + if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { + para->bus_width = 16; + para->page_size = 2048; + setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); + setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); + clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); + clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); + } + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP2, &mctl_phy->pir); + udelay(10); + await_completion(&mctl_phy->pgsr, 0x11, 0x11); + + if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) + panic("Training error initialising DRAM\n"); + + /* Move to configure state */ + writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); + await_completion(&mctl_ctl->sstat, 0x07, 0x01); + + /* Set number of clks per micro-second */ + writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u); + /* Set number of clks per 100 nano-seconds */ + writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n); + /* Set memory timing registers */ + writel(MCTL_TREFI, &mctl_ctl->trefi); + writel(MCTL_TMRD, &mctl_ctl->tmrd); + writel(MCTL_TRFC, &mctl_ctl->trfc); + writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); + writel(MCTL_TRTW, &mctl_ctl->trtw); + writel(MCTL_TAL, &mctl_ctl->tal); + writel(MCTL_TCL, &mctl_ctl->tcl); + writel(MCTL_TCWL, &mctl_ctl->tcwl); + writel(MCTL_TRAS, &mctl_ctl->tras); + writel(MCTL_TRC, &mctl_ctl->trc); + writel(MCTL_TRCD, &mctl_ctl->trcd); + writel(MCTL_TRRD, &mctl_ctl->trrd); + writel(MCTL_TRTP, &mctl_ctl->trtp); + writel(MCTL_TWR, &mctl_ctl->twr); + writel(MCTL_TWTR, &mctl_ctl->twtr); + writel(MCTL_TEXSR, &mctl_ctl->texsr); + writel(MCTL_TXP, &mctl_ctl->txp); + writel(MCTL_TXPDLL, &mctl_ctl->txpdll); + writel(MCTL_TZQCS, &mctl_ctl->tzqcs); + writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); + writel(MCTL_TDQS, &mctl_ctl->tdqs); + writel(MCTL_TCKSRE, &mctl_ctl->tcksre); + writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); + writel(MCTL_TCKE, &mctl_ctl->tcke); + writel(MCTL_TMOD, &mctl_ctl->tmod); + writel(MCTL_TRSTL, &mctl_ctl->trstl); + writel(MCTL_TZQCL, &mctl_ctl->tzqcl); + writel(MCTL_TMRR, &mctl_ctl->tmrr); + writel(MCTL_TCKESR, &mctl_ctl->tckesr); + writel(MCTL_TDPD, &mctl_ctl->tdpd); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); + clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); + + /* Select 16/32-bits mode for MCTL */ + if (para->bus_width == 16) + setbits_le32(&mctl_ctl->ppcfg, 1); + + /* Set DFI timing registers */ + writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); + writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); + writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); + writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); + + writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); + + /* DFI update configuration register */ + writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); + + /* Move to access state */ + writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); + await_completion(&mctl_ctl->sstat, 0x07, 0x03); +} + +static void mctl_com_init(struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy1 = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | + ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_com->dbgcr, (1 << 6)); + + if (para->chan == 1) { + /* Shutdown channel 1 */ + setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); + setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); + clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); + /* + * CH0 ?? this is what boot0 does. Leave as is until we can + * confirm this. + */ + setbits_le32(&prcm->vdd_sys_pwroff, + PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); + } +} + +static void mctl_port_cfg(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable DRAM AXI clock for CPU access */ + setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); + + /* Bunch of magic writes performed by boot0 */ + writel(0x00400302, &mctl_com->rmcr[0]); + writel(0x01000307, &mctl_com->rmcr[1]); + writel(0x00400302, &mctl_com->rmcr[2]); + writel(0x01000307, &mctl_com->rmcr[3]); + writel(0x01000307, &mctl_com->rmcr[4]); + writel(0x01000303, &mctl_com->rmcr[6]); + writel(0x01000303, &mctl_com->mmcr[0]); + writel(0x00400310, &mctl_com->mmcr[1]); + writel(0x01000307, &mctl_com->mmcr[2]); + writel(0x01000303, &mctl_com->mmcr[3]); + writel(0x01800303, &mctl_com->mmcr[4]); + writel(0x01800303, &mctl_com->mmcr[5]); + writel(0x01800303, &mctl_com->mmcr[6]); + writel(0x01800303, &mctl_com->mmcr[7]); + writel(0x01000303, &mctl_com->mmcr[8]); + writel(0x00000002, &mctl_com->mmcr[15]); + writel(0x00000310, &mctl_com->mbagcr[0]); + writel(0x00400310, &mctl_com->mbagcr[1]); + writel(0x00400310, &mctl_com->mbagcr[2]); + writel(0x00000307, &mctl_com->mbagcr[3]); + writel(0x00000317, &mctl_com->mbagcr[4]); + writel(0x00000307, &mctl_com->mbagcr[5]); +} + +static bool mctl_mem_matches(u32 offset) +{ + const int match_count = 64; + int i, matches = 0; + + for (i = 0; i < match_count; i++) { + if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) == + readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4)) + matches++; + } + + return matches == match_count; +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 offset; + int bank, bus, columns; + + /* Set initial parameters, these get modified by the autodetect code */ + struct dram_sun6i_para para = { + .bus_width = 32, + .chan = 2, + .rank = 2, + .page_size = 4096, + .rows = 16, + }; + + mctl_sys_init(); + + mctl_dll_init(0, ¶); + mctl_dll_init(1, ¶); + + setbits_le32(&mctl_com->ccr, + MCTL_CCR_MASTER_CLK_EN | + MCTL_CCR_CH0_CLK_EN | + MCTL_CCR_CH1_CLK_EN); + + mctl_channel_init(0, ¶); + mctl_channel_init(1, ¶); + mctl_com_init(¶); + mctl_port_cfg(); + + /* + * Change to 1 ch / sequence / 8192 byte pages / 16 rows / + * 8 bit banks / 1 rank mode. + */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | + MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | + MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); + + /* Detect and set page size */ + for (columns = 7; columns < 20; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + bus = (para.bus_width == 32) ? 2 : 1; + columns -= bus; + para.page_size = (1 << columns) * (bus << 1); + clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, + MCTL_CR_PAGE_SIZE(para.page_size)); + + /* Detect and set rows */ + for (para.rows = 11; para.rows < 16; para.rows++) { + offset = 1 << (para.rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(para.rows)); + + /* Detect bank size */ + offset = 1 << (para.rows + columns + bus + 2); + bank = mctl_mem_matches(offset) ? 0 : 1; + + /* Restore interleave, chan and rank values, set bank size */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | + MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | + MCTL_CR_RANK(para.rank)); + + return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); +} diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c new file mode 100644 index 0000000000..48613bd0ea --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/p2wi.c @@ -0,0 +1,117 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/p2wi.h> +#include <asm/arch/prcm.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +void p2wi_init(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA); + + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ + writel(P2WI_CTRL_RESET, &p2wi->ctrl); + sdelay(0x100); + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), + &p2wi->cc); +} + +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(P2WI_PM_DEV_ADDR(slave_addr) | + P2WI_PM_CTRL_ADDR(ctrl_reg) | + P2WI_PM_INIT_DATA(init_data) | + P2WI_PM_INIT_SEND, + &p2wi->pm); + + while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return 0; +} + +static int p2wi_await_trans(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + int ret; + u8 reg; + + while (1) { + reg = readl(&p2wi->status); + if (reg & P2WI_STAT_TRANS_ERR) { + ret = -EIO; + break; + } + if (reg & P2WI_STAT_TRANS_DONE) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(reg, &p2wi->status); /* Clear status bits */ + return ret; +} + +int p2wi_read(const u8 addr, u8 *data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + int ret; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_NUM_BYTES(1) | + P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + ret = p2wi_await_trans(); + + *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; + return ret; +} + +int p2wi_write(const u8 addr, u8 data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); + writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + return p2wi_await_trans(); +} diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 0084c811f3..b9ea78b84e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -87,8 +87,8 @@ psci_cpu_on: str r2, [r0] dsb - movw r0, #(SUNXI_CPUCFG_BASE & 0xffff) - movt r0, #(SUNXI_CPUCFG_BASE >> 16) + movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) + movt r0, #(SUN7I_CPUCFG_BASE >> 16) @ CPU mask and r1, r1, #3 @ only care about first cluster diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 3ea6d7651c..1446452c23 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,10 +20,6 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD -config SYS_CPU - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - source "arch/arm/cpu/armv7/tegra20/Kconfig" source "arch/arm/cpu/armv7/tegra30/Kconfig" source "arch/arm/cpu/armv7/tegra114/Kconfig" diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig index f418cd6d99..3a52535ce0 100644 --- a/arch/arm/cpu/armv7/zynq/Kconfig +++ b/arch/arm/cpu/armv7/zynq/Kconfig @@ -15,6 +15,9 @@ config TARGET_ZYNQ_ZC70X config TARGET_ZYNQ_ZC770 bool "Zynq ZC770 Board" +config TARGET_ZYNQ_ZYBO + bool "Zynq Zybo Board" + endchoice config SYS_BOARD @@ -31,5 +34,6 @@ config SYS_CONFIG_NAME default "zynq_microzed" if TARGET_ZYNQ_MICROZED default "zynq_zc70x" if TARGET_ZYNQ_ZC70X default "zynq_zc770" if TARGET_ZYNQ_ZC770 + default "zynq_zybo" if TARGET_ZYNQ_ZYBO endif diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig deleted file mode 100644 index 3d1655bd5c..0000000000 --- a/arch/arm/cpu/armv8/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -if ARM64 - -config SYS_CPU - default "armv8" - -endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 52f8926894..ba6dec930b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,12 +34,15 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb \ + zynq-zybo.dtb \ zynq-microzed.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000000..4472fd9268 --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000000..28c05e7a31 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 0000000000..a1814b4574 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts new file mode 100644 index 0000000000..20e0386777 --- /dev/null +++ b/arch/arm/dts/zynq-zybo.dts @@ -0,0 +1,23 @@ +/* + * Digilent ZYBO board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZYBO Board"; + compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h new file mode 100644 index 0000000000..6c61f188bc --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_GPIO_H +#define _SOCFPGA_GPIO_H + +#endif /* _SOCFPGA_GPIO_H */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 1857b80b3e..034135bff4 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); +void socfpga_spim_enable(void); struct socfpga_reset_manager { u32 status; @@ -35,5 +36,7 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_SPIM0_LSB 18 +#define RSTMGR_PERMODRST_SPIM1_LSB 19 #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 42382a8ae2..b40c16b6e7 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -25,6 +25,7 @@ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); +void clock_set_pll5(unsigned int hz); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); void clock_init_safe(void); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 90af8e2506..9dca800d78 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -262,5 +262,8 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) #define CCM_USB_CTRL_PHYGATE (0x1 << 8) +/* These 2 are sun6i only, define them as 0 on sun4i */ +#define CCM_USB_CTRL_PHY1_CLK 0 +#define CCM_USB_CTRL_PHY2_CLK 0 #endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 1397b35889..e16a7647ed 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -170,7 +170,17 @@ struct sunxi_ccm_reg { #define CPU_CLK_SRC_OSC24M 1 #define CPU_CLK_SRC_PLL1 2 -#define PLL1_CFG_DEFAULT 0x90011b21 +#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL1_CTRL_MAGIC (0x1 << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 20) +#define CCM_PLL5_CTRL_EN (0x1 << 31) #define PLL6_CFG_DEFAULT 0x90041811 @@ -179,6 +189,15 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_K_SHIFT 4 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define AHB1_ABP1_DIV_DEFAULT 0x00002020 + +#define AXI_GATE_OFFSET_DRAM 0 + +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 #define AHB_GATE_OFFSET_MMC1 9 @@ -190,6 +209,23 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_ENABLE (0x1 << 31) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ + +#define AHB_RESET_OFFSET_MCTL 14 #define AHB_RESET_OFFSET_MMC3 11 #define AHB_RESET_OFFSET_MMC2 10 #define AHB_RESET_OFFSET_MMC1 9 diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 0de79a0d50..bdee89e87d 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -37,16 +37,24 @@ #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_USB0_BASE 0x01c13000 #define SUNXI_USB1_BASE 0x01c14000 +#endif #define SUNXI_SS_BASE 0x01c15000 #define SUNXI_HDMI_BASE 0x01c16000 #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_PATA_BASE 0x01c19000 #define SUNXI_ACE_BASE 0x01c1a000 #define SUNXI_TVE1_BASE 0x01c1b000 #define SUNXI_USB2_BASE 0x01c1c000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 @@ -70,7 +78,7 @@ #define SUNXI_TP_BASE 0x01c25000 #define SUNXI_PMU_BASE 0x01c25400 -#define SUNXI_CPUCFG_BASE 0x01c25c00 +#define SUN7I_CPUCFG_BASE 0x01c25c00 #define SUNXI_UART0_BASE 0x01c28000 #define SUNXI_UART1_BASE 0x01c28400 @@ -96,9 +104,10 @@ #define SUNXI_GMAC_BASE 0x01c50000 #define SUNXI_DRAM_COM_BASE 0x01c62000 -#define SUNXI_DRAM_CTL_BASE 0x01c63000 -#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000 -#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000 +#define SUNXI_DRAM_CTL0_BASE 0x01c63000 +#define SUNXI_DRAM_CTL1_BASE 0x01c64000 +#define SUNXI_DRAM_PHY0_BASE 0x01c65000 +#define SUNXI_DRAM_PHY1_BASE 0x01c66000 /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 @@ -110,7 +119,9 @@ #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 +#define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 #define SUNXI_P2WI_BASE 0x01f03400 diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h new file mode 100644 index 0000000000..e2a29cb181 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h @@ -0,0 +1,67 @@ +/* + * Sunxi A31 CPUCFG register definition. + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPUCFG_H +#define _SUNXI_CPUCFG_H + +#ifndef __ASSEMBLY__ + +struct sunxi_cpucfg_reg { + u8 res0[0x40]; /* 0x000 */ + u32 cpu0_rst; /* 0x040 */ + u32 cpu0_ctrl; /* 0x044 */ + u32 cpu0_status; /* 0x048 */ + u8 res1[0x34]; /* 0x04c */ + u32 cpu1_rst; /* 0x080 */ + u32 cpu1_ctrl; /* 0x084 */ + u32 cpu1_status; /* 0x088 */ + u8 res2[0x34]; /* 0x08c */ + u32 cpu2_rst; /* 0x0c0 */ + u32 cpu2_ctrl; /* 0x0c4 */ + u32 cpu2_status; /* 0x0c8 */ + u8 res3[0x34]; /* 0x0cc */ + u32 cpu3_rst; /* 0x100 */ + u32 cpu3_ctrl; /* 0x104 */ + u32 cpu3_status; /* 0x108 */ + u8 res4[0x78]; /* 0x10c */ + u32 gen_ctrl; /* 0x184 */ + u32 l2_status; /* 0x188 */ + u8 res5[0x4]; /* 0x18c */ + u32 event_in; /* 0x190 */ + u8 res6[0xc]; /* 0x194 */ + u32 super_standy_flag; /* 0x1a0 */ + u32 priv0; /* 0x1a4 */ + u32 priv1; /* 0x1a8 */ + u8 res7[0x54]; /* 0x1ac */ + u32 idle_cnt0_low; /* 0x200 */ + u32 idle_cnt0_high; /* 0x204 */ + u32 idle_cnt0_ctrl; /* 0x208 */ + u8 res8[0x4]; /* 0x20c */ + u32 idle_cnt1_low; /* 0x210 */ + u32 idle_cnt1_high; /* 0x214 */ + u32 idle_cnt1_ctrl; /* 0x218 */ + u8 res9[0x4]; /* 0x21c */ + u32 idle_cnt2_low; /* 0x220 */ + u32 idle_cnt2_high; /* 0x224 */ + u32 idle_cnt2_ctrl; /* 0x228 */ + u8 res10[0x4]; /* 0x22c */ + u32 idle_cnt3_low; /* 0x230 */ + u32 idle_cnt3_high; /* 0x234 */ + u32 idle_cnt3_ctrl; /* 0x238 */ + u8 res11[0x4]; /* 0x23c */ + u32 idle_cnt4_low; /* 0x240 */ + u32 idle_cnt4_high; /* 0x244 */ + u32 idle_cnt4_ctrl; /* 0x248 */ + u8 res12[0x34]; /* 0x24c */ + u32 cnt64_ctrl; /* 0x280 */ + u32 cnt64_low; /* 0x284 */ + u32 cnt64_high; /* 0x288 */ +}; + +#endif /* __ASSEMBLY__ */ +#endif /* _SUNXI_CPUCFG_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 1945f75441..9072e68229 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -14,172 +14,13 @@ #include <linux/types.h> -struct sunxi_dram_reg { - u32 ccr; /* 0x00 controller configuration register */ - u32 dcr; /* 0x04 dram configuration register */ - u32 iocr; /* 0x08 i/o configuration register */ - u32 csr; /* 0x0c controller status register */ - u32 drr; /* 0x10 dram refresh register */ - u32 tpr0; /* 0x14 dram timing parameters register 0 */ - u32 tpr1; /* 0x18 dram timing parameters register 1 */ - u32 tpr2; /* 0x1c dram timing parameters register 2 */ - u32 gdllcr; /* 0x20 global dll control register */ - u8 res0[0x28]; - u32 rslr0; /* 0x4c rank system latency register */ - u32 rslr1; /* 0x50 rank system latency register */ - u8 res1[0x8]; - u32 rdgr0; /* 0x5c rank dqs gating register */ - u32 rdgr1; /* 0x60 rank dqs gating register */ - u8 res2[0x34]; - u32 odtcr; /* 0x98 odt configuration register */ - u32 dtr0; /* 0x9c data training register 0 */ - u32 dtr1; /* 0xa0 data training register 1 */ - u32 dtar; /* 0xa4 data training address register */ - u32 zqcr0; /* 0xa8 zq control register 0 */ - u32 zqcr1; /* 0xac zq control register 1 */ - u32 zqsr; /* 0xb0 zq status register */ - u32 idcr; /* 0xb4 initializaton delay configure reg */ - u8 res3[0x138]; - u32 mr; /* 0x1f0 mode register */ - u32 emr; /* 0x1f4 extended mode register */ - u32 emr2; /* 0x1f8 extended mode register */ - u32 emr3; /* 0x1fc extended mode register */ - u32 dllctr; /* 0x200 dll control register */ - u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ - /* 0x208 dll control register 1(byte 1) */ - /* 0x20c dll control register 2(byte 2) */ - /* 0x210 dll control register 3(byte 3) */ - /* 0x214 dll control register 4(byte 4) */ - u32 dqtr0; /* 0x218 dq timing register */ - u32 dqtr1; /* 0x21c dq timing register */ - u32 dqtr2; /* 0x220 dq timing register */ - u32 dqtr3; /* 0x224 dq timing register */ - u32 dqstr; /* 0x228 dqs timing register */ - u32 dqsbtr; /* 0x22c dqsb timing register */ - u32 mcr; /* 0x230 mode configure register */ - u8 res[0x8]; - u32 ppwrsctl; /* 0x23c pad power save control */ - u32 apr; /* 0x240 arbiter period register */ - u32 pldtr; /* 0x244 priority level data threshold reg */ - u8 res5[0x8]; - u32 hpcr[32]; /* 0x250 host port configure register */ - u8 res6[0x10]; - u32 csel; /* 0x2e0 controller select register */ -}; - -struct dram_para { - u32 clock; - u32 mbus_clock; - u32 type; - u32 rank_num; - u32 density; - u32 io_width; - u32 bus_width; - u32 cas; - u32 zq; - u32 odt_en; - u32 size; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 emr1; - u32 emr2; - u32 emr3; - u32 dqs_gating_delay; - u32 active_windowing; -}; - -#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) -#define DRAM_CCR_DQS_GATE (0x1 << 14) -#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) -#define DRAM_CCR_ITM_OFF (0x1 << 28) -#define DRAM_CCR_DATA_TRAINING (0x1 << 30) -#define DRAM_CCR_INIT (0x1 << 31) - -#define DRAM_MEMORY_TYPE_DDR1 1 -#define DRAM_MEMORY_TYPE_DDR2 2 -#define DRAM_MEMORY_TYPE_DDR3 3 -#define DRAM_MEMORY_TYPE_LPDDR2 4 -#define DRAM_MEMORY_TYPE_LPDDR 5 -#define DRAM_DCR_TYPE (0x1 << 0) -#define DRAM_DCR_TYPE_DDR2 0x0 -#define DRAM_DCR_TYPE_DDR3 0x1 -#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) -#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) -#define DRAM_DCR_IO_WIDTH_8BIT 0x0 -#define DRAM_DCR_IO_WIDTH_16BIT 0x1 -#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) -#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) -#define DRAM_DCR_CHIP_DENSITY_256M 0x0 -#define DRAM_DCR_CHIP_DENSITY_512M 0x1 -#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 -#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 -#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 -#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 -#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) -#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) -#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 -#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 -#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 -#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) -#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) -#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) -#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) -#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) -#define DRAM_DCR_MODE_SEQ 0x0 -#define DRAM_DCR_MODE_INTERLEAVE 0x1 - -#define DRAM_CSR_DTERR (0x1 << 20) -#define DRAM_CSR_DTIERR (0x1 << 21) -#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) - -#define DRAM_DRR_TRFC(n) ((n) & 0xff) -#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) -#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) - -#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) -#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) -#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) -#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) -#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) -#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) -#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) -#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) -#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) -#define DRAM_MCR_RESET (0x1 << 12) -#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) -#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) -#define DRAM_MCR_DCLK_OUT (0x1 << 16) - -#define DRAM_DLLCR_NRESET (0x1 << 30) -#define DRAM_DLLCR_DISABLE (0x1 << 31) - -#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) -#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) -#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ -#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ - -#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ - -#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) -#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) - -#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) -#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) -#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) -#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) -#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) -#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) -#define DRAM_MR_POWER_DOWN (0x1 << 12) - -#define DRAM_CSEL_MAGIC 0x16237495 +/* dram regs definition */ +#if defined(CONFIG_MACH_SUN6I) +#include <asm/arch/dram_sun6i.h> +#else +#include <asm/arch/dram_sun4i.h> +#endif unsigned long sunxi_dram_init(void); -unsigned long dramc_init(struct dram_para *para); #endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h new file mode 100644 index 0000000000..6c1ec5be86 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Sunxi platform dram register definition. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN4I_H +#define _SUNXI_DRAM_SUN4I_H + +struct sunxi_dram_reg { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 mbus_clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; + u32 dqs_gating_delay; + u32 active_windowing; +}; + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_DTERR (0x1 << 20) +#define DRAM_CSR_DTIERR (0x1 << 21) +#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) + +#define DRAM_DRR_TRFC(n) ((n) & 0xff) +#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) +#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) +#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ +#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ + +#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ + +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +unsigned long dramc_init(struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h new file mode 100644 index 0000000000..9b0b310c2e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h @@ -0,0 +1,359 @@ +/* + * Sun6i platform dram controller register and constant defines + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN6I_H +#define _SUNXI_DRAM_SUN6I_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u32 dbgcr1; /* 0x0c */ + u32 rmcr[8]; /* 0x10 */ + u32 mmcr[16]; /* 0x30 */ + u32 mbagcr[6]; /* 0x70 */ + u32 maer; /* 0x88 */ + u8 res0[0x14]; /* 0x8c */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ + u32 mdfsmrmr; /* 0x108 */ + u32 mdfstr0; /* 0x10c */ + u32 mdfstr1; /* 0x110 */ + u32 mdfstr2; /* 0x114 */ + u32 mdfstr3; /* 0x118 */ + u32 mdfsgcr; /* 0x11c */ + u8 res1[0x1c]; /* 0x120 */ + u32 mdfsivr; /* 0x13c */ + u8 res2[0x0c]; /* 0x140 */ + u32 mdfstcr; /* 0x14c */ +}; + +struct sunxi_mctl_ctl_reg { + u8 res0[0x04]; /* 0x00 */ + u32 sctl; /* 0x04 */ + u32 sstat; /* 0x08 */ + u8 res1[0x34]; /* 0x0c */ + u32 mcmd; /* 0x40 */ + u8 res2[0x08]; /* 0x44 */ + u32 cmdstat; /* 0x4c */ + u32 cmdstaten; /* 0x50 */ + u8 res3[0x0c]; /* 0x54 */ + u32 mrrcfg0; /* 0x60 */ + u32 mrrstat0; /* 0x64 */ + u32 mrrstat1; /* 0x68 */ + u8 res4[0x10]; /* 0x6c */ + u32 mcfg1; /* 0x7c */ + u32 mcfg; /* 0x80 */ + u32 ppcfg; /* 0x84 */ + u32 mstat; /* 0x88 */ + u32 lp2zqcfg; /* 0x8c */ + u8 res5[0x04]; /* 0x90 */ + u32 dtustat; /* 0x94 */ + u32 dtuna; /* 0x98 */ + u32 dtune; /* 0x9c */ + u32 dtuprd0; /* 0xa0 */ + u32 dtuprd1; /* 0xa4 */ + u32 dtuprd2; /* 0xa8 */ + u32 dtuprd3; /* 0xac */ + u32 dtuawdt; /* 0xb0 */ + u8 res6[0x0c]; /* 0xb4 */ + u32 togcnt1u; /* 0xc0 */ + u8 res7[0x08]; /* 0xc4 */ + u32 togcnt100n; /* 0xcc */ + u32 trefi; /* 0xd0 */ + u32 tmrd; /* 0xd4 */ + u32 trfc; /* 0xd8 */ + u32 trp; /* 0xdc */ + u32 trtw; /* 0xe0 */ + u32 tal; /* 0xe4 */ + u32 tcl; /* 0xe8 */ + u32 tcwl; /* 0xec */ + u32 tras; /* 0xf0 */ + u32 trc; /* 0xf4 */ + u32 trcd; /* 0xf8 */ + u32 trrd; /* 0xfc */ + u32 trtp; /* 0x100 */ + u32 twr; /* 0x104 */ + u32 twtr; /* 0x108 */ + u32 texsr; /* 0x10c */ + u32 txp; /* 0x110 */ + u32 txpdll; /* 0x114 */ + u32 tzqcs; /* 0x118 */ + u32 tzqcsi; /* 0x11c */ + u32 tdqs; /* 0x120 */ + u32 tcksre; /* 0x124 */ + u32 tcksrx; /* 0x128 */ + u32 tcke; /* 0x12c */ + u32 tmod; /* 0x130 */ + u32 trstl; /* 0x134 */ + u32 tzqcl; /* 0x138 */ + u32 tmrr; /* 0x13c */ + u32 tckesr; /* 0x140 */ + u32 tdpd; /* 0x144 */ + u8 res8[0xb8]; /* 0x148 */ + u32 dtuwactl; /* 0x200 */ + u32 dturactl; /* 0x204 */ + u32 dtucfg; /* 0x208 */ + u32 dtuectl; /* 0x20c */ + u32 dtuwd0; /* 0x210 */ + u32 dtuwd1; /* 0x214 */ + u32 dtuwd2; /* 0x218 */ + u32 dtuwd3; /* 0x21c */ + u32 dtuwdm; /* 0x220 */ + u32 dturd0; /* 0x224 */ + u32 dturd1; /* 0x228 */ + u32 dturd2; /* 0x22c */ + u32 dturd3; /* 0x230 */ + u32 dtulfsrwd; /* 0x234 */ + u32 dtulfsrrd; /* 0x238 */ + u32 dtueaf; /* 0x23c */ + u32 dfitctldly; /* 0x240 */ + u32 dfiodtcfg; /* 0x244 */ + u32 dfiodtcfg1; /* 0x248 */ + u32 dfiodtrmap; /* 0x24c */ + u32 dfitphywrd; /* 0x250 */ + u32 dfitphywrl; /* 0x254 */ + u8 res9[0x08]; /* 0x258 */ + u32 dfitrdden; /* 0x260 */ + u32 dfitphyrdl; /* 0x264 */ + u8 res10[0x08]; /* 0x268 */ + u32 dfitphyupdtype0; /* 0x270 */ + u32 dfitphyupdtype1; /* 0x274 */ + u32 dfitphyupdtype2; /* 0x278 */ + u32 dfitphyupdtype3; /* 0x27c */ + u32 dfitctrlupdmin; /* 0x280 */ + u32 dfitctrlupdmax; /* 0x284 */ + u32 dfitctrlupddly; /* 0x288 */ + u8 res11[4]; /* 0x28c */ + u32 dfiupdcfg; /* 0x290 */ + u32 dfitrefmski; /* 0x294 */ + u32 dfitcrlupdi; /* 0x298 */ + u8 res12[0x10]; /* 0x29c */ + u32 dfitrcfg0; /* 0x2ac */ + u32 dfitrstat0; /* 0x2b0 */ + u32 dfitrwrlvlen; /* 0x2b4 */ + u32 dfitrrdlvlen; /* 0x2b8 */ + u32 dfitrrdlvlgateen; /* 0x2bc */ + u8 res13[0x04]; /* 0x2c0 */ + u32 dfistcfg0; /* 0x2c4 */ + u32 dfistcfg1; /* 0x2c8 */ + u8 res14[0x04]; /* 0x2cc */ + u32 dfitdramclken; /* 0x2d0 */ + u32 dfitdramclkdis; /* 0x2d4 */ + u8 res15[0x18]; /* 0x2d8 */ + u32 dfilpcfg0; /* 0x2f0 */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr; /* 0x08 phy general configuration register */ + u32 pgsr; /* 0x0c */ + u32 dllgcr; /* 0x10 */ + u32 acdllcr; /* 0x14 */ + u32 ptr0; /* 0x18 */ + u32 ptr1; /* 0x1c */ + u32 ptr2; /* 0x20 */ + u32 aciocr; /* 0x24 */ + u32 dxccr; /* 0x28 DATX8 common configuration register */ + u32 dsgcr; /* 0x2c dram system general config register */ + u32 dcr; /* 0x30 */ + u32 dtpr0; /* 0x34 dram timing parameters register 0 */ + u32 dtpr1; /* 0x38 dram timing parameters register 1 */ + u32 dtpr2; /* 0x3c dram timing parameters register 2 */ + u32 mr0; /* 0x40 mode register 0 */ + u32 mr1; /* 0x44 mode register 1 */ + u32 mr2; /* 0x48 mode register 2 */ + u32 mr3; /* 0x4c mode register 3 */ + u32 odtcr; /* 0x50 */ + u32 dtar; /* 0x54 data training address register */ + u32 dtd0; /* 0x58 */ + u32 dtd1; /* 0x5c */ + u8 res1[0x60]; /* 0x60 */ + u32 dcuar; /* 0xc0 */ + u32 dcudr; /* 0xc4 */ + u32 dcurr; /* 0xc8 */ + u32 dculr; /* 0xcc */ + u32 dcugcr; /* 0xd0 */ + u32 dcutpr; /* 0xd4 */ + u32 dcusr0; /* 0xd8 */ + u32 dcusr1; /* 0xdc */ + u8 res2[0x20]; /* 0xe0 */ + u32 bistrr; /* 0x100 */ + u32 bistmskr0; /* 0x104 */ + u32 bistmskr1; /* 0x108 */ + u32 bistwcr; /* 0x10c */ + u32 bistlsr; /* 0x110 */ + u32 bistar0; /* 0x114 */ + u32 bistar1; /* 0x118 */ + u32 bistar2; /* 0x11c */ + u32 bistupdr; /* 0x120 */ + u32 bistgsr; /* 0x124 */ + u32 bistwer; /* 0x128 */ + u32 bistber0; /* 0x12c */ + u32 bistber1; /* 0x130 */ + u32 bistber2; /* 0x134 */ + u32 bistwcsr; /* 0x138 */ + u32 bistfwr0; /* 0x13c */ + u32 bistfwr1; /* 0x140 */ + u8 res3[0x3c]; /* 0x144 */ + u32 zq0cr0; /* 0x180 zq 0 control register 0 */ + u32 zq0cr1; /* 0x184 zq 0 control register 1 */ + u32 zq0sr0; /* 0x188 zq 0 status register 0 */ + u32 zq0sr1; /* 0x18c zq 0 status register 1 */ + u8 res4[0x30]; /* 0x190 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0dllcr; /* 0x1cc */ + u32 dx0dqtr; /* 0x1d0 */ + u32 dx0dqstr; /* 0x1d4 */ + u8 res5[0x28]; /* 0x1d8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1dllcr; /* 0x20c */ + u32 dx1dqtr; /* 0x210 */ + u32 dx1dqstr; /* 0x214 */ + u8 res6[0x28]; /* 0x218 */ + u32 dx2gcr; /* 0x240 */ + u32 dx2gsr0; /* 0x244 */ + u32 dx2gsr1; /* 0x248 */ + u32 dx2dllcr; /* 0x24c */ + u32 dx2dqtr; /* 0x250 */ + u32 dx2dqstr; /* 0x254 */ + u8 res7[0x28]; /* 0x258 */ + u32 dx3gcr; /* 0x280 */ + u32 dx3gsr0; /* 0x284 */ + u32 dx3gsr1; /* 0x288 */ + u32 dx3dllcr; /* 0x28c */ + u32 dx3dqtr; /* 0x290 */ + u32 dx3dqstr; /* 0x294 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (3 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_BUSW32 (3 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) +#define MCTL_CCR_CH0_CLK_EN (1 << 0) +#define MCTL_CCR_CH1_CLK_EN (1 << 1) +#define MCTL_CCR_MASTER_CLK_EN (1 << 2) + +/* + * DRAM control (sunxi_mctl_ctl_reg) register constants. + * Note that we use constant values for a lot of the timings, this is what + * the original boot0 bootloader does. + */ +#define MCTL_SCTL_CONFIG 1 +#define MCTL_SCTL_ACCESS 2 +#define MCTL_MCMD_NOP 0x88000000 +#define MCTL_MCMD_BUSY 0x80000000 +#define MCTL_MCFG_DDR3 0x70061 +#define MCTL_TREFI 78 +#define MCTL_TMRD 4 +#define MCTL_TRFC 115 +#define MCTL_TRP 9 +#define MCTL_TPREA 0 +#define MCTL_TRTW 2 +#define MCTL_TAL 0 +#define MCTL_TCL 9 +#define MCTL_TCWL 8 +#define MCTL_TRAS 18 +#define MCTL_TRC 23 +#define MCTL_TRCD 9 +#define MCTL_TRRD 4 +#define MCTL_TRTP 4 +#define MCTL_TWR 8 +#define MCTL_TWTR 4 +#define MCTL_TEXSR 512 +#define MCTL_TXP 4 +#define MCTL_TXPDLL 14 +#define MCTL_TZQCS 64 +#define MCTL_TZQCSI 0 +#define MCTL_TDQS 1 +#define MCTL_TCKSRE 5 +#define MCTL_TCKSRX 5 +#define MCTL_TCKE 4 +#define MCTL_TMOD 12 +#define MCTL_TRSTL 80 +#define MCTL_TZQCL 512 +#define MCTL_TMRR 2 +#define MCTL_TCKESR 5 +#define MCTL_TDPD 0 +#define MCTL_DFITPHYRDL 15 +#define MCTL_DFIUPDCFG_UPD (1 << 1) +#define MCTL_DFISTCFG0 5 + +/* + * DRAM phy (sunxi_mctl_phy_reg) register values / constants. + */ +#define MCTL_PIR_CLEAR_STATUS (1 << 28) +#define MCTL_PIR_STEP1 0xe9 +#define MCTL_PIR_STEP2 0x81 +#define MCTL_PGCR_RANK (1 << 19) +#define MCTL_PGCR 0x018c0202 +#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) +/* constants for both acdllcr as well as dx#dllcr */ +#define MCTL_DLLCR_NRESET (1 << 30) +#define MCTL_DLLCR_DISABLE (1 << 31) +/* ptr constants these are or-ed together to get the final ptr# values */ +#define MCTL_TITMSRST 10 +#define MCTL_TDLLLOCK 2250 +#define MCTL_TDLLSRST 23 +#define MCTL_TDINIT0 217000 +#define MCTL_TDINIT1 160 +#define MCTL_TDINIT2 87000 +#define MCTL_TDINIT3 433 +/* end ptr constants */ +#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) +#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) +#define MCTL_DXCCR 0x800 +#define MCTL_DSGCR_ENABLE (1 << 28) +#define MCTL_DSGCR 0xf200001b +#define MCTL_DCR_DDR3 0x0b +/* dtpr constants these are or-ed together to get the final dtpr# values */ +#define MCTL_TCCD 0 +#define MCTL_TDQSCKMAX 1 +#define MCTL_TDQSCK 1 +#define MCTL_TRTODT 0 +#define MCTL_TFAW 20 +#define MCTL_TAOND 0 +#define MCTL_TDLLK 512 +/* end dtpr constants */ +#define MCTL_MR0 0x1a50 +#define MCTL_MR1 0x4 +#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) +#define MCTL_MR3 0x0 +#define MCTL_DX_GCR_EN (1 << 0) +#define MCTL_DX_GCR 0x880 +#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) +#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) +#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) +#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) + +#endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 437dd35b68..c734cf015e 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -172,6 +172,9 @@ enum sunxi_gpio_number { #define SUN4I_GPI4_SDC3 2 +#define SUNXI_GPL0_R_P2WI_SCK 3 +#define SUNXI_GPL1_R_P2WI_SDA 3 + #define SUN8I_GPL2_R_UART_TX 2 #define SUN8I_GPL3_R_UART_RX 2 diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h new file mode 100644 index 0000000000..2cf2d51c61 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/p2wi.h @@ -0,0 +1,140 @@ +/* + * Sunxi platform Push-Push i2c register definition. + * + * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * + * (c)Copyright 2006-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_P2WI_H +#define _SUNXI_P2WI_H + +#include <linux/types.h> + +#define P2WI_CTRL_RESET (0x1 << 0) +#define P2WI_CTRL_IRQ_EN (0x1 << 1) +#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) +#define P2WI_CTRL_TRANS_START (0x1 << 7) + +#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) +#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) +#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) +#define P2WI_CC_CLK_DIV(n) \ + __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) +#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) +#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) + +#define P2WI_IRQ_TRANS_DONE (0x1 << 0) +#define P2WI_IRQ_TRANS_ERR (0x1 << 1) +#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) + +#define P2WI_STAT_TRANS_DONE (0x1 << 0) +#define P2WI_STAT_TRANS_ERR (0x1 << 1) +#define P2WI_STAT_LOAD_BUSY (0x1 << 2) +#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) +#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) +#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 +#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 +#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 +#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 +#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 +#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 +#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 +#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 +#define P2WI_STAT_TRANS_ERR_BYTE_1 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) +#define P2WI_STAT_TRANS_ERR_BYTE_2 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) +#define P2WI_STAT_TRANS_ERR_BYTE_3 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) +#define P2WI_STAT_TRANS_ERR_BYTE_4 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) +#define P2WI_STAT_TRANS_ERR_BYTE_5 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) +#define P2WI_STAT_TRANS_ERR_BYTE_6 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) +#define P2WI_STAT_TRANS_ERR_BYTE_7 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) +#define P2WI_STAT_TRANS_ERR_BYTE_8 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) + +#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) +#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) +#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) +#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) +#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) +#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) +#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) +#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) + +#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) +#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) +#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) +#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) + +#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) +#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) +#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) +#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) +#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) +#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) +#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) +#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) + +#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) +#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) +#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) +#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) +#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) +#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) + +#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) +#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) +#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) +#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) +#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) +#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) +#define P2WI_PM_INIT_SEND (0x1 << 31) + +struct sunxi_p2wi_reg { + u32 ctrl; /* 0x00 control */ + u32 cc; /* 0x04 clock control */ + u32 irq; /* 0x08 interrupt */ + u32 status; /* 0x0c status */ + u32 dataddr0; /* 0x10 data address 0 */ + u32 dataddr1; /* 0x14 data address 1 */ + u32 numbytes; /* 0x18 num bytes */ + u32 data0; /* 0x1c data buffer 0 */ + u32 data1; /* 0x20 data buffer 1 */ + u32 linectrl; /* 0x24 line control */ + u32 pm; /* 0x28 power management */ +}; + +void p2wi_init(void); +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); +int p2wi_read(const u8 addr, u8 *data); +int p2wi_write(const u8 addr, u8 data); + +#endif /* _SUNXI_P2WI_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 3d3bfa6cd1..88de1ff675 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -119,6 +119,7 @@ #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) +#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) #define PRCM_CLK_1WIRE_GATE (0x1 << 31) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index ca2d44faf4..61e2914d44 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -201,7 +201,7 @@ enum { * \param size size of memory region to change * \param option dcache option to select */ -void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); /** diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 2155fe8187..0291afa7bd 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; - u32 upto, end; + unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; start = start >> MMU_SECTION_SHIFT; - debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, + debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index c1fb92af4b..bd64ea694f 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -38,9 +38,6 @@ config TARGET_IPEK01 config TARGET_JUPITER bool "Support jupiter" -config TARGET_MCC200 - bool "Support mcc200" - config TARGET_MOTIONPRO bool "Support motionpro" @@ -130,7 +127,6 @@ source "board/jupiter/Kconfig" source "board/manroland/hmi1001/Kconfig" source "board/manroland/mucmc52/Kconfig" source "board/manroland/uc101/Kconfig" -source "board/mcc200/Kconfig" source "board/motionpro/Kconfig" source "board/munices/Kconfig" source "board/phytec/pcm030/Kconfig" diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig index f94a444cf2..98aa10ade0 100644 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -1,23 +1,15 @@ if TARGET_DB_MV784MP_GP -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "db-mv784mp-gp" config SYS_VENDOR - string default "Marvell" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "db-mv784mp-gp" endif diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d899a6..ce625e54d0 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -8,6 +8,10 @@ #include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <usb_mass_storage.h> + #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,3 +43,20 @@ int board_init(void) return 0; } + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig index 4ba63999ae..94f1754a47 100644 --- a/board/kosagi/novena/Kconfig +++ b/board/kosagi/novena/Kconfig @@ -1,8 +1,5 @@ if TARGET_KOSAGI_NOVENA -config SYS_CPU - default "armv7" - config SYS_BOARD default "novena" diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig index d34e2abf36..d833ca0e25 100644 --- a/board/maxbcm/Kconfig +++ b/board/maxbcm/Kconfig @@ -1,19 +1,12 @@ if TARGET_MAXBCM -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "maxbcm" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "maxbcm" endif diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig deleted file mode 100644 index 3b27eeb1de..0000000000 --- a/board/mcc200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MCC200 - -config SYS_BOARD - default "mcc200" - -config SYS_CONFIG_NAME - default "mcc200" - -endif diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS deleted file mode 100644 index a59a498795..0000000000 --- a/board/mcc200/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -MCC200 BOARD -#M: - -S: Maintained -F: board/mcc200/ -F: include/configs/mcc200.h -F: configs/mcc200_defconfig -F: configs/mcc200_COM12_defconfig -F: configs/mcc200_COM12_highboot_defconfig -F: configs/mcc200_COM12_highboot_SDRAM_defconfig -F: configs/mcc200_COM12_SDRAM_defconfig -F: configs/mcc200_highboot_defconfig -F: configs/mcc200_highboot_SDRAM_defconfig -F: configs/mcc200_SDRAM_defconfig -F: configs/prs200_defconfig -F: configs/prs200_DDR_defconfig -F: configs/prs200_highboot_defconfig -F: configs/prs200_highboot_DDR_defconfig diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile deleted file mode 100644 index db3b39646a..0000000000 --- a/board/mcc200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mcc200.o lcd.o auto_update.o diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c deleted file mode 100644 index 43173ce060..0000000000 --- a/board/mcc200/auto_update.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <image.h> -#include <asm/byteorder.h> -#include <usb.h> -#include <part.h> - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CONFIG_SYS_HUSH_PARSER -#error "must define CONFIG_SYS_HUSH_PARSER" -#endif - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_FIRMWARE "u-boot.img" -#define AU_KERNEL "kernel.img" -#define AU_ROOTFS "rootfs.img" - -struct flash_layout { - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#define AU_FL_FIRMWARE_ST 0xfC000000 -#define AU_FL_FIRMWARE_ND 0xfC03FFFF -#define AU_FL_KERNEL_ST 0xfC0C0000 -#define AU_FL_KERNEL_ND 0xfC1BFFFF -#define AU_FL_ROOTFS_ST 0xFC1C0000 -#define AU_FL_ROOTFS_ND 0xFCFBFFFF - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_FIRMWARE 0 -#define IDX_KERNEL 1 -#define IDX_ROOTFS 2 - -/* max. number of files which could interest us */ -#define AU_MAXFILES 3 - -/* pointers to file names */ -char *aufile[AU_MAXFILES] = { - AU_FIRMWARE, - AU_KERNEL, - AU_ROOTFS -}; - -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES] = { - (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST, - (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST, - (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST, -}; - -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES] = { - { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, }, - { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, }, - { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, }, -}; - -ulong totsize; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x00200000) - -/* the root file system is the largest image */ -#define MAX_LOADSZ ausize[IDX_ROOTFS] - -/*i2c address of the keypad status*/ -#define I2C_PSOC_KEYPAD_ADDR 0x53 - -/* keypad mask */ -#define KEYPAD_ROW 2 -#define KEYPAD_COL 2 -#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) -#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -extern int u_boot_hush_start(void); -#ifdef CONFIG_PROGRESSBAR -extern void show_progress(int, int); -extern void lcd_puts (char *); -extern void lcd_enable(void); -#endif - -int au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (nbytes != image_get_image_size (hdr)) { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum, fsize; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_ROOTFS) && - (!image_check_type (hdr, IH_TYPE_RAMDISK) && - !image_check_type (hdr, IH_TYPE_FILESYSTEM))) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - - fsize = checksum + image_get_header_size (); - /* for kernel and ramdisk the image header must also fit into flash */ - if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK)) - checksum += image_get_header_size (); - - /* check the size does not exceed space in flash. HUSH scripts */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* Update with the real filesize */ - ausize[idx] = fsize; - - return checksum; /* return size to be written to flash */ -} - -int au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - run_command_list(addr, -1, 0); - return 0; - } - - start = aufl_layout[idx].start; - end = aufl_layout[idx].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - mdelay(100); -#ifdef CONFIG_PROGRESSBAR - show_progress(end - start, totsize); -#endif - - /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - -#ifdef CONFIG_PROGRESSBAR - show_progress(nbytes, totsize); -#endif - - /* check the data CRC of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res = 0, cnt, old_ctrlc; - char *env; - long start, end; - -#if 0 /* disable key-press detection to speed up boot-up time */ - uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; - - /* - * Read keypad status - */ - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); - mdelay(500); - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); - - /* - * Check keypad - */ - if ( !(keypad_status1[1] & KEYPAD_MASK_LO) || - (keypad_status1[1] != keypad_status2[1])) { - return 0; - } - -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - res = -1; - goto xit; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - res = -1; - goto xit; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[IDX_FIRMWARE].start = start; - aufl_layout[IDX_FIRMWARE].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[IDX_KERNEL].start = start; - aufl_layout[IDX_KERNEL].end = end; - } - start = -1; - end = 0; - env = getenv("rootfs_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("rootfs_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_ROOTFS] = (end + 1) - start; - aufl_layout[IDX_ROOTFS].start = start; - aufl_layout[IDX_ROOTFS].end = end; - } - - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - /* validate the images first */ - for (i = 0; i < AU_MAXFILES; i++) { - ulong imsize; - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - ausize[i] = 0; - continue; - } - /* au_check_header_valid() updates ausize[] */ - if ((imsize = au_check_header_valid(i, sz)) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - /* totsize accounts for image size and flash erase size */ - totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start)); - } - -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - lcd_puts(" Update in progress\n"); - lcd_enable(); - } -#endif - - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES && totsize; i++) { - if (!ausize[i]) { - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]); - - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - - if (sz != ausize[i]) { - printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz); - continue; - } - - if (sz <= 0 || sz <= image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < (AU_MAXFILES + 1)); - if (cnt < (AU_MAXFILES + 1)) -#else - } while (res < 0); -#endif - } - - /* restore the old state */ - disable_ctrlc(old_ctrlc); -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - if (!res) { - lcd_puts("\n Update completed\n"); - } else { - lcd_puts("\n Update error\n"); - } - lcd_enable(); - } -#endif - xit: - usb_stop(); - return res; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c deleted file mode 100644 index c911445d97..0000000000 --- a/board/mcc200/lcd.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <mpc5xxx.h> -#include <malloc.h> - -#ifdef CONFIG_LCD - -#undef SWAPPED_LCD /* For the previous h/w version */ -/* - * The name of the device used for communication - * with the PSoC. - */ -#define PSOC_PSC MPC5XXX_PSC2 -#define PSOC_BAUD 230400UL - -#define RTS_ASSERT 1 -#define RTS_NEGATE 0 -#define CTS_ASSERT 1 -#define CTS_NEGATE 0 - -/* - * Dimensions in pixels - */ -#define LCD_WIDTH 160 -#define LCD_HEIGHT 100 - -/* - * Dimensions in bytes - */ -#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) - -#if LCD_BPP != LCD_MONOCHROME -#error "MCC200 support only monochrome displays (1 bpp)!" -#endif - -#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ -#define PSOC_WAIT_TIME 10 /* usec */ - -#include <video_font.h> -#define FONT_WIDTH VIDEO_FONT_WIDTH - -DECLARE_GLOBAL_DATA_PTR; - -/* - * LCD information - */ -vidinfo_t panel_info = { - LCD_WIDTH, LCD_HEIGHT, LCD_BPP -}; - - -/* - * The device we use to communicate with PSoC - */ -int serial_inited = 0; - -/* - * Imported functions to support the PSoC protocol - */ -extern int serial_init_dev (unsigned long dev_base); -extern void serial_setrts_dev (unsigned long dev_base, int s); -extern int serial_getcts_dev (unsigned long dev_base); -extern void serial_putc_raw_dev(unsigned long dev_base, const char c); - -/* - * Just stubs for our driver, needed for compiling compabilty with - * the common LCD driver code. - */ -void lcd_initcolregs (void) -{ -} - -void lcd_ctrl_init (void *lcdbase) -{ -} - -/* - * Function sends the contents of the frame-buffer to the LCD - */ -void lcd_enable (void) -{ - int i, retries, fb_size; - - if (!serial_inited) { - unsigned long baud; - - baud = gd->baudrate; - gd->baudrate = PSOC_BAUD; - serial_init_dev(PSOC_PSC); - gd->baudrate = baud; - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - serial_inited = 1; - } - - /* - * Implement PSoC communication protocol: - * 1. Assert RTS, wait CTS assertion - * 2. Transmit data - * 3. Negate RTS, wait CTS negation - */ - - /* 1 */ - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) - break; - udelay (PSOC_WAIT_TIME); - } - if (!retries) { - printf ("%s Error: PSoC doesn't respond on " - "RTS ASSERT\n", __FUNCTION__); - } - - /* 2 */ - fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); - -#if !defined(SWAPPED_LCD) - for (i=0; i<fb_size; i++) { - serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]); - } -#else - { - int x, y, pwidth; - char *p = (char *)gd->fb_base; - - pwidth = ((panel_info.vl_col+7) >> 3); - for (y=0; y<panel_info.vl_row; y++) { - i = y * pwidth; - for (x=0; x<pwidth; x+=5) { - serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); - } - } - } -#endif - - /* 3 */ - serial_setrts_dev (PSOC_PSC, RTS_NEGATE); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) - break; - udelay (PSOC_WAIT_TIME); - } - - return; -} -#ifdef CONFIG_PROGRESSBAR - -void show_progress (int size, int tot) -{ - int cnt; - int i; - static int rc = 0; - - rc += size; - - cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot; - - rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH); - - for (i = 0; i < cnt; i++) { - lcd_putc(0xdc); - } - - if (cnt) { - lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */ - } -} - -#endif - -int bmp_display(ulong addr, int x, int y) -{ - int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - - ret = lcd_display_bitmap((ulong)bmp, x, y); - - if ((unsigned long)bmp != addr) - free(bmp); - - return ret; -} - -#endif /* CONFIG_LCD */ diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c deleted file mode 100644 index 706886b84a..0000000000 --- a/board/mcc200/mcc200.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> - -/* Two MT48LC8M32B2 for 32 MB */ -/* #include "mt48lc8m32b2-6-7.h" */ - -/* One MT48LC16M32S2 for 64 MB */ -/* #include "mt48lc16m32s2-75.h" */ -#if defined (CONFIG_MCC200_SDRAM) -#include "mt48lc16m16a2-75.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -extern int do_auto_update(void); -ulong flash_get_size (ulong base, int banknum); - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); - - udelay(10); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ -#if defined(CONFIG_PRS200) - puts ("Board: PRS200\n"); -#else - puts ("Board: MCC200\n"); -#endif - return 0; -} - -int misc_init_r (void) -{ - ulong flash_sup_end, snum; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(gd->bd->bi_flashstart); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - if (gd->bd->bi_flashsize > (32 << 20)) { - /* Unprotect the upper bank of the Flash */ - *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); - flash_protect (FLAG_PROTECT_CLEAR, - flash_info[0].start[0] + flash_info[0].size / 2, - (flash_info[0].start[0] - 1) + flash_info[0].size, - &flash_info[0]); - *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); - printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); - flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; - snum++); - flash_info[0].sector_count = snum; - } - -#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); -#endif - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h deleted file mode 100644 index 9068fbf36f..0000000000 --- a/board/mcc200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h deleted file mode 100644 index 13aebbd8af..0000000000 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ -#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ -#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ -#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5b2d091122..c3f865d298 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -16,6 +16,7 @@ config MACH_SUN5I config MACH_SUN6I bool "sun6i (Allwinner A31)" select CPU_V7 + select SUPPORT_SPL config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -111,6 +112,10 @@ config TARGET_MELE_M3 bool "MELE_M3" depends on MACH_SUN7I +config TARGET_MELE_M9 + bool "MELE_M9" + depends on MACH_SUN6I + config TARGET_MINI_X_1GB bool "MINI_X_1GB" depends on MACH_SUN4I @@ -192,4 +197,20 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config USB1_VBUS_PIN + string "Vbus enable pin for usb1 (ehci0)" + default "PH6" if MACH_SUN4I || MACH_SUN7I + default "PH27" if MACH_SUN6I + ---help--- + Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes + a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config USB2_VBUS_PIN + string "Vbus enable pin for usb2 (ehci1)" + default "PH3" if MACH_SUN4I || MACH_SUN7I + default "PH24" if MACH_SUN6I + ---help--- + See USB1_VBUS_PIN help text. + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index b3c77a83cb..ca0300272e 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -9,6 +9,7 @@ F: configs/Cubieboard_defconfig F: configs/Mele_A1000_defconfig F: configs/Mele_A1000G_defconfig F: configs/Mele_M3_defconfig +F: configs/Mele_M9_defconfig F: configs/Mini-X_defconfig F: configs/Mini-X-1Gb_defconfig F: include/configs/sun5i.h diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 03890c8c9c..e6ec5b8fc1 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -19,6 +19,9 @@ #ifdef CONFIG_AXP209_POWER #include <axp209.h> #endif +#ifdef CONFIG_AXP221_POWER +#include <axp221.h> +#endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/dram.h> @@ -169,6 +172,29 @@ void sunxi_board_init(void) power_failed |= axp209_set_ldo3(2800); power_failed |= axp209_set_ldo4(2800); #endif +#ifdef CONFIG_AXP221_POWER + power_failed = axp221_init(); + power_failed |= axp221_set_dcdc1(3000); + power_failed |= axp221_set_dcdc2(1200); + power_failed |= axp221_set_dcdc3(1200); + power_failed |= axp221_set_dcdc4(1200); + power_failed |= axp221_set_dcdc5(1500); +#if CONFIG_AXP221_DLDO1_VOLT != -1 + power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); +#endif +#if CONFIG_AXP221_DLDO4_VOLT != -1 + power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); +#endif +#if CONFIG_AXP221_ALDO1_VOLT != -1 + power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); +#endif +#if CONFIG_AXP221_ALDO2_VOLT != -1 + power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); +#endif +#if CONFIG_AXP221_ALDO3_VOLT != -1 + power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); +#endif +#endif printf("DRAM:"); ramsize = sunxi_dram_init(); diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 6348d27282..051aca01a8 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -29,7 +29,7 @@ int sunxi_gmac_initialize(bd_t *bis) * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" * of the GMAC clk register to 3. */ -#ifdef CONFIG_BANANAPI +#ifdef CONFIG_TARGET_BANANAPI setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); #endif diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 96c5f22ead..384b175e9c 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -27,15 +27,12 @@ endif if TARGET_K2L_EVM config SYS_BOARD - string default "ks2_evm" config SYS_VENDOR - string default "ti" config SYS_CONFIG_NAME - string default "k2l_evm" endif diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore index 68b8edd260..7c36bc963f 100644 --- a/board/xilinx/zynq/.gitignore +++ b/board/xilinx/zynq/.gitignore @@ -1 +1,2 @@ ps7_init.[ch] +ps7_init_gpl.[ch] diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 71c0c351f9..3b1eb4f74a 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -7,9 +7,11 @@ obj-y := board.o -# Please copy ps7_init.c/h from hw project to this directory +# Please copy ps7_init_gpl.c/h from hw project to this directory obj-$(CONFIG_SPL_BUILD) += \ - $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o) + $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \ + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o)) # Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c new file mode 100644 index 0000000000..4ae913eefe --- /dev/null +++ b/board/xilinx/zynq/legacy.c @@ -0,0 +1,2 @@ + +#warning usage of ps7_init files is deprecated please use ps7_init_gpl diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h index e59a977eb1..1eccf8d91d 100644 --- a/board/xilinx/zynq/xil_io.h +++ b/board/xilinx/zynq/xil_io.h @@ -6,7 +6,7 @@ #define XIL_IO_H /* - * This empty file is here because ps7_init.c exported by hw project + * This empty file is here because ps7_init_gpl.c exported by hw project * has #include "xil_io.h" line. */ diff --git a/common/dlmalloc.c b/common/dlmalloc.c index d87834df67..991229d5f7 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1533,6 +1533,9 @@ void mem_malloc_init(ulong start, ulong size) mem_malloc_end = start + size; mem_malloc_brk = start; + debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, + mem_malloc_end); + memset((void *)mem_malloc_start, 0, size); malloc_bin_reloc(); diff --git a/common/lcd.c b/common/lcd.c index 787d80e3cb..37147af805 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -881,7 +881,7 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, } #endif -#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200) +#if defined(CONFIG_MPC823) #define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++) #else #define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++ @@ -906,9 +906,7 @@ static inline void fb_put_word(uchar **fb, uchar **from) int lcd_display_bitmap(ulong bmp_image, int x, int y) { -#if !defined(CONFIG_MCC200) ushort *cmap = NULL; -#endif ushort *cmap_base = NULL; ushort i, j; uchar *fb; @@ -956,8 +954,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) debug("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); -#if !defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bmp_bpix == 8) { cmap = configuration_get_cmap(); cmap_base = cmap; @@ -985,24 +981,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #endif } } -#endif - /* - * BMP format for Monochrome assumes that the state of a - * pixel is described on a per Bit basis, not per Byte. - * So, in case of Monochrome BMP we should align widths - * on a byte boundary and convert them from Bit to Byte - * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in - * their own ways, so make the converting to be MCC200 - * specific. - */ -#if defined(CONFIG_MCC200) - if (bpix == 1) { - width = ((width + 7) & ~7) >> 3; - x = ((x + 7) & ~7) >> 3; - pwidth= ((pwidth + 7) & ~7) >> 3; - } -#endif padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width); diff --git a/common/usb_storage.c b/common/usb_storage.c index eb7706c100..1411737bed 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1351,8 +1351,11 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, perq = usb_stor_buf[0]; modi = usb_stor_buf[1]; - if ((perq & 0x1f) == 0x1f) { - /* skip unknown devices */ + /* + * Skip unknown devices (0x1f) and enclosure service devices (0x0d), + * they would not respond to test_unit_ready . + */ + if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) { return 0; } if ((modi&0x80) == 0x80) { diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 64756755bf..94fafa6b97 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -1,7 +1,8 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)" +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI" CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +CONFIG_USB1_VBUS_PIN="PB10" +S:CONFIG_MMC0_CD_PIN="PG1" +S:CONFIG_MMC1_CD_PIN="PG13" +S:CONFIG_ARM=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index d8b12391d8..8517203613 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb" +CONFIG_USB1_VBUS_PIN="PG11" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 91039dfc96..61f54666c2 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI" CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb" +CONFIG_USB1_VBUS_PIN="PG11" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 5b06ea0aea..7fe9059179 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)" +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb" +CONFIG_USB1_VBUS_PIN="PG13" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 89291f90e9..bef568df71 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -1,5 +1,6 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN6I=y -CONFIG_TARGET_COLOMBUS=y +CONFIG_SPL=y CONFIG_FDTFILE="sun6i-a31-colombus.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_COLOMBUS=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig new file mode 100644 index 0000000000..f46439fa4e --- /dev/null +++ b/configs/Mele_M9_defconfig @@ -0,0 +1,18 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" +CONFIG_FDTFILE="sun6i-a31-m9.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_MELE_M9=y +# Ethernet phy power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 +# USB hub power ++S:CONFIG_AXP221_DLDO4_VOLT=3300 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# HDMI power ? ++S:CONFIG_AXP221_ALDO2_VOLT=1800 ++S:CONFIG_AXP221_ALDO3_VOLT=3000 +# No Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="" diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 0a1abea0a8..6ca7c57186 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)" +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb" +CONFIG_USB1_VBUS_PIN="PH12" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN4I=y diff --git a/configs/mcc200_COM12_SDRAM_defconfig b/configs/mcc200_COM12_SDRAM_defconfig deleted file mode 100644 index be6dbd7240..0000000000 --- a/configs/mcc200_COM12_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_defconfig b/configs/mcc200_COM12_defconfig deleted file mode 100644 index 6ed86358a1..0000000000 --- a/configs/mcc200_COM12_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_highboot_SDRAM_defconfig b/configs/mcc200_COM12_highboot_SDRAM_defconfig deleted file mode 100644 index 5f93702f0e..0000000000 --- a/configs/mcc200_COM12_highboot_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_highboot_defconfig b/configs/mcc200_COM12_highboot_defconfig deleted file mode 100644 index 7abb0a40be..0000000000 --- a/configs/mcc200_COM12_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_SDRAM_defconfig b/configs/mcc200_SDRAM_defconfig deleted file mode 100644 index 37761b5625..0000000000 --- a/configs/mcc200_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_defconfig b/configs/mcc200_defconfig deleted file mode 100644 index b6aafec3ee..0000000000 --- a/configs/mcc200_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_highboot_SDRAM_defconfig b/configs/mcc200_highboot_SDRAM_defconfig deleted file mode 100644 index 94d33e5896..0000000000 --- a/configs/mcc200_highboot_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_highboot_defconfig b/configs/mcc200_highboot_defconfig deleted file mode 100644 index f863dd9fcb..0000000000 --- a/configs/mcc200_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index a560afb730..cadf461cdb 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -1,4 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q" +S:CONFIG_ARM=y +S:CONFIG_TARGET_KOSAGI_NOVENA=y diff --git a/configs/prs200_DDR_defconfig b/configs/prs200_DDR_defconfig deleted file mode 100644 index 541fb995af..0000000000 --- a/configs/prs200_DDR_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_defconfig b/configs/prs200_defconfig deleted file mode 100644 index a094a088cb..0000000000 --- a/configs/prs200_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_highboot_DDR_defconfig b/configs/prs200_highboot_DDR_defconfig deleted file mode 100644 index b8eb8d4d81..0000000000 --- a/configs/prs200_highboot_DDR_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_highboot_defconfig b/configs/prs200_highboot_defconfig deleted file mode 100644 index 8d68cc06b8..0000000000 --- a/configs/prs200_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 7dbff40b50..b9fd59c16a 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)" +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb" +CONFIG_USB1_VBUS_PIN="PG13" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig new file mode 100644 index 0000000000..0f3896d5f0 --- /dev/null +++ b/configs/socfpga_socrates_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig new file mode 100644 index 0000000000..12311cd83b --- /dev/null +++ b/configs/zynq_zybo_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZYBO=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" diff --git a/doc/README.scrapyard b/doc/README.scrapyard index bd4dd3c829..8ba6e0ae65 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,9 +12,11 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> -TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> -TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +PRS200 powerpc mpc5200 - - +MCC200 powerpc mpc5200 - - +TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de> TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de> IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de> diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index e69de29bb2..1ec7c0e59a 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -0,0 +1,47 @@ +config AXP221_POWER + boolean "axp221 pmic support" + depends on MACH_SUN6I + default y + ---help--- + Say y here to enable support for the axp221 pmic found on most sun6i + (A31) boards. + +config AXP221_DLDO1_VOLT + int "axp221 dldo1 voltage" + depends on AXP221_POWER + default -1 + ---help--- + Set the voltage (mV) to program the axp221 dldo1 at, set to -1 to + disable dldo1. + +config AXP221_DLDO4_VOLT + int "axp221 dldo4 voltage" + depends on AXP221_POWER + default -1 + ---help--- + Set the voltage (mV) to program the axp221 dldo4 at, set to -1 to + disable dldo4. + +config AXP221_ALDO1_VOLT + int "axp221 aldo1 voltage" + depends on AXP221_POWER + default -1 + ---help--- + Set the voltage (mV) to program the axp221 aldo1 at, set to -1 to + disable aldo1. + +config AXP221_ALDO2_VOLT + int "axp221 aldo2 voltage" + depends on AXP221_POWER + default -1 + ---help--- + Set the voltage (mV) to program the axp221 aldo2 at, set to -1 to + disable aldo2. + +config AXP221_ALDO3_VOLT + int "axp221 aldo3 voltage" + depends on AXP221_POWER + default -1 + ---help--- + Set the voltage (mV) to program the axp221 aldo3 at, set to -1 to + disable aldo3. diff --git a/drivers/power/Makefile b/drivers/power/Makefile index dc64e4d32b..04bd996cad 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o +obj-$(CONFIG_AXP221_POWER) += axp221.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c new file mode 100644 index 0000000000..941193a19d --- /dev/null +++ b/drivers/power/axp221.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/p2wi.h> +#include <axp221.h> + +static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +static int axp221_setbits(u8 reg, u8 bits) +{ + int ret; + u8 val; + + ret = p2wi_read(reg, &val); + if (ret) + return ret; + + val |= bits; + return p2wi_write(reg, val); +} + +int axp221_set_dcdc1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); + + ret = p2wi_write(AXP221_DCDC1_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DCDC1_EN); +} + +int axp221_set_dcdc2(unsigned int mvolt) +{ + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); + + return p2wi_write(AXP221_DCDC2_CTRL, cfg); +} + +int axp221_set_dcdc3(unsigned int mvolt) +{ + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); + + return p2wi_write(AXP221_DCDC3_CTRL, cfg); +} + +int axp221_set_dcdc4(unsigned int mvolt) +{ + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); + + return p2wi_write(AXP221_DCDC4_CTRL, cfg); +} + +int axp221_set_dcdc5(unsigned int mvolt) +{ + u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50); + + return p2wi_write(AXP221_DCDC5_CTRL, cfg); +} + +int axp221_set_dldo1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_DLDO1_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO1_EN); +} + +int axp221_set_dldo2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_DLDO2_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO2_EN); +} + +int axp221_set_dldo3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_DLDO3_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO3_EN); +} + +int axp221_set_dldo4(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_DLDO4_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO4_EN); +} + +int axp221_set_aldo1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_ALDO1_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO1_EN); +} + +int axp221_set_aldo2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_ALDO2_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO2_EN); +} + +int axp221_set_aldo3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + ret = p2wi_write(AXP221_ALDO3_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL3, + AXP221_OUTPUT_CTRL3_ALDO3_EN); +} + +int axp221_init(void) +{ + u8 axp_chip_id; + int ret; + + p2wi_init(); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, + AXP221_INIT_DATA); + if (ret) + return ret; + + ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id); + if (ret) + return ret; + + if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17)) + return -ENODEV; + + return 0; +} diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 94551c4c0c..e6ae9f1e52 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -5,8 +5,6 @@ # new USB host ethernet layer dependencies obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o -ifdef CONFIG_USB_ETHER_ASIX -obj-y += asix.o -endif +obj-$(CONFIG_USB_ETHER_ASIX) += asix.o obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 2efd5a4d5b..70bb550fa4 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o +obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_THOR_FUNCTION) += f_thor.o diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index b9816dfe30..7653f03949 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -31,7 +31,6 @@ #include <asm/io.h> #include <asm/mach-types.h> -#include <asm/arch/gpio.h> #include "regs-otg.h" #include <usb/lin_gadget_compat.h> @@ -105,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev, struct usb_gadget_driver *driver); static int udc_enable(struct s3c_udc *dev); static void udc_set_address(struct s3c_udc *dev, unsigned char address); -static void reconfig_usbd(void); +static void reconfig_usbd(struct s3c_udc *dev); static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed); static void nuke(struct s3c_ep *ep, int status); static int s3c_udc_set_halt(struct usb_ep *_ep, int value); @@ -146,68 +145,14 @@ static struct usb_ep_ops s3c_ep_ops = { void __iomem *regs_otg; struct s3c_usbotg_reg *reg; -struct s3c_usbotg_phy *phy; -static unsigned int usb_phy_ctrl; bool dfu_usb_get_reset(void) { return !!(readl(®->gintsts) & INT_RESET); } -void otg_phy_init(struct s3c_udc *dev) -{ - dev->pdata->phy_control(1); - - /*USB PHY0 Enable */ - printf("USB PHY0 Enable\n"); - - /* Enable PHY */ - writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); - - if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ - writel((readl(&phy->phypwr) - &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - else /* C110 GONI */ - writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - - if (s5p_cpu_id == 0x4412) - writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | - EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, - &phy->phyclk); /* PLL 24Mhz */ - else - writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ - - writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) - | PHY_SW_RST0, &phy->rstcon); - udelay(10); - writel(readl(&phy->rstcon) - &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); - udelay(10); -} - -void otg_phy_off(struct s3c_udc *dev) -{ - /* reset controller just in case */ - writel(PHY_SW_RST0, &phy->rstcon); - udelay(20); - writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); - udelay(20); - - writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN - | FORCE_SUSPEND_0, &phy->phypwr); - - writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); - - writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), - &phy->phyclk); - - udelay(10000); - - dev->pdata->phy_control(0); -} +__weak void otg_phy_init(struct s3c_udc *dev) {} +__weak void otg_phy_off(struct s3c_udc *dev) {} /***********************************************************/ @@ -270,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev) debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); otg_phy_init(dev); - reconfig_usbd(); + reconfig_usbd(dev); debug_cond(DEBUG_SETUP != 0, "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n", @@ -451,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev, udc_reinit(dev); } -static void reconfig_usbd(void) +static void reconfig_usbd(struct s3c_udc *dev) { /* 2. Soft-reset OTG Core and then unreset again. */ int i; unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); + uint32_t dflt_gusbcfg; debug("Reseting OTG controller\n"); - writel(0<<15 /* PHY Low Power Clock sel*/ + dflt_gusbcfg = + 0<<15 /* PHY Low Power Clock sel*/ |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ |0x5<<10 /* Turnaround time*/ |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/ @@ -468,8 +415,12 @@ static void reconfig_usbd(void) |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/ |1<<3 /* phy i/f 0:8bit, 1:16bit*/ - |0x7<<0, /* HS/FS Timeout**/ - ®->gusbcfg); + |0x7<<0; /* HS/FS Timeout**/ + + if (dev->pdata->usb_gusbcfg) + dflt_gusbcfg = dev->pdata->usb_gusbcfg; + + writel(dflt_gusbcfg, ®->gusbcfg); /* 3. Put the OTG device core in the disconnected state.*/ uTemp = readl(®->dctl); @@ -854,9 +805,7 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) dev->pdata = pdata; - phy = (struct s3c_usbotg_phy *)pdata->regs_phy; reg = (struct s3c_usbotg_reg *)pdata->regs_otg; - usb_phy_ctrl = pdata->usb_phy_ctrl; /* regs_otg = (void *)pdata->regs_otg; */ diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/s3c_udc_otg_phy.c new file mode 100644 index 0000000000..f13cb8910a --- /dev/null +++ b/drivers/usb/gadget/s3c_udc_otg_phy.c @@ -0,0 +1,101 @@ +/* + * drivers/usb/gadget/s3c_udc_otg.c + * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * + * Copyright (C) 2008 for Samsung Electronics + * + * BSP Support for Samsung's UDC driver + * available at: + * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git + * + * State machine bugfixes: + * Marek Szyprowski <m.szyprowski@samsung.com> + * + * Ported to u-boot: + * Marek Szyprowski <m.szyprowski@samsung.com> + * Lukasz Majewski <l.majewski@samsumg.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <linux/list.h> +#include <malloc.h> + +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> + +#include <asm/byteorder.h> +#include <asm/unaligned.h> +#include <asm/io.h> + +#include <asm/mach-types.h> + +#include "regs-otg.h" +#include <usb/lin_gadget_compat.h> + +#include <usb/s3c_udc.h> + +void otg_phy_init(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + dev->pdata->phy_control(1); + + /* USB PHY0 Enable */ + printf("USB PHY0 Enable\n"); + + /* Enable PHY */ + writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); + + if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ + writel((readl(&phy->phypwr) + &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + else /* C110 GONI */ + writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + + if (s5p_cpu_id == 0x4412) + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | + EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, + &phy->phyclk); /* PLL 24Mhz */ + else + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | + CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ + + writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) + | PHY_SW_RST0, &phy->rstcon); + udelay(10); + writel(readl(&phy->rstcon) + &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); + udelay(10); +} + +void otg_phy_off(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + /* reset controller just in case */ + writel(PHY_SW_RST0, &phy->rstcon); + udelay(20); + writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); + udelay(20); + + writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN + | FORCE_SUSPEND_0, &phy->phypwr); + + writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); + + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), + &phy->phyclk); + + udelay(10000); + + dev->pdata->phy_control(0); +} diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 4f69b22a25..9c54b462c4 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -551,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev) debug_cond(DEBUG_ISR, "\t\tOTG core got reset (%d)!!\n", reset_available); - reconfig_usbd(); + reconfig_usbd(dev); dev->ep0state = WAIT_FOR_SETUP; reset_available = 0; s3c_udc_pre_setup(); diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index b4330876f8..7fe79efc17 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -13,18 +13,18 @@ #include "ehci.h" #if defined(CONFIG_R8A7740) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xC6700000 }; #elif defined(CONFIG_R8A7790) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xEE080000, /* USB0 (EHCI) */ 0xEE0A0000, /* USB1 */ 0xEE0C0000, /* USB2 */ }; #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ defined(CONFIG_R8A7794) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xEE080000, /* USB0 (EHCI) */ 0xEE0C0000, /* USB1 */ }; @@ -53,7 +53,7 @@ int ehci_hcd_stop(int index) if (!i) printf("error : ehci(%d) reset failed.\n", index); - if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) + if (index == (ARRAY_SIZE(usb_base_address) - 1)) setbits_le32(SMSTPCR7, SMSTPCR703); return 0; diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 4befd57454..cc9a8fa71e 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -10,16 +10,14 @@ */ #include <asm/arch/clock.h> +#include <asm/arch/cpu.h> #include <asm/gpio.h> #include <asm/io.h> #include <common.h> #include "ehci.h" -#define SUNXI_USB1_IO_BASE 0x01c14000 -#define SUNXI_USB2_IO_BASE 0x01c1c000 - #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 -#define SUNXI_USB_CSR 0x01c13404 +#define SUNXI_USB_CSR 0x404 #define SUNXI_USB_PASSBY_EN 1 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) @@ -32,25 +30,28 @@ static struct sunxi_ehci_hcd { int usb_rst_mask; int ahb_clk_mask; int gpio_vbus; - void *csr; int irq; int id; } sunxi_echi_hcd[] = { { - .usb_rst_mask = CCM_USB_CTRL_PHY1_RST, + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO, - .csr = (void *)SUNXI_USB_CSR, +#ifndef CONFIG_MACH_SUN6I .irq = 39, +#else + .irq = 72, +#endif .id = 1, }, #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { - .usb_rst_mask = CCM_USB_CTRL_PHY2_RST, + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1, - .gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO, - .csr = (void *)SUNXI_USB_CSR, +#ifndef CONFIG_MACH_SUN6I .irq = 40, +#else + .irq = 74, +#endif .id = 2, } #endif @@ -60,19 +61,32 @@ static int enabled_hcd_count; static void *get_io_base(int hcd_id) { - if (hcd_id == 1) - return (void *)SUNXI_USB1_IO_BASE; - else if (hcd_id == 2) - return (void *)SUNXI_USB2_IO_BASE; - else + switch (hcd_id) { + case 0: + return (void *)SUNXI_USB0_BASE; + case 1: + return (void *)SUNXI_USB1_BASE; + case 2: + return (void *)SUNXI_USB2_BASE; + default: return NULL; + } +} + +static int get_vbus_gpio(int hcd_id) +{ + switch (hcd_id) { + case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); + case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); + } + return -1; } static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr, int data, int len) { int j = 0, usbc_bit = 0; - void *dest = sunxi_ehci->csr; + void *dest = get_io_base(0) + SUNXI_USB_CSR; usbc_bit = 1 << (sunxi_ehci->id * 2); for (j = 0; j < len; j++) { @@ -105,7 +119,7 @@ static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci) usb_phy_write(sunxi_ehci, 0x20, 0x14, 5); /* threshold adjustment disconnect */ -#ifdef CONFIG_MACH_SUN4I +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I usb_phy_write(sunxi_ehci, 0x2a, 3, 2); #else usb_phy_write(sunxi_ehci, 0x2a, 2, 2); @@ -138,22 +152,30 @@ static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci) setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); +#ifdef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask); +#endif sunxi_usb_phy_init(sunxi_ehci); sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN); - gpio_direction_output(sunxi_ehci->gpio_vbus, 1); + if (sunxi_ehci->gpio_vbus != -1) + gpio_direction_output(sunxi_ehci->gpio_vbus, 1); } static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - gpio_direction_output(sunxi_ehci->gpio_vbus, 0); + if (sunxi_ehci->gpio_vbus != -1) + gpio_direction_output(sunxi_ehci->gpio_vbus, 0); sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN); +#ifdef CONFIG_MACH_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask); +#endif clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); } @@ -165,13 +187,17 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index]; int err; + sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id); + /* enable common PHY only once */ if (index == 0) setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); - err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus"); - if (err) - return err; + if (sunxi_ehci->gpio_vbus != -1) { + err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus"); + if (err) + return err; + } sunxi_ehci_enable(sunxi_ehci); @@ -197,9 +223,11 @@ int ehci_hcd_stop(int index) sunxi_ehci_disable(sunxi_ehci); - err = gpio_free(sunxi_ehci->gpio_vbus); - if (err) - return err; + if (sunxi_ehci->gpio_vbus != -1) { + err = gpio_free(sunxi_ehci->gpio_vbus); + if (err) + return err; + } /* disable common PHY only once, for the last enabled hcd */ if (enabled_hcd_count == 1) diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 433e703da8..79aecd414e 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -47,9 +47,9 @@ struct ehci_hcor { uint32_t or_usbcmd; #define CMD_PARK (1 << 11) /* enable "park" */ #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ -#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_LRESET (1 << 7) /* partial reset */ -#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ +#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ +#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_PSE (1 << 4) /* periodic schedule enable */ #define CMD_RESET (1 << 1) /* reset HC not bus */ #define CMD_RUN (1 << 0) /* start/stop HC */ diff --git a/include/axp221.h b/include/axp221.h new file mode 100644 index 0000000000..e3b4409a95 --- /dev/null +++ b/include/axp221.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * + * X-Powers AXP221 Power Management IC driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP221_CHIP_ADDR 0x68 +#define AXP221_CTRL_ADDR 0x3e +#define AXP221_INIT_DATA 0x3e + +#define AXP221_CHIP_ID 0x03 +#define AXP221_OUTPUT_CTRL1 0x10 +#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) +#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP221_OUTPUT_CTRL2 0x12 +#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP221_OUTPUT_CTRL2_DCDC1_EN (1 << 7) +#define AXP221_OUTPUT_CTRL3 0x13 +#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7) +#define AXP221_DLDO1_CTRL 0x15 +#define AXP221_DLDO2_CTRL 0x16 +#define AXP221_DLDO3_CTRL 0x17 +#define AXP221_DLDO4_CTRL 0x18 +#define AXP221_DCDC1_CTRL 0x21 +#define AXP221_DCDC2_CTRL 0x22 +#define AXP221_DCDC3_CTRL 0x23 +#define AXP221_DCDC4_CTRL 0x24 +#define AXP221_DCDC5_CTRL 0x25 +#define AXP221_ALDO1_CTRL 0x28 +#define AXP221_ALDO2_CTRL 0x28 +#define AXP221_ALDO3_CTRL 0x2a + +int axp221_set_dcdc1(unsigned int mvolt); +int axp221_set_dcdc2(unsigned int mvolt); +int axp221_set_dcdc3(unsigned int mvolt); +int axp221_set_dcdc4(unsigned int mvolt); +int axp221_set_dcdc5(unsigned int mvolt); +int axp221_set_dldo1(unsigned int mvolt); +int axp221_set_dldo2(unsigned int mvolt); +int axp221_set_dldo3(unsigned int mvolt); +int axp221_set_dldo4(unsigned int mvolt); +int axp221_set_aldo1(unsigned int mvolt); +int axp221_set_aldo2(unsigned int mvolt); +int axp221_set_aldo3(unsigned int mvolt); +int axp221_init(void); diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 89ba14e05d..41631c72e9 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -59,6 +59,7 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index d31e674eac..f780f8b5bb 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -20,6 +20,8 @@ #ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H +#define CONFIG_SYS_GENERIC_BOARD + /* We got removed from Linux mach-types.h */ #define MACH_TYPE_KM_KIRKWOOD 2255 diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h deleted file mode 100644 index a317782dbe..0000000000 --- a/include/configs/mcc200.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MCC200 1 /* MCC200 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration) - * 0xFFF00000 boot high - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - * - * To select console on the one of 8 external UARTs, - * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, - * or as 5, 6, 7, or 8 for the second Quad UART. - * COM11, COM12, COM13, COM14 are located on the second Quad UART. - * - * CONFIG_PSC_CONSOLE must be undefined in this case. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#ifdef CONFIG_CONSOLE_COM12 -#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ -#else -#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ -#endif -#else -/* PRS200 configuration: */ -#undef CONFIG_QUART_CONSOLE -#endif /* CONFIG_PRS200 */ -/* - * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 - * and undefine CONFIG_QUART_CONSOLE. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ -#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ -#else -/* PRS200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII 1 - -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -/* automatic software updates (see board/mcc200/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_USB - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#ifdef CONFIG_PRS200 -# define CONFIG_SYS__BOARDNAME "prs200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyS0" -#else -# define CONFIG_SYS__BOARDNAME "mcc200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" -#endif - -/* Network */ -#define CONFIG_ETHADDR 00:17:17:ff:00:00 -#define CONFIG_IPADDR 10.76.9.29 -#define CONFIG_SERVERIP 10.76.9.1 - -#include <version.h> /* For U-Boot version */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootver=" U_BOOT_VERSION "\0" \ - "netdev=eth0\0" \ - "hostname=" CONFIG_SYS__BOARDNAME "\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/mtdblock2 " \ - "rootfstype=cramfs\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate} " \ - "ubootver=${ubootver} board=${board}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ - "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ - "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "kernel_addr=0xFC0C0000\0" \ - "update=protect off ${text_base} +${filesize};" \ - "era ${text_base} +${filesize};" \ - "cp.b 200000 ${text_base} ${filesize}\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -/* #define CONFIG_MPC5xxx_FEC 1 */ -/* #define CONFIG_MPC5xxx_FEC_MII100 */ -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 1 - -/* - * LCD Splash Screen - */ -#if !defined(CONFIG_PRS200) -#define CONFIG_LCD 1 -#define CONFIG_PROGRESSBAR 1 -#endif - -#if defined(CONFIG_LCD) -#define CONFIG_SPLASH_SCREEN 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME -#endif - -/* - * GPIO configuration - */ -/* 0x10000004 = 32MB SDRAM */ -/* 0x90000004 = 64MB SDRAM */ -#if defined(CONFIG_LCD) -/* set PSC2 in UART mode */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 -#else -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x00001000 -#define CONFIG_SYS_CS2_CFG 0x1d300 - -/* Second Quad UART @0x80010000 */ -#define CONFIG_SYS_CS1_START 0x80010000 -#define CONFIG_SYS_CS1_SIZE 0x00001000 -#define CONFIG_SYS_CS1_CFG 0x1d300 - -/* Leica - build revision resistors */ -/* -#define CONFIG_SYS_CS3_START 0x80020000 -#define CONFIG_SYS_CS3_SIZE 0x00000004 -#define CONFIG_SYS_CS3_CFG 0x1d300 -*/ - -/* - * Select one of quarts as a default - * console. If undefined - PSC console - * wil be default - */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * QUART Expanders support - */ -#if defined(CONFIG_QUART_CONSOLE) -/* - * We'll use NS16550 chip routines, - */ -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL 1 -#define CONFIG_CONS_INDEX 1 -/* - * To achieve necessary offset on SC16C554 - * A0-A2 (register select) pins with NS16550 - * functions (in struct NS16550), REG_SIZE - * should be 4, because A0-A2 pins are connected - * to DA2-DA4 address bus lines. - */ -#define CONFIG_SYS_NS16550_REG_SIZE 4 -/* - * LocalPlus Bus already inited in cpu_init_f(), - * so can work with QUART's chip selects. - * One of four SC16C554 UARTs is selected with - * A3-A4 (DA5-DA6) lines. - */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) -#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#else -#error "Wrong QUART expander number." -#endif - -/* - * SC16C554 chip's external crystal oscillator frequency - * is 7.3728 MHz - */ -#define CONFIG_SYS_NS16550_CLK 7372800 -#endif /* CONFIG_QUART_CONSOLE */ -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "432" -#define CONFIG_SILENT_CONSOLE 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3633a355bd..dfa2e07948 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -281,6 +281,7 @@ #define CONFIG_SYS_MAX_I2C_BUS 7 #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_CMD_USB_MASS_STORAGE diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 4b30d148c3..e7bace4345 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -181,6 +181,7 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED /* diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index a2469eb60c..655025c912 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -14,6 +14,7 @@ #undef CONFIG_BOARD_COMMON #undef CONFIG_USB_GADGET #undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #undef CONFIG_CMD_USB_MASS_STORAGE #undef CONFIG_REVISION_TAG #undef CONFIG_CMD_THOR_DOWNLOAD diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcdfbe..c436fdaf52 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -37,7 +37,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 + */ +#endif + +/* * Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) @@ -141,6 +160,33 @@ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif + /* + * I2C support + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_SYS_I2C_BUS_MAX 4 +#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS +#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS +#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS +#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS +/* Using standard mode which the speed up to 100Kb/s */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 +#define CONFIG_SYS_I2C_SPEED3 100000 +/* Address of device when used as slave */ +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_SYS_I2C_SLAVE1 0x02 +#define CONFIG_SYS_I2C_SLAVE2 0x02 +#define CONFIG_SYS_I2C_SLAVE3 0x02 +#ifndef __ASSEMBLY__ +/* Clock supplied to I2C controller in unit of MHz */ +unsigned int cm_get_l4_sp_clk_hz(void); +#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) +#endif +#define CONFIG_CMD_I2C + /* * Serial Driver */ @@ -172,6 +218,34 @@ #endif /* + * USB Gadget (DFU, UMS) + */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_MASS_STORAGE + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM +#ifndef CONFIG_G_DNL_MANUFACTURER +#define CONFIG_G_DNL_MANUFACTURER "Altera" +#endif +#endif + +/* * U-Boot environment */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 942738c138..c3d958cb30 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -42,7 +42,7 @@ /* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_BOOTCOMMAND "run ramboot" #else diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index e0ec52dcde..7b857405e9 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -18,14 +18,7 @@ #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI - #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO -#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6) -#endif -#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO -#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3) -#endif #endif /* diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index b7144745c9..1b73852799 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -14,9 +14,15 @@ /* * A31 specific configuration */ +#define CONFIG_CLK_FULL_SPEED 1008000000 #define CONFIG_SYS_PROMPT "sun6i# " +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 0193826a9d..ea40790322 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -19,14 +19,7 @@ #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI - #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO -#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6) -#endif -#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO -#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3) -#endif #endif #define CONFIG_ARMV7_VIRT 1 diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h new file mode 100644 index 0000000000..191f2a5f30 --- /dev/null +++ b/include/configs/zynq_zybo.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2012 Xilinx + * (C) Copyright 2014 Digilent Inc. + * + * Configuration for Zynq Development Board - ZYBO + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZYBO_H +#define __CONFIG_ZYNQ_ZYBO_H + +#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +/* Define ZYBO PS Clock Frequency to 50MHz */ +#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL + +#include <configs/zynq-common.h> + +#endif /* __CONFIG_ZYNQ_ZYBO_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000000..3f04908fb8 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif diff --git a/include/lcd.h b/include/lcd.h index ea5860c861..020d8800e9 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -250,7 +250,7 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; -#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ +#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */ extern vidinfo_t panel_info; diff --git a/include/usb.h b/include/usb.h index 9d0d04dd8e..d3c741597c 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,6 +11,8 @@ #include <usb_defs.h> #include <linux/usb/ch9.h> +#include <asm/cache.h> +#include <part.h> /* * The EHCI spec says that we must align to at least 32 bytes. However, diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 70e48f88ee..7f49a4e2d5 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -108,5 +108,6 @@ struct s3c_plat_otg_data { unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; + unsigned int usb_gusbcfg; }; #endif diff --git a/scripts/binutils-version.sh b/scripts/binutils-version.sh index d4d9eb4361..d4d9eb4361 100644..100755 --- a/scripts/binutils-version.sh +++ b/scripts/binutils-version.sh diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index e8c94d390b..e8c94d390b 100644..100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh diff --git a/scripts/gcc-stack-usage.sh b/scripts/gcc-stack-usage.sh index 27ac928969..27ac928969 100644..100755 --- a/scripts/gcc-stack-usage.sh +++ b/scripts/gcc-stack-usage.sh diff --git a/scripts/gcc-version.sh b/scripts/gcc-version.sh index debecb5561..debecb5561 100644..100755 --- a/scripts/gcc-version.sh +++ b/scripts/gcc-version.sh diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh index 9d2a4c585e..9d2a4c585e 100644..100755 --- a/scripts/kconfig/lxdialog/check-lxdialog.sh +++ b/scripts/kconfig/lxdialog/check-lxdialog.sh diff --git a/scripts/kconfig/streamline_config.pl b/scripts/kconfig/streamline_config.pl index 9cb8522d8d..9cb8522d8d 100644..100755 --- a/scripts/kconfig/streamline_config.pl +++ b/scripts/kconfig/streamline_config.pl diff --git a/scripts/mkmakefile b/scripts/mkmakefile index 84af27bf0f..84af27bf0f 100644..100755 --- a/scripts/mkmakefile +++ b/scripts/mkmakefile diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 70f3a5df6f..70f3a5df6f 100644..100755 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh |
