diff options
| -rw-r--r-- | README | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c | 19 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
| -rw-r--r-- | board/sunxi/Kconfig | 28 | ||||
| -rw-r--r-- | board/sunxi/MAINTAINERS | 1 | ||||
| -rw-r--r-- | board/sunxi/board.c | 22 | ||||
| -rw-r--r-- | board/sunxi/dram_sun4i_auto.c | 3 | ||||
| -rw-r--r-- | board/sunxi/dram_sun5i_auto.c | 3 | ||||
| -rw-r--r-- | common/console.c | 40 | ||||
| -rw-r--r-- | configs/ga10h_v1_1_defconfig | 29 | ||||
| -rw-r--r-- | doc/README.scrapyard | 8 | ||||
| -rw-r--r-- | drivers/video/sunxi_display.c | 18 | ||||
| -rw-r--r-- | include/configs/sunxi-common.h | 8 |
20 files changed, 166 insertions, 50 deletions
@@ -948,6 +948,9 @@ The following options need to be configured: bytes are output before the console is initialised, the earlier bytes are discarded. + Note that when printing the buffer a copy is made on the + stack so CONFIG_PRE_CON_BUF_SZ must fit on the stack. + 'Sane' compilers will generate smaller code if CONFIG_PRE_CON_BUF_SZ is a power of 2 diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6718ae2205..e6730c0dfa 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -68,6 +68,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index c736fa3b47..f7b4915037 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -508,7 +508,7 @@ static void mctl_ddr3_initialize(void) /* * Perform impedance calibration on the DRAM controller side of the wire. */ -static void mctl_set_impedance(u32 zq, u32 odt_en) +static void mctl_set_impedance(u32 zq, bool odt_en) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; u32 reg_val; @@ -556,7 +556,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); /* Set I/O configure register */ - writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr); + writel(DRAM_IOCR_ODT_EN, &dram->iocr); } static unsigned long dramc_init_helper(struct dram_para *para) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c index 3d7964d1af..165c052122 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -26,12 +26,14 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> static const struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, .type = 3, .zq = CONFIG_DRAM_ZQ, - .odt_en = 1, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .odt_correction = CONFIG_DRAM_ODT_CORRECTION, .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ .mr0 = 6736, @@ -97,7 +99,6 @@ static void mctl_init(u32 *bus_width) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - int correction; if (dram_para.tpr13 & 0x20) writel(0x40b, &mctl_phy->dcr); @@ -138,7 +139,7 @@ static void mctl_init(u32 *bus_width) writel(0x01000081, &mctl_phy->dtcr); - if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { + if (dram_para.clock <= 240 || !dram_para.odt_en) { clrbits_le32(&mctl_phy->dx0gcr, 0x600); clrbits_le32(&mctl_phy->dx1gcr, 0x600); } @@ -251,13 +252,11 @@ static void mctl_init(u32 *bus_width) } else *bus_width = 16; - correction = (dram_para.odt_en >> 8) & 0xff; - if (correction) { - if (dram_para.odt_en & 0x80000000) - correction = -correction; - - mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); - mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); + if (dram_para.odt_correction) { + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, + dram_para.odt_correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, + dram_para.odt_correction); } mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index d03f00dc4b..ebba438319 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -14,12 +14,12 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ #define DRAM_CLK_MUL 2 #define DRAM_CLK_DIV 4 #define DRAM_SIGMA_DELTA_ENABLE 1 -#define DRAM_ODT_EN 0 struct dram_para { u8 cs1; @@ -195,7 +195,7 @@ static int mctl_train_dram(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; mctl_data_train_cfg(para); - mctl_set_pir(0x1f3); + mctl_set_pir(0x5f3); return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; } @@ -215,7 +215,7 @@ static int mctl_channel_init(struct dram_para *para) clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); /* Set ODT */ - if ((CONFIG_DRAM_CLK > 400) && DRAM_ODT_EN) { + if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { setbits_le32(DXnGCR0(0), 0x3 << 9); setbits_le32(DXnGCR0(1), 0x3 << 9); } else { diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index bacd70adf6..6465f215e8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -331,6 +331,9 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_LCD1 5 #define AHB_RESET_OFFSET_LCD0 4 +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + /* apb2 reset */ #define APB2_RESET_UART_SHIFT (16) #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 5e94253203..ae954171f3 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -363,6 +363,11 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) +#else +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ +#endif #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) @@ -372,8 +377,15 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_LVDS_ANA0 0x40040320 +#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) +#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) +#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) +#else #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#endif #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h index 40c385a5bc..139e3366a6 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -164,8 +164,7 @@ struct dram_para { #define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ -#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) -#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) +#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0)) #define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) #define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h index 06adee2723..316a3338f8 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h @@ -19,6 +19,7 @@ struct dram_para { u32 type; u32 zq; u32 odt_en; + s32 odt_correction; u32 para1; u32 para2; u32 mr0; diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 59d8210e88..148123a87f 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -155,6 +155,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_TWI2 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 +#define SUN8I_GPB_UART2 2 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5b6cc5c82f..a6bbf6e786 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -91,6 +91,13 @@ config DRAM_ZQ ---help--- Set the dram zq value. +config DRAM_ODT_EN + bool "sunxi dram odt enable" + default n if !MACH_SUN8I_A23 + default y if MACH_SUN8I_A23 + ---help--- + Select this to enable dram odt (on die termination). + if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I config DRAM_EMR1 int "sunxi dram emr1 value" @@ -99,13 +106,6 @@ config DRAM_EMR1 ---help--- Set the dram controller emr1 value. -config DRAM_ODT_EN - int "sunxi dram odt_en value" - default 0 - ---help--- - Set the dram controller odt_en parameter. This can be used to - enable/disable the ODT feature. - config DRAM_TPR3 hex "sunxi dram tpr3 value" default 0 @@ -166,6 +166,17 @@ endchoice endif +if MACH_SUN8I_A23 +config DRAM_ODT_CORRECTION + int "sunxi dram odt correction value" + default 0 + ---help--- + Set the dram odt correction value (range -255 - 255). In allwinner + fex files, this option is found in bits 8-15 of the u32 odt_en variable + in the [dram] section. When bit 31 of the odt_en variable is set + then the correction is negative. Usually the value for this is 0. +endif + config SYS_CLK_FREQ default 912000000 if MACH_SUN7I default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I @@ -544,6 +555,9 @@ config GMAC_TX_DELAY ---help--- Set the GMAC Transmit Clock Delay Chain value. +config SYS_MALLOC_CLEAR_ON_INIT + default n + config NET default y diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 339904b84f..a650554938 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -37,6 +37,7 @@ F: configs/Orangepi_mini_defconfig F: configs/qt840a_defconfig F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h +F: configs/ga10h_v1_1_defconfig F: configs/Ippo_q8h_v1_2_defconfig F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d9f7691373..5f79cc1bb8 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -476,7 +476,27 @@ static struct musb_hdrc_platform_data musb_plat = { #ifdef CONFIG_USB_GADGET int g_dnl_board_usb_cable_connected(void) { - return sunxi_usbc_vbus_detect(0); + return sunxi_usb_phy_vbus_detect(0); +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + unsigned long long serial; + + serial_string = getenv("serial#"); + + if (serial_string) { + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (unsigned int) (serial >> 32); + serialnr->low = (unsigned int) (serial & 0xffffffff); + } else { + serialnr->high = 0; + serialnr->low = 0; + } } #endif diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 09e0c9ae2e..149bb51dcb 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -1,5 +1,6 @@ #include <common.h> #include <asm/arch/dram.h> +#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, @@ -9,7 +10,7 @@ static struct dram_para dram_para = { .io_width = 0, .bus_width = 0, .zq = CONFIG_DRAM_ZQ, - .odt_en = CONFIG_DRAM_ODT_EN, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), .size = 0, #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC .cas = 6, diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index 660b18ebbd..596a206072 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -2,6 +2,7 @@ #include <common.h> #include <asm/arch/dram.h> +#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, @@ -12,7 +13,7 @@ static struct dram_para dram_para = { .io_width = 0, .bus_width = 0, .zq = CONFIG_DRAM_ZQ, - .odt_en = CONFIG_DRAM_ODT_EN, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), .size = 0, #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC .cas = 9, diff --git a/common/console.c b/common/console.c index 3f25e76fe7..00582224d4 100644 --- a/common/console.c +++ b/common/console.c @@ -200,15 +200,15 @@ static void console_putc(int file, const char c) } #ifdef CONFIG_PRE_CONSOLE_BUFFER -static void console_putc_noserial(int file, const char c) +static void console_puts_noserial(int file, const char *s) { int i; struct stdio_dev *dev; for (i = 0; i < cd_count[file]; i++) { dev = console_devices[file][i]; - if (dev->putc != NULL && strcmp(dev->name, "serial") != 0) - dev->putc(dev, c); + if (dev->puts != NULL && strcmp(dev->name, "serial") != 0) + dev->puts(dev, s); } } #endif @@ -251,10 +251,10 @@ static inline void console_putc(int file, const char c) } #ifdef CONFIG_PRE_CONSOLE_BUFFER -static inline void console_putc_noserial(int file, const char c) +static inline void console_puts_noserial(int file, const char *s) { if (strcmp(stdio_devices[file]->name, "serial") != 0) - stdio_devices[file]->putc(stdio_devices[file], c); + stdio_devices[file]->puts(stdio_devices[file], s); } #endif @@ -425,22 +425,26 @@ static void pre_console_puts(const char *s) static void print_pre_console_buffer(int flushpoint) { - unsigned long i = 0; - char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR; + unsigned long in = 0, out = 0; + char *buf_in = (char *)CONFIG_PRE_CON_BUF_ADDR; + char buf_out[CONFIG_PRE_CON_BUF_SZ + 1]; if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ) - i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ; + in = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ; - while (i < gd->precon_buf_idx) - switch (flushpoint) { - case PRE_CONSOLE_FLUSHPOINT1_SERIAL: - putc(buffer[CIRC_BUF_IDX(i++)]); - break; - case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL: - console_putc_noserial(stdout, - buffer[CIRC_BUF_IDX(i++)]); - break; - } + while (in < gd->precon_buf_idx) + buf_out[out++] = buf_in[CIRC_BUF_IDX(in++)]; + + buf_out[out] = 0; + + switch (flushpoint) { + case PRE_CONSOLE_FLUSHPOINT1_SERIAL: + puts(buf_out); + break; + case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL: + console_puts_noserial(stdout, buf_out); + break; + } } #else static inline void pre_console_putc(const char c) {} diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig new file mode 100644 index 0000000000..3eca0237f3 --- /dev/null +++ b/configs/ga10h_v1_1_defconfig @@ -0,0 +1,29 @@ +# The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand, +# sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot. +# +# This defconfig is for the v1.1 pcb with an a33 soc. +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" +CONFIG_VIDEO_LCD_PANEL_LVDS=y +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH7" +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" +#CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=432 +# zq = 0x3bbb +CONFIG_DRAM_ZQ=15291 +CONFIG_DRAM_ODT_EN=y +# Wifi power +CONFIG_AXP221_DLDO1_VOLT=3300 +# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP +CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index aa2b07b4ba..a62bd0ba4c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,9 +12,11 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -afeb9260 arm arm926ejs - - Sergey Lapin <slapin@ossfans.org> -tny_a9260 arm arm926ejs - - Albin Tonnerre <albin.tonnerre@free-electrons.com> -sbc35_a9g20 arm arm926ejs - - Albin Tonnerre <albin.tonnerre@free-electrons.com> +afeb9260 arm arm926ejs f6b42c14 2015-05-13 Sergey Lapin <slapin@ossfans.org> +tny_a9260 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com> +sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com> +sc3 powerpc ppc4xx 27e72156 2015-05-10 Heiko Schocher <hs@denx.de> +T4240EMU powerpc mpc85xx 7fc63cca 2015-05-05 York Sun <yorksun@freescale.com> korat powerpc ppc4xx 5043045d 2015-03-17 Larry Johnson <lrj@acm.org> galaxy5200 powerpc mpc5xxx 41eb4e5c 2015-03-17 Eric Millbrandt <emillbrandt@dekaresearch.com> W7OLMC powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen <etheisen@mindspring.com> diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 48dbdf5795..269083b666 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -558,8 +558,12 @@ static void sunxi_lcdc_init(void) /* Clock on */ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); #ifdef CONFIG_VIDEO_LCD_IF_LVDS +#ifdef CONFIG_SUNXI_GEN_SUN6I + setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS); +#else setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST); #endif +#endif /* Init lcdc */ writel(0, &lcdc->ctrl); /* Disable tcon */ @@ -582,6 +586,16 @@ static void sunxi_lcdc_enable(void) #ifdef CONFIG_VIDEO_LCD_IF_LVDS setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); +#ifdef CONFIG_SUNXI_GEN_SUN6I + udelay(2); /* delay at least 1200 ns */ + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); + udelay(2); /* delay at least 1200 ns */ + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); + if (sunxi_display.depth == 18) + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); + else + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); +#else setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); udelay(2); /* delay at least 1200 ns */ setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); @@ -589,6 +603,7 @@ static void sunxi_lcdc_enable(void) setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); #endif +#endif } static void sunxi_lcdc_panel_enable(void) @@ -706,7 +721,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, #endif #ifdef CONFIG_VIDEO_LCD_IF_LVDS val = (sunxi_display.depth == 18) ? 1 : 0; - writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf); + writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) | + SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf); #endif if (sunxi_display.depth == 18 || sunxi_display.depth == 16) { diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 2d6b815739..d829899c07 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -66,6 +66,9 @@ # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif +/* CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 @@ -98,6 +101,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG /* mmc config */ #if !defined(CONFIG_UART0_PORT_F) @@ -240,6 +244,8 @@ extern int soft_i2c_gpio_scl; #endif #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) +#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" #else @@ -335,7 +341,7 @@ extern int soft_i2c_gpio_scl; /* Enable pre-console buffer to get complete log on the VGA console */ #define CONFIG_PRE_CONSOLE_BUFFER -#define CONFIG_PRE_CON_BUF_SZ (1024 * 1024) +#define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ /* Use the room between the end of bootm_size and the framebuffer */ #define CONFIG_PRE_CON_BUF_ADDR 0x4f000000 |
