diff options
243 files changed, 10559 insertions, 3462 deletions
@@ -1,3 +1,1059 @@ +commit 43ddd9c820fec44816188f53346b464e20b3142d +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Sat Mar 22 14:23:49 2008 -0400 + + Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T + + These defines embedded the u-boot env variables and/or the bd_t structure + in the fdt blob. The conclusion of discussion on the u-boot email list + was that embedding these in the fdt blob is not useful: there are better + ways of passing the data (in fact, the fdt blob itself replaces the + bd_t struct). + + The only board that enables these is the stxxtc and they don't appear + to be used by linux. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + +commit 22ed2285743359fd1fe73e411dff914b2256e68f +Author: Stefan Roese <sr@denx.de> +Date: Mon Mar 17 10:49:25 2008 +0100 + + rtc: Remove 2nd reference to max6900.o in drivers/rtc/Makefile + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 1bb707c39a0833e91d9f797dd862aaaaf4af264d +Author: Kyungmin Park <kmpark@infradead.org> +Date: Mon Mar 17 08:54:06 2008 +0900 + + Add Flex-OneNAND booting support + + Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array + using a NOR Flash interface. This on-chip integration enables system designers + to reduce external system logic and use high-density NAND Flash + in applications that would otherwise have to use more NOR components. + + Flex-OneNAND enables users to configure to partition it into SLC and MLC areas + in more flexible way. While MLC area of Flex-OneNAND can be used to store data + that require low reliability and high density, SLC area of Flex-OneNAND + to store data that need high reliability and high performance. Flex-OneNAND + can let users take advantage of storing these two different types of data + into one chip, which is making Flex-OneNAND more cost- and space-effective. + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit c512389cc4a10253249271ff6c887c6dab1f0db2 +Author: AndrĂ© Schwarz <andre.schwarz@matrix-vision.de> +Date: Thu Mar 13 13:50:52 2008 +0100 + + MPC5200: support setup without FEC + + Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is + defined. Systems without FEC, i.e. no FEC node in DTB, should be possible. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Acked-by: Grant Likely <grant.likely@secretlab.ca> + +commit aa3511e422946041ef626f80a05ae5e8bfc700e6 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 18:05:46 2008 -0600 + + FSL: Move board/mpc8266ads under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 7f1d846e5c5754449c286587d099d85246062772 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 18:05:47 2008 -0600 + + FSL: Move board/mpc7448hpc2 under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit b7e24d283e34727c2a6cdfdac2e09a426c579b73 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 18:05:45 2008 -0600 + + FSL: Move board/mpc8260ads under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 6a8a5dc4759867c45aa95580deb8bf26669a5d97 +Author: goda.yusuke <goda.yusuke@renesas.com> +Date: Wed Mar 5 17:08:33 2008 +0900 + + net: Add support AX88796L ethernet device + + AX88796L is device of NE2000 compatible. + This patch support AX88796L ethernet device. + + Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> + Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit e0a6140dd381e1eed1ada2291166ef2616d8822b +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Mar 25 22:50:41 2008 +0100 + + ne2000 driver: change #ifdef to Makefile conditional compilation + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit e710185aae90c64d39c2d453e40e58ceefe4f250 +Author: goda.yusuke <goda.yusuke@renesas.com> +Date: Wed Mar 5 17:08:20 2008 +0900 + + net: Divided code of NE2000 ethernet driver + + There are more devices of the NE2000 base. + A present code is difficult for us to support more devices. + To support more NE2000 clone devices, separated the function. + + Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> + Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 395bce4f59a507a60a475f7ee46bed47de9482df +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sun Feb 24 23:58:13 2008 -0500 + + net/Blackfin: move on-chip MAC driver into drivers/net/ + + The Blackfin on-chip MAC driver was being managed in the BF537-STAMP board + directory, but it is not board specific, so relocate it to the drivers dir + so that other Blackfin ports can utilize it. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 8a30b4700942f37495d2e67f5998cdffb6e3ba8a +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sun Feb 24 23:52:35 2008 -0500 + + smc91111: use SSYNC() rather than asm(ssync) for Blackfin + + Since the "ssync" instruction may have hardware anomalies associated with + it, have the smc91111 driver use the SSYNC macro rather than invoking it + directly. We workaround all the anomalies via this macro. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 77ff7b7444ceb8022b46114f3d0b6d18e2fd1138 +Author: Bryan O'Donoghue <bodonoghue@codehermit.ie> +Date: Sun Feb 17 22:57:47 2008 +0000 + + 8xx: Update OF support on 8xx + + This patch does some shifting around of OF support on 8xx. + + Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie> + +commit 9c666a7db0b2285a270c68810889ce7d5dba304b +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Feb 15 15:16:18 2008 -0600 + + ppc: Allow boards to specify how much memory they can map + + For historical reasons we limited the stack to 256M because some boards + could only map that much via BATS. However newer boards are capable of + mapping more memory (for example 85xx is capble of doing up to 2G). + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit a6f5f317cd074bbbfa2aab4fca05904c811c19fb +Author: Bryan O'Donoghue <bodonoghue@codehermit.ie> +Date: Fri Feb 15 01:05:58 2008 +0000 + + 8xx : Add OF support to Adder875 board port - resubmit + + Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie> + +commit d058698fd2d9f769ff38ac53c8708b3fdd314f2d +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Feb 14 20:44:42 2008 -0600 + + Add setexpr command + + Add a simple expr style command that will set an env variable as the result + of the command. This allows us to do simple math in shell. The following + operations are supported: &, |, ^, +, -, *, /. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 3f105faa64b9826e088711fdfcaa70cb1230397a +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 17:27:48 2008 -0600 + + FSL: Move board/mpc7448hpc2 under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 449c703374a8868453425e15da7e2f76221b72e4 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 17:21:43 2008 -0600 + + FSL: Move board/mpc8266ads under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 5863577989ad689427bb750107e9a75f1c1645d2 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Mar 5 16:41:41 2008 -0600 + + FSL: Move board/mpc8260ads under board/freescale + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 8a773983957ee6c4aa344469b742f29c7d26afbd +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:08 2008 +0900 + + [MIPS] Move gth2_config from ARM section to MIPS + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 373b16fc0c5ae34d28b9027f809ae3cbf45cdd15 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit d98e348e2ed5aab8f7a6471ff628ab0688b8a459 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] Fix dcache_status() + + You can't judge UNCACHED by Config.K0 LSB. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit b0c66af53ec9385ac2d1cc2e5d7d1ecdc81caf34 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] Introduce _machine_restart + + Handles machine specific functions by using weak functions. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit decaba6f5cf386d569ac3997bebb871b966c6b18 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] Cleanup CP0 Status initialization + + Add setup_c0_status from Linux. For the moment we disable interrupts, set + CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for + reset-time configuration and will work well across most processors. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit d43d43ef2845af309c25a64bb9c2c5fb3261bc23 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] Initialize CP0 Cause before setting up CP0 Status register + + Without this change, we'll be suffering from deffered WATCH exception + once Status.EXL is cleared. Make sure Cause.WP is cleared. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 26138623230ca2bad3c78e05a65527ea70c8b688 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:07 2008 +0900 + + [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init() + + Move things to appropriate place. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit ccf8f824ef67df028dedb29f8ea5d71a5a88d895 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:06 2008 +0900 + + [MIPS] Implement flush_cache() + + We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you + don't need to do Hit_Invalidate_I, but flush_cache() needs it since this + function is used not only in U-Boot specfic programs but also at loading + target binaries. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 2e0e5271aac917812a76c72030a2b2c6f1d3387d +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:06 2008 +0900 + + [MIPS] Fix I-/D-cache initialization loops + + Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I + again per a loop for I-cache initialization. But according to 'See MIPS + Run', we're encouraged to use three separate loops rather than combining + them *for both I- and D-cache*. This patch tries to fix this. + + In accordance with fixing above, mips_init_[id]cache are separated from + mips_cache_reset(), and rewrite cache loops are completely rewritten with + useful macros. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 1898840797c7f50799377bd5b285a8a93a82c419 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:06 2008 +0900 + + [MIPS] Replace memory clearance code with f_fill64 + + This routine fills memory with zero by 64 bytes, and is 64-bit capable. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 2f5d414ccb4024dd0992ff6b22561732dbc73590 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 21:30:06 2008 +0900 + + [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros + + This patch replaces the current function definitions with NESTED, LEAF + and END macro. They specify some more additional information about the + function; an alignment of symbol, type of symbol, stack frame usage, etc. + These information explicitly tells the assembler and the debugger about + the types of code we want to generate. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 282223a607c611425fa33f5428f8eae6636972bb +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 11:43:17 2008 +0900 + + [MIPS] asm headers' updates + + Make some asm headers adjusted to the latest Linux kernel. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Tue Mar 25 11:39:29 2008 +0900 + + [MIPS] Request for the 'mips_cache_lock()' removal + + The initial intension of having mips_cache_lock() was to use the cache + as memory for temporary stack use so that a C environment can be set up + as early as possible. + + But now mips_cache_lock() follow lowlevel_init(). We've already have the + real memory initilaized at this point, therefore we could/should use it. + No reason to lock at all. + + Other problems: + + Cache locking is not consistent across MIPS implementaions. Some imple- + mentations don't support locking at all. The style of locking varies - + some support per line locking, others per way, etc. Some parts use bits + in status registers instead of cache ops. Current mips_cache_lock() is + not necessarily general-purpose. + + And this is worthy of special mention; once U-Boot/MIPS locks the lines, + they are never get unlocked, so the code relies on whatever gets loaded + after U-Boot to re-initialize the cache and clear the locks. We're sup- + posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, + but leave the situation as it is for a long time. + + For these reasons, I proposed the removal of mips_cache_lock() from the + global start-up code. + + This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that + *things have changed*. If he wants the same behavior as before, he needs + to have CFG_INIT_RAM_LOCK_MIPS in his config file. + + If we don't have any regression report through several releases, then + we'll remove codes entirely. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + Acked-by: Andrew Dyer <amdyer@gmail.com> + +commit 0d48926c87ec96f974a6ac4034f4a2f2eab3255f +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Mon Mar 24 11:30:54 2008 +0100 + + lwmon5 SYSMON POST: fix backlight control + + If the LWMON5 config has SYSMON POST among CONFIG_POSTs which may be + run on the board, then the SYSMON POST controls the display backlight + (doesn't switch backlight ON if POST FAILED, and does switch the + backlight ON if PASSED). + + If not, then the video driver controls the display backlight (just + switch ON the backlight upon initialization). + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit ff2bdfb2c1e073f65c065011f1e18d0a130bd3d8 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Mon Mar 24 11:29:14 2008 +0100 + + lwmon5 SYSMON POST: fix handling of negative temperatures + + Fix errors in the LWMON5 Sysmon POST for negative temperatures. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Fri Mar 7 16:04:25 2008 +0900 + + pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config option + + In current source code, when the device number of PCI is 0, process PCI + bridge without fail. However, when the device number is 0, it is not PCI + always bridge. There are times when device of PCI allocates. + + When CONFIG_PCI_SKIP_HOST_BRIDGE is enable, this problem is solved when + use this patch. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + Acked-by: Stefan Roese <sr@denx.de> + +commit 86aea3eaefa248ffb9328e2b50c64720489cdbeb +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Fri Mar 21 09:18:40 2008 +0100 + + LWMON5: fix dsPIC POST + + Add test for DPIC_SYS_ERROR_REG to be zero in the LWMON5 dsPIC POST. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> --- + +commit 81a0ac62ea29f8252d0a714709d0ecfdbba2a15e +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Mar 20 22:01:38 2008 +0100 + + lwmon5 POST: remove unreachable code + + plus some coding style cleanup + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit b73a19e1609d0f705cbab8014ca17aefe89e4c76 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu Mar 20 17:56:04 2008 +0300 + + LWMON5: POST RTC fix + + Modify the RTC API to provide one a status for the time reported by + the rtc_get() function: + 0 - a reliable time is guaranteed, + < 0 - a reliable time isn't guaranteed (power fault, clock issues, + and so on). + + The RTC chip drivers are responsible for providing this info if the + corresponding chip supports such functionality. If not - always + report that the time is reliable. + + The POST RTC test was modified to detect the RTC faults utilizing + this new rtc_get() feature. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit a5cc5555ccee596908a7d8cf22a104f6b993bfd5 +Author: Martin Krause <martin.krause@tqs.de> +Date: Wed Mar 19 14:25:14 2008 +0100 + + TQM5200B: update MTD partition layout + + - insert partition for dtb blob to TQM5200B MTD layout + - set env variables dependent on the configured board + (TQM5200 or TQM5200B) + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit f0105727d132f56a21fa3ed8b162309cca6cac44 +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 19 07:09:26 2008 +0100 + + CFI: Small cleanup for FLASH_SHOW_PROGRESS + + With this patch we don't need that many #ifdef's in the code. It moves + the subtraction into the macro and defines a NOP-macro when + CONFIG_FLASH_SHOW_PROGRESS is not defined. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 9a042e9ca512beaaa2cb450274313fc477141241 +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Sat Mar 8 13:48:01 2008 -0500 + + Flash programming progress countdown. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 11abe45c48ec3485a6c1a5168ce8d79c3288adc1 +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Mon Feb 18 18:09:04 2008 +1100 + + libfdt: Remove no longer used code from fdt_node_offset_by_compatible() + + Since fdt_node_offset_by_compatible() was converted to the new + fdt_next_node() iterator, a chunk of initialization code became + redundant, but was not removed by oversight. This patch cleans it up. + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit d0ccb9b140b472039732de102fc14597eedb14df +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Mon Feb 18 18:06:31 2008 +1100 + + libfdt: Trivial cleanup for CHECK_HEADER) + + Currently the CHECK_HEADER() macro is defined local to fdt_ro.c. + However, there are a handful of functions (fdt_move, rw_check_header, + fdt_open_into) from other files which could also use it (currently + they open-code something more-or-less identical). Therefore, this + patch moves CHECK_HEADER() to libfdt_internal.h and uses it in those + places. + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit fe30a354cdbb808b5f15366a935b151a4ccee74f +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Feb 20 14:32:36 2008 -0600 + + Fix fdt boardsetup command parsing + + The introduciton of the 'fdt bootcpu' broke parsing for 'fdt boardsetup'. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 804887e6001e2f00bea11431bf34d6d472512cda +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Feb 15 03:34:36 2008 -0600 + + Add sub-commands to fdt + + fdt header - Display header info + fdt bootcpu <id> - Set boot cpuid + fdt memory <addr> <size> - Add/Update memory node + fdt rsvmem print - Show current mem reserves + fdt rsvmem add <addr> <size> - Add a mem reserve + fdt rsvmem delete <index> - Delete a mem reserves + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f84d65f9b085ffbed464d1d58e8aaa8f5a2efc07 +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Thu Feb 14 16:50:34 2008 +1100 + + libfdt: Fix NOP handling bug in fdt_add_subnode_namelen() + + fdt_add_subnode_namelen() has a bug if asked to add a subnode to a + node which has NOP tags interspersed with its properties. In this + case fdt_add_subnode_namelen() will put the new subnode before the + first NOP tag, even if there are properties after it, which will + result in an invalid blob. + + This patch fixes the bug, and adds a testcase for it. + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit ae0b5908de3b9855f8931bc9b32c9fc4962df5a9 +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Tue Feb 12 11:58:31 2008 +1100 + + libfdt: Add and use a node iteration helper function. + + This patch adds an fdt_next_node() function which can be used to + iterate through nodes of the tree while keeping track of depth. This + function is used to simplify the iteration code in a lot of other + functions, and is also exported for use by library users. + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit 9eaeb07a7185d852c7aa10735ecd4e9edf24fb5d +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Fri Jan 11 14:55:05 2008 +1100 + + libfdt: Add fdt_set_name() function + + This patch adds an fdt_set_name() function to libfdt, mirroring + fdt_get_name(). This is a r/w function which alters the name of a + given device tree node. + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit 23e20aa6488e6c0622496549861bfdc74108debe +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Tue Mar 18 13:33:30 2008 +0100 + + lwmon5: Fix register test logic to match the specific GDC h/w. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 46bc0a938779aa1d664b847d36b08aa00f22e539 +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Tue Mar 18 13:27:57 2008 +0100 + + Fix backlight in the lwmon5 POST. + + Backlight was switched on even when temperature was too low. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 3d61018643a2cd38c145aa6dde53f3f5f1a0e9cf +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Wed Feb 6 18:48:36 2008 +0100 + + The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). + + To enable this, alternative, configuration the U-Boot board configuration + file for lwmon5 includes the definitions of alternative addresses for header + (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). + + The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, + and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the + lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 0f009f781b5b88f25769e154ea4d42db13baf0c6 +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Mon Feb 4 17:11:53 2008 +0100 + + Add support for the lwmon5 board reset via GPIO58. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit f694e32f93565ec1fa8d0226c584d6b89e931ed9 +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Mon Feb 4 17:09:55 2008 +0100 + + Some fixes to dspic, fpga, and gdc post tests for lwmon5. Disable external watch-dog for now. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit b428f6a8c65c5303e5f96db8d24f2f699d94a98c +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Mon Feb 4 14:11:03 2008 +0100 + + The patch introduces the CRITICAL feature of POST tests. If the test marked as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 8f15d4addd49c956412e1e3bfc764a0c8b1f3184 +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Mon Feb 4 14:10:42 2008 +0100 + + The patch adds new POST tests for the Lwmon5 board. These are: + + * External Watchdog test; + * dsPIC tests; + * FPGA test; + * GDC test; + * Sysmon tests. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit c2ed33efbfff5767bca236828e021c55fd547b6c +Author: Yuri Tikhonov <yur@pollux.denx.de> +Date: Mon Feb 4 14:10:01 2008 +0100 + + Enable CODEC POST with CFG_POST_CODEC rather than with CFG_POST_DSP. + + Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> + +commit 3515fd18d4e8e44f863ac7142b55e22b109e9af2 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Mar 18 17:35:51 2008 +0100 + + HMI1001: fix compile problem. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 1f2a9970109cebf7446e0503b10b71f8673045ee +Author: Mike Frysinger <vapier@gentoo.org> +Date: Mon Feb 18 05:32:30 2008 -0500 + + Blackfin: BF537-stamp: drop board-specific flash driver for CFI + + The parallel flash on the BF537-STAMP is CFI compliant, so there is no need + for the board specific driver at all. Just use the common CFI driver. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 5b22163fef865af2b6bfb6b75f1b7bf443ce170c +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Feb 19 00:36:14 2008 -0500 + + Blackfin: add proper ELF markings to some assembly functions + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit cf675d3b2b9c3511c1d99bc8f8f38fd2f08bfcaf +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Feb 19 00:35:17 2008 -0500 + + Blackfin: new cplbinfo command for viewing cplb tables + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit aadb72503cd1602349a5fe53356d5f55ecc1b900 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Mon Feb 18 05:37:51 2008 -0500 + + Blackfin: update MAINTAINERS list + + Add maintainer information for the Blackfin boards. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit f7ce12cb65a30c6e152eecf26f0304b7d78cf39d +Author: Mike Frysinger <vapier@gentoo.org> +Date: Mon Feb 18 05:26:48 2008 -0500 + + Blackfin: convert BFIN_CPU to CONFIG_BFIN_CPU + + Stop tying things to the processor that should be tied to other defines and + change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build + system to select the -mcpu option. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 86a20fb920bd198105acf7b1191117f566d637ed +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sat Feb 16 07:40:36 2008 -0500 + + Blackfin: move bootldr command to common code + + This moves the Blackfin-common bootldr command out of the BF537-STAMP + specific board directory and into the common directory so that all Blackfin + boards may utilize it. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit decbe029b2a9d3333d02c433389b1c821eea96d7 +Author: Heiko Schocher <hs@denx.de> +Date: Fri Mar 14 11:05:20 2008 +0100 + + mgcoge: update configuration + + Fix configuration for mgcoge board + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit c136724cda0219c49f1d4b346f00da29b14fdf14 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Mar 16 01:22:59 2008 +0100 + + drivers/rtc/Makefile: keep list sorted + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 9536dfcce03e7be4ccbceb47a08d9ba07ada362f +Author: Tor Krill <tor@excito.com> +Date: Sat Mar 15 15:40:26 2008 +0100 + + Add support for Intersil isl1208 RTC + + Signed-off-by: Tor Krill <tor@excito.com> + +commit 0210cff3d079d97b2156b13685ee8de368e68a1a +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sat Mar 15 17:36:41 2008 +0100 + + cramfs: Fix ifdef + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 0b8f2a27861a9fd06eb55a34f855ec9c5102aab4 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Mar 16 01:12:58 2008 +0100 + + Conding style cleanup + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 41712b4e8c95dff23354bcd620e1f9477160c190 +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 5 12:31:53 2008 +0100 + + ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board + + This patch adds USB OHCI support to the Canyonlands board port. It also + enables EXT2 support. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 2596f5b9d353ff3e4387a3325d05740f16958038 +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 5 12:29:32 2008 +0100 + + usb: Add CFG_OHCI_USE_NPS to common USB-OHCI driver + + This patch adds CFG_OHCI_USE_NPS to the common USB-OHCI driver. This + way a board just needs to define this new option to enable the "force + NoPowerSwitching mode" instead of adding new CPU/architecture defines + to the USB source itself. + + This new option will be used first with the new AMCC 460EX Canyonlands + board port, which will be posted in a few days. + + This patch also fixes a small compilation problem when DEBUG is enabled. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 71665ebf88408ff2acb762af47989fd4365b321a +Author: Stefan Roese <sr@denx.de> +Date: Mon Mar 3 17:27:02 2008 +0100 + + ppc4xx: Add Canyonlands NAND booting support + + 460EX doesn't support a fixed bootstrap option to boot from 512 byte page + NAND devices. The only bootstrap option for NAND booting is option F for + 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap + EEPROM needs to be programmed accordingly. + + This patch adds basic NAND booting support for the AMCC Canyonlands aval + board and also adds support to the "bootstrap" command, to enable NAND + booting I2C setting. + + Tested with 512 byte page NAND device (32MByte) on Canyonlands. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c813f1f835a7edfdb929f2843b09db72cd5cd2f2 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 16:53:00 2008 +0100 + + ppc4xx: Add AMCC Canyonlands support (460EX) (3/3) + + This patch adds support for the AMCC Canyonlands 460EX evaluation + board. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 6983fe21f774a924d3adb263a270bc2f301f2aa2 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 16:52:24 2008 +0100 + + ppc4xx: Add AMCC Canyonlands support (460EX) (2/3) + + This patch adds support for the AMCC Canyonlands 460EX evaluation + board. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8e1a3fe545bbcfceafe183344ebc9f1ad03819c1 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 16:51:17 2008 +0100 + + ppc4xx: Add AMCC Canyonlands support (460EX) (1/3) + + This patch adds support for the AMCC Canyonlands 460EX evaluation + board. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 43c60992cdf72496e7eaaa3fbd37ebbe75835f69 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 15:11:43 2008 +0100 + + ppc4xx: Add basic support for AMCC 460EX/460GT (5/5) + + This patch adds basic support for the AMCC 460EX/460GT PPC's. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 6f2eb3f3d8ea2dbb224d0da5a12038693bab9945 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 15:11:18 2008 +0100 + + ppc4xx: Add basic support for AMCC 460EX/460GT (4/5) + + This patch adds basic support for the AMCC 460EX/460GT PPC's. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 999ecd5aca381984d8ebbeb207ece82a1c275577 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 15:07:10 2008 +0100 + + ppc4xx: Add basic support for AMCC 460EX/460GT (3/5) + + This patch adds basic support for the AMCC 460EX/460GT PPC's. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 2801b2d2a9906f206ab9ee8d0b6e746d2b7fe05a +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 15:05:50 2008 +0100 + + ppc4xx: Add basic support for AMCC 460EX/460GT (2/5) + + This patch adds basic support for the AMCC 460EX/460GT PPC's. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8ac41e3e37c3080c6b1d9461d654161cfe2aa492 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 15:05:26 2008 +0100 + + ppc4xx: Add basic support for AMCC 460EX/460GT (1/5) + + This patch adds basic support for the AMCC 460EX/460GT PPC's. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 56e410178375d9f20be25fb24e180974f0ae120b +Author: Stefan Roese <sr@denx.de> +Date: Tue Feb 19 22:07:57 2008 +0100 + + ppc4xx: interrupt.c reworked + + This patch is a rework of the 4xx interrupt handling done while + adding the 460EX/GT support. Interrupts are needed on 4xx for the + EMAC driver. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 84a999b6cdd0b02dc7de2cacc306eaa84afe2b46 +Author: Stefan Roese <sr@denx.de> +Date: Tue Feb 19 22:01:57 2008 +0100 + + ppc4xx: program_tlb now uses 64bit physical addess + + This patch changes the physical addess parameter from 32bit to 64bit. + This is needed for 36bit 4xx platforms to access areas located + beyond the 4GB border, like SoC peripherals (EBC etc.). + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c3307fa186af85771924c434997089b8104c0a46 +Author: Stefan Roese <sr@denx.de> +Date: Tue Feb 19 21:58:25 2008 +0100 + + ppc4xx: miiphy.c reworked + + While adding the 460EX/GT support I reworked the 4xx miiphy code. It + badly neede some cleanup. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 88aff62df39c0756241ea9f9b5a7b3ade26cb82b +Author: Stefan Roese <sr@denx.de> +Date: Tue Feb 19 16:21:49 2008 +0100 + + rtc: Add M41T62 support + + This patch add support for the STM M41T62 RTC. It is used and tested + on the AMCC Canyonlands 406EX platform. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 217d383e201adc7f2271145ae345ea5eae2b7170 +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Feb 25 18:46:43 2008 +0100 + + ppc4xx: Add 405GPr based MCU25 board specific files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 75a66dcdb383863ad33f0534cfc27b7a86947dad +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Feb 25 18:46:42 2008 +0100 + + ppc4xx: Add 405GPr based MCU25 board config file + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit b05f35436b733a240559e77e46bed8439665ecc5 +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Feb 25 18:46:41 2008 +0100 + + ppc4xx: Add 405GPr based MCU25 board. Global files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 14c27b35ac812a71abce6e3e2f4129d5e9313660 +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Feb 25 18:37:02 2008 +0100 + + ppc4xx: HCU4/5. remove obsolete hcu_flash.c + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit a079494853cc2bfeddb26673219db0b4b2b31566 +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Feb 25 18:37:01 2008 +0100 + + ppc4xx: HCU4/5. Use FLASH_CFI_LEGACY + + Cleanup: Remove custom flash driver for 8 bit boot-eprom and replace it with + the FLASH_CFI_LEGACY et al. config options. + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit e4170e5a50c8110f792bc37472833ae669d69951 +Author: Stefan Roese <sr@denx.de> +Date: Tue Mar 11 13:52:25 2008 +0100 + + ppc4xx: Fix comment in 405EX DDR2 init code + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit b8aa57b5d4d69e8f0810a5e632c0ce41c0f46ee0 +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Mar 14 16:04:54 2008 +0100 + + tools/setlocalversion: use a git-describe-ish format + + Change the automatic local version to have the form -nnnnn-gSHA1SUMID, + where 'nnnnn' is the number of commits since the last tag (i.e., + 1.3.2-rc3). This makes it much easier to recognize "newer" versions + and to see how much has been changed since the referenced tag. + + Stolen from Linux kernel's scripts/setlocalversio, see commit d882421f. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c6dc21c84de0f159a1752c5ebd33cff843f63609 +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Mar 13 14:32:03 2008 +0100 + + HMI1001: add support for MPC5200 Rev. B processors. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 90f13dce7a7a9a84d5730576c9a24d0dbb07cb3a +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Mar 13 14:29:49 2008 +0100 + + TQM5200: remove dead code + + This board never used a MGT5100 processor. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 30f1806f60978d707b0cff2d7bf89d141fc24290 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Mar 9 16:20:02 2008 +0100 + + Release v1.3.2 + + Update CHANGELOG for release. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 5b464c289ba715d0979b6e1f94947bb8f1068d16 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Date: Sun Mar 9 14:52:11 2008 +0100 diff --git a/MAINTAINERS b/MAINTAINERS index dc135802ef..e31ea06afb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -172,6 +172,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> Niklaus Giger <niklaus.giger@netstal.com> HCU4 PPC405GPr + MCU25 PPC405GPr HCU5 PPC440EPx Frank Gottschling <fgottschling@eltec.de> @@ -319,6 +320,7 @@ Stefan Roese <sr@denx.de> alpr PPC440GX bamboo PPC440EP bunbinga PPC405EP + canyonlands PPC460EX ebony PPC440GP haleakala PPC405EXr katmai PPC440SPe @@ -702,5 +704,20 @@ Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> MS7720SE SH7720 ######################################################################### +# Blackfin Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Mike Frysinger <vapier@gentoo.org> +Blackfin Team <u-boot-devel@blackfin.uclinux.org> + + BF533-EZKIT BF533 + BF533-STAMP BF533 + BF537-STAMP BF537 + BF561-EZKIT BF561 + +######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -165,6 +165,8 @@ LIST_4xx=" \ bamboo_nand \ bubinga \ CANBT \ + canyonlands \ + canyonlands_nand \ CMS700 \ CPCI2DP \ CPCI405 \ @@ -198,6 +200,7 @@ LIST_4xx=" \ luan \ lwmon5 \ makalu \ + mcu25 \ METROBOX \ MIP405 \ MIP405T \ @@ -339,10 +339,12 @@ $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all + $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all $(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk + $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin + cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin $(VERSION_FILE): @( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \ @@ -1170,6 +1172,17 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd +canyonlands_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc + +canyonlands_nand_config: unconfig + @mkdir -p $(obj)include $(obj)board/amcc/canyonlands + @mkdir -p $(obj)nand_spl/board/amcc/canyonlands + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc + @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + CATcenter_config \ CATcenter_25_config \ CATcenter_33_config: unconfig @@ -1281,6 +1294,10 @@ lwmon5_config: unconfig makalu_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc +mcu25_config: unconfig + @mkdir -p $(obj)board/netstal/common + @$(MKCONFIG) $(@:_config=) ppc ppc4xx mcu25 netstal + METROBOX_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst @@ -1594,7 +1611,7 @@ PQ2FADS-ZU_66MHz_config \ PQ2FADS-ZU_66MHz_lowboot_config \ : unconfig @mkdir -p $(obj)include - @mkdir -p $(obj)board/mpc8260ads + @mkdir -p $(obj)board/freescale/mpc8260ads $(if $(findstring PQ2FADS,$@), \ @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \ @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h) @@ -1603,13 +1620,13 @@ PQ2FADS-ZU_66MHz_lowboot_config \ $(if $(findstring VR,$@), \ @echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h)) @[ -z "$(findstring lowboot_,$@)" ] || \ - { echo "TEXT_BASE = 0xFF800000" >$(obj)board/mpc8260ads/config.tmp ; \ + { echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp ; \ $(XECHO) "... with lowboot configuration" ; \ } - @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads + @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads freescale MPC8266ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads + @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale # PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash PM825_config \ @@ -2228,7 +2245,7 @@ EVB64260_750CX_config: unconfig @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260 mpc7448hpc2_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 + @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 freescale P3G4_config: unconfig @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 @@ -2455,11 +2472,6 @@ cm4008_config : unconfig cm41xx_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 -gth2_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_GTH2 1" >$(obj)include/config.h - @$(MKCONFIG) -a gth2 mips mips gth2 - ######################################################################### ## S3C44B0 Systems ######################################################################### @@ -2662,6 +2674,11 @@ pb1000_config : unconfig @echo "#define CONFIG_PB1000 1" >$(obj)include/config.h @$(MKCONFIG) -a pb1x00 mips mips pb1x00 +gth2_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_GTH2 1" >$(obj)include/config.h + @$(MKCONFIG) -a gth2 mips mips gth2 + qemu_mips_config: unconfig @mkdir -p $(obj)include @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h @@ -2858,7 +2875,7 @@ clean: $(obj)board/{integratorap,integratorcp}/u-boot.lds \ $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds @rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map} - @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl.map} + @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map} @rm -f $(obj)api_examples/demo $(VERSION_FILE) @find $(OBJTREE) -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' \ @@ -669,6 +669,7 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC Note that if the RTC uses I2C, then the I2C interface @@ -2001,6 +2002,11 @@ Configuration Settings: is useful, if some of the configured banks are only optionally available. +- CONFIG_FLASH_SHOW_PROGRESS + If defined (must be an integer), print out countdown + digits and dots. Recommended value: 45 (9..1) for 80 + column displays, 15 (3..1) for 40 column displays. + - CFG_RX_ETH_BUFFER: Defines the number of ethernet receive buffers. On some ethernet controllers it is recommended to set this value diff --git a/blackfin_config.mk b/blackfin_config.mk index a7513ea4dc..d90eb238c3 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -24,9 +24,13 @@ PLATFORM_RELFLAGS += -ffixed-P5 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN +ifneq (,$(CONFIG_BFIN_CPU)) +PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) +endif + SYM_PREFIX = _ LDR_FLAGS += --use-vmas -ifeq (,$(findstring s,$(MAKEFLAGS))) +ifneq (,$(findstring s,$(MAKEFLAGS))) LDR_FLAGS += --quiet endif diff --git a/board/adder/adder.c b/board/adder/adder.c index aa7815848c..817c8649aa 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -26,6 +26,9 @@ #include <common.h> #include <mpc8xx.h> +#if defined(CONFIG_OF_LIBFDT) + #include <libfdt.h> +#endif /* * SDRAM is single Samsung K4S643232F-T70 chip (8MB) @@ -111,3 +114,11 @@ int checkboard( void ) return 0; } + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +} +#endif diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile new file mode 100644 index 0000000000..7a2eaa5163 --- /dev/null +++ b/board/amcc/canyonlands/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +COBJS += bootstrap.o +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c new file mode 100644 index 0000000000..37fa1c926c --- /dev/null +++ b/board/amcc/canyonlands/bootstrap.c @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/io.h> + +/* + * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The + * values are independent of the rest of the clock settings. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +#define I2C_EEPROM_ADDR 0x52 + +static char *config_labels[] = { + "CPU: 600 PLB: 200 OPB: 100 EBC: 100", + "CPU: 800 PLB: 200 OPB: 100 EBC: 100", + NULL +}; + +static u8 boot_configs[][17] = { + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } +}; + +/* + * Bytes 5,6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0x90, 0x01, 0xa0, 0x68, 0x58 +}; + +static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 *buf, b_nand; + int x, y, nbytes, selcfg; + extern char console_buffer[]; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); + return 1; + } + + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + b_nand = 1; + else + b_nand = 0; + + printf("Available configurations: \n\n"); + + if (b_nand) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } + } + } else { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } + } + } + + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (b_nand) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (b_nand) { + buf[5] = nand_boot[0]; + buf[6] = nand_boot[1]; + buf[8] = nand_boot[2]; + buf[9] = nand_boot[3]; + buf[11] = nand_boot[4]; + } + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + + printf("Done\n"); + printf("Please power-cycle the board for the changes to take effect\n"); + + return 0; +} + +U_BOOT_CMD( + bootstrap, 2, 0, do_bootstrap, + "bootstrap - program the I2C bootstrap EEPROM\n", + "<nand|nor> - strap to boot from NAND or NOR flash\n" + ); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c new file mode 100644 index 0000000000..36779f576f --- /dev/null +++ b/board/amcc/canyonlands/canyonlands.c @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc440.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/4xx_pcie.h> +#include <asm/gpio.h> + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + u32 sdr0_cust0; + + /*------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + *------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(uic3er, 0x00000000); /* disable all */ + mtdcr(uic3cr, 0x00000000); /* all non-critical */ + mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic3sr, 0xffffffff); /* clear all */ + + /* SDR Setting - enable NDFC */ + mfsdr(SDR0_CUST0, sdr0_cust0); + sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + SDR0_CUST0_NDFC_BAC_ENCODE(3) | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, sdr0_cust0); + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 4 pins + */ + mtsdr(SDR0_PFC1, 0x00040000); + + /* Enable PCI host functionality in SDR0_PCI0 */ + mtsdr(SDR0_PCI0, 0xe0000000); + + /* Enable ethernet and take out of reset */ + out_8((void *)CFG_BCSR_BASE + 6, 0); + + /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ + out_8((void *)CFG_BCSR_BASE + 5, 0); + + /* Enable USB host & USB-OTG */ + out_8((void *)CFG_BCSR_BASE + 7, 0); + + mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + u32 pvr = get_pvr(); + + if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) + printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); + else + printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +u32 ddr_wrdtr(u32 default_val) { + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); +} + +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_90_DEG_ADV); +} + +#if defined(CONFIG_NAND_U_BOOT) +/* + * NAND booting U-Boot version uses a fixed initialization, since the whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot + * code. + */ +long int initdram(int board_type) +{ + return CFG_MBYTES_SDRAM << 20; +} +#endif + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + /*-------------------------------------------------------------------+ + * Disable everything + *-------------------------------------------------------------------*/ + out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ + + /*-------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 + * strapping options to not support sizes such as 128/256 MB. + *-------------------------------------------------------------------*/ + out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out_le32((void *)PCIX0_PIM0LAH, 0); + out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIX0_BAR0, 0); + + /*-------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *-------------------------------------------------------------------*/ + out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + + out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +#if defined(CONFIG_PCI) +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + */ +int is_pci_host(struct pci_controller *hose) +{ + /* Board is always configured as host. */ + return (1); +} + +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + char *env; + unsigned int delay; + + /* + * assume we're called after the PCIX hose is initialized, which takes + * bus ID 0 and therefore start numbering PCIe's from 1. + */ + bus = busno; + for (i = 0; i <= 1; i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif /* CONFIG_PCI */ + +int board_early_init_r (void) +{ + /* + * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + + /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#else + mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#endif + + /* Remove TLB entry of boot EBC mapping */ + remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20); + + /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ + program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE, + TLB_WORD2_I_ENABLE); + + /* + * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address + * 0xfc00.0000 is possible + */ + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + u32 eth_cfg; + + /* + * Set EMAC mode/configuration (GMII, SGMII, RGMII...). + * This is board specific, so let's do it here. + */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + /* disable SGMII mode */ + eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | + SDR0_ETH_CFG_SGMII1_ENABLE | + SDR0_ETH_CFG_SGMII0_ENABLE); + /* Set the for 2 RGMII mode */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; + eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + mtsdr(SDR0_ETH_CFG, eth_cfg); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk new file mode 100644 index 0000000000..1e4bbc47e6 --- /dev/null +++ b/board/amcc/canyonlands/config.mk @@ -0,0 +1,49 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 460EX/460GT Evaluation Board (Canyonlands) board +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +endif + +ifeq ($(CONFIG_PCIBOOT_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S new file mode 100644 index 0000000000..bd4cab56d8 --- /dev/null +++ b/board/amcc/canyonlands/init.S @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ +#else + tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) +#endif + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) +#endif + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + /* PCIe UTL register */ + tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry for NAND */ + tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB-entry for CPLD */ + tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry for OCM */ + tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* AHB: Internal USB Peripherals (USB, SATA) */ + tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbtab_end + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * For NAND booting the first TLB has to be reconfigured to full size + * and with caching disabled after running from RAM! + */ +#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) + + .globl reconfig_tlb0 +reconfig_tlb0: + sync + isync + addi r4,r0,0x0000 /* TLB entry #0 */ + lis r5,TLB00@h + ori r5,r5,TLB00@l + tlbwe r5,r4,0x0000 /* Save it out */ + lis r5,TLB01@h + ori r5,r5,TLB01@l + tlbwe r5,r4,0x0001 /* Save it out */ + lis r5,TLB02@h + ori r5,r5,TLB02@l + tlbwe r5,r4,0x0002 /* Save it out */ + sync + isync + blr +#endif diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds new file mode 100644 index 0000000000..12a5dcf85c --- /dev/null +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds new file mode 100644 index 0000000000..7496f485ea --- /dev/null +++ b/board/amcc/canyonlands/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2008 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/canyonlands/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S index 43387445b1..053fe19c07 100644 --- a/board/amcc/kilauea/init.S +++ b/board/amcc/kilauea/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on code provided from UDTech and AMCC @@ -64,7 +64,7 @@ ext_bus_cntlr_init: /* SET SDRAM_MB3CF - Not enabled */ mtsdram_as(SDRAM_MB3CF, 0x00000000); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR, 0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 57c1774e02..5e9a5e08d3 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on code provided from Senao and AMCC @@ -57,7 +57,7 @@ ext_bus_cntlr_init: /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR,0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 98ed6f81d2..738f69c781 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { -#if (BFIN_CPU == ADSP_BF531) - printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF532) - printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF533 EZ-Kit Lite board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index af035976ff..c4dde92c1a 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -43,13 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { -#if (BFIN_CPU == ADSP_BF531) - printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF532) - printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF533 Stamp board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index e4888441a9..5d22393371 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o +COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index d279817bba..6ca8e21f3a 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -31,7 +31,6 @@ #include <asm/blackfin.h> #include <asm/io.h> #include <net.h> -#include "ether_bf537.h" #include <asm/mach-common/bits/bootrom.h> /** @@ -54,60 +53,8 @@ DECLARE_GLOBAL_DATA_PTR; #define POST_WORD_ADDR 0xFF903FFC -/* - * the bootldr command loads an address, checks to see if there - * is a Boot stream that the on-chip BOOTROM can understand, - * and loads it via the BOOTROM Callback. It is possible - * to also add booting from SPI, or TWI, but this function does - * not currently support that. - */ -int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr, entry; - ulong *data; - - /* Get the address */ - if (argc < 2) { - addr = load_addr; - } else { - addr = simple_strtoul(argv[1], NULL, 16); - } - - /* Check if it is a LDR file */ - data = (ulong *) addr; - if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) { - /* We want to boot from FLASH or SDRAM */ - entry = _BOOTROM_BOOT_DXE_FLASH; - printf("## Booting ldr image at 0x%08lx ...\n", addr); - if (icache_status()) - icache_disable(); - if (dcache_status()) - dcache_disable(); - - __asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n": - :[a] "d"(addr),[b] "a"(entry) - :"R7", "P0"); - - } else { - printf("## No ldr image at address 0x%08lx\n", addr); - } - - return 0; -} - -U_BOOT_CMD(bootldr, 2, 0, do_bootldr, - "bootldr - boot ldr image from memory\n", - "[addr]\n - boot ldr image stored in memory\n"); - int checkboard(void) { -#if (BFIN_CPU == ADSP_BF534) - printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF536) - printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF537 stamp board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; @@ -187,9 +134,6 @@ int misc_init_r(void) pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]); setenv("ethaddr", nid); } - if (getenv("ethaddr")) { - SetupMacAddr(SrcAddr); - } #endif #endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */ diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h deleted file mode 100644 index 1fa7a10bda..0000000000 --- a/board/bf537-stamp/flash-defines.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * U-boot - flash-defines.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __FLASHDEFINES_H__ -#define __FLASHDEFINES_H__ - -#include <common.h> - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) -#define TRUE 0x1 -#define FALSE 0x0 -#define BUFFER_SIZE 0x80000 -#define NO_COMMAND 0 -#define GET_CODES 1 -#define RESET 2 -#define WRITE 3 -#define FILL 4 -#define ERASE_ALL 5 -#define ERASE_SECT 6 -#define READ 7 -#define GET_SECTNUM 8 -#define FLASH_START_L 0x0000 -#define FLASH_START_H 0x2000 -#define FLASH_MAN_ST 2 -#define RESET_VAL 0xF0 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -int get_codes(void); -int poll_toggle_bit(long lOffset); -void reset_flash(void); -int erase_flash(void); -int erase_block_flash(int); -void unlock_flash(long lOffset); -int write_data(long lStart, long lCount, uchar * pnData); -int read_flash(long nOffset, int *pnValue); -int write_flash(long nOffset, int nValue); -void get_sector_number(long lOffset, int *pnSector); -int GetSectorProtectionStatus(flash_info_t * info, int nSector); -int GetOffset(int nBlock); -int AFP_NumSectors = 71; -long AFP_SectorSize2 = 0x10000; -int AFP_SectorSize1 = 0x2000; - -#define NUM_SECTORS 71 - -#define WRITESEQ1 0x0AAA -#define WRITESEQ2 0x0554 -#define WRITESEQ3 0x0AAA -#define WRITESEQ4 0x0AAA -#define WRITESEQ5 0x0554 -#define WRITESEQ6 0x0AAA -#define WRITEDATA1 0xaa -#define WRITEDATA2 0x55 -#define WRITEDATA3 0x80 -#define WRITEDATA4 0xaa -#define WRITEDATA5 0x55 -#define WRITEDATA6 0x10 -#define PriFlashABegin 0 -#define SecFlashABegin 8 -#define SecFlashBBegin 36 -#define PriFlashAOff 0x0 -#define PriFlashBOff 0x100000 -#define SecFlashAOff 0x10000 -#define SecFlashBOff 0x280000 -#define INVALIDLOCNSTART 0x20270000 -#define INVALIDLOCNEND 0x20280000 -#define BlockEraseVal 0x30 -#define UNLOCKDATA1 0xaa -#define UNLOCKDATA2 0x55 -#define UNLOCKDATA3 0xa0 -#define GETCODEDATA1 0xaa -#define GETCODEDATA2 0x55 -#define GETCODEDATA3 0x90 -#define SecFlashASec1Off 0x200000 -#define SecFlashASec2Off 0x204000 -#define SecFlashASec3Off 0x206000 -#define SecFlashASec4Off 0x208000 -#define SecFlashAEndOff 0x210000 -#define SecFlashBSec1Off 0x280000 -#define SecFlashBSec2Off 0x284000 -#define SecFlashBSec3Off 0x286000 -#define SecFlashBSec4Off 0x288000 -#define SecFlashBEndOff 0x290000 - -#define SECT32 32 -#define SECT33 33 -#define SECT34 34 -#define SECT35 35 -#define SECT36 36 -#define SECT37 37 -#define SECT38 38 -#define SECT39 39 - -#define FLASH_SUCCESS 0 -#define FLASH_FAIL -1 - -#endif diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c deleted file mode 100644 index 8252c42fd8..0000000000 --- a/board/bf537-stamp/flash.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * U-boot - flash.c Flash driver for PSD4256GV - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <malloc.h> -#include <config.h> -#include <asm/io.h> -#include "flash-defines.h" - -void flash_reset(void) -{ - reset_flash(); -} - -unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag) -{ - int id = 0, i = 0; - static int FlagDev = 1; - - id = get_codes(); - if (FlagDev) { - FlagDev = 0; - } - info->flash_id = id; - switch (bank_flag) { - case 0: - for (i = PriFlashABegin; i < SecFlashABegin; i++) - info->start[i] = (baseaddr + (i * AFP_SectorSize1)); - for (i = SecFlashABegin; i < NUM_SECTORS; i++) - info->start[i] = - (baseaddr + SecFlashAOff + - ((i - SecFlashABegin) * AFP_SectorSize2)); - info->size = 0x400000; - info->sector_count = NUM_SECTORS; - break; - case 1: - info->start[0] = baseaddr + SecFlashASec1Off; - info->start[1] = baseaddr + SecFlashASec2Off; - info->start[2] = baseaddr + SecFlashASec3Off; - info->start[3] = baseaddr + SecFlashASec4Off; - info->size = 0x10000; - info->sector_count = 4; - break; - case 2: - info->start[0] = baseaddr + SecFlashBSec1Off; - info->start[1] = baseaddr + SecFlashBSec2Off; - info->start[2] = baseaddr + SecFlashBSec3Off; - info->start[3] = baseaddr + SecFlashBSec4Off; - info->size = 0x10000; - info->sector_count = 4; - break; - } - return (info->size); -} - -unsigned long flash_init(void) -{ - unsigned long size_b; - int i; - - size_b = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0); - - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b, size_b >> 20); - } - - /* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, - (flash_info[0].start[2] - 1), &flash_info[0]); -#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) - (void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, - &flash_info[0]); -#endif - - return (size_b); -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id) { - case (STM_ID_29W320EB & 0xFFFF): - case (STM_ID_29W320DB & 0xFFFF): - printf("ST Microelectronics "); - break; - default: - printf("Unknown Vendor: (0x%08X) ", info->flash_id); - break; - } - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int cnt = 0, i; - int prot, sect; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - cnt = s_last - s_first + 1; - -#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) - printf("Erasing Flash locations, Please Wait\n"); - for (i = s_first; i <= s_last; i++) { - if (info->protect[i] == 0) { /* not protected */ - if (erase_block_flash(i) < 0) { - printf("Error Sector erasing \n"); - return FLASH_FAIL; - } - } - } -#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - if (cnt == FLASH_TOT_SECT) { - printf("Erasing flash, Please Wait \n"); - if (erase_flash() < 0) { - printf("Erasing flash failed \n"); - return FLASH_FAIL; - } - } else { - printf("Erasing Flash locations, Please Wait\n"); - for (i = s_first; i <= s_last; i++) { - if (info->protect[i] == 0) { /* not protected */ - if (erase_block_flash(i) < 0) { - printf("Error Sector erasing \n"); - return FLASH_FAIL; - } - } - } - } -#endif - printf("\n"); - return FLASH_SUCCESS; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int d; - if (addr % 2) { - read_flash(addr - 1 - CFG_FLASH_BASE, &d); - d = (int)((d & 0x00FF) | (*src++ << 8)); - write_data(addr - 1, 2, (uchar *) & d); - write_data(addr + 1, cnt - 1, src); - } else - write_data(addr, cnt, src); - return FLASH_SUCCESS; -} - -int write_data(long lStart, long lCount, uchar * pnData) -{ - long i = 0; - unsigned long ulOffset = lStart - CFG_FLASH_BASE; - int d; - int nSector = 0; - int flag = 0; - - if (lCount % 2) { - flag = 1; - lCount = lCount - 1; - } - - for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) { - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - d = (int)(pnData[i] | pnData[i + 1] << 8); - write_flash(ulOffset, d); - if (poll_toggle_bit(ulOffset) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - if ((i > 0) && (!(i % AFP_SectorSize2))) - printf("."); - } - if (flag) { - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - d = (int)(pnData[i] | (d & 0xFF00)); - write_flash(ulOffset, d); - if (poll_toggle_bit(ulOffset) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - } - return FLASH_SUCCESS; -} - -int write_flash(long nOffset, int nValue) -{ - long addr; - - addr = (CFG_FLASH_BASE + nOffset); - *(unsigned volatile short *)addr = nValue; - SSYNC(); -#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - if (icache_status()) - udelay(CONFIG_CCLK_HZ / 1000000); -#endif - return FLASH_SUCCESS; -} - -int read_flash(long nOffset, int *pnValue) -{ - unsigned short *pFlashAddr = - (unsigned short *)(CFG_FLASH_BASE + nOffset); - - *pnValue = *pFlashAddr; - - return TRUE; -} - -int poll_toggle_bit(long lOffset) -{ - unsigned int u1, u2; - volatile unsigned long *FB = - (volatile unsigned long *)(CFG_FLASH_BASE + lOffset); - while (1) { - u1 = *(volatile unsigned short *)FB; - u2 = *(volatile unsigned short *)FB; - u1 ^= u2; - if (!(u1 & 0x0040)) - break; - if (!(u2 & 0x0020)) - continue; - else { - u1 = *(volatile unsigned short *)FB; - u2 = *(volatile unsigned short *)FB; - u1 ^= u2; - if (!(u1 & 0x0040)) - break; - else { - reset_flash(); - return FLASH_FAIL; - } - } - } - return FLASH_SUCCESS; -} - -void reset_flash(void) -{ - write_flash(WRITESEQ1, RESET_VAL); - /* Wait for 10 micro seconds */ - udelay(10); -} - -int erase_flash(void) -{ - write_flash(WRITESEQ1, WRITEDATA1); - write_flash(WRITESEQ2, WRITEDATA2); - write_flash(WRITESEQ3, WRITEDATA3); - write_flash(WRITESEQ4, WRITEDATA4); - write_flash(WRITESEQ5, WRITEDATA5); - write_flash(WRITESEQ6, WRITEDATA6); - - if (poll_toggle_bit(0x0000) < 0) - return FLASH_FAIL; - - return FLASH_SUCCESS; -} - -int erase_block_flash(int nBlock) -{ - long ulSectorOff = 0x0; - - if ((nBlock < 0) || (nBlock > AFP_NumSectors)) - return FALSE; - - /* figure out the offset of the block in flash */ - if ((nBlock >= 0) && (nBlock < SecFlashABegin)) - ulSectorOff = nBlock * AFP_SectorSize1; - - else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS)) - ulSectorOff = - SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2; - /* no such sector */ - else - return FLASH_FAIL; - - write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); - write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); - write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); - write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); - write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); - - write_flash(ulSectorOff, BlockEraseVal); - - if (poll_toggle_bit(ulSectorOff) < 0) - return FLASH_FAIL; - printf("."); - - return FLASH_SUCCESS; -} - -void unlock_flash(long ulOffset) -{ - unsigned long ulOffsetAddr = ulOffset; - ulOffsetAddr &= 0xFFFF0000; - - write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); - write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); - write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); -} - -int get_codes() -{ - int dev_id = 0; - - write_flash(WRITESEQ1, GETCODEDATA1); - write_flash(WRITESEQ2, GETCODEDATA2); - write_flash(WRITESEQ3, GETCODEDATA3); - - read_flash(0x0402, &dev_id); - dev_id &= 0x0000FFFF; - - reset_flash(); - - return dev_id; -} - -void get_sector_number(long ulOffset, int *pnSector) -{ - int nSector = 0; - long lMainEnd = 0x400000; - long lBootEnd = 0x10000; - - /* sector numbers for the FLASH A boot sectors */ - if (ulOffset < lBootEnd) { - nSector = (int)ulOffset / AFP_SectorSize1; - } - /* sector numbers for the FLASH B boot sectors */ - else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) { - nSector = ((ulOffset / (AFP_SectorSize2)) + 7); - } - /* if it is a valid sector, set it */ - if ((nSector >= 0) && (nSector < AFP_NumSectors)) - *pnSector = nSector; - -} diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c index d72c861a13..a1a85d0fc9 100644 --- a/board/bmw/m48t59y.c +++ b/board/bmw/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -void +int rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,6 +295,8 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + + return 0; } void diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 77f7f48a6e..a72ba4620b 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -177,9 +177,9 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ /* stubs so we can print dates w/o any nvram RTC.*/ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { - return; + return 0; } void rtc_set (struct rtc_time *tmp) { diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c index 18ab5005ef..263da6b7c9 100644 --- a/board/etin/debris/phantom.c +++ b/board/etin/debris/phantom.c @@ -182,7 +182,7 @@ static int get_century_flag(void) return flag; } -void rtc_get( struct rtc_time *tmp) +int rtc_get( struct rtc_time *tmp) { if (phantom_flag < 0) phantom_flag = get_phantom_flag(); @@ -250,6 +250,8 @@ void rtc_get( struct rtc_time *tmp) tmp->tm_yday = 0; tmp->tm_isdst= 0; } + + return 0; } void rtc_set( struct rtc_time *tmp ) diff --git a/board/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile index e3d757d5dd..e3d757d5dd 100644 --- a/board/mpc7448hpc2/Makefile +++ b/board/freescale/mpc7448hpc2/Makefile diff --git a/board/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S index a7a40a134c..a7a40a134c 100644 --- a/board/mpc7448hpc2/asm_init.S +++ b/board/freescale/mpc7448hpc2/asm_init.S diff --git a/board/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk index 2e58858c4f..2e58858c4f 100644 --- a/board/mpc7448hpc2/config.mk +++ b/board/freescale/mpc7448hpc2/config.mk diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c index 81846eba77..81846eba77 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c index 30ae17d872..30ae17d872 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/freescale/mpc7448hpc2/tsi108_init.c diff --git a/board/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds index 05f0269f40..05f0269f40 100644 --- a/board/mpc7448hpc2/u-boot.lds +++ b/board/freescale/mpc7448hpc2/u-boot.lds diff --git a/board/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile index de7d847a5f..de7d847a5f 100644 --- a/board/mpc8260ads/Makefile +++ b/board/freescale/mpc8260ads/Makefile diff --git a/board/mpc8260ads/config.mk b/board/freescale/mpc8260ads/config.mk index e99e181dda..e99e181dda 100644 --- a/board/mpc8260ads/config.mk +++ b/board/freescale/mpc8260ads/config.mk diff --git a/board/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c index 59997aac4f..59997aac4f 100644 --- a/board/mpc8260ads/flash.c +++ b/board/freescale/mpc8260ads/flash.c diff --git a/board/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index 93550e2ad0..93550e2ad0 100644 --- a/board/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c diff --git a/board/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile index 291a1c9566..291a1c9566 100644 --- a/board/mpc8266ads/Makefile +++ b/board/freescale/mpc8266ads/Makefile diff --git a/board/mpc8266ads/config.mk b/board/freescale/mpc8266ads/config.mk index ecc2a7db61..ecc2a7db61 100644 --- a/board/mpc8266ads/config.mk +++ b/board/freescale/mpc8266ads/config.mk diff --git a/board/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c index 9512c72a0b..9512c72a0b 100644 --- a/board/mpc8266ads/flash.c +++ b/board/freescale/mpc8266ads/flash.c diff --git a/board/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 8f7273c41d..8f7273c41d 100644 --- a/board/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 42019fb80c..7cbdb7bf31 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -28,6 +28,7 @@ #endif #include <pci.h> #include <mpc83xx.h> +#include <vsc7385.h> DECLARE_GLOBAL_DATA_PTR; @@ -98,6 +99,26 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 972361fd68..704f9636bc 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -25,6 +25,7 @@ #include <mpc83xx.h> #include <i2c.h> #include <miiphy.h> +#include <vsc7385.h> #ifdef CONFIG_PCI #include <asm/mpc8349_pci.h> #include <pci.h> @@ -177,7 +178,7 @@ int checkboard(void) */ int misc_init_f(void) { -#ifdef CONFIG_VSC7385 +#ifdef CONFIG_VSC7385_ENET volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -239,6 +240,8 @@ int misc_init_f(void) } /* + * Miscellaneous late-boot configurations + * * Make sure the EEPROM has the HRCW correctly programmed. * Make sure the RTC is correctly programmed. * @@ -250,6 +253,8 @@ int misc_init_f(void) * * This function makes sure that the I2C EEPROM is programmed * correctly. + * + * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { @@ -375,6 +380,14 @@ int misc_init_r(void) i2c_set_bus_num(orig_bus); #endif +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + return rc; } diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index acc954488f..53e0c48276 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_CMD_NAND) += nand.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 8005a50531..3bcdda7334 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -186,6 +186,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + /* AD7843 ADC/Touchscreen controller */ + {4, 14, 1, 0, 0}, /* SPI_nCS0 */ + {4, 28, 3, 0, 3}, /* SPI_MOSI */ + {4, 29, 3, 0, 3}, /* SPI_MISO */ + {4, 30, 3, 0, 3}, /* SPI_CLK */ + + /* Freescale QUICC Engine USB Host Controller (FHCI) */ + {1, 2, 1, 0, 3}, /* USBOE */ + {1, 3, 1, 0, 3}, /* USBTP */ + {1, 8, 1, 0, 1}, /* USBTN */ + {1, 9, 2, 1, 3}, /* USBRP */ + {1, 10, 2, 0, 3}, /* USBRXD */ + {1, 11, 2, 1, 3}, /* USBRN */ + {2, 20, 2, 0, 1}, /* CLK21 */ + {4, 20, 1, 0, 0}, /* SPEED */ + {4, 21, 1, 0, 0}, /* SUSPND */ + /* END of table */ {0, 0, 0, 0, QE_IOP_TAB_END}, }; diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c new file mode 100644 index 0000000000..e1e790b34f --- /dev/null +++ b/board/freescale/mpc8360erdk/nand.c @@ -0,0 +1,72 @@ +/* + * MPC8360E-RDK support for the NAND on FSL UPM + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +static struct immap *im = (struct immap *)CFG_IMMR; + +static const u32 upm_array[] = { + 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ + 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ + 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ + 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ + 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ + 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ + 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ + 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ + 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ + 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ + 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ +}; + +static int dev_ready(void) +{ + if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { + debug("nand ready\n"); + return 1; + } + + debug("nand busy\n"); + return 0; +} + +static struct fsl_upm_nand fun = { + .upm = { + .array = upm_array, + .io_addr = (void *)CFG_NAND_BASE, + }, + .width = 1, + .upm_cmd_offset = 8, + .upm_addr_offset = 16, + .dev_ready = dev_ready, + .wait_pattern = 1, + .chip_delay = 50, +}; + +int board_nand_init(struct nand_chip *nand) +{ + fun.upm.mxmr = &im->lbus.mamr; + fun.upm.mdr = &im->lbus.mdr; + fun.upm.mar = &im->lbus.mar; + return fsl_upm_nand_init(nand, &fun); +} diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index bed0fc37ea..83fb60da00 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -15,7 +15,10 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> +#include <vsc7385.h> + #if defined(CFG_DRAM_TEST) int @@ -56,11 +59,6 @@ testdram(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) void ddr_enable_ecc(unsigned int dram_size); #endif @@ -135,6 +133,62 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CFG_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (spridr >> 16) { + case SPR_8379E_REV10 >> 16: + case SPR_8379_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378E_REV10 >> 16: + case SPR_8378_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8377E_REV10 >> 16: + case SPR_8377_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) @@ -143,5 +197,6 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 9fa0e747b9..8bdfe78e41 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2004 + * (C) Copyright 2003-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004 @@ -30,6 +30,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> #include <malloc.h> #ifndef CFG_RAMBOOT @@ -84,6 +85,7 @@ long int initdram (int board_type) ulong dramsize = 0; #ifndef CFG_RAMBOOT ulong test1, test2; + uint svr, pvr; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -147,6 +149,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + /* return dramsize + dramsize2; */ return dramsize; } diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index dbf0ecc5af..c624b3d82e 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -26,9 +26,15 @@ #include <asm/addrspace.h> #include <asm/inca-ip.h> #include <asm/io.h> +#include <asm/reboot.h> extern uint incaip_get_cpuclk(void); +void _machine_restart(void) +{ + *INCA_IP_WDT_RST_REQ = 0x3f; +} + static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index 14d738aa1a..b39f93d43f 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -276,6 +276,12 @@ __sdram_init: .ent lowlevel_init lowlevel_init: + /* Disable Watchdog. + */ + la t9, disable_incaip_wdt + jalr t9 + nop + /* EBU, CGU and SDRAM Initialization. */ li a0, CPU_CLOCK_RATE diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 815c01f4e4..e5fa25937b 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,25 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); +#if CONFIG_POST & CFG_POST_BSPEC1 + gpio_write_bit(CFG_GPIO_HIGHSIDE, 1); + + reg = 0; /* reuse as counter */ + out_be32((void *)CFG_DSPIC_TEST_ADDR, + in_be32((void *)CFG_DSPIC_TEST_ADDR) + & ~CFG_DSPIC_TEST_MASK); + while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) { + udelay(1000); + } + gpio_write_bit(CFG_GPIO_HIGHSIDE, 0); + if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) { + /* set "boot error" flag */ + out_be32((void *)CFG_DSPIC_TEST_ADDR, + in_be32((void *)CFG_DSPIC_TEST_ADDR) | + CFG_DSPIC_TEST_MASK); + } +#endif + /* * Reset PHY's: * The PHY's need a 2nd reset pulse, since the MDIO address is latched @@ -548,11 +567,13 @@ unsigned int board_video_init (void) return CFG_LIME_BASE_0; } -void board_backlight_switch (int flag) +#define DEFAULT_BRIGHTNESS 0x64 + +static void board_backlight_brightness(int brightness) { - if (flag) { + if (brightness > 0) { /* pwm duty, lamp on */ - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x64); + out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness); out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701); } else { /* lamp off */ @@ -561,6 +582,22 @@ void board_backlight_switch (int flag) } } +void board_backlight_switch (int flag) +{ + char * param; + int rc; + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + #if defined(CONFIG_CONSOLE_EXTRA_INFO) /* * Return text to be printed besides the logo. @@ -575,3 +612,8 @@ void video_get_info_str (int line_number, char *info) } #endif #endif /* CONFIG_VIDEO */ + +void board_reset(void) +{ + gpio_write_bit(CFG_GPIO_BOARD_RESET, 1); +} diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c index 37a6244198..2c1e6cf8b7 100644 --- a/board/mousse/m48t59y.c +++ b/board/mousse/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -void +int rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,6 +295,8 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + + return 0; } void diff --git a/board/netstal/common/hcu_flash.c b/board/netstal/common/hcu_flash.c deleted file mode 100644 index d0322f20da..0000000000 --- a/board/netstal/common/hcu_flash.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*-----------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*-----------------------------------------------------------------------*/ -/* - * This implementation assumes that the flash chips are uniform sector - * devices. This is true for all likely flash devices on a HCUx. - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - unsigned idx; - unsigned long sector_size = info->size / info->sector_count; - - for (idx = 0; idx < info->sector_count; idx += 1) { - info->start[idx] = base + (idx * sector_size); - } -} - -/*-----------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("ST Micro "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* (Reduced table of only parts expected in HCUx boards.) */ - switch (info->flash_id) { - case FLASH_MAN_AMD | FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_MAN_STM | FLASH_AM040: - printf ("MM29W040W (512 Kbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*-----------------------------------------------------------------------*/ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - asm("isync"); - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - asm("isync"); - - value = addr2[0]; - asm("isync"); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - printf("Unknown flash manufacturer code: 0x%x at %p\n", - value, addr); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* Calculate the sector offsets (Use HCUx Optimized code). */ - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, - *(A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors not erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* block erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; - for (i = 0; i < 50; i++) udelay (1000); - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* sector erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index 3d1d65d35e..53df61edbb 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a # NOBJS : Netstal common objects -NOBJS = fixed_sdram.o hcu_flash.o nm_bsp.o +NOBJS = fixed_sdram.o nm_bsp.o COBJS = $(BOARD).o SOBJS = diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index bb610e2d53..dc526fcd7a 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -201,3 +201,18 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 349c653e7f..5ffae65ea1 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -24,7 +24,7 @@ LIB = $(obj)lib$(BOARD).a # NOBJS : Netstal common objects -NOBJS = hcu_flash.o nm_bsp.o +NOBJS = nm_bsp.o COBJS = $(BOARD).o sdram.o SOBJS = init.o diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index c494e93ada..55e4cc69c6 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -499,3 +499,18 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index d3c2233606..0b16b50502 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -70,8 +70,6 @@ void dflush(void); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); - void board_add_ram_info(int use_default) { PPC4xx_SYS_INFO board_cfg; diff --git a/board/netstal/mcu25/Makefile b/board/netstal/mcu25/Makefile new file mode 100644 index 0000000000..53df61edbb --- /dev/null +++ b/board/netstal/mcu25/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007-2008 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +# NOBJS : Netstal common objects +NOBJS = fixed_sdram.o nm_bsp.o +COBJS = $(BOARD).o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj)../common/,$(NOBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/mcu25/README.txt b/board/netstal/mcu25/README.txt new file mode 100644 index 0000000000..d25fddd9ce --- /dev/null +++ b/board/netstal/mcu25/README.txt @@ -0,0 +1,59 @@ +MCU25 Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +0x70000000 + +Chip-Select 3: CAN Interface +---------------------------- +0x7800000 + + +Chip-Select 4: IMC-bus standard +------------------------------- + +Our IO-Bus (slow version) + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +Our IO-Bus (fast, but not yet use) + + +Memory Bank 1 -- SDRAM +------------------------------------- + +0x00000000 - 0x2ffffff # Default 64 MB diff --git a/board/netstal/mcu25/config.mk b/board/netstal/mcu25/config.mk new file mode 100644 index 0000000000..f0f2ea176e --- /dev/null +++ b/board/netstal/mcu25/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: MCU25 board +# +TEXT_BASE = 0xFFFB0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c new file mode 100644 index 0000000000..2b21444e2d --- /dev/null +++ b/board/netstal/mcu25/mcu25.c @@ -0,0 +1,217 @@ +/* + *(C) Copyright 2005-2008 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm-ppc/u-boot.h> +#include "../common/nm.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A) +#define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0) + +#define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10) +#define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C) +#define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e) +#define MCU_SW_INSTALL_REQUESTED 0x08 + +#define SDRAM_LEN (32 << 20) /* 32 MB - RAM */ + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +/* Attention: If you want 1 microsecs times from the external oscillator + * 0x00004051 is okay for u-boot/linux, but different from old vxworks values + * 0x00804051 causes problems with u-boot and linux! + */ +#define CPC0_CR0_VALUE 0x0007F03C +#define CPC0_CR1_VALUE 0x00004051 + +int board_early_init_f (void) +{ + /* Documented in A-1171 + * + * Interrupt controller setup for the MCU25 board. + * Note: IRQ 0-15 405GP internally generated; high; level sensitive + * IRQ 16 405GP internally generated; low; level sensitive + * IRQ 17-24 RESERVED/UNUSED + * IRQ 31 (EXT IRQ 6) (unused) + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr(cntrl1, CPC0_CR1_VALUE); + mtdcr(ecr, 0x60606000); + mtdcr(CPC0_EIRR, 0x7C000000); + out32(GPIO0_OR, CFG_GPIO0_OR ); + out32(GPIO0_TCR, CFG_GPIO0_TCR); + out32(GPIO0_ODR, CFG_GPIO0_ODR); + mtspr(ccr0, 0x00700000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} +#endif + +int sys_install_requested(void) +{ + u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER); + return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0; +} + +int checkboard (void) +{ + u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER); + u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION); + u16 generation = boardVersReg & 0x0f; + u16 index = boardVersReg & 0xf0; + + /* Cannot be done in board_early_init */ + mtdcr(cntrl0, CPC0_CR0_VALUE); + + /* Force /RTS to active. The board it not wired quite + * correctly to use cts/rtc flow control, so just force the + * /RST active and forget about it. + */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + nm_show_print(generation, index, hwConfig); + return 0; +} + +u32 hcu_led_get(void) +{ + return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff; +} + +/* + * hcu_led_set value to be placed into the LEDs (max 6 bit) + */ +void hcu_led_set(u32 value) +{ + out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram or initdram + * used for HCUx + */ +void sdram_init(void) +{ + return; +} + +/* + * hcu_get_slot + */ +u32 hcu_get_slot(void) +{ + u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS); + return slot & 0x7f; +} + +/* + * get_serial_number + */ +u32 get_serial_number(void) +{ + u32 serial = in_be32((u32 *)CFG_FLASH_BASE); + + if (serial == 0xffffffff) + return 0; + + return serial; +} + + +/* + * misc_init_r. + */ + +int misc_init_r(void) +{ + common_misc_init_r(); + set_params_for_sw_install( sys_install_requested(), "mcu25" ); + return 0; +} + +long int initdram(int board_type) +{ + unsigned int dram_size = 64*1024*1024; + init_ppc405_sdram(dram_size); + +#ifdef DEBUG + show_sdram_registers(); +#endif + + return dram_size; +} + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/mcu25/u-boot.lds b/board/netstal/mcu25/u-boot.lds new file mode 100644 index 0000000000..b6e28f839d --- /dev/null +++ b/board/netstal/mcu25/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/purple/purple.c b/board/purple/purple.c index 74718afb48..13a14556ba 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/addrspace.h> #include <asm/cacheops.h> +#include <asm/reboot.h> #include "sconsole.h" @@ -52,6 +53,13 @@ extern int asc_serial_getc (void); extern int asc_serial_tstc (void); extern void asc_serial_setbrg (void); +void _machine_restart(void) +{ + void (*f)(void) = (void *) 0xbfc00000; + + f(); +} + static void sdram_timing_init (ulong size) { register uint pass; diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index 61c2e9bd36..d08b422451 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -12,10 +12,17 @@ #include <common.h> #include <command.h> #include <asm/addrspace.h> -#include <asm/inca-ip.h> #include <asm/io.h> +#include <asm/reboot.h> #include <pci.h> +void _machine_restart(void) +{ + void (*f)(void) = (void *) 0xbfc00000; + + f(); +} + #if defined(CONFIG_PCI) static struct pci_controller hose; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 33ad2a32a5..e67145eb5b 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int initdram (int board_type) { ulong dramsize = 0; @@ -230,57 +229,6 @@ long int initdram (int board_type) #endif /* CONFIG_TQM5200_B */ } -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined(CONFIG_AEVFIFO) @@ -323,10 +271,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/common/Makefile b/common/Makefile index fc842225d5..1c81fcfe4f 100644 --- a/common/Makefile +++ b/common/Makefile @@ -39,9 +39,11 @@ COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o COBJS-y += image.o COBJS-y += gunzip.o COBJS-y += cmd_boot.o +COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o COBJS-y += cmd_bootm.o COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o +COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o COBJS-$(CONFIG_CMD_DATE) += cmd_date.o ifdef CONFIG_4xx COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o @@ -88,6 +90,7 @@ COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o COBJS-y += cmd_sata.o COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o +COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o diff --git a/common/cmd_bootldr.c b/common/cmd_bootldr.c new file mode 100644 index 0000000000..e6474aab22 --- /dev/null +++ b/common/cmd_bootldr.c @@ -0,0 +1,64 @@ +/* + * U-boot - bootldr.c + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <common.h> +#include <command.h> + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/bootrom.h> + +/* + * the bootldr command loads an address, checks to see if there + * is a Boot stream that the on-chip BOOTROM can understand, + * and loads it via the BOOTROM Callback. It is possible + * to also add booting from SPI, or TWI, but this function does + * not currently support that. + */ + +int do_bootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + void *addr; + uint32_t *data; + + /* Get the address */ + if (argc < 2) + addr = (void *)load_addr; + else + addr = (void *)simple_strtoul(argv[1], NULL, 16); + + /* Check if it is a LDR file */ + data = addr; +#if defined(__ADSPBF54x__) || defined(__ADSPBF52x__) + if ((*data & 0xFF000000) == 0xAD000000 && data[2] == 0x00000000) { +#else + if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) { +#endif + /* We want to boot from FLASH or SDRAM */ + printf("## Booting ldr image at 0x%p ...\n", addr); + + icache_disable(); + dcache_disable(); + + __asm__( + "jump (%1);" + : + : "q7" (addr), "a" (_BOOTROM_MEMBOOT)); + } else + printf("## No ldr image at address 0x%p\n", addr); + + return 0; +} + +U_BOOT_CMD(bootldr, 2, 0, do_bootldr, + "bootldr - boot ldr image from memory\n", + "[addr]\n" + " - boot ldr image stored in memory\n"); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 789ee03387..9e5ce4b38f 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -427,6 +427,17 @@ static int fit_check_kernel (const void *fit, int os_noffset, int verify) } show_boot_progress (105); +#ifdef CONFIG_LOGBUFFER +#ifndef CONFIG_ALT_LB_ADDR + kbd=gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD; + debug ("## Logbuffer at 0x%08lX ", kbd->bi_memsize-LOGBUFF_LEN); +#else + debug ("## Logbuffer at 0x%08lX ", CONFIG_ALT_LB_ADDR); +#endif +#endif if (!fit_image_check_target_arch (fit, os_noffset)) { puts ("Unsupported Architecture\n"); show_boot_progress (-105); diff --git a/common/cmd_cplbinfo.c b/common/cmd_cplbinfo.c new file mode 100644 index 0000000000..b2bbec12ea --- /dev/null +++ b/common/cmd_cplbinfo.c @@ -0,0 +1,59 @@ +/* + * cmd_cplbinfo.c - dump the instruction/data cplb tables + * + * Copyright (c) 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/cplb.h> +#include <asm/mach-common/bits/mpu.h> + +/* + * Translate the PAGE_SIZE bits into a human string + */ +static const char *cplb_page_size(uint32_t data) +{ + static const char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; + return page_size_string_table[(data & PAGE_SIZE_MASK) >> PAGE_SIZE_SHIFT]; +} + +/* + * show a hardware cplb table + */ +static void show_cplb_table(uint32_t *addr, uint32_t *data) +{ + size_t i; + printf(" Address Data Size Valid Locked\n"); + for (i = 1; i <= 16; ++i) { + printf(" %2i 0x%p 0x%05X %s %c %c\n", + i, *addr, *data, + cplb_page_size(*data), + (*data & CPLB_VALID ? 'Y' : 'N'), + (*data & CPLB_LOCK ? 'Y' : 'N')); + ++addr; + ++data; + } +} + +/* + * display current instruction and data cplb tables + */ +int do_cplbinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("%s CPLB table [%08x]:\n", "Instruction", *(uint32_t *)DMEM_CONTROL); + show_cplb_table((uint32_t *)ICPLB_ADDR0, (uint32_t *)ICPLB_DATA0); + + printf("%s CPLB table [%08x]:\n", "Data", *(uint32_t *)IMEM_CONTROL); + show_cplb_table((uint32_t *)DCPLB_ADDR0, (uint32_t *)DCPLB_DATA0); + + return 0; +} + +U_BOOT_CMD(cplbinfo, 1, 0, do_cplbinfo, + "cplbinfo- display current CPLB tables\n", + "\n" + " - display current CPLB tables\n"); diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 9cd22ee94a..a52284e2fe 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -260,7 +260,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /******************************************************************** * Remove a property/node ********************************************************************/ - } else if (argv[1][0] == 'r') { + } else if ((argv[1][0] == 'r') && (argv[1][1] == 'm')) { int nodeoffset; /* node offset from libfdt */ int err; @@ -296,6 +296,111 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return err; } } + + /******************************************************************** + * Display header info + ********************************************************************/ + } else if (argv[1][0] == 'h') { + u32 version = fdt_version(fdt); + printf("magic:\t\t\t0x%x\n", fdt_magic(fdt)); + printf("totalsize:\t\t0x%x (%d)\n", fdt_totalsize(fdt), fdt_totalsize(fdt)); + printf("off_dt_struct:\t\t0x%x\n", fdt_off_dt_struct(fdt)); + printf("off_dt_strings:\t\t0x%x\n", fdt_off_dt_strings(fdt)); + printf("off_mem_rsvmap:\t\t0x%x\n", fdt_off_mem_rsvmap(fdt)); + printf("version:\t\t%d\n", version); + printf("last_comp_version:\t%d\n", fdt_last_comp_version(fdt)); + if (version >= 2) + printf("boot_cpuid_phys:\t0x%x\n", + fdt_boot_cpuid_phys(fdt)); + if (version >= 3) + printf("size_dt_strings:\t0x%x\n", + fdt_size_dt_strings(fdt)); + if (version >= 17) + printf("size_dt_struct:\t\t0x%x\n", + fdt_size_dt_struct(fdt)); + printf("number mem_rsv:\t\t0x%x\n", fdt_num_mem_rsv(fdt)); + printf("\n"); + + /******************************************************************** + * Set boot cpu id + ********************************************************************/ + } else if ((argv[1][0] == 'b') && (argv[1][1] == 'o') && + (argv[1][2] == 'o')) { + unsigned long tmp = simple_strtoul(argv[2], NULL, 16); + fdt_set_boot_cpuid_phys(fdt, tmp); + + /******************************************************************** + * memory command + ********************************************************************/ + } else if ((argv[1][0] == 'm') && (argv[1][1] == 'e')) { + uint64_t addr, size; + int err; +#ifdef CFG_64BIT_STRTOUL + addr = simple_strtoull(argv[2], NULL, 16); + size = simple_strtoull(argv[3], NULL, 16); +#else + addr = simple_strtoul(argv[2], NULL, 16); + size = simple_strtoul(argv[3], NULL, 16); +#endif + err = fdt_fixup_memory(fdt, addr, size); + if (err < 0) + return err; + + /******************************************************************** + * mem reserve commands + ********************************************************************/ + } else if ((argv[1][0] == 'r') && (argv[1][1] == 's')) { + if (argv[2][0] == 'p') { + uint64_t addr, size; + int total = fdt_num_mem_rsv(fdt); + int j, err; + printf("index\t\t start\t\t size\n"); + printf("-------------------------------" + "-----------------\n"); + for (j = 0; j < total; j++) { + err = fdt_get_mem_rsv(fdt, j, &addr, &size); + if (err < 0) { + printf("libfdt fdt_get_mem_rsv(): %s\n", + fdt_strerror(err)); + return err; + } + printf(" %x\t%08x%08x\t%08x%08x\n", j, + (u32)(addr >> 32), + (u32)(addr & 0xffffffff), + (u32)(size >> 32), + (u32)(size & 0xffffffff)); + } + } else if (argv[2][0] == 'a') { + uint64_t addr, size; + int err; +#ifdef CFG_64BIT_STRTOUL + addr = simple_strtoull(argv[3], NULL, 16); + size = simple_strtoull(argv[4], NULL, 16); +#else + addr = simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 16); +#endif + err = fdt_add_mem_rsv(fdt, addr, size); + + if (err < 0) { + printf("libfdt fdt_add_mem_rsv(): %s\n", + fdt_strerror(err)); + return err; + } + } else if (argv[2][0] == 'd') { + unsigned long idx = simple_strtoul(argv[3], NULL, 16); + int err = fdt_del_mem_rsv(fdt, idx); + + if (err < 0) { + printf("libfdt fdt_del_mem_rsv(): %s\n", + fdt_strerror(err)); + return err; + } + } else { + /* Unrecognized command */ + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } } #ifdef CONFIG_OF_BOARD_SETUP /* Call the board-specific fixup routine */ @@ -305,17 +410,6 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Create a chosen node */ else if (argv[1][0] == 'c') fdt_chosen(fdt, 0, 0, 1); - -#ifdef CONFIG_OF_HAS_UBOOT_ENV - /* Create a u-boot-env node */ - else if (argv[1][0] == 'e') - fdt_env(fdt); -#endif -#ifdef CONFIG_OF_HAS_BD_T - /* Create a bd_t node */ - else if (argv[1][0] == 'b') - fdt_bd_t(fdt); -#endif else { /* Unrecognized command */ printf ("Usage:\n%s\n", cmdtp->usage); @@ -689,13 +783,13 @@ U_BOOT_CMD( "fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n" "fdt mknode <path> <node> - Create a new node after <path>\n" "fdt rm <path> [<prop>] - Delete the node or <property>\n" + "fdt header - Display header info\n" + "fdt bootcpu <id> - Set boot cpuid\n" + "fdt memory <addr> <size> - Add/Update memory node\n" + "fdt rsvmem print - Show current mem reserves\n" + "fdt rsvmem add <addr> <size> - Add a mem reserve\n" + "fdt rsvmem delete <index> - Delete a mem reserves\n" "fdt chosen - Add/update the /chosen branch in the tree\n" -#ifdef CONFIG_OF_HAS_UBOOT_ENV - "fdt env - Add/replace the /u-boot-env branch in the tree\n" -#endif -#ifdef CONFIG_OF_HAS_BD_T - "fdt bd_t - Add/replace the /bd_t branch in the tree\n" -#endif "NOTE: If the path or property you are setting/printing has a '#' character\n" " or spaces, you MUST escape it with a \\ character or quote it with \".\n" ); diff --git a/common/cmd_log.c b/common/cmd_log.c index e593dbedd3..34b36ff1dd 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -59,14 +59,25 @@ static char buf[1024]; static unsigned console_loglevel = 3; static unsigned default_message_loglevel = 4; static unsigned log_version = 1; +#ifdef CONFIG_ALT_LB_ADDR +static volatile logbuff_t *log; +#else static logbuff_t *log; +#endif +static char *lbuf; void logbuff_init_ptrs (void) { unsigned long tag, post_word; char *s; +#ifdef CONFIG_ALT_LB_ADDR + log = (logbuff_t *)CONFIG_ALT_LH_ADDR; + lbuf = (char *)CONFIG_ALT_LB_ADDR; +#else log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1; + lbuf = log->buf; +#endif /* Set up log version */ if ((s = getenv ("logversion")) != NULL) @@ -101,11 +112,26 @@ void logbuff_init_ptrs (void) void logbuff_reset (void) { +#ifndef CONFIG_ALT_LB_ADDR memset (log, 0, sizeof (logbuff_t)); - if (log_version == 2) +#endif + if (log_version == 2) { log->v2.tag = LOGBUFF_MAGIC; - else +#ifdef CONFIG_ALT_LB_ADDR + log->v2.start = 0; + log->v2.con = 0; + log->v2.end = 0; + log->v2.chars = 0; +#endif + } else { log->v1.tag = LOGBUFF_MAGIC; +#ifdef CONFIG_ALT_LB_ADDR + log->v1.dummy = 0; + log->v1.start = 0; + log->v1.size = 0; + log->v1.chars = 0; +#endif + } } int drv_logbuff_init (void) @@ -188,7 +214,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) size = log->v1.size; } for (i=0; i < (size&LOGBUFF_MASK); i++) { - s = (char *)log->buf+((start+i)&LOGBUFF_MASK); + s = lbuf+((start+i)&LOGBUFF_MASK); putc (*s); } return 0; @@ -196,7 +222,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) logbuff_reset (); return 0; } else if (strcmp(argv[1],"info") == 0) { - printf ("Logbuffer at %08lx\n", (unsigned long)log->buf); + printf ("Logbuffer at %08lx\n", (unsigned long)lbuf); if (log_version == 2) { printf ("log_start = %08lx\n", log->v2.start); printf ("log_end = %08lx\n", log->v2.end); @@ -257,14 +283,14 @@ static int logbuff_printk(const char *line) line_feed = 0; for (; p < buf_end; p++) { if (log_version == 2) { - log->buf[log->v2.end & LOGBUFF_MASK] = *p; + lbuf[log->v2.end & LOGBUFF_MASK] = *p; log->v2.end++; if (log->v2.end - log->v2.start > LOGBUFF_LEN) log->v2.start++; log->v2.chars++; } else { - log->buf[(log->v1.start + log->v1.size) & + lbuf[(log->v1.start + log->v1.size) & LOGBUFF_MASK] = *p; if (log->v1.size < LOGBUFF_LEN) log->v1.size++; diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c new file mode 100644 index 0000000000..2e49b6dd92 --- /dev/null +++ b/common/cmd_setexpr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file provides a shell like 'expr' function to return. + */ + +#include <common.h> +#include <config.h> +#include <command.h> + +int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong a, b; + char buf[16]; + + /* Validate arguments */ + if ((argc != 5) || (strlen(argv[3]) != 1)) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + a = simple_strtoul(argv[2], NULL, 16); + b = simple_strtoul(argv[4], NULL, 16); + + switch (argv[3][0]) { + case '|': sprintf(buf, "%lx", (a | b)); break; + case '&': sprintf(buf, "%lx", (a & b)); break; + case '+': sprintf(buf, "%lx", (a + b)); break; + case '^': sprintf(buf, "%lx", (a ^ b)); break; + case '-': sprintf(buf, "%lx", (a - b)); break; + case '*': sprintf(buf, "%lx", (a * b)); break; + case '/': sprintf(buf, "%lx", (a / b)); break; + case '%': sprintf(buf, "%lx", (a % b)); break; + default: + printf("invalid op\n"); + return 1; + } + + setenv(argv[1], buf); + + return 0; +} + +U_BOOT_CMD( + setexpr, 5, 0, do_setexpr, + "setexpr - set environment variable as the result of eval expression\n", + "name value1 <op> value2\n" + " - set environment variable 'name' to the result of the evaluated\n" + " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n" +); diff --git a/common/fdt_support.c b/common/fdt_support.c index 69eb667954..75077442d8 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -40,7 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; */ struct fdt_header *fdt; -/********************************************************************/ /** * fdt_find_and_setprop: Find a node and set it's property @@ -218,198 +217,6 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) return err; } -/********************************************************************/ - -#ifdef CONFIG_OF_HAS_UBOOT_ENV - -/* Function that returns a character from the environment */ -extern uchar(*env_get_char) (int); - - -int fdt_env(void *fdt) -{ - int nodeoffset; - int err; - int k, nxt; - int i; - static char tmpenv[256]; - - err = fdt_check_header(fdt); - if (err < 0) { - printf("fdt_env: %s\n", fdt_strerror(err)); - return err; - } - - /* - * See if we already have a "u-boot-env" node, delete it if so. - * Then create a new empty node. - */ - nodeoffset = fdt_path_offset (fdt, "/u-boot-env"); - if (nodeoffset >= 0) { - err = fdt_del_node(fdt, nodeoffset); - if (err < 0) { - printf("fdt_env: %s\n", fdt_strerror(err)); - return err; - } - } - /* - * Create a new node "/u-boot-env" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env"); - if (nodeoffset < 0) { - printf("WARNING: could not create /u-boot-env %s.\n", - fdt_strerror(nodeoffset)); - return nodeoffset; - } - - for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { - char *s, *lval, *rval; - - /* - * Find the end of the name=definition - */ - for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) - ; - s = tmpenv; - for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) - *s++ = env_get_char(k); - *s++ = '\0'; - lval = tmpenv; - /* - * Find the first '=': it separates the name from the value - */ - s = strchr(tmpenv, '='); - if (s != NULL) { - *s++ = '\0'; - rval = s; - } else - continue; - err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1); - if (err < 0) { - printf("WARNING: could not set %s %s.\n", - lval, fdt_strerror(err)); - return err; - } - } - return 0; -} -#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */ - -/********************************************************************/ - -#ifdef CONFIG_OF_HAS_BD_T - -#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } - -static const struct { - const char *name; - int offset; -} bd_map[] = { - BDM(memstart), - BDM(memsize), - BDM(flashstart), - BDM(flashsize), - BDM(flashoffset), - BDM(sramstart), - BDM(sramsize), -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) - BDM(immr_base), -#endif -#if defined(CONFIG_MPC5xxx) - BDM(mbar_base), -#endif -#if defined(CONFIG_MPC83XX) - BDM(immrbar), -#endif -#if defined(CONFIG_MPC8220) - BDM(mbar_base), - BDM(inpfreq), - BDM(pcifreq), - BDM(pevfreq), - BDM(flbfreq), - BDM(vcofreq), -#endif - BDM(bootflags), - BDM(ip_addr), - BDM(intfreq), - BDM(busfreq), -#ifdef CONFIG_CPM2 - BDM(cpmfreq), - BDM(brgfreq), - BDM(sccfreq), - BDM(vco), -#endif -#if defined(CONFIG_MPC5xxx) - BDM(ipbfreq), - BDM(pcifreq), -#endif - BDM(baudrate), -}; - - -int fdt_bd_t(void *fdt) -{ - bd_t *bd = gd->bd; - int nodeoffset; - int err; - u32 tmp; /* used to set 32 bit integer properties */ - int i; - - err = fdt_check_header(fdt); - if (err < 0) { - printf("fdt_bd_t: %s\n", fdt_strerror(err)); - return err; - } - - /* - * See if we already have a "bd_t" node, delete it if so. - * Then create a new empty node. - */ - nodeoffset = fdt_path_offset (fdt, "/bd_t"); - if (nodeoffset >= 0) { - err = fdt_del_node(fdt, nodeoffset); - if (err < 0) { - printf("fdt_bd_t: %s\n", fdt_strerror(err)); - return err; - } - } - /* - * Create a new node "/bd_t" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "bd_t"); - if (nodeoffset < 0) { - printf("WARNING: could not create /bd_t %s.\n", - fdt_strerror(nodeoffset)); - printf("fdt_bd_t: %s\n", fdt_strerror(nodeoffset)); - return nodeoffset; - } - /* - * Use the string/pointer structure to create the entries... - */ - for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { - tmp = cpu_to_be32(getenv("bootargs")); - err = fdt_setprop(fdt, nodeoffset, - bd_map[i].name, &tmp, sizeof(tmp)); - if (err < 0) - printf("WARNING: could not set %s %s.\n", - bd_map[i].name, fdt_strerror(err)); - } - /* - * Add a couple of oddball entries... - */ - err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6); - if (err < 0) - printf("WARNING: could not set enetaddr %s.\n", - fdt_strerror(err)); - err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4); - if (err < 0) - printf("WARNING: could not set ethspeed %s.\n", - fdt_strerror(err)); - return 0; -} -#endif /* ifdef CONFIG_OF_HAS_BD_T */ - void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create) { @@ -615,3 +422,28 @@ void fdt_fixup_ethernet(void *fdt, bd_t *bd) } } #endif + +#ifdef CONFIG_HAS_FSL_DR_USB +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + char *mode; + const char *compat = "fsl-usb2-dr"; + const char *prop = "dr_mode"; + int node_offset; + int err; + + mode = getenv("usb_dr_mode"); + if (!mode) + return; + + node_offset = fdt_node_offset_by_compatible(blob, 0, compat); + if (node_offset < 0) + printf("WARNING: could not find compatible node %s: %s.\n", + compat, fdt_strerror(node_offset)); + + err = fdt_setprop(blob, node_offset, prop, mode, strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop, compat, fdt_strerror(err)); +} +#endif /* CONFIG_HAS_FSL_DR_USB */ diff --git a/common/main.c b/common/main.c index 163ba02e62..21e7afab61 100644 --- a/common/main.c +++ b/common/main.c @@ -40,7 +40,7 @@ #include <post.h> -#ifdef CONFIG_SILENT_CONSOLE +#if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST) DECLARE_GLOBAL_DATA_PTR; #endif @@ -369,6 +369,12 @@ void main_loop (void) init_cmd_timeout (); # endif /* CONFIG_BOOT_RETRY_TIME */ +#ifdef CONFIG_POST + if (gd->flags & GD_FLG_POSTFAIL) { + s = getenv("failbootcmd"); + } + else +#endif /* CONFIG_POST */ #ifdef CONFIG_BOOTCOUNT_LIMIT if (bootlimit && (bootcount > bootlimit)) { printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 443240e540..89ada716c3 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -1,5 +1,5 @@ /* - * Cache-handling routined for MIPS 4K CPUs + * Cache-handling routined for MIPS CPUs * * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> * @@ -24,15 +24,32 @@ #include <config.h> #include <version.h> +#include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/addrspace.h> #include <asm/cacheops.h> - /* 16KB is the maximum size of instruction and data caches on - * MIPS 4K. - */ -#define MIPS_MAX_CACHE_SIZE 0x4000 +#define RA t8 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE 0x10000 + +#define INDEX_BASE KSEG0 + + .macro cache_op op addr + .set push + .set noreorder + .set mips3 + cache \op, 0(\addr) + .set pop + .endm /* * cacheop macro to automate cache operations @@ -103,6 +120,77 @@ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_op Fill t0 + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + /******************************************************************************* * * mips_cache_reset - low level initialisation of the primary caches @@ -119,10 +207,8 @@ * RETURNS: N/A * */ - .globl mips_cache_reset - .ent mips_cache_reset -mips_cache_reset: - +NESTED(mips_cache_reset, 0, ra) + move RA, ra li t2, CFG_ICACHE_SIZE li t3, CFG_DCACHE_SIZE li t4, CFG_CACHELINE_SIZE @@ -130,27 +216,14 @@ mips_cache_reset: li v0, MIPS_MAX_CACHE_SIZE - /* Now clear that much memory starting from zero. - */ - - li a0, KSEG1 - addu a1, a0, v0 -2: - sw zero, 0(a0) - sw zero, 4(a0) - sw zero, 8(a0) - sw zero, 12(a0) - sw zero, 16(a0) - sw zero, 20(a0) - sw zero, 24(a0) - sw zero, 28(a0) - addu a0, 32 - bltu a0, a1, 2b - - /* Set invalid tag. + /* + * Now clear that much memory starting from zero. */ - - mtc0 zero, CP0_TAGLO + PTR_LI a0, KSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b /* * The caches are probably in an indeterminate state, @@ -158,48 +231,26 @@ mips_cache_reset: * invalidate, load/fill, invalidate for each line. */ - /* Assume bottom of RAM will generate good parity for the cache. - */ - - li a0, K0BASE - move a2, t2 # icacheSize - move a3, t4 # icacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - - /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ - - /* 1: initialise dcache tags. + /* + * Assume bottom of RAM will generate good parity for the cache. */ - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - /* 2: fill dcache. + /* + * Initialize the I-cache first, */ + move a1, t2 + move a2, t4 + bal mips_init_icache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,1lw,(dummy)) - - /* 3: clear dcache tags. + /* + * then initialize D-cache. */ + move a1, t3 + move a2, t5 + bal mips_init_dcache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - j ra - - .end mips_cache_reset + jr RA + END(mips_cache_reset) /******************************************************************************* * @@ -208,15 +259,15 @@ mips_cache_reset: * RETURNS: 0 - cache disabled; 1 - cache enabled * */ - .globl dcache_status - .ent dcache_status -dcache_status: - - mfc0 v0, CP0_CONFIG - andi v0, v0, 1 - j ra - - .end dcache_status +LEAF(dcache_status) + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_UNCACHED + andi t0, t0, CONF_CM_CMASK + move v0, zero + beq t0, t1, 2f + li v0, 1 +2: jr ra + END(dcache_status) /******************************************************************************* * @@ -225,19 +276,16 @@ dcache_status: * RETURNS: N/A * */ - .globl dcache_disable - .ent dcache_disable -dcache_disable: - +LEAF(dcache_disable) mfc0 t0, CP0_CONFIG li t1, -8 and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG j ra + END(dcache_disable) - .end dcache_disable - +#ifdef CFG_INIT_RAM_LOCK_MIPS /******************************************************************************* * * mips_cache_lock - lock RAM area pointed to by a0 in cache. @@ -263,3 +311,4 @@ mips_cache_lock: j ra .end mips_cache_lock +#endif /* CFG_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 7559ac657f..8b43d8eb36 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -23,24 +23,45 @@ #include <common.h> #include <command.h> -#include <asm/inca-ip.h> #include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ +} int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_INCA_IP) - *INCA_IP_WDT_RST_REQ = 0x3f; -#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) - void (*f)(void) = (void *) 0xbfc00000; + _machine_restart(); - f(); -#endif fprintf(stderr, "*** reset failed ***\n"); return 0; } void flush_cache(ulong start_addr, ulong size) { + unsigned long lsize = CFG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, start_addr); + cache_op(Hit_Invalidate_I, start_addr); + if (addr == aend) + break; + addr += lsize; + } } void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162782..baac2ceaf0 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -27,6 +27,30 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -211,19 +235,11 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS - - /* CAUSE register */ + /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0 zero, CP0_CAUSE + setup_c0_status_reset + /* Init Timer */ mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE @@ -240,14 +256,6 @@ reset: 1: lw gp, 0(ra) -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop -#endif - /* Initialize any external memory. */ la t9, lowlevel_init @@ -267,10 +275,12 @@ reset: /* Set up temporary stack. */ +#ifdef CFG_INIT_RAM_LOCK_MIPS li a0, CFG_INIT_SP_OFFSET la t9, mips_cache_lock jalr t9 nop +#endif li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0) diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 7522afe477..ace16535ff 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -119,7 +119,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) { int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; char * cpu_path = "/cpus/" OF_CPU; +#ifdef CONFIG_MPC5xxx_FEC char * eth_path = "/" OF_SOC "/ethernet@3000"; +#endif do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); @@ -127,7 +129,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", bd->bi_busfreq*div, 1); +#ifdef CONFIG_MPC5xxx_FEC do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); +#endif } #endif diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 94a3cb8334..fcb6a52465 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -28,9 +28,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o ecc.o qe_io.o pci.o fdt.o +COBJS-y += traps.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += speed.o +COBJS-y += interrupts.o +COBJS-y += spd_sdram.o +COBJS-y += ecc.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_FSL_SERDES) += serdes.o +COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e643037d27..fba5b02ece 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -79,6 +79,12 @@ void cpu_init_f (volatile immap_t * im) (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); #endif +#ifdef CFG_SPCR_OPT + /* Optimize transactions between CSB and other devices */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | + (CFG_SPCR_OPT << SPCR_OPT_SHIFT); +#endif + #ifdef CFG_SPCR_TSECEP /* all eTSEC's Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 6f55932da2..b39f678f1a 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -24,9 +24,6 @@ */ #include <common.h> - -#if defined(CONFIG_OF_LIBFDT) - #include <libfdt.h> #include <fdt_support.h> @@ -49,6 +46,14 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", gd->core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,soc", + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,soc", + "clock-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,immr", + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,immr", + "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif @@ -68,4 +73,3 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 18558db537..adabf7aac7 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -33,7 +33,6 @@ #include <asm/mpc8349_pci.h> -#ifdef CONFIG_83XX_GENERIC_PCI #define MAX_BUSES 2 DECLARE_GLOBAL_DATA_PTR; @@ -209,4 +208,3 @@ void ft_pci_setup(void *blob, bd_t *bd) } } #endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_83XX_GENERIC_PCI */ diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index 8b3937aa9b..ce91a07d72 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -25,7 +25,6 @@ #include "asm/io.h" #include "asm/immap_83xx.h" -#if defined(CONFIG_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { @@ -81,5 +80,3 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); } } - -#endif /* CONFIG_QE */ diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c new file mode 100644 index 0000000000..020c4c8f91 --- /dev/null +++ b/cpu/mpc83xx/serdes.c @@ -0,0 +1,145 @@ +/* + * Freescale SerDes initialization routine + * + * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * + * Author: Li Yang <leoli@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> + +/* SerDes registers */ +#define FSL_SRDSCR0_OFFS 0x0 +#define FSL_SRDSCR0_DPP_1V2 0x00008800 +#define FSL_SRDSCR1_OFFS 0x4 +#define FSL_SRDSCR1_PLLBW 0x00000040 +#define FSL_SRDSCR2_OFFS 0x8 +#define FSL_SRDSCR2_VDD_1V2 0x00800000 +#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c +#define FSL_SRDSCR2_SEIC_SATA 0x00001414 +#define FSL_SRDSCR2_SEIC_PEX 0x00001010 +#define FSL_SRDSCR2_SEIC_SGMII 0x00000101 +#define FSL_SRDSCR3_OFFS 0xc +#define FSL_SRDSCR3_KFR_SATA 0x10100000 +#define FSL_SRDSCR3_KPH_SATA 0x04040000 +#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 +#define FSL_SRDSCR3_SDTXL_SATA 0x00000505 +#define FSL_SRDSCR4_OFFS 0x10 +#define FSL_SRDSCR4_PROT_SATA 0x00000808 +#define FSL_SRDSCR4_PROT_PEX 0x00000101 +#define FSL_SRDSCR4_PROT_SGMII 0x00000505 +#define FSL_SRDSCR4_PLANE_X2 0x01000000 +#define FSL_SRDSRSTCTL_OFFS 0x20 +#define FSL_SRDSRSTCTL_RST 0x80000000 +#define FSL_SRDSRSTCTL_SATA_RESET 0xf + +void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) +{ + void *regs = (void *)CFG_IMMR + offset; + u32 tmp; + + /* 1.0V corevdd */ + if (vdd) { + /* DPPE/DPPA = 0 */ + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_DPP_1V2; + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); + + /* VDD = 0 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_VDD_1V2; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + } + + /* protocol specific configuration */ + switch (proto) { + case FSL_SERDES_PROTO_SATA: + /* Set and clear reset bits */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + udelay(1000); + tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SATA; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | + FSL_SRDSCR3_SDFM_SATA_PEX | + FSL_SRDSCR3_SDTXL_SATA; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SATA; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_PEX: + case FSL_SERDES_PROTO_PEX_X2: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp |= FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_PEX; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_SDFM_SATA_PEX; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_PEX; + if (proto == FSL_SERDES_PROTO_PEX_X2) + tmp |= FSL_SRDSCR4_PLANE_X2; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_SGMII: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SGMII; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + out_be32(regs + FSL_SRDSCR3_OFFS, 0); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + default: + return; + } + + /* Do a software reset */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_RST; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); +} diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index 223b30cbcc..dbdc2e0612 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o kgdb.o COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ - fec.o i2c.o interrupts.o lcd.o scc.o \ + fec.o fdt.o i2c.o interrupts.o lcd.o scc.o \ serial.o speed.o spi.o \ traps.o upatch.o video.o SOBJS = plprcr_write.o diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index 5d4ab82034..ec6a3fd5d6 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -634,17 +634,4 @@ void reset_8xx_watchdog (volatile immap_t * immr) immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ # endif /* CONFIG_LWMON */ } - #endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup (void *blob, bd_t *bd) -{ - char * cpu_path = "/cpus/" OF_CPU; - - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc8xx/fdt.c b/cpu/mpc8xx/fdt.c new file mode 100644 index 0000000000..567094a96b --- /dev/null +++ b/cpu/mpc8xx/fdt.c @@ -0,0 +1,46 @@ +/* + * Copyright 2008 (C) Bryan O'Donoghue + * + * Code copied & edited from Freescale mpc85xx stuff. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", get_tbclk(), 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", + gd->brg_clk, 1); + + /* Fixup ethernet MAC addresses */ + fdt_fixup_ethernet(blob, bd); + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 11b089330b..070babcc9a 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -174,6 +174,27 @@ unsigned long measure_gclk(void) #endif +void get_brgclk(uint sccr) +{ + uint divider = 0; + + switch((sccr&SCCR_DFBRG11)>>11){ + case 0: + divider = 1; + break; + case 1: + divider = 4; + break; + case 2: + divider = 16; + break; + case 3: + divider = 64; + break; + } + gd->brg_clk = gd->cpu_clk/divider; +} + #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) /* @@ -223,6 +244,8 @@ int get_clocks (void) gd->bus_clk = gd->cpu_clk / 2; } + get_brgclk(sccr); + return (0); } @@ -254,6 +277,8 @@ int get_clocks_866 (void) gd->cpu_clk = measure_gclk (); #endif + get_brgclk(immr->im_clkrst.car_sccr); + /* if cpu clock <= 66 MHz then set bus division factor to 1, * otherwise set it to 2 */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 3bafea3a95..9e722b9984 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -42,7 +42,8 @@ #include <asm/mmu.h> #if defined(CONFIG_SPD_EEPROM) && \ - (defined(CONFIG_440SP) || defined(CONFIG_440SPE)) + (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) /*-----------------------------------------------------------------------------+ * Defines @@ -579,6 +580,13 @@ long int initdram(int board_type) ppc440sp_sdram_register_dump(); + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + return dram_size; } @@ -2125,6 +2133,7 @@ static void program_memory_queue(unsigned long *dimm_populated, unsigned long baseadd_size; unsigned long i; unsigned long bank_0_populated = 0; + unsigned long total_size = 0; /*------------------------------------------------------------------ * Reset the rank_base_address. @@ -2147,28 +2156,38 @@ static void program_memory_queue(unsigned long *dimm_populated, * Set the sizes *-----------------------------------------------------------------*/ baseadd_size = 0; - rank_size_bytes = 4 * 1024 * 1024 * rank_size_id; switch (rank_size_id) { + case 0x01: + baseadd_size |= SDRAM_RXBAS_SDSZ_1024; + total_size = 1024; + break; case 0x02: - baseadd_size |= SDRAM_RXBAS_SDSZ_8; + baseadd_size |= SDRAM_RXBAS_SDSZ_2048; + total_size = 2048; break; case 0x04: - baseadd_size |= SDRAM_RXBAS_SDSZ_16; + baseadd_size |= SDRAM_RXBAS_SDSZ_4096; + total_size = 4096; break; case 0x08: baseadd_size |= SDRAM_RXBAS_SDSZ_32; + total_size = 32; break; case 0x10: baseadd_size |= SDRAM_RXBAS_SDSZ_64; + total_size = 64; break; case 0x20: baseadd_size |= SDRAM_RXBAS_SDSZ_128; + total_size = 128; break; case 0x40: baseadd_size |= SDRAM_RXBAS_SDSZ_256; + total_size = 256; break; case 0x80: baseadd_size |= SDRAM_RXBAS_SDSZ_512; + total_size = 512; break; default: printf("DDR-SDRAM: DIMM %d memory queue configuration.\n", @@ -2178,6 +2197,7 @@ static void program_memory_queue(unsigned long *dimm_populated, printf("Replace the DIMM module with a supported DIMM.\n\n"); spd_ddr_init_hang (); } + rank_size_bytes = total_size << 20; if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) bank_0_populated = 1; @@ -2190,6 +2210,19 @@ static void program_memory_queue(unsigned long *dimm_populated, } } } + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* + * Enable high bandwidth access on 460EX/GT. + * This should/could probably be done on other + * PPC's too, like 440SPe. + * This is currently not used, but with this setup + * it is possible to use it later on in e.g. the Linux + * EMAC driver for performance gain. + */ + mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ + mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ +#endif } /*-----------------------------------------------------------------------------+ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 599f5ceb56..d990250fcb 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -137,17 +137,32 @@ #define BI_PHYMODE_RTBI 4 #define BI_PHYMODE_TBI 5 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #define BI_PHYMODE_SMII 6 #define BI_PHYMODE_MII 7 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define BI_PHYMODE_RMII 8 +#endif #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ +#else +#define MAL_RX_CHAN_MUL 1 +#endif + /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ @@ -214,6 +229,44 @@ extern int emac4xx_miiphy_write (char *devname, unsigned char addr, int board_emac_count(void); +static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) +{ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) + u32 val; + + mfsdr(sdr_mfr, val); + val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); + mtsdr(sdr_mfr, val); +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 val; + + mfsdr(SDR0_ETH_CFG, val); + val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_ETH_CFG, val); +#endif +} + +static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) +{ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) + u32 val; + + mfsdr(sdr_mfr, val); + val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); + mtsdr(sdr_mfr, val); +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 val; + + mfsdr(SDR0_ETH_CFG, val); + val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_ETH_CFG, val); +#endif +} + /*-----------------------------------------------------------------------------+ | ppc_4xx_eth_halt | Disable MAL channel, and EMACn @@ -222,11 +275,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) - unsigned long mfr; -#endif out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -247,27 +295,14 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) break; } - /* EMAC RESET */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); - mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, mfr); -#endif + emac_loopback_enable(hw_p); + /* EMAC RESET */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) /* remove clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, mfr); -#endif - + emac_loopback_disable(hw_p); #ifndef CONFIG_NETCONSOLE hw_p->print_speed = 1; /* print speed message again next time */ @@ -452,6 +487,187 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } #endif /* CONFIG_405EX */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + u32 eth_cfg; + u32 zmiifer; /* ZMII0_FER reg. */ + u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ + u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ + + zmiifer = 0; + rmiifer = 0; + rmiifer1 = 0; + + /* TODO: + * NOTE: 460GT has 2 RGMII bridge cores: + * emac0 ------ RGMII0_BASE + * | + * emac1 -----+ + * + * emac2 ------ RGMII1_BASE + * | + * emac3 -----+ + * + * 460EX has 1 RGMII bridge core: + * and RGMII1_BASE is disabled + * emac0 ------ RGMII0_BASE + * | + * emac1 -----+ + */ + + /* + * Right now only 2*RGMII is supported. Please extend when needed. + * sr - 2008-02-19 + */ + switch (9) { + case 1: + /* 1 MII - 460EX */ + /* GMC0 EMAC4_0, ZMII Bridge */ + zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 2: + /* 2 MII - 460GT */ + /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ + zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_MII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 3: + /* 2 RMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + bis->bi_phymode[0] = BI_PHYMODE_RMII; + bis->bi_phymode[1] = BI_PHYMODE_RMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 4: + /* 4 RMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ + /* ZMII Bridge */ + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_RMII; + bis->bi_phymode[1] = BI_PHYMODE_RMII; + bis->bi_phymode[2] = BI_PHYMODE_RMII; + bis->bi_phymode[3] = BI_PHYMODE_RMII; + break; + case 5: + /* 2 SMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 6: + /* 4 SMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ + /* ZMII Bridge */ + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + bis->bi_phymode[2] = BI_PHYMODE_SMII; + bis->bi_phymode[3] = BI_PHYMODE_SMII; + break; + case 7: + /* This is the default mode that we want for board bringup - Maple */ + /* 1 GMII - 460EX */ + /* GMC0 EMAC4_0, RGMII Bridge 0 */ + rmiifer |= RGMII_FER_MDIO(0); + + if (devnum == 0) { + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + } else { + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_GMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + } + break; + case 8: + /* 2 GMII - 460GT */ + /* GMC0 EMAC4_0, RGMII Bridge 0 */ + /* GMC1 EMAC4_2, RGMII Bridge 1 */ + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ + rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ + rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ + rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ + + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_GMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 9: + /* 2 RGMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ + + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 10: + /* 4 RGMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + default: + break; + } + + /* Set EMAC for MDIO */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; + mtsdr(SDR0_ETH_CFG, eth_cfg); + + out_be32((void *)RGMII_FER, rmiifer); +#if defined(CONFIG_460GT) + out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); +#endif + + /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, eth_cfg); + + return 0; +} +#endif /* CONFIG_460EX || CONFIG_460GT */ + static inline void *malloc_aligned(u32 size, u32 align) { return (void *)(((u32)malloc(size + align) + align - 1) & @@ -472,19 +688,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) sys_info_t sysinfo; #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) int ethgroup = -1; #endif #endif -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_405EX) - unsigned long mfr; -#endif u32 bd_cached; u32 bd_uncached = 0; #ifdef CONFIG_4xx_DCACHE @@ -503,6 +716,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); @@ -556,21 +770,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) out_be32((void *)ZMII_FER, 0); udelay (100); -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); -#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#elif defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); -#elif defined(CONFIG_440GP) - /* set RMII mode */ - out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0); -#else - if ((devnum == 0) || (devnum == 1)) { - out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); - } else { /* ((devnum == 2) || (devnum == 3)) */ - out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); - out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | - (RGMII_FER_RGMII << RGMII_FER_V (3)))); - } #endif out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); @@ -579,20 +784,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #endif - __asm__ volatile ("eieio"); + sync(); - /* reset emac so we have access to the phy */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); - mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr(sdr_mfr, mfr); -#endif + emac_loopback_enable(hw_p); + /* EMAC RESET */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + /* remove clocks for EMAC internal loopback */ + emac_loopback_disable(hw_p); + failsafe = 1000; while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); @@ -601,18 +803,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (failsafe <= 0) printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) - /* remove clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr(sdr_mfr, mfr); -#endif - #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) /* Whack the M1 register */ mode_reg = 0x0; @@ -674,6 +868,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #if defined(CONFIG_CIS8201_PHY) @@ -772,8 +967,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->devnum); } -#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) +#if defined(CONFIG_440) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_460EX) && !defined(CONFIG_460GT) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { @@ -807,6 +1004,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) if (speed == 1000) reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); @@ -819,12 +1017,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) return -1; } out_be32((void *)RGMII_SSR, reg); +#if defined(CONFIG_460GT) + if ((devnum == 2) || (devnum == 3)) + out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); +#endif #endif /* set the Mal configuration reg */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); @@ -926,9 +1129,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + mtdcr (malrxctp8r, hw_p->rx); + /* set RX buffer size */ + mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); +#else mtdcr (malrxctp1r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); +#endif break; #if defined (CONFIG_440GX) case 2: @@ -1087,7 +1297,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, hw_p->tx[hw_p->tx_slot].data_len = (short) len; hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; - __asm__ volatile ("eieio"); + sync(); out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); @@ -1127,15 +1337,31 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, */ #define UIC0MSR uic1msr #define UIC0SR uic1sr +#define UIC1MSR uic1msr +#define UIC1SR uic1sr +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* + * Hack: On 460EX/GT all enet irq sources are located on UIC2 + * Needs some cleanup. --ag + */ +#define UIC0MSR uic2msr +#define UIC0SR uic2sr +#define UIC1MSR uic2msr +#define UIC1SR uic2sr #else #define UIC0MSR uic0msr #define UIC0SR uic0sr +#define UIC1MSR uic1msr +#define UIC1SR uic1sr #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) #define UICMSR_ETHX uic0msr #define UICSR_ETHX uic0sr +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define UICMSR_ETHX uic2msr +#define UICSR_ETHX uic2sr #else #define UICMSR_ETHX uic1msr #define UICSR_ETHX uic1sr @@ -1173,7 +1399,7 @@ int enetInt (struct eth_device *dev) serviced = 0; my_uic0msr = mfdcr (UIC0MSR); - my_uic1msr = mfdcr (uic1msr); + my_uic1msr = mfdcr (UIC1MSR); #if defined(CONFIG_440GX) my_uic2msr = mfdcr (uic2msr); #endif @@ -1219,7 +1445,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ return (rc); /* we had errors so get out */ } @@ -1238,7 +1464,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ return (rc); /* we had errors so get out */ } @@ -1256,7 +1482,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (uic2sr, UIC_ETH2); return (rc); /* we had errors so get out */ } @@ -1274,7 +1500,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (uic2sr, UIC_ETH3); return (rc); /* we had errors so get out */ } @@ -1292,7 +1518,9 @@ int enetInt (struct eth_device *dev) /* check for EOB on valid channels */ if (my_uic0msr & UIC_MRE) { mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ + if ((mal_rx_eob & + (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) + != 0) { /* call emac routine for channel x */ /* clear EOB mtdcr(malrxeobisr, mal_rx_eob); */ enet_rcv (dev, emac_isr); @@ -1303,7 +1531,7 @@ int enetInt (struct eth_device *dev) } mtdcr (UIC0SR, UIC_MRE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ switch (hw_p->devnum) { case 0: mtdcr (UICSR_ETHX, UIC_ETH0); @@ -1468,7 +1696,7 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) int loop_count = 0; rx_eob_isr = mfdcr (malrxeobisr); - if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { + if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { /* clear EOB */ mtdcr (malrxeobisr, rx_eob_isr); @@ -1482,7 +1710,7 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) loop_count++; handled++; - data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ + data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ if (data_len) { if (data_len > ENET_MAX_MTU) /* Check len */ data_len = 0; @@ -1568,7 +1796,7 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) msr = mfmsr (); mtmsr (msr & ~(MSR_EE)); - length = hw_p->rx[user_index].data_len; + length = hw_p->rx[user_index].data_len & 0x0fff; /* Pass the packet up to the protocol layers. */ /* NetReceive(NetRxPackets[rxIdx], length - 4); */ @@ -1718,6 +1946,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) /* set the MAL IER ??? names may change with new spec ??? */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) mal_ier = MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index a5b9690bec..941d4dc788 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -531,7 +531,8 @@ int pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -549,7 +550,8 @@ int pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_POM0LAL, 0x10000000 ); out32r( PCIX0_POM0LAH, 0x0000000c ); #else @@ -586,7 +588,8 @@ void pci_init_board(void) int busno; busno = pci_440_init (&ppc440_hose); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) pcie_setup_hoses(busno + 1); #endif } diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 3af9862bff..f9a1988d41 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 - 2007 + * (C) Copyright 2006 - 2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Copyright (c) 2005 Cisco Systems. All rights reserved. @@ -31,7 +31,8 @@ #include <common.h> #include <pci.h> -#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \ +#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ defined(CONFIG_PCI) #include <asm/4xx_pcie.h> @@ -306,9 +307,8 @@ static int check_error(void) int err = 0; /* SDR0_PEGPLLLCT1 reset */ - if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); - } valPE0 = SDR_READ(PESDR0_RCSSET); valPE1 = SDR_READ(PESDR1_RCSSET); @@ -400,7 +400,108 @@ int ppc4xx_init_pcie(void) } return 0; } -#else +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +static void ppc4xx_setup_utl(u32 port) +{ + volatile void *utl_base = NULL; + + /* + * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE) + + 0x1000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + break; + } + utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */ + out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */ + out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */ + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */ +} + +/* + * TODO: double check PCI express SDR based on the latest user manual + * Some registers specified here no longer exist.. has to be + * updated based on the final EAS spec. + */ +static int check_error(void) +{ + u32 valPE0, valPE1; + int err = 0; + + valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0)); + valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1)); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + return err; +} + +/* + * Initialize PCI Express core as described in User Manual + * TODO: double check PE SDR PLL Register with the updated user manual. + */ +int ppc4xx_init_pcie(void) +{ + if (check_error()) + return -1; + + return 0; +} +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_405EX) static void ppc4xx_setup_utl(u32 port) { u32 utl_base; @@ -450,7 +551,7 @@ int ppc4xx_init_pcie(void) */ return 0; } -#endif +#endif /* CONFIG_405EX */ /* * Board-specific pcie initialization @@ -511,6 +612,82 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) } #endif /* CONFIG_440SPE */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val = 1 << 24; + u32 utlset1; + + if (rootport) { + val = PTYPE_ROOT_PORT << 20; + utlset1 = 0x21222222; + } else { + val = PTYPE_LEGACY_ENDPOINT << 20; + utlset1 = 0x20222222; + } + + if (port == 0) { + val |= LNKW_X1 << 12; + } else { + val |= LNKW_X4 << 12; + utlset1 |= 0x00101101; + } + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000); + + switch (port) { + case 0: + SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR0_L0DRV, 0x00000136); + SDR_WRITE(PESDR0_L0CLK, 0x00000006); + + SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); + break; + + case 1: + SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L0DRV, 0x00000136); + SDR_WRITE(PESDR1_L1DRV, 0x00000136); + SDR_WRITE(PESDR1_L2DRV, 0x00000136); + SDR_WRITE(PESDR1_L3DRV, 0x00000136); + SDR_WRITE(PESDR1_L0CLK, 0x00000006); + SDR_WRITE(PESDR1_L1CLK, 0x00000006); + SDR_WRITE(PESDR1_L2CLK, 0x00000006); + SDR_WRITE(PESDR1_L3CLK, 0x00000006); + + SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) | + (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); + + /* Poll for PHY reset */ + switch (port) { + case 0: + while (!(SDR_READ(PESDR0_RSTSTA) & 0x1)) + udelay(10); + break; + case 1: + while (!(SDR_READ(PESDR1_RSTSTA) & 0x1)) + udelay(10); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), + (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | + PESDRx_RCSSET_RSTPYN); + + return 0; +} +#endif /* CONFIG_440SPE */ + #if defined(CONFIG_405EX) int __ppc4xx_init_pcie_port_hw(int port, int rootport) { @@ -564,12 +741,12 @@ __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); * range (hangs the core upon config transaction attempts when set * otherwise) while revA uses c_nnnn_nnnn. * - * For revA: + * For 440SPe revA: * PCIE0: 0xc_4000_0000 * PCIE1: 0xc_8000_0000 * PCIE2: 0xc_c000_0000 * - * For revB: + * For 440SPe revB: * PCIE0: 0xd_0000_0000 * PCIE1: 0xd_2000_0000 * PCIE2: 0xd_4000_0000 @@ -577,6 +754,10 @@ __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); * For 405EX: * PCIE0: 0xa000_0000 * PCIE1: 0xc000_0000 + * + * For 460EX/GT: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 */ static inline u64 ppc4xx_get_cfgaddr(int port) { @@ -609,6 +790,12 @@ static inline u64 ppc4xx_get_cfgaddr(int port) } } #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + if (port == 0) + return 0x0000000d00000000ULL; + else + return 0x0000000d20000000ULL; +#endif } /* diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 3d1124e0b2..ffbc222e7a 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -64,16 +64,22 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000300) +#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000400) #else -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000200) +#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000300) #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000600) +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000500) +#define UART3_BASE (CFG_PERIPHERAL_BASE + 0x00000600) #endif #if defined(CONFIG_440GP) @@ -94,11 +100,13 @@ DECLARE_GLOBAL_DATA_PTR; #define UART1_SDR sdr_uart1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) + defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART2_SDR sdr_uart2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) + defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART3_SDR sdr_uart3 #endif #define MFREG(a, d) mfsdr(a, d) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 9e9c685afe..54cc256797 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -54,7 +54,8 @@ static int pci_async_enabled(void) #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -86,7 +87,8 @@ static int pci_arbiter_enabled(void) return (val & 0x80000000); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; mfsdr(sdr_pci0, val); @@ -167,6 +169,21 @@ static char *bootstrap_str[] = { static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "EBC (16 bits)", + "PCI", + "PCI", + "EBC (16 bits)", + "NAND (8 bits)", + "I2C (Addr 0x54)", /* A8 */ + "I2C (Addr 0x52)", /* A4 */ +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; +#endif + #if defined(CONFIG_405EZ) #define SDR0_PINSTP_SHIFT 28 static char *bootstrap_str[] = { @@ -257,8 +274,12 @@ int checkcpu (void) puts("05"); #endif #if defined(CONFIG_440) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + puts("60"); +#else puts("40"); #endif +#endif switch (pvr) { case PVR_405GP_RB: @@ -448,6 +469,26 @@ int checkcpu (void) strcpy(addstr, "No RAID 6 support"); break; + case PVR_460EX_RA: + puts("EX Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); + break; + + case PVR_460EX_SE_RA: + puts("EX Rev. A"); + strcpy(addstr, "Security/Kasumi support"); + break; + + case PVR_460GT_RA: + puts("GT Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); + break; + + case PVR_460GT_SE_RA: + puts("GT Rev. A"); + strcpy(addstr, "Security/Kasumi support"); + break; + default: printf (" UNKNOWN (PVR=%08x)", pvr); break; diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 2e0dd6f062..5d15e2f2a0 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -302,5 +302,6 @@ int cpu_init_r (void) } #endif /* defined(CONFIG_405GP) */ #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ + return (0); } diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 2f3dc326b4..698bcb57d7 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -38,7 +38,22 @@ DECLARE_GLOBAL_DATA_PTR; -/****************************************************************************/ +/* + * Define the number of UIC's + */ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define UIC_MAX 4 +#elif defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) +#define UIC_MAX 3 +#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UIC_MAX 2 +#else +#define UIC_MAX 1 +#endif /* * CPM interrupt vector functions. @@ -49,28 +64,15 @@ struct irq_action { int count; }; -static struct irq_action irq_vecs[32]; -void uic0_interrupt( void * parms); /* UIC0 handler */ +static struct irq_action irq_vecs[UIC_MAX * 32]; -#if defined(CONFIG_440) || defined(CONFIG_405EX) -static struct irq_action irq_vecs1[32]; /* For UIC1 */ +u32 get_dcr(u16); +void set_dcr(u16, u32); -void uic1_interrupt( void * parms); /* UIC1 handler */ - -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -static struct irq_action irq_vecs2[32]; /* For UIC2 */ -void uic2_interrupt( void * parms); /* UIC2 handler */ -#endif /* CONFIG_440GX CONFIG_440SPE */ - -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -static struct irq_action irq_vecs3[32]; /* For UIC3 */ -void uic3_interrupt( void * parms); /* UIC3 handler */ -#endif /* CONFIG_440SPE */ - -#endif /* CONFIG_440 */ +#if (UIC_MAX > 1) && !defined(CONFIG_440GX) +static void uic_cascade_interrupt(void *para); +#endif -/****************************************************************************/ #if defined(CONFIG_440) /* SPRN changed in 440 */ @@ -99,8 +101,6 @@ static __inline__ void set_evpr(unsigned long val) } #endif /* defined(CONFIG_440 */ -/****************************************************************************/ - int interrupt_init_cpu (unsigned *decrementer_count) { int vec; @@ -112,26 +112,10 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Mark all irqs as free */ - for (vec=0; vec<32; vec++) { + for (vec = 0; vec < (UIC_MAX * 32); vec++) { irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; irq_vecs[vec].count = 0; -#if defined(CONFIG_440) || defined(CONFIG_405EX) - irq_vecs1[vec].handler = NULL; - irq_vecs1[vec].arg = NULL; - irq_vecs1[vec].count = 0; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - irq_vecs2[vec].handler = NULL; - irq_vecs2[vec].arg = NULL; - irq_vecs2[vec].count = 0; -#endif /* CONFIG_440GX */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - irq_vecs3[vec].handler = NULL; - irq_vecs3[vec].arg = NULL; - irq_vecs3[vec].count = 0; -#endif /* CONFIG_440SPE */ -#endif } #ifdef CONFIG_4xx @@ -172,15 +156,21 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); -#if defined(CONFIG_440) || defined(CONFIG_405EX) #if !defined(CONFIG_440GX) +#if (UIC_MAX > 1) /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); - irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0); + irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0); #endif +#if (UIC_MAX > 2) + irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0); #endif - -#if defined(CONFIG_440GX) +#if (UIC_MAX > 3) + irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0); +#endif +#else /* !defined(CONFIG_440GX) */ /* Take the GX out of compatibility mode * Travis Sawyer, 9 Mar 2004 * NOTE: 440gx user manual inconsistency here @@ -196,110 +186,24 @@ int interrupt_init_cpu (unsigned *decrementer_count) mtdcr(uicb0er, 0x54000000); /* None are critical */ mtdcr(uicb0cr, 0); -#endif +#endif /* !defined(CONFIG_440GX) */ return (0); } -/****************************************************************************/ - -/* - * Handle external interrupts - */ -#if defined(CONFIG_440GX) -void external_interrupt(struct pt_regs *regs) +/* Handler for UIC interrupt */ +static void uic_interrupt(u32 uic_base, int vec_base) { - ulong uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - /* 440 GX uses base uic register */ - uic_msr = mfdcr(uicb0msr); - - if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) ) - uic0_interrupt(0); - - if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) - uic1_interrupt(0); - - if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) - uic2_interrupt(0); - - mtdcr(uicb0sr, uic_msr); - - return; - -} /* external_interrupt CONFIG_440GX */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -void external_interrupt(struct pt_regs *regs) -{ - ulong uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - /* 440 SPe uses base uic register */ - uic_msr = mfdcr(uic0msr); - - if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) - uic1_interrupt(0); - - if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) - uic2_interrupt(0); - - if (uic_msr & ~(UICB0_ALL)) - uic0_interrupt(0); - - mtdcr(uic0sr, uic_msr); - - return; - -} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */ - -#elif defined(CONFIG_440SPE) -void external_interrupt(struct pt_regs *regs) -{ - ulong uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - /* 440 SPe uses base uic register */ - uic_msr = mfdcr(uic0msr); - - if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) - uic1_interrupt(0); - - if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) - uic2_interrupt(0); - - if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) ) - uic3_interrupt(0); - - if (uic_msr & ~(UICB0_ALL)) - uic0_interrupt(0); - - mtdcr(uic0sr, uic_msr); - - return; -} /* external_interrupt CONFIG_440SPE */ - -#else - -void external_interrupt(struct pt_regs *regs) -{ - ulong uic_msr; - ulong msr_shift; + u32 uic_msr; + u32 msr_shift; int vec; /* * Read masked interrupt status register to determine interrupt source */ - uic_msr = mfdcr(uicmsr); + uic_msr = get_dcr(uic_base + UIC_MSR); msr_shift = uic_msr; - vec = 0; + vec = vec_base; while (msr_shift != 0) { if (msr_shift & 0x80000000) { @@ -312,14 +216,17 @@ void external_interrupt(struct pt_regs *regs) /* call isr */ (*irq_vecs[vec].handler)(irq_vecs[vec].arg); } else { - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector 0x%x\n", vec); + set_dcr(uic_base + UIC_ER, + get_dcr(uic_base + UIC_ER) & + ~(0x80000000 >> vec)); + printf("Masking bogus interrupt vector %d" + " (UIC_BASE=0x%x)\n", vec, uic_base); } /* * After servicing the interrupt, we have to remove the status indicator. */ - mtdcr(uicsr, (0x80000000 >> vec)); + set_dcr(uic_base + UIC_SR, (0x80000000 >> vec)); } /* @@ -329,324 +236,150 @@ void external_interrupt(struct pt_regs *regs) vec++; } } -#endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* Handler for UIC0 interrupt */ -void uic0_interrupt( void * parms) +#if (UIC_MAX > 1) && !defined(CONFIG_440GX) +static void uic_cascade_interrupt(void *para) { - ulong uic_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = mfdcr(uicmsr); - msr_shift = uic_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs[vec].count++; - - if (irq_vecs[vec].handler != NULL) { - /* call isr */ - (*irq_vecs[vec].handler)(irq_vecs[vec].arg); - } else { - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uicsr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + external_interrupt(para); } +#endif -#endif /* CONFIG_440GX */ - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -/* Handler for UIC1 interrupt */ -void uic1_interrupt( void * parms) -{ - ulong uic1_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic1_msr = mfdcr(uic1msr); - msr_shift = uic1_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs1[vec].count++; - - if (irq_vecs1[vec].handler != NULL) { - /* call isr */ - (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg); - } else { - mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uic1sr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} -#endif /* defined(CONFIG_440) */ +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) +/* 440GX uses base uic register */ +#define UIC_BMSR uicb0msr +#define UIC_BSR uicb0sr +#else +#define UIC_BMSR uic0msr +#define UIC_BSR uic0sr +#endif +#else /* CONFIG_440 */ +#define UIC_BMSR uicmsr +#define UIC_BSR uicsr +#endif /* CONFIG_440 */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* Handler for UIC2 interrupt */ -void uic2_interrupt( void * parms) +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) { - ulong uic2_msr; - ulong msr_shift; - int vec; + u32 uic_msr; /* * Read masked interrupt status register to determine interrupt source */ - uic2_msr = mfdcr(uic2msr); - msr_shift = uic2_msr; - vec = 0; + uic_msr = mfdcr(UIC_BMSR); - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs2[vec].count++; - - if (irq_vecs2[vec].handler != NULL) { - /* call isr */ - (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); - } else { - mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uic2sr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} -#endif /* defined(CONFIG_440GX) */ - -#if defined(CONFIG_440SPE) -/* Handler for UIC3 interrupt */ -void uic3_interrupt( void * parms) -{ - ulong uic3_msr; - ulong msr_shift; - int vec; +#if (UIC_MAX > 1) + if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr)) + uic_interrupt(UIC1_DCR_BASE, 32); +#endif - /* - * Read masked interrupt status register to determine interrupt source - */ - uic3_msr = mfdcr(uic3msr); - msr_shift = uic3_msr; - vec = 0; +#if (UIC_MAX > 2) + if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr)) + uic_interrupt(UIC2_DCR_BASE, 64); +#endif - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs3[vec].count++; +#if (UIC_MAX > 3) + if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr)) + uic_interrupt(UIC3_DCR_BASE, 96); +#endif - if (irq_vecs3[vec].handler != NULL) { - /* call isr */ - (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg); - } else { - mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec); - } +#if defined(CONFIG_440) +#if !defined(CONFIG_440GX) + if (uic_msr & ~(UICB0_ALL)) + uic_interrupt(UIC0_DCR_BASE, 0); +#else + if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr)) + uic_interrupt(UIC0_DCR_BASE, 0); +#endif +#else /* CONFIG_440 */ + uic_interrupt(UIC0_DCR_BASE, 0); +#endif /* CONFIG_440 */ - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uic3sr, (0x80000000 >> vec)); - } + mtdcr(UIC_BSR, uic_msr); - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + return; } -#endif /* defined(CONFIG_440SPE) */ - -/****************************************************************************/ /* * Install and free a interrupt handler. */ - -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) { - struct irq_action *irqa = irq_vecs; - int i = vec; - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - if ((vec > 31) && (vec < 64)) { - i = vec - 32; - irqa = irq_vecs1; - } else if (vec > 63) { - i = vec - 64; - irqa = irq_vecs2; - } -#else /* CONFIG_440GX */ - if (vec > 31) { - i = vec - 32; - irqa = irq_vecs1; - } -#endif /* CONFIG_440GX */ -#endif /* CONFIG_440 */ + int i; /* - * print warning when replacing with a different irq vector + * Print warning when replacing with a different irq vector */ - if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) { - printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n", - vec, (uint) handler, (uint) irqa[i].handler); + if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) { + printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n", + vec, (uint) handler, (uint) irq_vecs[vec].handler); } - irqa[i].handler = handler; - irqa[i].arg = arg; - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - if ((vec > 31) && (vec < 64)) - mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); - else if (vec > 63) - mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i)); - else -#endif /* CONFIG_440GX */ - if (vec > 31) - mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); - else + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; + + i = vec & 0x1f; + if ((vec >= 0) && (vec < 32)) + mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i)); +#if (UIC_MAX > 1) + else if ((vec >= 32) && (vec < 64)) + mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i)); +#endif +#if (UIC_MAX > 2) + else if ((vec >= 64) && (vec < 96)) + mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i)); #endif - mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i)); -#if 0 - printf ("Install interrupt for vector %d ==> %p\n", vec, handler); +#if (UIC_MAX > 3) + else if (vec >= 96) + mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i)); #endif + + debug("Install interrupt for vector %d ==> %p\n", vec, handler); } void irq_free_handler (int vec) { - struct irq_action *irqa = irq_vecs; - int i = vec; - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - if ((vec > 31) && (vec < 64)) { - irqa = irq_vecs1; - i = vec - 32; - } else if (vec > 63) { - irqa = irq_vecs2; - i = vec - 64; - } -#endif /* CONFIG_440GX */ - if (vec > 31) { - irqa = irq_vecs1; - i = vec - 32; - } -#endif + int i; -#if 0 - printf ("Free interrupt for vector %d ==> %p\n", - vec, irq_vecs[vec].handler); -#endif + debug("Free interrupt for vector %d ==> %p\n", + vec, irq_vecs[vec].handler); -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - if ((vec > 31) && (vec < 64)) - mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); - else if (vec > 63) - mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i)); - else -#endif /* CONFIG_440GX */ - if (vec > 31) - mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); - else + i = vec & 0x1f; + if ((vec >= 0) && (vec < 32)) + mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i)); +#if (UIC_MAX > 1) + else if ((vec >= 32) && (vec < 64)) + mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i)); +#endif +#if (UIC_MAX > 2) + else if ((vec >= 64) && (vec < 96)) + mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i)); +#endif +#if (UIC_MAX > 3) + else if (vec >= 96) + mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i)); #endif - mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i)); - irqa[i].handler = NULL; - irqa[i].arg = NULL; + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; } -/****************************************************************************/ - void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ return; } -/****************************************************************************/ - #if defined(CONFIG_CMD_IRQ) - -/******************************************************************************* - * - * irqinfo - print information about PCI devices - * - */ -int -do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int vec; - printf ("\nInterrupt-Information:\n"); -#if defined(CONFIG_440) || defined(CONFIG_405EX) - printf ("\nUIC 0\n"); -#endif + printf ("Interrupt-Information:\n"); printf ("Nr Routine Arg Count\n"); - for (vec=0; vec<32; vec++) { + for (vec = 0; vec < (UIC_MAX * 32); vec++) { if (irq_vecs[vec].handler != NULL) { printf ("%02d %08lx %08lx %d\n", vec, @@ -656,46 +389,6 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } -#if defined(CONFIG_440) || defined(CONFIG_405EX) - printf ("\nUIC 1\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs1[vec].handler != NULL) - printf ("%02d %08lx %08lx %d\n", - vec+31, (ulong)irq_vecs1[vec].handler, - (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count); - } - printf("\n"); -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - printf ("\nUIC 2\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs2[vec].handler != NULL) - printf ("%02d %08lx %08lx %d\n", - vec+63, (ulong)irq_vecs2[vec].handler, - (ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count); - } - printf("\n"); -#endif - -#if defined(CONFIG_440SPE) - printf ("\nUIC 3\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs3[vec].handler != NULL) - printf ("%02d %08lx %08lx %d\n", - vec+63, (ulong)irq_vecs3[vec].handler, - (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count); - } - printf("\n"); -#endif - return 0; } #endif diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 3978773f9f..c8827201e9 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -29,6 +29,11 @@ | +-----------------------------------------------------------------------------*/ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + #include <common.h> #include <asm/processor.h> #include <asm/io.h> @@ -38,7 +43,10 @@ #include <405_mal.h> #include <miiphy.h> -#undef ET_DEBUG +#if !defined(CONFIG_PHY_CLK_FREQ) +#define CONFIG_PHY_CLK_FREQ 0 +#endif + /***********************************************************/ /* Dump out to the screen PHY regs */ /***********************************************************/ @@ -164,9 +172,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) /***********************************************************/ /* read a phy reg and return the value with a rc */ /***********************************************************/ +/* AMCC_TODO: + * Find out of the choice for the emac for MDIO is from the bridges, + * i.e. ZMII or RGMII as approporiate. If the bridges are not used + * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL] + * used? If so, then this routine below does not apply to the 460EX/GT. + * + * sr: Currently on 460EX only EMAC0 works with MDIO, so we always + * return EMAC0 offset here + */ unsigned int miiphy_getemac_offset (void) { -#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI) +#if (defined(CONFIG_440) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \ + defined(CONFIG_NET_MULTI) unsigned long zmii; unsigned long eoffset; @@ -217,153 +237,97 @@ unsigned int miiphy_getemac_offset (void) #endif } -int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) +static int emac_miiphy_wait(u32 emac_reg) { - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; - unsigned long emac_reg; + u32 sta_reg; + int i; - emac_reg = miiphy_getemac_offset (); - /* see if it is ready for 1000 nsec */ + /* wait for completion */ i = 0; - - /* see if it is ready for sec */ - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == - EMAC_STACR_OC_MASK) { - udelay (7); - if (i > 5) { -#ifdef ET_DEBUG - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); - printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ - printf ("read err 1\n"); -#endif + do { + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); + if (i++ > 5) { + debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__, + __LINE__, sta_reg); return -1; } - i++; - } + udelay(10); + } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK); + + return 0; +} + +static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) +{ + u32 emac_reg; + u32 sta_reg; + + emac_reg = miiphy_getemac_offset(); + + /* wait for completion */ + if (emac_miiphy_wait(emac_reg) != 0) + return -1; + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd; #else - sta_reg |= EMAC_STACR_READ; + sta_reg |= cmd; #endif #else - sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; + sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ - !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ - !defined(CONFIG_405EX) + /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; -#endif - sta_reg = sta_reg | (addr << 5); /* Phy address */ + sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ + if (cmd == EMAC_STACR_WRITE) + memcpy(&sta_reg, &value, 2); /* put in data */ + out_be32((void *)EMAC_STACR + emac_reg, sta_reg); -#ifdef ET_DEBUG - printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif + debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); -#ifdef ET_DEBUG - printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif - i = 0; - while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { - udelay (7); - if (i > 5) - return -1; + /* wait for completion */ + if (emac_miiphy_wait(emac_reg) != 0) + return -1; - i++; - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); -#ifdef ET_DEBUG - printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif - } + debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); if ((sta_reg & EMAC_STACR_PHYE) != 0) return -1; - *value = *(short *)(&sta_reg); return 0; +} -} /* phy_read */ - -/***********************************************************/ -/* write a phy reg and return the value with a rc */ -/***********************************************************/ - -int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, - unsigned short value) +int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) { - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; + unsigned long sta_reg; unsigned long emac_reg; emac_reg = miiphy_getemac_offset (); - /* see if it is ready for 1000 nsec */ - i = 0; - - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == - EMAC_STACR_OC_MASK) { - if (i > 5) - return -1; - - udelay (7); - i++; - } - sta_reg = 0; - sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; -#else - sta_reg |= EMAC_STACR_WRITE; -#endif -#else - sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; -#endif - -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ - !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ - !defined(CONFIG_405EX) - sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ -#endif - sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */ - sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ - memcpy (&sta_reg, &value, 2); /* put in data */ - out_be32((void *)EMAC_STACR + emac_reg, sta_reg); + if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) + return -1; - /* wait for completion */ - i = 0; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); -#ifdef ET_DEBUG - printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif - while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { - udelay (7); - if (i > 5) - return -1; - - i++; - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); -#ifdef ET_DEBUG - printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif - } - - if ((sta_reg & EMAC_STACR_PHYE) != 0) - return -1; + *value = *(u16 *)(&sta_reg); return 0; +} -} /* phy_write */ +/***********************************************************/ +/* write a phy reg and return the value with a rc */ +/***********************************************************/ + +int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); +} diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 9e2229daf9..5b2ae88d93 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -34,7 +34,8 @@ #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EZ) || defined(CONFIG_405EX)) + defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) #include <nand.h> #include <linux/mtd/ndfc.h> diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 90066142de..fa799529d3 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2007 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -35,6 +35,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + #if defined(CONFIG_405GP) || defined(CONFIG_405CR) void get_sys_info (PPC4xx_SYS_INFO * sysInfo) @@ -201,7 +203,126 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +static u8 pll_fwdv_multi_bits[] = { + /* values for: 1 - 16 */ + 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, + 0x05, 0x08, 0x07, 0x02, 0x0b, 0x06 +}; + +u32 get_cpr0_fwdv(unsigned long cpr_reg_fwdv) +{ + u32 index; + + for (index = 0; index < ARRAY_SIZE(pll_fwdv_multi_bits); index++) + if (cpr_reg_fwdv == (u32)pll_fwdv_multi_bits[index]) + return index + 1; + + return 0; +} + +static u8 pll_fbdv_multi_bits[] = { + /* values for: 1 - 100 */ + 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4, + 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb, + 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96, + 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde, + 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb, + 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91, + 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b, + 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95, + 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4, + 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc, + /* values for: 101 - 200 */ + 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3, + 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90, + 0x20, 0xc0, 0x01, 0x83, 0x77, 0xff, 0x1f, 0xbf, 0x7f, 0xfe, + 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6, + 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd, + 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1, + 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6, + 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9, + 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e, + 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf, + /* values for: 201 - 255 */ + 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae, + 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2, + 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2, + 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98, + 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81, + 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */ +}; + +u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) +{ + u32 index; + + for (index = 0; index < ARRAY_SIZE(pll_fbdv_multi_bits); index++) + if (cpr_reg_fbdv == (u32)pll_fbdv_multi_bits[index]) + return index + 1; + + return 0; +} + +/* + * AMCC_TODO: verify this routine against latest EAS, cause stuff changed + * with latest EAS + */ +void get_sys_info (sys_info_t * sysInfo) +{ + unsigned long strp0; + unsigned long strp1; + unsigned long temp; + unsigned long m; + unsigned long plbedv0; + + /* Extract configured divisors */ + mfsdr(sdr_sdstp0, strp0); + mfsdr(sdr_sdstp1, strp1); + + temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK); + sysInfo->pllFwdDivB = get_cpr0_fwdv(temp); + + temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8; + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26; + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */ + temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24; + sysInfo->pllExtBusDiv = temp ? temp : 4; + + temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29; + plbedv0 = temp ? temp: 8; + + /* Calculate 'M' based on feedback source */ + temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; + if (temp == 0) { + /* PLL internal feedback */ + m = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + m = sysInfo->pllFwdDivA * plbedv0 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; + sysInfo->freqPLB = sysInfo->freqVCOMhz / sysInfo->pllFwdDivA / plbedv0; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqPLB; + sysInfo->freqUART = sysInfo->freqPLB; + + return; +} + +#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) void get_sys_info (sys_info_t *sysInfo) { diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index d8df67b0da..8d2777dcd9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -403,7 +403,8 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ 2: #if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) /* * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) */ @@ -415,6 +416,11 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ mfdcr r1,isram0_pmeg and r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x4000 /* BAS = 8000_0000 */ + ori r1,r1,0x4580 /* 16k */ + mtdcr isram0_sb0cr,r1 +#endif #endif #if defined(CONFIG_440EP) /* @@ -672,7 +678,9 @@ _start: /* 440EP & 440GR are only 440er PPC's without internal SRAM */ #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) /* not all PPC's have internal SRAM usable as L2-cache */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif @@ -711,6 +719,10 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr isram0_sb3cr,r1 +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x4000 /* BAS = 8000_0000 */ + ori r1,r1,0x4580 /* 16k */ + mtdcr isram0_sb0cr,r1 #elif defined(CONFIG_440GP) ori r1,r1,0x0380 /* 8k rw */ mtdcr isram0_sb0cr,r1 @@ -1370,7 +1382,8 @@ relocate_code: #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index ed493f1a71..2bfcba19bd 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -31,9 +31,9 @@ #include <asm/mmu.h> typedef struct region { - unsigned long base; - unsigned long size; - unsigned long tlb_word2_i_value; + u64 base; + u32 size; + u32 tlb_word2_i_value; } region_t; void remove_tlb(u32 vaddr, u32 size) @@ -182,10 +182,10 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) asm("isync"); } -static int add_tlb_entry(unsigned long phys_addr, - unsigned long virt_addr, - unsigned long tlb_word0_size_value, - unsigned long tlb_word2_i_value) +static int add_tlb_entry(u64 phys_addr, + u32 virt_addr, + u32 tlb_word0_size_value, + u32 tlb_word2_i_value) { int i; unsigned long tlb_word0_value; @@ -204,7 +204,8 @@ static int add_tlb_entry(unsigned long phys_addr, /* Second, create the TLB entry */ tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE | TLB_WORD0_TS_0 | tlb_word0_size_value; - tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0); + tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) | + TLB_WORD1_ERPN_ENCODE(phys_addr >> 32); tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | TLB_WORD2_W_DISABLE | tlb_word2_i_value | @@ -228,10 +229,10 @@ static int add_tlb_entry(unsigned long phys_addr, return 0; } -static void program_tlb_addr(unsigned long phys_addr, - unsigned long virt_addr, - unsigned long mem_size, - unsigned long tlb_word2_i_value) +static void program_tlb_addr(u64 phys_addr, + u32 virt_addr, + u32 mem_size, + u32 tlb_word2_i_value) { int rc; int tlb_i; @@ -331,7 +332,7 @@ static void program_tlb_addr(unsigned long phys_addr, * Common usage for boards with SDRAM DIMM modules to dynamically * configure the TLB's for the SDRAM */ -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value) +void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value) { region_t region_array; diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index 5d50b3cea0..eae6adbc0b 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -155,7 +155,7 @@ int dcache_status (void) #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) #endif -void rtc_get (struct rtc_time* tm) +int rtc_get (struct rtc_time* tm) { RTCCON |= 1; tm->tm_year = BCD2HEX(BCDYEAR); @@ -184,6 +184,8 @@ void rtc_get (struct rtc_time* tm) tm->tm_year += 1900; else tm->tm_year += 2000; + + return 0; } void rtc_set (struct rtc_time* tm) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 439c950cf2..f04c72d05a 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1180,6 +1180,27 @@ void flash_print_info (flash_info_t * info) } /*----------------------------------------------------------------------- + * This is used in a few places in write_buf() to show programming + * progress. Making it a function is nasty because it needs to do side + * effect updates to digit and dots. Repeated code is nasty too, so + * we define it once here. + */ +#ifdef CONFIG_FLASH_SHOW_PROGRESS +#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ + dots -= dots_sub; \ + if ((scale > 0) && (dots <= 0)) { \ + if ((digit % 5) == 0) \ + printf ("%d", digit / 5); \ + else \ + putc ('.'); \ + digit--; \ + dots += scale; \ + } +#else +#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) +#endif + +/*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK * 1 - write timeout @@ -1192,10 +1213,23 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int aln; cfiword_t cword; int i, rc; - #ifdef CFG_FLASH_USE_BUFFER_WRITE int buffered_size; #endif +#ifdef CONFIG_FLASH_SHOW_PROGRESS + int digit = CONFIG_FLASH_SHOW_PROGRESS; + int scale = 0; + int dots = 0; + + /* + * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. + */ + if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { + scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / + CONFIG_FLASH_SHOW_PROGRESS); + } +#endif + /* get lower aligned address */ wp = (addr & ~(info->portwidth - 1)); @@ -1219,6 +1253,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return rc; wp += i; + FLASH_SHOW_PROGRESS(scale, dots, digit, i); } /* handle the aligned part */ @@ -1248,6 +1283,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) wp += i; src += i; cnt -= i; + FLASH_SHOW_PROGRESS(scale, dots, digit, i); } #else while (cnt >= info->portwidth) { @@ -1259,8 +1295,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return rc; wp += info->portwidth; cnt -= info->portwidth; + FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); } #endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { return (0); } diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d4003a20f2..3b828fb627 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1180,6 +1180,12 @@ static int onenand_probe(struct mtd_info *mtd) if (maf_id != bram_maf_id || dev_id != bram_dev_id) return -ENXIO; + /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */ + if (dev_id & (1 << 9)) { + printk("Not yet support Flex-OneNAND\n"); + return -ENXIO; + } + /* Flash device information */ onenand_print_device_info(dev_id, 0); this->device_id = dev_id; diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b9723fa78f..320dc3ebac 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a COBJS-y += 3c589.o COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-y += cs8900.o COBJS-y += dc2114x.o COBJS-y += dm9000x.o @@ -40,7 +41,7 @@ COBJS-y += lan91c96.o COBJS-y += macb.o COBJS-y += mcffec.o COBJS-y += natsemi.o -COBJS-y += ne2000.o +COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o COBJS-y += netarm_eth.o COBJS-y += netconsole.o COBJS-y += ns7520_eth.o @@ -57,6 +58,7 @@ COBJS-y += tigon3.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o COBJS-y += uli526x.o +COBJS-y += vsc7385.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h new file mode 100644 index 0000000000..069ae80fa8 --- /dev/null +++ b/drivers/net/ax88796.h @@ -0,0 +1,217 @@ +/* + * AX88796L(NE2000) support + * + * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __DRIVERS_AX88796L_H__ +#define __DRIVERS_AX88796L_H__ + +#define DP_DATA (0x10 << 1) +#define START_PG 0x40 /* First page of TX buffer */ +#define START_PG2 0x48 +#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define TX_PAGES 12 +#define RX_START (START_PG+TX_PAGES) +#define RX_END STOP_PG + +#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE +#define AX88796L_BYTE_ACCESS 0x00001000 +#define AX88796L_OFFSET 0x00000400 +#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ + AX88796L_BYTE_ACCESS + AX88796L_OFFSET +#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) +#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) + +#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) +#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) + +#define EECS_HIGH (AX88796L_MEMR |= 0x10) +#define EECS_LOW (AX88796L_MEMR &= 0xef) +#define EECLK_HIGH (AX88796L_MEMR |= 0x80) +#define EECLK_LOW (AX88796L_MEMR &= 0x7f) +#define EEDI_HIGH (AX88796L_MEMR |= 0x20) +#define EEDI_LOW (AX88796L_MEMR &= 0xdf) +#define EEDO ((AX88796L_MEMR & 0x40)>>6) + +#define PAGE0_SET (AX88796L_CR &= 0x3f) +#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) + +#define BIT_DUMMY 0 +#define MAC_EEP_READ 1 +#define MAC_EEP_WRITE 2 +#define MAC_EEP_ERACE 3 +#define MAC_EEP_EWEN 4 +#define MAC_EEP_EWDS 5 + +/* R7780MP Specific code */ +#if defined(CONFIG_R7780MP) +#define ISA_OFFSET 0x1400 +#define DP_IN(_b_, _o_, _d_) (_d_) = \ + *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) \ + *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#else +/* Please change for your target boards */ +#define ISA_OFFSET 0x0000 +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#endif + + +/* + * Set 1 bit data + */ +static void ax88796_bitset(u32 bit) +{ + /* DATA1 */ + if( bit ) + EEDI_HIGH; + else + EEDI_LOW; + + EECLK_LOW; + udelay(1000); + EECLK_HIGH; + udelay(1000); + EEDI_LOW; +} + +/* + * Get 1 bit data + */ +static u8 ax88796_bitget(void) +{ + u8 bit; + + EECLK_LOW; + udelay(1000); + /* DATA */ + bit = EEDO; + EECLK_HIGH; + udelay(1000); + + return bit; +} + +/* + * Send COMMAND to EEPROM + */ +static void ax88796_eep_cmd(u8 cmd) +{ + ax88796_bitset(BIT_DUMMY); + switch(cmd){ + case MAC_EEP_READ: + ax88796_bitset(1); + ax88796_bitset(1); + ax88796_bitset(0); + break; + + case MAC_EEP_WRITE: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(1); + break; + + case MAC_EEP_ERACE: + ax88796_bitset(1); + ax88796_bitset(1); + ax88796_bitset(1); + break; + + case MAC_EEP_EWEN: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(0); + break; + + case MAC_EEP_EWDS: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(0); + break; + default: + break; + } +} + +static void ax88796_eep_setaddr(u16 addr) +{ + int i ; + for( i = 7 ; i >= 0 ; i-- ) + ax88796_bitset(addr & (1 << i)); +} + +/* + * Get data from EEPROM + */ +static u16 ax88796_eep_getdata(void) +{ + ushort data = 0; + int i; + + ax88796_bitget(); /* DUMMY */ + for( i = 0 ; i < 16 ; i++ ){ + data <<= 1; + data |= ax88796_bitget(); + } + return data; +} + +static void ax88796_mac_read(u8 *buff) +{ + int i ; + u16 data, addr = 0; + + for( i = 0 ; i < 3; i++ ) + { + EECS_HIGH; + EEDI_LOW; + udelay(1000); + /* READ COMMAND */ + ax88796_eep_cmd(MAC_EEP_READ); + /* ADDRESS */ + ax88796_eep_setaddr(addr++); + /* GET DATA */ + data = ax88796_eep_getdata(); + *buff++ = (uchar)(data & 0xff); + *buff++ = (uchar)((data >> 8) & 0xff); + EECLK_LOW; + EEDI_LOW; + EECS_LOW; + } +} + +int get_prom(u8* mac_addr) +{ + u8 prom[32]; + int i; + + ax88796_mac_read(prom); + for (i = 0; i < 6; i++){ + mac_addr[i] = prom[i]; + } + return 1; +} + +#endif /* __DRIVERS_AX88796L_H__ */ diff --git a/board/bf537-stamp/ether_bf537.c b/drivers/net/bfin_mac.c index 6c514c6609..afe122a337 100644 --- a/board/bf537-stamp/ether_bf537.c +++ b/drivers/net/bfin_mac.c @@ -1,39 +1,24 @@ /* - * ADI Blackfin 537 MAC Ethernet + * Driver for Blackfin On-Chip MAC device * - * Copyright (c) 2005 Analog Device, Inc. + * Copyright (c) 2005-2008 Analog Device, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Licensed under the GPL-2 or later. */ #include <common.h> #include <config.h> -#include <asm/blackfin.h> #include <net.h> #include <command.h> #include <malloc.h> -#include "ether_bf537.h" +#include <asm/blackfin.h> #include <asm/mach-common/bits/dma.h> #include <asm/mach-common/bits/emac.h> #include <asm/mach-common/bits/pll.h> +#include "bfin_mac.h" + #ifdef CONFIG_POST #include <post.h> #endif @@ -41,66 +26,50 @@ #undef DEBUG_ETHERNET #ifdef DEBUG_ETHERNET -#define DEBUGF(fmt,args...) printf(fmt,##args) +#define DEBUGF(fmt, args...) printf(fmt, ##args) #else -#define DEBUGF(fmt,args...) +#define DEBUGF(fmt, args...) #endif -#if defined(CONFIG_CMD_NET) - #define RXBUF_BASE_ADDR 0xFF900000 #define TXBUF_BASE_ADDR 0xFF800000 #define TX_BUF_CNT 1 -#define TOUT_LOOP 1000000 +#define TOUT_LOOP 1000000 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; static u16 txIdx; /* index of the current RX buffer */ static u16 rxIdx; /* index of the current TX buffer */ -u8 SrcAddr[6]; u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */ /* DMAx_CONFIG values at DMA Restart */ -const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 }; - -#if 0 - rxdmacfg.b_DMA_EN = 1; /* enabled */ - rxdmacfg.b_WNR = 1; /* write to memory */ - rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */ - rxdmacfg.b_DMA2D = 0; /* N/A */ - rxdmacfg.b_RESTART= 0; /* N/A */ - rxdmacfg.b_DI_SEL = 0; /* N/A */ - rxdmacfg.b_DI_EN = 0; /* no interrupt */ - rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */ - rxdmacfg.b_FLOW = 7; /* large desc flow */ -#endif - -const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 }; - -#if 0 - txdmacfg.b_DMA_EN = 1; /* enabled */ - txdmacfg.b_WNR = 0; /* read from memory */ - txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */ - txdmacfg.b_DMA2D = 0; /* N/A */ - txdmacfg.b_RESTART= 0; /* N/A */ - txdmacfg.b_DI_SEL = 0; /* N/A */ - txdmacfg.b_DI_EN = 0; /* no interrupt */ - txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */ - txdmacfg.b_FLOW = 7; /* large desc flow */ -#endif - -ADI_ETHER_BUFFER *SetupRxBuffer(int no); -ADI_ETHER_BUFFER *SetupTxBuffer(int no); - -static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd); -static void bfin_EMAC_halt(struct eth_device *dev); -static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, - int length); -static int bfin_EMAC_recv(struct eth_device *dev); - -int bfin_EMAC_initialize(bd_t * bis) +const ADI_DMA_CONFIG_REG rxdmacfg = { + .b_DMA_EN = 1, /* enabled */ + .b_WNR = 1, /* write to memory */ + .b_WDSIZE = 2, /* wordsize is 32 bits */ + .b_DMA2D = 0, + .b_RESTART = 0, + .b_DI_SEL = 0, + .b_DI_EN = 0, /* no interrupt */ + .b_NDSIZE = 5, /* 5 half words is desc size */ + .b_FLOW = 7 /* large desc flow */ +}; + +const ADI_DMA_CONFIG_REG txdmacfg = { + .b_DMA_EN = 1, /* enabled */ + .b_WNR = 0, /* read from memory */ + .b_WDSIZE = 2, /* wordsize is 32 bits */ + .b_DMA2D = 0, + .b_RESTART = 0, + .b_DI_SEL = 0, + .b_DI_EN = 0, /* no interrupt */ + .b_NDSIZE = 5, /* 5 half words is desc size */ + .b_FLOW = 7 /* large desc flow */ +}; + +int bfin_EMAC_initialize(bd_t *bis) { struct eth_device *dev; dev = (struct eth_device *)malloc(sizeof(*dev)); @@ -108,7 +77,7 @@ int bfin_EMAC_initialize(bd_t * bis) hang(); memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "BF537 ETHERNET"); + sprintf(dev->name, "Blackfin EMAC"); dev->iobase = 0; dev->priv = 0; @@ -165,7 +134,7 @@ static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, txIdx = 0; else txIdx++; - out: + out: DEBUGF("BFIN EMAC send: length = %d\n", length); return result; } @@ -212,7 +181,7 @@ static int bfin_EMAC_recv(struct eth_device *dev) * *************************************************************/ -static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd) +static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) { u32 opmode; int dat; @@ -227,7 +196,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd) return -1; /* Initialize EMAC address */ - SetupMacAddr(SrcAddr); + bfin_EMAC_setup_addr(bd); /* Initialize TX and RX buffer */ for (i = 0; i < PKTBUFSRX; i++) { @@ -289,37 +258,25 @@ static void bfin_EMAC_halt(struct eth_device *dev) } -void SetupMacAddr(u8 * MACaddr) +void bfin_EMAC_setup_addr(bd_t *bd) { - char *tmp, *end; - int i; - /* this depends on a little-endian machine */ - tmp = getenv("ethaddr"); - if (tmp) { - for (i = 0; i < 6; i++) { - MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - -#ifndef CONFIG_NETCONSOLE - printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", - MACaddr[0], MACaddr[1], - MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]); -#endif - *pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 | - MACaddr[2] << 16 | MACaddr[3] << 24; - *pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8; - } + *pEMAC_ADDRLO = + bd->bi_enetaddr[0] | + bd->bi_enetaddr[1] << 8 | + bd->bi_enetaddr[2] << 16 | + bd->bi_enetaddr[3] << 24; + *pEMAC_ADDRHI = + bd->bi_enetaddr[4] | + bd->bi_enetaddr[5] << 8; } -void PollMdcDone(void) +static void PollMdcDone(void) { /* poll the STABUSY bit */ while (*pEMAC_STAADD & STABUSY) ; } -void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data) +static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data) { PollMdcDone(); @@ -332,7 +289,7 @@ void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data) /********************************************************************************* * Read an off-chip register in a PHY through the MDC/MDIO port * *********************************************************************************/ -u16 RdPHYReg(u16 PHYAddr, u16 RegAddr) +static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr) { u16 Data; @@ -350,7 +307,8 @@ u16 RdPHYReg(u16 PHYAddr, u16 RegAddr) return Data; } -void SoftResetPHY(void) +#if 0 /* dead code ? */ +static void SoftResetPHY(void) { u16 phydat; /* set the reset bit */ @@ -362,13 +320,30 @@ void SoftResetPHY(void) phydat = RdPHYReg(PHYADDR, PHY_MODECTL); } while ((phydat & PHY_RESET) != 0); } +#endif -int SetupSystemRegs(int *opmode) +static int SetupSystemRegs(int *opmode) { u16 sysctl, phydat; int count = 0; /* Enable PHY output */ *pVR_CTL |= CLKBUFOE; + /* Set all the pins to peripheral mode */ + +#ifndef CONFIG_BFIN_MAC_RMII + *pPORTH_FER = 0xFFFF; +#ifdef __ADSPBF52x__ + *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2; +#endif +#else +#if defined(__ADSPBF536__) || defined(__ADSPBF537__) + *pPORTH_FER = 0xC373; +#endif +#ifdef __ADSPBF52x__ + *pPORTH_FER = 0x01FF; + *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2; +#endif +#endif /* MDC = 2.5 MHz */ sysctl = SET_MDCDIV(24); /* Odd word alignment for Receive Frame DMA word */ @@ -546,4 +521,3 @@ int ether_post_test(int flags) return 0; } #endif -#endif diff --git a/board/bf537-stamp/ether_bf537.h b/drivers/net/bfin_mac.h index 22fc392ddc..c8a94d0c9f 100644 --- a/board/bf537-stamp/ether_bf537.h +++ b/drivers/net/bfin_mac.h @@ -1,3 +1,14 @@ +/* + * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC. + * + * Copyright (c) 2005-2008 Analog Device, Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MAC_H__ +#define __BFIN_MAC_H__ + #define PHYADDR 0x01 #define NO_PHY_REGS 0x20 @@ -60,12 +71,19 @@ typedef struct adi_ether_buffer { } ADI_ETHER_BUFFER; /* 40 bytes/struct in 44 bytes */ -void SetupMacAddr(u8 * MACaddr); +static ADI_ETHER_BUFFER *SetupRxBuffer(int no); +static ADI_ETHER_BUFFER *SetupTxBuffer(int no); + +static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd); +static void bfin_EMAC_halt(struct eth_device *dev); +static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length); +static int bfin_EMAC_recv(struct eth_device *dev); + +static void PollMdcDone(void); +static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data); +static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr); +static int SetupSystemRegs(int *opmode); -void PollMdcDone(void); -void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data); -u16 RdPHYReg(u16 PHYAddr, u16 RegAddr); -void SoftResetPHY(void); -void DumpPHYRegs(void); +static void bfin_EMAC_setup_addr(bd_t *bd); -int SetupSystemRegs(int *opmode); +#endif diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index b100657539..99baeea3e8 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -5,7 +5,6 @@ Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world are GPL, so this is, of course, GPL. - ========================================================================== dev/if_dp83902a.c @@ -70,9 +69,7 @@ Add SNMP ####DESCRIPTIONEND#### - ========================================================================== - */ #include <common.h> @@ -80,27 +77,11 @@ Add SNMP #include <net.h> #include <malloc.h> -#ifdef CONFIG_DRIVER_NE2000 - -/* wor around udelay resetting OCR */ -static void my_udelay(long us) { - long tmo; - - tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */ - while (get_timer (0) < tmo); -} - -#define mdelay(n) my_udelay((n)*1000) - +#define mdelay(n) udelay((n)*1000) /* forward definition of function used for the uboot interface */ void uboot_push_packet_len(int len); void uboot_push_tx_done(int key, int val); -/* timeout for tx/rx in s */ -#define TOUT 5 - -#define ETHER_ADDR_LEN 6 - /* ------------------------------------------------------------------------ Debugging details @@ -118,17 +99,22 @@ void uboot_push_tx_done(int key, int val); #if DEBUG & 1 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) #define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) +#define PRINTK(args...) printf(args) #else #define DEBUG_FUNCTION() do {} while(0) #define DEBUG_LINE() do {} while(0) +#define PRINTK(args...) #endif -#include "ne2000.h" +/* NE2000 base header file */ +#include "ne2000_base.h" -#if DEBUG & 1 -#define PRINTK(args...) printf(args) +#if defined(CONFIG_DRIVER_AX88796L) +/* AX88796L support */ +#include "ax88796.h" #else -#define PRINTK(args...) +/* Basic NE2000 chip support */ +#include "ne2000.h" #endif static dp83902a_priv_data_t nic; /* just one instance of the card supported */ @@ -137,8 +123,7 @@ static bool dp83902a_init(void) { dp83902a_priv_data_t *dp = &nic; - cyg_uint8* base; - int i; + u8* base; DEBUG_FUNCTION(); @@ -147,6 +132,8 @@ dp83902a_init(void) DEBUG_LINE(); +#if defined(NE2000_BASIC_INIT) + /* AX88796L doesn't need */ /* Prepare ESA */ DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ /* Use the address from the serial EEPROM */ @@ -163,6 +150,7 @@ dp83902a_init(void) dp->esa[4], dp->esa[5] ); +#endif /* NE2000_BASIC_INIT */ return true; } @@ -170,7 +158,7 @@ static void dp83902a_stop(void) { dp83902a_priv_data_t *dp = &nic; - cyg_uint8 *base = dp->base; + u8 *base = dp->base; DEBUG_FUNCTION(); @@ -188,10 +176,10 @@ dp83902a_stop(void) the hardware ready to send/receive packets. */ static void -dp83902a_start(unsigned char * enaddr) +dp83902a_start(u8 * enaddr) { dp83902a_priv_data_t *dp = &nic; - cyg_uint8 *base = dp->base; + u8 *base = dp->base; int i; DEBUG_FUNCTION(); @@ -206,15 +194,21 @@ dp83902a_start(unsigned char * enaddr) dp->tx1 = dp->tx2 = 0; dp->tx_next = dp->tx_buf1; dp->tx_started = false; + dp->running = true; DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */ DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ dp->rx_next = dp->rx_buf_start-1; + dp->running = true; DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + dp->running = true; for (i = 0; i < ETHER_ADDR_LEN; i++) { + /* FIXME */ + /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + + * 0x1400)) = enaddr[i];*/ DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); } /* Enable and start device */ @@ -234,7 +228,7 @@ static void dp83902a_start_xmit(int start_page, int len) { dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; - cyg_uint8 *base = dp->base; + u8 *base = dp->base; DEBUG_FUNCTION(); @@ -259,10 +253,10 @@ dp83902a_start_xmit(int start_page, int len) that there is free buffer space (dp->tx_next). */ static void -dp83902a_send(unsigned char *data, int total_len, unsigned long key) +dp83902a_send(u8 *data, int total_len, u32 key) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; + u8 *base = dp->base; int len, start_page, pkt_len, i, isr; #if DEBUG & 4 int dx; @@ -296,7 +290,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key) /* but the code is extended a bit to do what Hitachi's monitor */ /* does (i.e., also read data). */ - cyg_uint16 tmp; + u16 tmp; int len = 1; DP_OUT(base, DP_RSAL, 0x100-len); @@ -322,7 +316,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key) /* Put data into buffer */ #if DEBUG & 4 - printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len); + printf(" sg buf %08lx len %08x\n ", (u32)data, len); dx = 0; #endif while (len > 0) { @@ -330,6 +324,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key) printf(" %02x", *data); if (0 == (++dx % 16)) printf("\n "); #endif + DP_OUT_DATA(dp->data, *data++); len--; } @@ -358,6 +353,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key) do { DP_IN(base, DP_ISR, isr); } while ((isr & DP_ISR_RDC) == 0); + /* Then disable DMA */ DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); @@ -383,9 +379,9 @@ static void dp83902a_RxEvent(void) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; - unsigned char rsr; - unsigned char rcv_hdr[4]; + u8 *base = dp->base; + u8 rsr; + u8 rcv_hdr[4]; int i, len, pkt, cur; DEBUG_FUNCTION(); @@ -423,6 +419,7 @@ dp83902a_RxEvent(void) CYGACC_CALL_IF_DELAY_US(10); #endif + /* read header (get data size)*/ for (i = 0; i < sizeof(rcv_hdr);) { DP_IN_DATA(dp->data, rcv_hdr[i++]); } @@ -432,7 +429,10 @@ dp83902a_RxEvent(void) rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); #endif len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); + + /* data read */ uboot_push_packet_len(len); + if (rcv_hdr[1] == dp->rx_buf_start) DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); else @@ -448,12 +448,12 @@ dp83902a_RxEvent(void) efficient processing in the upper layers of the stack. */ static void -dp83902a_recv(unsigned char *data, int len) +dp83902a_recv(u8 *data, int len) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; + u8 *base = dp->base; int i, mlen; - cyg_uint8 saved_char = 0; + u8 saved_char = 0; bool saved; #if DEBUG & 4 int dx; @@ -482,7 +482,7 @@ dp83902a_recv(unsigned char *data, int len) if (data) { mlen = len; #if DEBUG & 4 - printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen); + printf(" sg buf %08lx len %08x \n", (u32) data, mlen); dx = 0; #endif while (0 < mlen) { @@ -495,7 +495,7 @@ dp83902a_recv(unsigned char *data, int len) } { - cyg_uint8 tmp; + u8 tmp; DP_IN_DATA(dp->data, tmp); #if DEBUG & 4 printf(" %02x", tmp); @@ -516,9 +516,9 @@ static void dp83902a_TxEvent(void) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; - unsigned char tsr; - unsigned long key; + u8 *base = dp->base; + u8 tsr; + u32 key; DEBUG_FUNCTION(); @@ -551,8 +551,8 @@ static void dp83902a_ClearCounters(void) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; - cyg_uint8 cnt1, cnt2, cnt3; + u8 *base = dp->base; + u8 cnt1, cnt2, cnt3; DP_IN(base, DP_FER, cnt1); DP_IN(base, DP_CER, cnt2); @@ -566,8 +566,8 @@ static void dp83902a_Overflow(void) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; - cyg_uint8 *base = dp->base; - cyg_uint8 isr; + u8 *base = dp->base; + u8 isr; /* Issue a stop command and wait 1.6ms for it to complete. */ DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); @@ -603,8 +603,8 @@ static void dp83902a_poll(void) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - cyg_uint8 *base = dp->base; - unsigned char isr; + u8 *base = dp->base; + u8 isr; DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); DP_IN(base, DP_ISR, isr); @@ -642,13 +642,13 @@ dp83902a_poll(void) /* find prom (taken from pc_net_cs.c from Linux) */ #include "8390.h" - +/* typedef struct hw_info_t { u_int offset; u_char a0, a1, a2; u_int flags; } hw_info_t; - +*/ #define DELAY_OUTPUT 0x01 #define HAS_MISC_REG 0x02 #define USE_BIG_BUF 0x04 @@ -731,102 +731,17 @@ static hw_info_t hw_info[] = { static hw_info_t default_info = { 0, 0, 0, 0, 0 }; -unsigned char dev_addr[6]; +u8 dev_addr[6]; #define PCNET_CMD 0x00 #define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ #define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ -unsigned long nic_base; - -static void pcnet_reset_8390(void) -{ - int i, r; - - PRINTK("nic base is %lx\n", nic_base); - - n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); - n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); - n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); - n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - - n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); - - for (i = 0; i < 100; i++) { - if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) - break; - PRINTK("got %x in reset\n", r); - my_udelay(100); - } - n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */ - - if (i == 100) - printf("pcnet_reset_8390() did not complete.\n"); -} /* pcnet_reset_8390 */ - -static hw_info_t * get_prom(void ) { - unsigned char prom[32]; - int i, j; - struct { - u_char value, offset; - } program_seq[] = { - {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ - {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ - {0x00, EN0_RCNTLO}, /* Clear the count regs. */ - {0x00, EN0_RCNTHI}, - {0x00, EN0_IMR}, /* Mask completion irq. */ - {0xFF, EN0_ISR}, - {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ - {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ - {32, EN0_RCNTLO}, - {0x00, EN0_RCNTHI}, - {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ - {0x00, EN0_RSARHI}, - {E8390_RREAD+E8390_START, E8390_CMD}, - }; - - PRINTK("trying to get MAC via prom reading\n"); - - pcnet_reset_8390(); - - mdelay(10); - - for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++) - n2k_outb(program_seq[i].value, program_seq[i].offset); - - PRINTK("PROM:"); - for (i = 0; i < 32; i++) { - prom[i] = n2k_inb(PCNET_DATAPORT); - PRINTK(" %02x", prom[i]); - } - PRINTK("\n"); - for (i = 0; i < NR_INFO; i++) { - if ((prom[0] == hw_info[i].a0) && - (prom[2] == hw_info[i].a1) && - (prom[4] == hw_info[i].a2)) { - PRINTK("matched board %d\n", i); - break; - } - } - if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { - for (j = 0; j < 6; j++) - dev_addr[j] = prom[j<<1]; - PRINTK("on exit i is %d/%ld\n", i, NR_INFO); - PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", - dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]); - return (i < NR_INFO) ? hw_info+i : &default_info; - } - return NULL; -} +u32 nic_base; /* U-boot specific routines */ - - -static unsigned char *pbuf = NULL; +static u8 *pbuf = NULL; static int pkey = -1; static int initialized=0; @@ -839,7 +754,7 @@ void uboot_push_packet_len(int len) { } dp83902a_recv(&pbuf[0], len); - /* Just pass it to the upper layer */ + /*Just pass it to the upper layer*/ NetReceive(&pbuf[0], len); } @@ -864,7 +779,7 @@ int eth_init(bd_t *bd) { #ifdef CONFIG_DRIVER_NE2000_CCR { - volatile unsigned char *p = (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR; + vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; PRINTK("CCR before is %x\n", *p); *p = CONFIG_DRIVER_NE2000_VAL; @@ -873,9 +788,9 @@ int eth_init(bd_t *bd) { #endif nic_base = CONFIG_DRIVER_NE2000_BASE; - nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE; + nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; - r = get_prom(); + r = get_prom(dev_addr); if (!r) return -1; @@ -886,22 +801,23 @@ int eth_init(bd_t *bd) { PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); setenv ("ethaddr", ethaddr); - -#define DP_DATA 0x10 nic.data = nic.base + DP_DATA; - nic.tx_buf1 = 0x40; - nic.tx_buf2 = 0x48; - nic.rx_buf_start = 0x50; - nic.rx_buf_end = 0x80; + nic.tx_buf1 = START_PG; + nic.tx_buf2 = START_PG2; + nic.rx_buf_start = RX_START; + nic.rx_buf_end = RX_END; if (dp83902a_init() == false) return -1; + dp83902a_start(dev_addr); initialized=1; + return 0; } void eth_halt() { + PRINTK("### eth_halt\n"); if(initialized) dp83902a_stop(); @@ -920,7 +836,7 @@ int eth_send(volatile void *packet, int length) { pkey = -1; - dp83902a_send((unsigned char *) packet, length, 666); + dp83902a_send((u8 *) packet, length, 666); tmo = get_timer (0) + TOUT * CFG_HZ; while(1) { dp83902a_poll(); @@ -936,4 +852,3 @@ int eth_send(volatile void *packet, int length) { } return 0; } -#endif diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h index c13d9f0bbb..d324a00084 100644 --- a/drivers/net/ne2000.h +++ b/drivers/net/ne2000.h @@ -5,7 +5,6 @@ Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world are GPL, so this is, of course, GPL. - ========================================================================== dev/dp83902a.h @@ -67,213 +66,114 @@ are GPL, so this is, of course, GPL. ####DESCRIPTIONEND#### ========================================================================== - */ /* - ------------------------------------------------------------------------ - Macros for accessing DP registers - These can be overridden by the platform header -*/ - -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_))) -#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_) - -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_))) -#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_) - - -/* here is all the data */ - -#define cyg_uint8 unsigned char -#define cyg_uint16 unsigned short -#define bool int - -#define false 0 -#define true 1 - -#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 -#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X) - -typedef struct dp83902a_priv_data { - cyg_uint8* base; - cyg_uint8* data; - cyg_uint8* reset; - int tx_next; /* First free Tx page */ - int tx_int; /* Expecting interrupt from this buffer */ - int rx_next; /* First free Rx page */ - int tx1, tx2; /* Page numbers for Tx buffers */ - unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */ - int tx1_len, tx2_len; - bool tx_started, running, hardwired_esa; - cyg_uint8 esa[6]; - void* plf_priv; - - /* Buffer allocation */ - int tx_buf1, tx_buf2; - int rx_buf_start, rx_buf_end; -} dp83902a_priv_data_t; - -/* - ------------------------------------------------------------------------ - Some forward declarations -*/ -static void dp83902a_poll(void); - -/* ------------------------------------------------------------------------ */ -/* Register offsets */ - -#define DP_CR 0x00 -#define DP_CLDA0 0x01 -#define DP_PSTART 0x01 /* write */ -#define DP_CLDA1 0x02 -#define DP_PSTOP 0x02 /* write */ -#define DP_BNDRY 0x03 -#define DP_TSR 0x04 -#define DP_TPSR 0x04 /* write */ -#define DP_NCR 0x05 -#define DP_TBCL 0x05 /* write */ -#define DP_FIFO 0x06 -#define DP_TBCH 0x06 /* write */ -#define DP_ISR 0x07 -#define DP_CRDA0 0x08 -#define DP_RSAL 0x08 /* write */ -#define DP_CRDA1 0x09 -#define DP_RSAH 0x09 /* write */ -#define DP_RBCL 0x0a /* write */ -#define DP_RBCH 0x0b /* write */ -#define DP_RSR 0x0c -#define DP_RCR 0x0c /* write */ -#define DP_FER 0x0d -#define DP_TCR 0x0d /* write */ -#define DP_CER 0x0e -#define DP_DCR 0x0e /* write */ -#define DP_MISSED 0x0f -#define DP_IMR 0x0f /* write */ -#define DP_DATAPORT 0x10 /* "eprom" data port */ - -#define DP_P1_CR 0x00 -#define DP_P1_PAR0 0x01 -#define DP_P1_PAR1 0x02 -#define DP_P1_PAR2 0x03 -#define DP_P1_PAR3 0x04 -#define DP_P1_PAR4 0x05 -#define DP_P1_PAR5 0x06 -#define DP_P1_CURP 0x07 -#define DP_P1_MAR0 0x08 -#define DP_P1_MAR1 0x09 -#define DP_P1_MAR2 0x0a -#define DP_P1_MAR3 0x0b -#define DP_P1_MAR4 0x0c -#define DP_P1_MAR5 0x0d -#define DP_P1_MAR6 0x0e -#define DP_P1_MAR7 0x0f - -#define DP_P2_CR 0x00 -#define DP_P2_PSTART 0x01 -#define DP_P2_CLDA0 0x01 /* write */ -#define DP_P2_PSTOP 0x02 -#define DP_P2_CLDA1 0x02 /* write */ -#define DP_P2_RNPP 0x03 -#define DP_P2_TPSR 0x04 -#define DP_P2_LNPP 0x05 -#define DP_P2_ACH 0x06 -#define DP_P2_ACL 0x07 -#define DP_P2_RCR 0x0c -#define DP_P2_TCR 0x0d -#define DP_P2_DCR 0x0e -#define DP_P2_IMR 0x0f - -/* Command register - common to all pages */ - -#define DP_CR_STOP 0x01 /* Stop: software reset */ -#define DP_CR_START 0x02 /* Start: initialize device */ -#define DP_CR_TXPKT 0x04 /* Transmit packet */ -#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ -#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ -#define DP_CR_SEND 0x18 /* Send packet */ -#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ -#define DP_CR_PAGE0 0x00 /* Page select */ -#define DP_CR_PAGE1 0x40 -#define DP_CR_PAGE2 0x80 -#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ - -/* Data configuration register */ - -#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ -#define DP_DCR_BOS 0x02 /* 1=Little Endian */ -#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ -#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ -#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ -#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ -#define DP_DCR_FIFO_2 0x20 -#define DP_DCR_FIFO_4 0x40 -#define DP_DCR_FIFO_6 0x60 - -#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) - -/* Interrupt status register */ - -#define DP_ISR_RxP 0x01 /* Packet received */ -#define DP_ISR_TxP 0x02 /* Packet transmitted */ -#define DP_ISR_RxE 0x04 /* Receive error */ -#define DP_ISR_TxE 0x08 /* Transmit error */ -#define DP_ISR_OFLW 0x10 /* Receive overflow */ -#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ -#define DP_ISR_RDC 0x40 /* Remote DMA complete */ -#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ - -/* Interrupt mask register */ - -#define DP_IMR_RxP 0x01 /* Packet received */ -#define DP_IMR_TxP 0x02 /* Packet transmitted */ -#define DP_IMR_RxE 0x04 /* Receive error */ -#define DP_IMR_TxE 0x08 /* Transmit error */ -#define DP_IMR_OFLW 0x10 /* Receive overflow */ -#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ -#define DP_IMR_RDC 0x40 /* Remote DMA complete */ - -#define DP_IMR_All 0x3F /* Everything but remote DMA */ - -/* Receiver control register */ - -#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ -#define DP_RCR_AR 0x02 /* Accept runt packets */ -#define DP_RCR_AB 0x04 /* Accept broadcast packets */ -#define DP_RCR_AM 0x08 /* Accept multicast packets */ -#define DP_RCR_PROM 0x10 /* Promiscuous mode */ -#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ - -/* Receiver status register */ - -#define DP_RSR_RxP 0x01 /* Packet received */ -#define DP_RSR_CRC 0x02 /* CRC error */ -#define DP_RSR_FRAME 0x04 /* Framing error */ -#define DP_RSR_FO 0x08 /* FIFO overrun */ -#define DP_RSR_MISS 0x10 /* Missed packet */ -#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ -#define DP_RSR_DIS 0x40 /* Receiver disabled */ -#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ - -/* Transmitter control register */ - -#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ -#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ -#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ -#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ -#define DP_TCR_OUTLOOP 0x08 /* External loopback */ -#define DP_TCR_ATD 0x10 /* Auto transmit disable */ -#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ - -/* Transmit status register */ - -#define DP_TSR_TxP 0x01 /* Packet transmitted */ -#define DP_TSR_COL 0x04 /* Collision (at least one) */ -#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ -#define DP_TSR_CRS 0x10 /* Lost carrier */ -#define DP_TSR_FU 0x20 /* FIFO underrun */ -#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ -#define DP_TSR_OWC 0x80 /* Collision outside normal window */ - -#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ -#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ + * NE2000 support header file. + * Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + */ + +#ifndef __DRIVERS_NE2000_H__ +#define __DRIVERS_NE2000_H__ + +/* Enable NE2000 basic init function */ +#define NE2000_BASIC_INIT + +#define DP_DATA 0x10 +#define START_PG 0x50 /* First page of TX buffer */ +#define STOP_PG 0x80 /* Last page +1 of RX ring */ + +#define RX_START 0x50 +#define RX_END 0x80 + +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) + +static void pcnet_reset_8390(void) +{ + int i, r; + + PRINTK("nic base is %lx\n", nic_base); + + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + + n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); + + for (i = 0; i < 100; i++) { + if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) + break; + PRINTK("got %x in reset\n", r); + udelay(100); + } + n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */ + + if (i == 100) + printf("pcnet_reset_8390() did not complete.\n"); +} /* pcnet_reset_8390 */ + +int get_prom(u8* mac_addr) +{ + u8 prom[32]; + int i, j; + struct { + u_char value, offset; + } program_seq[] = { + {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ + {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ + {0x00, EN0_RCNTLO}, /* Clear the count regs. */ + {0x00, EN0_RCNTHI}, + {0x00, EN0_IMR}, /* Mask completion irq. */ + {0xFF, EN0_ISR}, + {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ + {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ + {32, EN0_RCNTLO}, + {0x00, EN0_RCNTHI}, + {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ + {0x00, EN0_RSARHI}, + {E8390_RREAD+E8390_START, E8390_CMD}, + }; + + PRINTK ("trying to get MAC via prom reading\n"); + + pcnet_reset_8390 (); + + mdelay (10); + + for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++) + n2k_outb (program_seq[i].value, program_seq[i].offset); + + PRINTK ("PROM:"); + for (i = 0; i < 32; i++) { + prom[i] = n2k_inb (PCNET_DATAPORT); + PRINTK (" %02x", prom[i]); + } + PRINTK ("\n"); + for (i = 0; i < NR_INFO; i++) { + if ((prom[0] == hw_info[i].a0) && + (prom[2] == hw_info[i].a1) && + (prom[4] == hw_info[i].a2)) { + PRINTK ("matched board %d\n", i); + break; + } + } + if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { + PRINTK ("on exit i is %d/%ld\n", i, NR_INFO); + PRINTK ("MAC address is "); + for (j = 0; j < 6; j++) { + mac_addr[j] = prom[j << 1]; + PRINTK ("%02x:", mac_addr[i]); + } + PRINTK ("\n"); + return (i < NR_INFO) ? i : 0; + } + return NULL; +} +#endif /* __DRIVERS_NE2000_H__ */ diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h new file mode 100644 index 0000000000..1badf62bf2 --- /dev/null +++ b/drivers/net/ne2000_base.h @@ -0,0 +1,282 @@ +/* +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + + dev/dp83902a.h + + National Semiconductor DP83902a ethernet chip + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### + ------------------------------------------- + This file is part of eCos, the Embedded Configurable Operating System. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + + eCos is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 or (at your option) any later version. + + eCos is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with eCos; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + As a special exception, if other files instantiate templates or use macros + or inline functions from this file, or you compile this file and link it + with other works to produce a work based on this file, this file does not + by itself cause the resulting work to be covered by the GNU General Public + License. However the source code for this file must still be made available + in accordance with section (3) of the GNU General Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + at http://sources.redhat.com/ecos/ecos-license/ + ------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + + ------------------------------------------- + + Portions of this software may have been derived from OpenBSD or other sources, + and are covered by the appropriate copyright disclaimers included herein. + + ------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 + Purpose: + Description: + +####DESCRIPTIONEND#### + +========================================================================== + +*/ + +/* + ------------------------------------------------------------------------ + Macros for accessing DP registers + These can be overridden by the platform header +*/ + +#define bool int + +#define false 0 +#define true 1 + +/* timeout for tx/rx in s */ +#define TOUT 5 +/* Ether MAC address size */ +#define ETHER_ADDR_LEN 6 + + +#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 +#define CYGACC_CALL_IF_DELAY_US(X) udelay(X) + +/* H/W infomation struct */ +typedef struct hw_info_t { + u32 offset; + u8 a0, a1, a2; + u32 flags; +} hw_info_t; + +typedef struct dp83902a_priv_data { + u8* base; + u8* data; + u8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + u32 tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + u8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; +} dp83902a_priv_data_t; + +/* + ------------------------------------------------------------------------ + Some forward declarations +*/ +int get_prom( u8* mac_addr); +static void dp83902a_poll(void); + +/* ------------------------------------------------------------------------ */ +/* Register offsets */ + +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f + +/* Command register - common to all pages */ + +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ + +/* Data configuration register */ + +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 + +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) + +/* Interrupt status register */ + +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ + +/* Interrupt mask register */ + +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ + +#define DP_IMR_All 0x3F /* Everything but remote DMA */ + +/* Receiver control register */ + +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ + +/* Receiver status register */ + +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ + +/* Transmitter control register */ + +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ + +/* Transmit status register */ + +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index d03cbc320b..8dcbb3e2aa 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -186,7 +186,7 @@ typedef unsigned long int dword; #ifdef CONFIG_ADNPESC1 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) #elif CONFIG_BLACKFIN -#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;}) +#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) #else #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) #endif @@ -195,7 +195,7 @@ typedef unsigned long int dword; #ifdef CONFIG_ADNPESC1 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");} +#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();} #else #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) #endif diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e91d9eadc1..431a8d2f23 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -583,10 +583,11 @@ uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) uint speed; mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); - if ((mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) && - !(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { + if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { int i = 0; + /* in case of timeout ->link is cleared */ + priv->link = 1; puts("Waiting for PHY realtime link"); while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { /* Timeout reached ? */ diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c new file mode 100644 index 0000000000..f440ce07e2 --- /dev/null +++ b/drivers/net/vsc7385.c @@ -0,0 +1,101 @@ +/* + * Vitesse 7385 Switch Firmware Upload + * + * Author: Timur Tabi <timur@freescale.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed + * under the terms of the GNU General Public License version 2. This + * program is licensed "as is" without any warranty of any kind, whether + * express or implied. + * + * This module uploads proprietary firmware for the Vitesse VSC7385 5-port + * switch. + */ + +#include <config.h> + +#ifdef CONFIG_VSC7385_ENET + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> + +/* + * Upload a Vitesse VSC7385 firmware image to the hardware + * + * This function takes a pointer to a VSC7385 firmware image and a size, and + * uploads that firmware to the VSC7385. + * + * This firmware is typically located at a board-specific flash address, + * and the size is typically 8KB. + * + * The firmware is Vitesse proprietary. + * + * Further details on the register information can be obtained from Vitesse. + */ +int vsc7385_upload_firmware(void *firmware, unsigned int size) +{ + u8 *fw = firmware; + unsigned int i; + + u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070); +#ifdef DEBUG + u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060); +#endif + + out_be32(gloreset, 3); + udelay(200); + + out_be32(icpu_ctrl, 0x8E); + udelay(20); + + out_be32(icpu_rom_map, 1); + udelay(20); + + /* Write the firmware to I-RAM */ + out_be32(icpu_addr, 0); + udelay(20); + + for (i = 0; i < size; i++) { + out_be32(icpu_data, fw[i]); + udelay(20); + if (ctrlc()) + return -EINTR; + } + + /* Read back and compare */ + out_be32(icpu_addr, 0); + udelay(20); + + for (i = 0; i < size; i++) { + u8 value; + + value = (u8) in_be32(icpu_data); + udelay(20); + if (value != fw[i]) { + debug("VSC7385: Upload mismatch: address 0x%x, " + "read value 0x%x, image value 0x%x\n", + i, value, fw[i]); + + return -EIO; + } + if (ctrlc()) + break; + } + + out_be32(icpu_ctrl, 0x0B); + udelay(20); + +#ifdef DEBUG + printf("VSC7385: Chip ID is %08x\n", in_be32(chipid)); + udelay(20); +#endif + + return 0; +} + +#endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 50ca6b0bad..7944b6684a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -425,6 +425,9 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); dev += PCI_BDF(0,0,1)) { + + /* Bus 0 is not necessarily PCI bridge. */ +#if defined(CONFIG_PCI_SKIP_HOST_BRIDGE) /* Skip our host bridge */ if ( dev == PCI_BDF(hose->first_busno,0,0) ) { #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ @@ -434,10 +437,11 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) if (getenv("pciconfighost") == NULL) { continue; /* Skip our host bridge */ } -#else +#else /* CONFIG_PCI_CONFIG_HOST_BRIDGE */ continue; /* Skip our host bridge */ -#endif +#endif /* CONFIG_PCI_CONFIG_HOST_BRIDGE */ } +#endif /* CONFIG_PCI_SKIP_HOST_BRIDGE */ if (PCI_FUNC(dev) && !found_multi) continue; @@ -473,8 +477,11 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) hose->fixup_irq(hose, dev); #ifdef CONFIG_PCI_SCAN_SHOW +#if defined(CONFIG_PCI_SKIP_HOST_BRIDGE) /* Skip our host bridge */ - if ( dev != PCI_BDF(hose->first_busno,0,0) ) { + if ( dev != PCI_BDF(hose->first_busno,0,0) ) +#endif + { unsigned char int_line; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE, diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 55f37cb55c..d34430c659 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -417,6 +417,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; upsmr |= (UPSMR_RPM | UPSMR_TBIM); break; + case ENET_1000_RGMII_RXID: case ENET_1000_RGMII: maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; upsmr |= UPSMR_RPM; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index c384055ceb..7762de6a8d 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -642,6 +642,7 @@ typedef enum enet_interface { ENET_100_RGMII, ENET_1000_GMII, ENET_1000_RGMII, + ENET_1000_RGMII_RXID, ENET_1000_TBI, ENET_1000_RTBI } enet_interface_e; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index a42701c59b..423ba789e9 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -318,16 +318,26 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return err; if (mii_info->autoneg) { - status = phy_read (mii_info, PHY_ANLPAR); + status = phy_read(mii_info, MII_1000BASETSTATUS); - if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; + if (status & (LPA_1000FULL | LPA_1000HALF)) { + mii_info->speed = SPEED_1000; + if (status & LPA_1000FULL) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } else { + status = phy_read(mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + } mii_info->pause = 0; } /* On non-aneg, we assume what we put in BMCR is the speed, @@ -337,6 +347,37 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; } +static int bcm_init(struct uec_mii_info *mii_info) +{ + struct eth_device *edev = mii_info->dev; + uec_private_t *uec = edev->priv; + + gbit_config_aneg(mii_info); + + if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) { + u16 val; + int cnt = 50; + + /* Wait for aneg to complete. */ + do + val = phy_read(mii_info, PHY_BMSR); + while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); + + /* Set RDX clk delay. */ + phy_write(mii_info, 0x18, 0x7 | (7 << 12)); + + val = phy_read(mii_info, 0x18); + /* Set RDX-RXC skew. */ + val |= (1 << 8); + val |= (7 | (7 << 12)); + /* Write bits 14:0. */ + val |= (1 << 15); + phy_write(mii_info, 0x18, val); + } + + return 0; +} + static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -505,6 +546,15 @@ static struct phy_info phy_info_marvell = { .config_intr = &marvell_config_intr, }; +static struct phy_info phy_info_bcm5481 = { + .phy_id = 0x0143bca0, + .phy_id_mask = 0xffffff0, + .name = "Broadcom 5481", + .features = MII_GBIT_FEATURES, + .read_status = genmii_read_status, + .init = bcm_init, +}; + static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -518,6 +568,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161, &phy_info_dm9161a, &phy_info_marvell, + &phy_info_bcm5481, &phy_info_genmii, NULL }; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940e0d..6f769fb50b 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 +/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200 + /* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af2bf4a51..800ab9934a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -27,8 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)librtc.a -COBJS-y += date.o COBJS-y += bfin_rtc.o +COBJS-y += date.o COBJS-y += ds12887.o COBJS-y += ds1302.o COBJS-y += ds1306.o @@ -39,19 +39,21 @@ COBJS-y += ds1556.o COBJS-y += ds164x.o COBJS-y += ds174x.o COBJS-y += ds3231.o +COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-y += m41t11.o COBJS-y += m41t60.o -COBJS-y += max6900.o +COBJS-$(CONFIG_RTC_M41T62) += m41t62.o COBJS-y += m48t35ax.o +COBJS-y += max6900.o COBJS-y += mc146818.o +COBJS-y += mcfrtc.o COBJS-y += mk48t59.o COBJS-y += mpc5xxx.o COBJS-y += mpc8xx.o COBJS-y += pcf8563.o -COBJS-y += s3c24x0_rtc.o COBJS-y += rs5c372.o COBJS-y += rx8025.o -COBJS-y += mcfrtc.o +COBJS-y += s3c24x0_rtc.o COBJS-y += x1205.o COBJS := $(COBJS-y) diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c index 5755a20bc5..ce4f1711dc 100644 --- a/drivers/rtc/bfin_rtc.c +++ b/drivers/rtc/bfin_rtc.c @@ -85,7 +85,7 @@ void rtc_set(struct rtc_time *tmp) } /* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ -void rtc_get(struct rtc_time *tmp) +int rtc_get(struct rtc_time *tmp) { uint32_t cur_rtc_stat; int time_in_sec; @@ -95,7 +95,7 @@ void rtc_get(struct rtc_time *tmp) if (tmp == NULL) { puts("Error getting the date/time\n"); - return; + return -1; } wait_for_complete(); @@ -112,6 +112,8 @@ void rtc_get(struct rtc_time *tmp) /* Calculate the total number of seconds since epoch */ time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day); to_tm(time_in_sec, tmp); + + return 0; } #endif diff --git a/drivers/rtc/ds12887.c b/drivers/rtc/ds12887.c index 84fecf0194..57a446d305 100644 --- a/drivers/rtc/ds12887.c +++ b/drivers/rtc/ds12887.c @@ -88,7 +88,7 @@ static unsigned char bin2bcd (unsigned int n) /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, mday, wday, mon, year; @@ -150,6 +150,8 @@ else tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/ds1302.c b/drivers/rtc/ds1302.c index 55af1302d5..3a856c840a 100644 --- a/drivers/rtc/ds1302.c +++ b/drivers/rtc/ds1302.c @@ -253,9 +253,10 @@ rtc_reset(void) /* TODO */ } -void +int rtc_get(struct rtc_time *tmp) { + int rel = 0; struct ds1302_st bbclk; if(!ds1302_initted) rtc_init(); @@ -265,6 +266,7 @@ rtc_get(struct rtc_time *tmp) if (bbclk.CH) { printf("ds1302: rtc_get: Clock was halted, clock probably " "corrupt\n"); + rel = -1; } tmp->tm_sec=10*bbclk.sec10+bbclk.sec; @@ -281,6 +283,8 @@ rtc_get(struct rtc_time *tmp) DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); + + return rel; } void diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 89e433dabd..1c8ac7f292 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -91,7 +91,7 @@ static void init_spi (void); /* ------------------------------------------------------------------------- */ /* read clock time from DS1306 and return it in *tmp */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { volatile immap_t *immap = (immap_t *) CFG_IMMR; unsigned char spi_byte; /* Data Byte */ @@ -141,6 +141,8 @@ void rtc_get (struct rtc_time *tmp) debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } /* ------------------------------------------------------------------------- */ @@ -304,7 +306,7 @@ static unsigned char rtc_read (unsigned char reg); static void rtc_write (unsigned char reg, unsigned char val); /* read clock time from DS1306 and return it in *tmp */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { unsigned char sec, min, hour, mday, wday, mon, year; @@ -349,6 +351,8 @@ void rtc_get (struct rtc_time *tmp) debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } /* ------------------------------------------------------------------------- */ diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index c882d7989a..b20f193b41 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -83,8 +83,9 @@ static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar sec, min, hour, mday, wday, mon, year; sec = rtc_read (RTC_SEC_REG_ADDR); @@ -104,6 +105,7 @@ void rtc_get (struct rtc_time *tmp) /* clear the CH flag */ rtc_write (RTC_SEC_REG_ADDR, rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); + rel = -1; } tmp->tm_sec = bcd2bin (sec & 0x7F); @@ -119,6 +121,8 @@ void rtc_get (struct rtc_time *tmp) DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index c636ac5948..50ab44690c 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -84,8 +84,9 @@ static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar sec, min, hour, mday, wday, mon_cent, year, control, status; control = rtc_read (RTC_CTL_REG_ADDR); @@ -107,6 +108,7 @@ void rtc_get (struct rtc_time *tmp) /* clear the OSF flag */ rtc_write (RTC_STAT_REG_ADDR, rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); + rel = -1; } tmp->tm_sec = bcd2bin (sec & 0x7F); @@ -122,6 +124,8 @@ void rtc_get (struct rtc_time *tmp) DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index e773dd9261..f6bb2965a4 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -107,8 +107,8 @@ static void rtc_write_raw (uchar reg, uchar val); /* * Get the current time from the RTC */ -void rtc_get (struct rtc_time *tm){ - +int rtc_get (struct rtc_time *tm){ + int rel = 0; unsigned long time1, time2; unsigned int limit; unsigned char tmp; @@ -138,18 +138,23 @@ void rtc_get (struct rtc_time *tm){ if (time1 != time2) { printf("can't get consistent time from rtc chip\n"); + rel = -1; } DEBUGR ("Get RTC s since 1.1.1970: %d\n", time1); to_tm(time1, tm); /* To Gregorian Date */ - if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) + if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) { printf ("### Warning: RTC oscillator has stopped\n"); + rel = -1; + } DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + + return rel; } /* diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c index 4365cfb981..2c496f510f 100644 --- a/drivers/rtc/ds1556.c +++ b/drivers/rtc/ds1556.c @@ -69,7 +69,7 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get( struct rtc_time *tmp ) +int rtc_get( struct rtc_time *tmp ) { uchar sec, min, hour; uchar mday, wday, mon, year; @@ -118,6 +118,7 @@ void rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + return 0; } void rtc_set( struct rtc_time *tmp ) diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c index bff22b9a05..5943f8711d 100644 --- a/drivers/rtc/ds164x.c +++ b/drivers/rtc/ds164x.c @@ -70,7 +70,7 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get( struct rtc_time *tmp ) +int rtc_get( struct rtc_time *tmp ) { uchar sec, min, hour; uchar mday, wday, mon, year; @@ -115,6 +115,8 @@ void rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + + return 0; } void rtc_set( struct rtc_time *tmp ) diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c index 5f85a68170..81a9cb3d39 100644 --- a/drivers/rtc/ds174x.c +++ b/drivers/rtc/ds174x.c @@ -65,7 +65,7 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get( struct rtc_time *tmp ) +int rtc_get( struct rtc_time *tmp ) { uchar sec, min, hour; uchar mday, wday, mon, year; @@ -142,6 +142,8 @@ void rtc_set( struct rtc_time *tmp ) /* unlock clock registers after read */ rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); + + return 0; } void rtc_reset (void) diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index fe11b869f5..95cb186348 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -86,8 +86,9 @@ static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar sec, min, hour, mday, wday, mon_cent, year, control, status; control = rtc_read (RTC_CTL_REG_ADDR); @@ -109,6 +110,7 @@ void rtc_get (struct rtc_time *tmp) /* clear the OSF flag */ rtc_write (RTC_STAT_REG_ADDR, rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); + rel = -1; } tmp->tm_sec = bcd2bin (sec & 0x7F); @@ -124,6 +126,8 @@ void rtc_get (struct rtc_time *tmp) DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c new file mode 100644 index 0000000000..3d46fd0653 --- /dev/null +++ b/drivers/rtc/isl1208.c @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2008 + * Tor Krill, Excito Elektronik i SkĂĄne , tor@excito.com + * + * Modelled after the ds1337 driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support (no alarms) for Intersil + * ISL1208 Real Time Clock (RTC). + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> + +/*---------------------------------------------------------------------*/ +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/* + * RTC register addresses + */ + +#define RTC_SEC_REG_ADDR 0x0 +#define RTC_MIN_REG_ADDR 0x1 +#define RTC_HR_REG_ADDR 0x2 +#define RTC_DATE_REG_ADDR 0x3 +#define RTC_MON_REG_ADDR 0x4 +#define RTC_YR_REG_ADDR 0x5 +#define RTC_DAY_REG_ADDR 0x6 +#define RTC_STAT_REG_ADDR 0x7 +/* + * RTC control register bits + */ + +/* + * RTC status register bits + */ +#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ +#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ +#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ +#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ +#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ +#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +/* + * Get the current time from the RTC + */ + +int rtc_get (struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, mday, wday, mon, year, status; + + status = rtc_read (RTC_STAT_REG_ADDR); + sec = rtc_read (RTC_SEC_REG_ADDR); + min = rtc_read (RTC_MIN_REG_ADDR); + hour = rtc_read (RTC_HR_REG_ADDR); + wday = rtc_read (RTC_DAY_REG_ADDR); + mday = rtc_read (RTC_DATE_REG_ADDR); + mon = rtc_read (RTC_MON_REG_ADDR); + year = rtc_read (RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x status: %02x\n", + year, mon, mday, wday, hour, min, sec, status); + + if (status & RTC_STAT_BIT_RTCF) { + printf ("### Warning: RTC oscillator has stopped\n"); + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF)); + rel = -1; + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year)+2000; + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* enable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */ + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + + /* disable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC); +} + +void rtc_reset (void) +{ +} + +/* + * Helper functions + */ + +static uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c index 81da33a31e..fce00d9353 100644 --- a/drivers/rtc/m41t11.c +++ b/drivers/rtc/m41t11.c @@ -96,14 +96,16 @@ static unsigned char bin2bcd (unsigned int n) #define M41T11_STORAGE_SZ (64-REG_CNT) -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar data[RTC_REG_CNT]; i2c_read(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); if( data[RTC_SEC_ADDR] & 0x80 ){ printf( "m41t11 RTC Clock stopped!!!\n" ); + rel = -1; } tmp->tm_sec = bcd2bin (data[RTC_SEC_ADDR] & 0x7F); tmp->tm_min = bcd2bin (data[RTC_MIN_ADDR] & 0x7F); @@ -120,6 +122,7 @@ void rtc_get (struct rtc_time *tmp) i2c_read(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); if( !(data[RTC_HOUR_ADDR] & 0x80) ){ printf( "m41t11 RTC: cann't keep track of years without CEB set\n" ); + rel = -1; } if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){ /*century flip store off new year*/ @@ -136,6 +139,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c index 7c80143e68..8a32ea0748 100644 --- a/drivers/rtc/m41t60.c +++ b/drivers/rtc/m41t60.c @@ -170,12 +170,12 @@ static uchar *rtc_validate(void) return data; } -void rtc_get(struct rtc_time *tmp) +int rtc_get(struct rtc_time *tmp) { uchar const *const data = rtc_validate(); if (!data) - return; + return -1; tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F); tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F); @@ -190,6 +190,8 @@ void rtc_get(struct rtc_time *tmp) debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } void rtc_set(struct rtc_time *tmp) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c new file mode 100644 index 0000000000..cf2a9574a9 --- /dev/null +++ b/drivers/rtc/m41t62.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * based on a the Linux rtc-m41t80.c driver which is: + * Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for STMicroelectronics M41T62 + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> +#include <bcd.h> + +#if defined(CONFIG_CMD_DATE) + +#define M41T62_REG_SSEC 0 +#define M41T62_REG_SEC 1 +#define M41T62_REG_MIN 2 +#define M41T62_REG_HOUR 3 +#define M41T62_REG_WDAY 4 +#define M41T62_REG_DAY 5 +#define M41T62_REG_MON 6 +#define M41T62_REG_YEAR 7 +#define M41T62_REG_ALARM_MON 0xa +#define M41T62_REG_ALARM_DAY 0xb +#define M41T62_REG_ALARM_HOUR 0xc +#define M41T62_REG_ALARM_MIN 0xd +#define M41T62_REG_ALARM_SEC 0xe +#define M41T62_REG_FLAGS 0xf + +#define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1) +#define M41T62_ALARM_REG_SIZE \ + (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON) + +#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */ +#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */ +#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ +#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ +#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ +#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ + +#define M41T62_FEATURE_HT (1 << 0) +#define M41T62_FEATURE_BL (1 << 1) + +int rtc_get(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " + "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", + __FUNCTION__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + tm->tm_sec = BCD2BIN(buf[M41T62_REG_SEC] & 0x7f); + tm->tm_min = BCD2BIN(buf[M41T62_REG_MIN] & 0x7f); + tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f); + tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f); + tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; + tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1; + + /* assume 20YY not 19YY, and ignore the Century Bit */ + /* U-Boot needs to add 1900 here */ + tm->tm_year = BCD2BIN(buf[M41T62_REG_YEAR]) + 100 + 1900; + + debug("%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __FUNCTION__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); + + return 0; +} + +void rtc_set(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + + /* Merge time-data and register flags into buf[0..7] */ + buf[M41T62_REG_SSEC] = 0; + buf[M41T62_REG_SEC] = + BIN2BCD(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); + buf[M41T62_REG_MIN] = + BIN2BCD(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); + buf[M41T62_REG_HOUR] = + BIN2BCD(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; + buf[M41T62_REG_WDAY] = + (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07); + buf[M41T62_REG_DAY] = + BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); + buf[M41T62_REG_MON] = + BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f); + /* assume 20YY not 19YY */ + buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); + + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) + printf("I2C write failed in %s()\n", __func__); +} + +void rtc_reset(void) +{ + /* + * Nothing to do + */ +} + +#endif diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c index 0a0ffa8aac..be29279d03 100644 --- a/drivers/rtc/m48t35ax.c +++ b/drivers/rtc/m48t35ax.c @@ -42,7 +42,7 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, cent_day, date, month, year; uchar ccr; /* Clock control register */ @@ -83,6 +83,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index c75a8e04c2..e9979f227d 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -63,7 +63,7 @@ static unsigned char bin2bcd (unsigned int n) /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, mday, wday, mon, cent, year; int retry = 1; @@ -103,6 +103,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index ab377ed73e..70f7017a3f 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -57,7 +57,7 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, mday, wday, mon, year; /* here check if rtc can be accessed */ @@ -101,6 +101,8 @@ void rtc_get (struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index 27386e586a..d235d10f28 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -39,7 +39,7 @@ #define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) #define STARTOFTIME 1970 -void rtc_get(struct rtc_time *tmp) +int rtc_get(struct rtc_time *tmp) { volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); @@ -64,6 +64,8 @@ void rtc_get(struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + + return 0; } void rtc_set(struct rtc_time *tmp) diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c index bacdb5b70b..59813998ed 100644 --- a/drivers/rtc/mk48t59.c +++ b/drivers/rtc/mk48t59.c @@ -135,7 +135,7 @@ void nvram_write(short dest, const void *src, size_t count) /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { uchar save_ctrl_a; uchar sec, min, hour, mday, wday, mon, year; @@ -183,6 +183,8 @@ void rtc_get (struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c index 216386aba0..a6555f5eb6 100644 --- a/drivers/rtc/mpc5xxx.c +++ b/drivers/rtc/mpc5xxx.c @@ -55,7 +55,7 @@ typedef struct rtc5200 { /***************************************************************************** * get time *****************************************************************************/ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800); ulong time, date, time2; @@ -81,6 +81,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } /***************************************************************************** diff --git a/drivers/rtc/mpc8xx.c b/drivers/rtc/mpc8xx.c index 8d10c0e465..057547bc3c 100644 --- a/drivers/rtc/mpc8xx.c +++ b/drivers/rtc/mpc8xx.c @@ -35,7 +35,7 @@ /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { volatile immap_t *immr = (immap_t *)CFG_IMMR; ulong tim; @@ -47,6 +47,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 2d73d5d7ef..c384975f35 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -41,8 +41,9 @@ static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar sec, min, hour, mday, wday, mon_cent, year; sec = rtc_read (0x02); @@ -65,6 +66,7 @@ void rtc_get (struct rtc_time *tmp) if (sec & 0x80) { puts ("### Warning: RTC Low Voltage - date/time not reliable\n"); + rel = -1; } tmp->tm_sec = bcd2bin (sec & 0x7F); @@ -80,6 +82,8 @@ void rtc_get (struct rtc_time *tmp) debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 3d1346eaa7..1c9b752429 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -166,7 +166,7 @@ rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf) /* * Get the current time from the RTC */ -void +int rtc_get (struct rtc_time *tmp) { unsigned char buf[RS5C372_RAM_SIZE]; @@ -176,7 +176,7 @@ rtc_get (struct rtc_time *tmp) rs5c372_enable(); if (!setup_done) - return; + return -1; memset(buf, 0, sizeof(buf)); @@ -184,12 +184,12 @@ rtc_get (struct rtc_time *tmp) ret = rs5c372_readram(buf, RS5C372_RAM_SIZE); if (ret != 0) { printf("%s: failed\n", __FUNCTION__); - return; + return -1; } rs5c372_convert_to_time(tmp, buf); - return; + return 0; } /* diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 9122f12fc0..64eafe5c37 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -96,8 +96,9 @@ static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { + int rel = 0; uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; @@ -118,14 +119,20 @@ void rtc_get (struct rtc_time *tmp) /* dump status */ ctl2 = rtc_read(RTC_CTL2_REG_ADDR); - if (ctl2 & RTC_CTL2_BIT_PON) + if (ctl2 & RTC_CTL2_BIT_PON) { printf("RTC: power-on detected\n"); + rel = -1; + } - if (ctl2 & RTC_CTL2_BIT_VDET) + if (ctl2 & RTC_CTL2_BIT_VDET) { printf("RTC: voltage drop detected\n"); + rel = -1; + } - if (!(ctl2 & RTC_CTL2_BIT_XST)) + if (!(ctl2 & RTC_CTL2_BIT_XST)) { printf("RTC: oscillator stop detected\n"); + rel = -1; + } tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); @@ -140,6 +147,8 @@ void rtc_get (struct rtc_time *tmp) DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; } /* diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 7f8b4fad0d..358aef751c 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -70,7 +70,7 @@ static unsigned char bin2bcd (unsigned int n) /* ------------------------------------------------------------------------- */ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); uchar sec, min, hour, mday, wday, mon, year; @@ -131,6 +131,8 @@ void rtc_get (struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + + return 0; } void rtc_set (struct rtc_time *tmp) diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index 319f0512ca..0e1813917f 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -104,7 +104,7 @@ static void rtc_write(int reg, u8 val) * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch * Epoch is initialized as 2000. Time is set to UTC. */ -void rtc_get(struct rtc_time *tm) +int rtc_get(struct rtc_time *tm) { u8 buf[8]; @@ -130,6 +130,8 @@ void rtc_get(struct rtc_time *tm) __FUNCTION__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); + + return 0; } void rtc_set(struct rtc_time *tm) diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c index fb4726f283..829bbcae3a 100644 --- a/drivers/usb/usb_ohci.c +++ b/drivers/usb/usb_ohci.c @@ -68,7 +68,8 @@ defined(CONFIG_S3C2410) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ - defined(CONFIG_MPC5200) + defined(CONFIG_MPC5200) || \ + defined(CFG_OHCI_USE_NPS) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -415,7 +416,7 @@ static void ohci_dump (ohci_t *controller, int verbose) ep_print_int_eds (controller, "hcca"); dbg ("hcca frame #%04x", controller->hcca->frame_no); ohci_dump_roothub (controller, 1); - +} #endif /* DEBUG */ /*-------------------------------------------------------------------------* diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index bfb057f513..9684cf3b7c 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -36,6 +36,9 @@ #include "videomodes.h" #include <mb862xx.h> +#if defined(CONFIG_POST) +#include <post.h> +#endif /* * Graphic Device */ @@ -354,7 +357,7 @@ void *video_hw_init (void) board_disp_init(); #endif -#if defined(CONFIG_LWMON5) +#if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c index e4189e51dd..cf67967904 100644 --- a/fs/cramfs/uncompress.c +++ b/fs/cramfs/uncompress.c @@ -25,7 +25,7 @@ #include <watchdog.h> #include <zlib.h> -#if defined(CONFIG_CMD_JFFS2) +#if defined(CONFIG_CMD_CRAMFS) static z_stream stream; diff --git a/include/405_mal.h b/include/405_mal.h index 7ea4eb1cc4..1415cbe1bc 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -94,6 +94,7 @@ /* Mal IER */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index 7c79bd153e..2df4fbde61 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -41,7 +41,8 @@ #endif /* CONFIG_I2C_MULTI_BUS */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS) #elif defined(CONFIG_440) || defined(CONFIG_405EX) /* all remaining 440 variants */ diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index c2d52915a8..0410b5ef70 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -60,6 +60,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 681c514ccf..daf64bc008 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -51,6 +51,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index cb0dfc2d93..6debfc7451 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -61,6 +61,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h index 1d309d5b50..68a9ad61ef 100644 --- a/include/asm-i386/global_data.h +++ b/include/asm-i386/global_data.h @@ -54,6 +54,7 @@ typedef struct { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ extern gd_t *global_data; diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index 1e26eb037e..958736ec70 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -68,6 +68,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #if 0 extern gd_t *global_data; diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h index a6e783424e..91243b22c0 100644 --- a/include/asm-microblaze/global_data.h +++ b/include/asm-microblaze/global_data.h @@ -52,6 +52,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h new file mode 100644 index 0000000000..608cfcfbb3 --- /dev/null +++ b/include/asm-mips/asm.h @@ -0,0 +1,409 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * Some useful macros for MIPS assembler code + * + * Some of the routines below contain useless nops that will be optimized + * away by gas in -O mode. These nops are however required to fill delay + * slots in noreorder mode. + */ +#ifndef __ASM_ASM_H +#define __ASM_ASM_H + +#include <asm/sgidefs.h> + +#ifndef CAT +#ifdef __STDC__ +#define __CAT(str1, str2) str1##str2 +#else +#define __CAT(str1, str2) str1/**/str2 +#endif +#define CAT(str1, str2) __CAT(str1, str2) +#endif + +/* + * PIC specific declarations + * Not used for the kernel but here seems to be the right place. + */ +#ifdef __PIC__ +#define CPRESTORE(register) \ + .cprestore register +#define CPADD(register) \ + .cpadd register +#define CPLOAD(register) \ + .cpload register +#else +#define CPRESTORE(register) +#define CPADD(register) +#define CPLOAD(register) +#endif + +/* + * LEAF - declare leaf routine + */ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: .frame sp, 0, ra + +/* + * NESTED - declare nested routine entry point + */ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: .frame sp, framesize, rpc + +/* + * END - mark end of function + */ +#define END(function) \ + .end function; \ + .size function, .-function + +/* + * EXPORT - export definition of symbol + */ +#define EXPORT(symbol) \ + .globl symbol; \ +symbol: + +/* + * FEXPORT - export definition of a function symbol + */ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol, @function; \ +symbol: + +/* + * ABS - export absolute symbol + */ +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value + +#define PANIC(msg) \ + .set push; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ + .set pop; \ + TEXT(msg) + +/* + * Print formatted string + */ +#ifdef CONFIG_PRINTK +#define PRINT(string) \ + .set push; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal printk; \ + .set pop; \ + TEXT(string) +#else +#define PRINT(string) +#endif + +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ + .popsection; + +/* + * Build text tables + */ +#define TTABLE(string) \ + .pushsection .text; \ + .word 1f; \ + .popsection \ + .pushsection .data; \ +1: .asciiz string; \ + .popsection + +/* + * MIPS IV pref instruction. + * Use with .set noreorder only! + * + * MIPS IV implementations are free to treat this as a nop. The R5000 + * is one of them. So we should have an option not to use this instruction. + */ +#ifdef CONFIG_CPU_HAS_PREFETCH + +#define PREF(hint,addr) \ + .set push; \ + .set mips4; \ + pref hint, addr; \ + .set pop + +#define PREFX(hint,addr) \ + .set push; \ + .set mips4; \ + prefx hint, addr; \ + .set pop + +#else /* !CONFIG_CPU_HAS_PREFETCH */ + +#define PREF(hint, addr) +#define PREFX(hint, addr) + +#endif /* !CONFIG_CPU_HAS_PREFETCH */ + +/* + * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1) +#define MOVN(rd, rs, rt) \ + .set push; \ + .set reorder; \ + beqz rt, 9f; \ + move rd, rs; \ + .set pop; \ +9: +#define MOVZ(rd, rs, rt) \ + .set push; \ + .set reorder; \ + bnez rt, 9f; \ + move rd, rs; \ + .set pop; \ +9: +#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) +#define MOVN(rd, rs, rt) \ + .set push; \ + .set noreorder; \ + bnezl rt, 9f; \ + move rd, rs; \ + .set pop; \ +9: +#define MOVZ(rd, rs, rt) \ + .set push; \ + .set noreorder; \ + beqzl rt, 9f; \ + move rd, rs; \ + .set pop; \ +9: +#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) +#define MOVN(rd, rs, rt) \ + movn rd, rs, rt +#define MOVZ(rd, rs, rt) \ + movz rd, rs, rt +#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ + +/* + * Stack alignment + */ +#if (_MIPS_SIM == _MIPS_SIM_ABI32) +#define ALSZ 7 +#define ALMASK ~7 +#endif +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#define ALSZ 15 +#define ALMASK ~15 +#endif + +/* + * Macros to handle different pointer/register sizes for 32/64-bit code + */ + +/* + * Size of a register + */ +#ifdef __mips64 +#define SZREG 8 +#else +#define SZREG 4 +#endif + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#if (_MIPS_SIM == _MIPS_SIM_ABI32) +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu +#endif +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#define REG_S sd +#define REG_L ld +#define REG_SUBU dsubu +#define REG_ADDU daddu +#endif + +/* + * How to add/sub/load/store/shift C int variables. + */ +#if (_MIPS_SZINT == 32) +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav +#endif + +#if (_MIPS_SZINT == 64) +#define INT_ADD dadd +#define INT_ADDU daddu +#define INT_ADDI daddi +#define INT_ADDIU daddiu +#define INT_SUB dsub +#define INT_SUBU dsubu +#define INT_L ld +#define INT_S sd +#define INT_SLL dsll +#define INT_SLLV dsllv +#define INT_SRL dsrl +#define INT_SRLV dsrlv +#define INT_SRA dsra +#define INT_SRAV dsrav +#endif + +/* + * How to add/sub/load/store/shift C long variables. + */ +#if (_MIPS_SZLONG == 32) +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav + +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 +#endif + +#if (_MIPS_SZLONG == 64) +#define LONG_ADD dadd +#define LONG_ADDU daddu +#define LONG_ADDI daddi +#define LONG_ADDIU daddiu +#define LONG_SUB dsub +#define LONG_SUBU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav + +#define LONG .dword +#define LONGSIZE 8 +#define LONGMASK 7 +#define LONGLOG 3 +#endif + +/* + * How to add/sub/load/store/shift pointers. + */ +#if (_MIPS_SZPTR == 32) +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_LI li +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav + +#define PTR_SCALESHIFT 2 + +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 +#endif + +#if (_MIPS_SZPTR == 64) +#define PTR_ADD dadd +#define PTR_ADDU daddu +#define PTR_ADDI daddi +#define PTR_ADDIU daddiu +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_LA dla +#define PTR_LI dli +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav + +#define PTR_SCALESHIFT 3 + +#define PTR .dword +#define PTRSIZE 8 +#define PTRLOG 3 +#endif + +/* + * Some cp0 registers were extended to 64bit for MIPS III. + */ +#if (_MIPS_SIM == _MIPS_SIM_ABI32) +#define MFC0 mfc0 +#define MTC0 mtc0 +#endif +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#define MFC0 dmfc0 +#define MTC0 dmtc0 +#endif + +#define SSNOP sll zero, zero, 1 + +#ifdef CONFIG_SGI_IP28 +/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ +#include <asm/cacheops.h> +#define R10KCBARRIER(addr) cache Cache_Barrier, addr; +#else +#define R10KCBARRIER(addr) +#endif + +#endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index b9604cf202..b5e685feb6 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -1,18 +1,62 @@ -/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) by Ralf Baechle + * Copyright (C) 1996, 99, 2003 by Ralf Baechle */ -#ifndef _MIPS_BYTEORDER_H -#define _MIPS_BYTEORDER_H +#ifndef _ASM_BYTEORDER_H +#define _ASM_BYTEORDER_H #include <asm/types.h> #ifdef __GNUC__ +#ifdef CONFIG_CPU_MIPSR2 + +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__( + " wsbh %0, %1 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab16(x) ___arch__swab16(x) + +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__( + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab32(x) ___arch__swab32(x) + +#ifdef CONFIG_CPU_MIPS64_R2 + +static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +{ + __asm__( + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " drotr %0, %0, 32 \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +#define __arch__swab64(x) ___arch__swab64(x) + +#endif /* CONFIG_CPU_MIPS64_R2 */ + +#endif /* CONFIG_CPU_MIPSR2 */ + #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ @@ -20,12 +64,12 @@ #endif /* __GNUC__ */ -#if defined (__MIPSEB__) +#if defined(__MIPSEB__) # include <linux/byteorder/big_endian.h> -#elif defined (__MIPSEL__) +#elif defined(__MIPSEL__) # include <linux/byteorder/little_endian.h> #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" #endif -#endif /* _MIPS_BYTEORDER_H */ +#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h index 9cc2b87215..f3ce721861 100644 --- a/include/asm-mips/cachectl.h +++ b/include/asm-mips/cachectl.h @@ -1,10 +1,12 @@ /* - * cachectl.h -- defines for MIPS cache control system calls + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ -#ifndef __ASM_MIPS_CACHECTL -#define __ASM_MIPS_CACHECTL +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL /* * Options for cacheflush system call @@ -21,4 +23,4 @@ #define CACHEABLE 0 /* make pages cacheable */ #define UNCACHEABLE 1 /* make pages uncacheable */ -#endif /* __ASM_MIPS_CACHECTL */ +#endif /* _ASM_CACHECTL */ diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index 66b0b361f0..256ad2cc6e 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -5,43 +5,81 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * (C) Copyright 1996, 1997 by Ralf Baechle + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_MIPS_CACHEOPS_H -#define __ASM_MIPS_CACHEOPS_H +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H /* - * Cache Operations + * Cache Operations available on all MIPS processors with R4000-style caches */ #define Index_Invalidate_I 0x00 #define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 #define Index_Load_Tag_I 0x04 #define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 #define Index_Store_Tag_SI 0x0A #define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d #define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 #define Hit_Invalidate_SI 0x12 #define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 - /* 0x16 is unused */ #define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - /* 0x1a is unused */ #define Hit_Writeback_SD 0x1b - /* 0x1c is unused */ - /* 0x1e is unused */ #define Hit_Set_Virtual_SI 0x1e #define Hit_Set_Virtual_SD 0x1f -#endif /* __ASM_MIPS_CACHEOPS_H */ +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h index a024194ba3..bd9e4dd862 100644 --- a/include/asm-mips/global_data.h +++ b/include/asm-mips/global_data.h @@ -54,6 +54,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h index 3cd1eb8eb5..24c6cda793 100644 --- a/include/asm-mips/isadep.h +++ b/include/asm-mips/isadep.h @@ -1,16 +1,15 @@ /* - * Various ISA level dependant constants. + * Various ISA level dependent constants. * Most of the following constants reflect the different layout * of Coprocessor 0 registers. * * Copyright (c) 1998 Harald Koerfgen */ -#include <linux/config.h> #ifndef __ASM_ISADEP_H #define __ASM_ISADEP_H -#if defined(CONFIG_CPU_R3000) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) /* * R2000 or R3000 */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 6838aee98c..24858ddda5 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -4,9 +4,9 @@ * for more details. * * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H @@ -15,92 +15,26 @@ #include <asm/isadep.h> -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#if !defined (_LANGUAGE_ASSEMBLY) -#if 0 -#include <linux/threads.h> -#endif #include <asm/cachectl.h> #include <asm/mipsregs.h> #include <asm/reg.h> #include <asm/system.h> -struct mips_cpuinfo { - unsigned long udelay_val; - unsigned long *pgd_quick; - unsigned long *pte_quick; - unsigned long pgtable_cache_sz; -}; - -/* - * System setup and hardware flags.. - * XXX: Should go into mips_cpuinfo. - */ -extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ -extern void r3081_wait(void); -extern void r4k_wait(void); -extern char cyclecounter_available; /* only available from R4000 upwards. */ - -extern struct mips_cpuinfo boot_cpu_data; -extern unsigned int vced_count, vcei_count; - -#ifdef CONFIG_SMP -extern struct mips_cpuinfo cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#else -#define cpu_data &boot_cpu_data -#define current_cpu_data boot_cpu_data -#endif - -/* - * Bus types (default is ISA, but people can check others with these..) - * MCA_bus hardcoded to 0 for now. - * - * This needs to be extended since MIPS systems are being delivered with - * numerous different types of bus systems. - */ -extern int EISA_bus; -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - /* - * MIPS has no problems with write protection + * Return current * instruction pointer ("program counter"). */ -#define wp_works_ok 1 -#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) /* - * User space process size: 2GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. TASK_SIZE - * for a 64 bit kernel expandable to 8192EB, of which the current MIPS - * implementations will "only" be able to use 1TB ... - */ -#define TASK_SIZE (0x7fff8000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. + * System setup and hardware flags.. */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) +extern void (*cpu_wait)(void); -/* - * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. - */ -#define IO_BITMAP_SIZE 32 +extern unsigned int vced_count, vcei_count; #define NUM_FPU_REGS 32 -struct mips_fpu_hard_struct { - double fp_regs[NUM_FPU_REGS]; - unsigned int control; -}; +typedef __u64 fpureg_t; /* * It would be nice to add some more fields for emulator statistics, but there @@ -108,25 +42,29 @@ struct mips_fpu_hard_struct { * be recalculated by hand. So the additional information will be private to * the FPU emulator for now. See asm-mips/fpu_emulator.h. */ -typedef u64 fpureg_t; -struct mips_fpu_soft_struct { - fpureg_t regs[NUM_FPU_REGS]; - unsigned int sr; -}; -union mips_fpu_union { - struct mips_fpu_hard_struct hard; - struct mips_fpu_soft_struct soft; +struct mips_fpu_struct { + fpureg_t fpr[NUM_FPU_REGS]; + unsigned int fcr31; }; -#define INIT_FPU { \ - {{0,},} \ -} +#define NUM_DSP_REGS 6 + +typedef __u32 dspreg_t; + +struct mips_dsp_state { + dspreg_t dspr[NUM_DSP_REGS]; + unsigned int dspcontrol; +}; typedef struct { unsigned long seg; } mm_segment_t; +#define ARCH_MIN_TASKALIGN 8 + +struct mips_abi; + /* * If you change thread_struct remember to change the #defines below too! */ @@ -140,131 +78,36 @@ struct thread_struct { unsigned long cp0_status; /* Saved fpu/fpu emulator stuff. */ - union mips_fpu_union fpu; + struct mips_fpu_struct fpu; +#ifdef CONFIG_MIPS_MT_FPAFF + /* Emulated instruction count */ + unsigned long emulated_fp; + /* Saved per-thread scheduler affinity mask */ + cpumask_t user_cpus_allowed; +#endif /* CONFIG_MIPS_MT_FPAFF */ + + /* Saved state of the DSP ASE, if available. */ + struct mips_dsp_state dsp; /* Other stuff associated with the thread. */ unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; -#define MF_FIXADE 1 /* Fix address errors in software */ -#define MF_LOGADE 2 /* Log address errors to syslog */ - unsigned long mflags; - mm_segment_t current_ds; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; - - /* - * These are really only needed if the full FPU emulator is configured. - * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the - * fact that having offset.h rebuilt differently for different config - * options would be asking for trouble. - * - * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) - */ - unsigned long dsemul_epc; - - /* - * Pointer to instruction used to induce address error - */ - unsigned long dsemul_aerpc; + struct mips_abi *abi; }; -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -#define INIT_THREAD { \ - /* \ - * saved main processor registers \ - */ \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, \ - /* \ - * saved cp0 stuff \ - */ \ - 0, \ - /* \ - * saved fpu/fpu emulator stuff \ - */ \ - INIT_FPU, \ - /* \ - * Other stuff associated with the process \ - */ \ - 0, 0, 0, 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - MF_FIXADE, { 0 }, 0, 0, \ - /* \ - * dsemul_epc and dsemul_aerpc should never be used uninitialized, \ - * but... \ - */ \ - 0 ,0 \ -} - -#ifdef __KERNEL__ - -#define KERNEL_STACK_SIZE 8192 - -#if !defined (_LANGUAGE_ASSEMBLY) +struct task_struct; /* Free all resources held by a thread. */ #define release_thread(thread) do { } while(0) -extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -/* Copy and release all segment info associated with a VM */ -#define copy_segments(p, mm) do { } while(0) -#define release_segments(mm) do { } while(0) - -/* - * Return saved PC of a blocked thread. - */ -extern inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - extern void ret_from_fork(void); - - /* New born processes are a special case */ - if (t->reg31 == (unsigned long) ret_from_fork) - return t->reg31; - - return ((unsigned long *)t->reg29)[10]; -} - -/* - * Do necessary setup to start up a newly executed thread. - */ -#define start_thread(regs, new_pc, new_sp) do { \ - /* New thread looses kernel privileges. */ \ - regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\ - regs->cp0_epc = new_pc; \ - regs->regs[29] = new_sp; \ - current->thread.current_ds = USER_DS; \ -} while (0) +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while (0) -unsigned long get_wchan(struct task_struct *p); - -#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) -#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32) -#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) -#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) - -/* Allocation and freeing of basic task resources. */ -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#define cpu_relax() do { } while (0) - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ -#endif /* __KERNEL__ */ +#define cpu_relax() barrier() /* * Return_address is a replacement for __builtin_return_address(count) @@ -280,4 +123,20 @@ unsigned long get_wchan(struct task_struct *p); */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) +#ifdef CONFIG_CPU_HAS_PREFETCH + +#define ARCH_HAS_PREFETCH + +static inline void prefetch(const void *addr) +{ + __asm__ __volatile__( + " .set mips4 \n" + " pref %0, (%1) \n" + " .set mips0 \n" + : + : "i" (Pref_Load), "r" (addr)); +} + +#endif + #endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 2517adb2a8..5659c0c873 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -3,17 +3,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * - * Machine dependent structs and defines to help the user use - * the ptrace system call. + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -#include <asm/isadep.h> -#include <linux/types.h> - /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 @@ -23,63 +18,69 @@ #define MMLO 68 #define FPC_CSR 69 #define FPC_EIR 70 +#define DSP_BASE 71 /* 3 more hi / lo register pairs */ +#define DSP_CONTROL 77 +#define ACX 78 -#ifndef _LANGUAGE_ASSEMBLY /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { +#ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ unsigned long pad0[6]; +#endif /* Saved main processor registers. */ unsigned long regs[32]; - /* Other saved registers. */ - unsigned long lo; + /* Saved special registers. */ + unsigned long cp0_status; unsigned long hi; - - /* - * saved cp0 registers - */ - unsigned long cp0_epc; + unsigned long lo; +#ifdef CONFIG_CPU_HAS_SMARTMIPS + unsigned long acx; +#endif unsigned long cp0_badvaddr; - unsigned long cp0_status; unsigned long cp0_cause; -}; - -#endif /* !(_LANGUAGE_ASSEMBLY) */ + unsigned long cp0_epc; +#ifdef CONFIG_MIPS_MT_SMTC + unsigned long cp0_tcstatus; +#endif /* CONFIG_MIPS_MT_SMTC */ +} __attribute__ ((aligned (8))); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -/* #define PTRACE_GETREGS 12 */ -/* #define PTRACE_SETREGS 13 */ -/* #define PTRACE_GETFPREGS 14 */ -/* #define PTRACE_SETFPREGS 15 */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 /* #define PTRACE_GETFPXREGS 18 */ /* #define PTRACE_SETFPXREGS 19 */ -#define PTRACE_SETOPTIONS 21 +#define PTRACE_OLDSETOPTIONS 21 -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 +#define PTRACE_GET_THREAD_AREA 25 +#define PTRACE_SET_THREAD_AREA 26 -#if 0 /* def _LANGUAGE_ASSEMBLY */ -#include <asm/offset.h> -#endif +/* Calls to trace a 64bit program from a 32bit program. */ +#define PTRACE_PEEKTEXT_3264 0xc0 +#define PTRACE_PEEKDATA_3264 0xc1 +#define PTRACE_POKETEXT_3264 0xc2 +#define PTRACE_POKEDATA_3264 0xc3 +#define PTRACE_GET_THREAD_AREA_3264 0xc4 #ifdef __KERNEL__ -#ifndef _LANGUAGE_ASSEMBLY +#include <asm/isadep.h> + /* * Does the process account for user or for system time? */ #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) #define instruction_pointer(regs) ((regs)->cp0_epc) - -extern void show_regs(struct pt_regs *); -#endif /* !(_LANGUAGE_ASSEMBLY) */ +#define profile_pc(regs) instruction_pointer(regs) #endif diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h new file mode 100644 index 0000000000..978d206816 --- /dev/null +++ b/include/asm-mips/reboot.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle + * Copyright (C) 2001 MIPS Technologies, Inc. + */ +#ifndef _ASM_REBOOT_H +#define _ASM_REBOOT_H + +extern void _machine_restart(void); + +#endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h index 35505b70f8..fc6bc0c169 100644 --- a/include/asm-mips/reg.h +++ b/include/asm-mips/reg.h @@ -7,48 +7,50 @@ * for more details. * * Copyright (C) 1995, 1999 by Ralf Baechle + * Copyright (C) 1995, 1999 Silicon Graphics */ #ifndef __ASM_MIPS_REG_H #define __ASM_MIPS_REG_H -/* - * This defines/structures correspond to the register layout on stack - - * if the order here is changed, it needs to be updated in - * include/asm-mips/stackframe.h - */ -#define EF_REG0 6 -#define EF_REG1 7 -#define EF_REG2 8 -#define EF_REG3 9 -#define EF_REG4 10 -#define EF_REG5 11 -#define EF_REG6 12 -#define EF_REG7 13 -#define EF_REG8 14 -#define EF_REG9 15 -#define EF_REG10 16 -#define EF_REG11 17 -#define EF_REG12 18 -#define EF_REG13 19 -#define EF_REG14 20 -#define EF_REG15 21 -#define EF_REG16 22 -#define EF_REG17 23 -#define EF_REG18 24 -#define EF_REG19 25 -#define EF_REG20 26 -#define EF_REG21 27 -#define EF_REG22 28 -#define EF_REG23 29 -#define EF_REG24 30 -#define EF_REG25 31 +#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) + +#define EF_R0 6 +#define EF_R1 7 +#define EF_R2 8 +#define EF_R3 9 +#define EF_R4 10 +#define EF_R5 11 +#define EF_R6 12 +#define EF_R7 13 +#define EF_R8 14 +#define EF_R9 15 +#define EF_R10 16 +#define EF_R11 17 +#define EF_R12 18 +#define EF_R13 19 +#define EF_R14 20 +#define EF_R15 21 +#define EF_R16 22 +#define EF_R17 23 +#define EF_R18 24 +#define EF_R19 25 +#define EF_R20 26 +#define EF_R21 27 +#define EF_R22 28 +#define EF_R23 29 +#define EF_R24 30 +#define EF_R25 31 + /* * k0/k1 unsaved */ -#define EF_REG28 34 -#define EF_REG29 35 -#define EF_REG30 36 -#define EF_REG31 37 +#define EF_R26 32 +#define EF_R27 33 + +#define EF_R28 34 +#define EF_R29 35 +#define EF_R30 36 +#define EF_R31 37 /* * Saved special registers @@ -59,8 +61,66 @@ #define EF_CP0_EPC 40 #define EF_CP0_BADVADDR 41 #define EF_CP0_STATUS 42 -#define EF_CP0_CAUSE 44 +#define EF_CP0_CAUSE 43 +#define EF_UNUSED0 44 + +#define EF_SIZE 180 + +#endif + +#ifdef CONFIG_64BIT + +#define EF_R0 0 +#define EF_R1 1 +#define EF_R2 2 +#define EF_R3 3 +#define EF_R4 4 +#define EF_R5 5 +#define EF_R6 6 +#define EF_R7 7 +#define EF_R8 8 +#define EF_R9 9 +#define EF_R10 10 +#define EF_R11 11 +#define EF_R12 12 +#define EF_R13 13 +#define EF_R14 14 +#define EF_R15 15 +#define EF_R16 16 +#define EF_R17 17 +#define EF_R18 18 +#define EF_R19 19 +#define EF_R20 20 +#define EF_R21 21 +#define EF_R22 22 +#define EF_R23 23 +#define EF_R24 24 +#define EF_R25 25 + +/* + * k0/k1 unsaved + */ +#define EF_R26 26 +#define EF_R27 27 + +#define EF_R28 28 +#define EF_R29 29 +#define EF_R30 30 +#define EF_R31 31 + +/* + * Saved special registers + */ +#define EF_LO 32 +#define EF_HI 33 + +#define EF_CP0_EPC 34 +#define EF_CP0_BADVADDR 35 +#define EF_CP0_STATUS 36 +#define EF_CP0_CAUSE 37 + +#define EF_SIZE 304 /* size in bytes */ -#define EF_SIZE 180 /* size in bytes */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h index 691d047b67..2e65cc3c43 100644 --- a/include/asm-mips/regdef.h +++ b/include/asm-mips/regdef.h @@ -1,52 +1,100 @@ /* - * include/asm-mips/regdefs.h - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Ralf Baechle + * Copyright (C) 1985 MIPS Computer Systems, Inc. + * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle + * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. */ +#ifndef _ASM_REGDEF_H +#define _ASM_REGDEF_H + +#include <asm/sgidefs.h> -#ifndef __ASM_MIPS_REGDEF_H -#define __ASM_MIPS_REGDEF_H +#if _MIPS_SIM == _MIPS_SIM_ABI32 /* * Symbolic register names for 32 bit ABI */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ #define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ +#define ra $31 /* return address */ + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ -#endif /* __ASM_MIPS_REGDEF_H */ +#endif /* _ASM_REGDEF_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index 707cbf42dc..f49a2176af 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -1,5 +1,4 @@ -/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -10,6 +9,8 @@ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H +#ifndef __ASSEMBLY__ + typedef unsigned short umode_t; /* @@ -40,11 +41,17 @@ __extension__ typedef unsigned long long __u64; #endif +#endif /* __ASSEMBLY__ */ + /* * These aren't exported outside the kernel to avoid name space clashes */ #ifdef __KERNEL__ +#define BITS_PER_LONG _MIPS_SZLONG + +#ifndef __ASSEMBLY__ + typedef __signed char s8; typedef unsigned char u8; @@ -68,9 +75,24 @@ typedef unsigned long long u64; #endif -#define BITS_PER_LONG _MIPS_SZLONG +#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ + || defined(CONFIG_64BIT) +typedef u64 dma_addr_t; +#else +typedef u32 dma_addr_t; +#endif +typedef u64 dma64_addr_t; + +/* + * Don't use phys_t. You've been warned. + */ +#ifdef CONFIG_64BIT_PHYS_ADDR +typedef unsigned long long phys_t; +#else +typedef unsigned long phys_t; +#endif -typedef unsigned long dma_addr_t; +#endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index fd1138920c..ddd66cfd40 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -45,6 +45,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7") diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index a1ac288568..ae5f61700e 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -44,6 +44,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15") diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 4c03b050fe..d27d2a965c 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -29,6 +29,18 @@ #define PCIE2_SDR 0x370 #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CFG_PCIE_NR_PORTS 2 + +#define CFG_PCIE_ADDR_HIGH 0x0000000d + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#endif + #if defined(CONFIG_405EX) #define CFG_PCIE_NR_PORTS 2 @@ -68,7 +80,7 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 -/* common regs, at least for 405EX and 440SPe */ +/* common regs, at for all 4xx with PCIe core */ #define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) #define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) #define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) @@ -198,8 +210,73 @@ #define PESDR1_LPB 0x044B #define PESDR1_PHYSTA 0x044C +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */ +#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */ +#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */ +#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */ +#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */ +#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */ +#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */ +#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */ +#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */ +#define PESDR0_OBS 0x0311 /* PE0 observation register */ +#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */ + +#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */ +#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */ +#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */ +#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */ +#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */ +#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */ +#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */ +#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */ +#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */ +#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */ +#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */ +#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */ +#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */ +#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */ +#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */ +#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */ +#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */ +#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */ +#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */ +#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */ +#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */ +#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */ +#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */ +#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */ +#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */ +#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */ +#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */ +#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */ +#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */ +#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */ +#define PESDR1_OBS 0x0366 /* PE1 observation register */ +#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */ +#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */ +#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */ +#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */ +#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */ +#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */ + #endif +/* SDR Bit Mappings */ +#define PESDRx_RCSSET_HLDPLB 0x10000000 +#define PESDRx_RCSSET_RSTGU 0x01000000 +#define PESDRx_RCSSET_RDY 0x00100000 +#define PESDRx_RCSSET_RSTDL 0x00010000 +#define PESDRx_RCSSET_RSTPYN 0x00001000 + +#define PESDRx_RCSSTS_PLBIDL 0x10000000 +#define PESDRx_RCSSTS_HRSTRQ 0x01000000 +#define PESDRx_RCSSTS_PGRST 0x00100000 +#define PESDRx_RCSSTS_VC0ACT 0x00010000 +#define PESDRx_RCSSTS_BMEN 0x00000100 + /* * UTL register offsets */ diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h new file mode 100644 index 0000000000..733f919cf8 --- /dev/null +++ b/include/asm-ppc/fsl_serdes.h @@ -0,0 +1,21 @@ +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +#define FSL_SERDES_CLK_100 0 +#define FSL_SERDES_CLK_125 1 +#define FSL_SERDES_CLK_150 3 +#define FSL_SERDES_PROTO_SATA 0 +#define FSL_SERDES_PROTO_PEX 1 +#define FSL_SERDES_PROTO_PEX_X2 2 +#define FSL_SERDES_PROTO_SGMII 3 +#define FSL_SERDES_VDD_1V 1 + +#ifdef CONFIG_FSL_SERDES +extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd); +#else +static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {} +#endif /* CONFIG_FSL_SERDES */ + +#endif /* __FSL_SERDES_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 205f7ed74b..ff6624a227 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -40,8 +40,11 @@ typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; +#if defined(CONFIG_8xx) + unsigned long brg_clk; +#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; @@ -164,6 +167,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #if 1 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c3a4a88d58..fc05dc0df7 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -27,7 +27,8 @@ /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define GPIO_GROUP_MAX 2 #else #define GPIO_GROUP_MAX 1 diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 5af22af995..49d6860fc7 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -549,14 +549,14 @@ extern int num_tlb_entries; /*----------------------------------------------------------------------------+ | TLB specific defines. +----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xF0000000 -#define TLB_16MB_ALIGN_MASK 0xFF000000 -#define TLB_1MB_ALIGN_MASK 0xFFF00000 -#define TLB_256KB_ALIGN_MASK 0xFFFC0000 -#define TLB_64KB_ALIGN_MASK 0xFFFF0000 -#define TLB_16KB_ALIGN_MASK 0xFFFFC000 -#define TLB_4KB_ALIGN_MASK 0xFFFFF000 -#define TLB_1KB_ALIGN_MASK 0xFFFFFC00 +#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL +#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL +#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL +#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL +#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL +#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL +#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL +#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL #define TLB_256MB_SIZE 0x10000000 #define TLB_16MB_SIZE 0x01000000 #define TLB_1MB_SIZE 0x00100000 @@ -697,7 +697,7 @@ unsigned long mftlb1(unsigned long index); unsigned long mftlb2(unsigned long index); unsigned long mftlb3(unsigned long index); -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); +void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void remove_tlb(u32 vaddr, u32 size); void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h index 8d04b69063..e2181190e3 100644 --- a/include/asm-ppc/ppc4xx-intvec.h +++ b/include/asm-ppc/ppc4xx-intvec.h @@ -117,6 +117,73 @@ #define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ #define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +/* UIC 0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 8 /* PCI MSI level 0 */ +#define VECNUM_EIR0 9 /* External interrupt 0 */ +#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ +#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ +#define VECNUM_EIR1 9 /* External interrupt 1 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ +#define VECNUM_U0 (32 + 1) /* UART0 */ +#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ +#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ +#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ +#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ +#define VECNUM_U2 (32 + 28) /* UART2 */ +#define VECNUM_U3 (32 + 29) /* UART3 */ +#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ +#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ + +/* UIC 2 */ +#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ +#define VECNUM_MS (64 + 3) /* MAL SERR */ +#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ +#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ +#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ +#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ +#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ +#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ +#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ +#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ +#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ +#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ +#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ +#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ +#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ +#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ + +/* UIC 3 */ +#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ +#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ +#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ +#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ +#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ +#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ +#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ +#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ +#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ +#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ +#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ +#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ + #elif defined(CONFIG_440SPE) /* UIC 0 */ @@ -130,10 +197,14 @@ #define VECNUM_MSI0 7 /* PCI MSI level 0 */ #define VECNUM_MSI1 8 /* PCI MSI level 0 */ #define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ #define VECNUM_D0 12 /* DMA channel 0 */ #define VECNUM_D1 13 /* DMA channel 1 */ #define VECNUM_D2 14 /* DMA channel 2 */ #define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ +#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 86c5df2dba..b7a5b28806 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -802,6 +802,10 @@ #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 2b31814b66..786ba030ea 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -115,7 +115,8 @@ typedef struct bd_info { #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif @@ -123,7 +124,8 @@ typedef struct bd_info { unsigned char bi_sernum[8]; #endif #if defined(CONFIG_4xx) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) int bi_phynum[4]; /* Determines phy mapping */ int bi_phymode[4]; /* Determines phy mode */ #elif defined(CONFIG_405EP) || defined(CONFIG_440) diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h index 0a44a34cef..521a66ffc3 100644 --- a/include/asm-sh/global_data.h +++ b/include/asm-sh/global_data.h @@ -44,6 +44,7 @@ typedef struct global_data #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") diff --git a/include/common.h b/include/common.h index 3351e2c0a6..e03ead10bc 100644 --- a/include/common.h +++ b/include/common.h @@ -270,7 +270,9 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) || defined(CONFIG_405EX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) void pcie_setup_hoses(int busno); #endif #endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index f3965efe95..69276a3894 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_CMD_SNTP /* SNTP support */ #define CONFIG_CMD_SPI /* SPI utility */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 4304ecca7d..79199912df 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -37,6 +37,8 @@ #define CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY @@ -212,4 +214,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index f12a3e605e..9576fa59e2 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -38,6 +38,14 @@ #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + */ +#define CONFIG_VSC7385_ENET + + #ifdef CFG_66MHZ #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ #elif defined(CFG_33MHZ) @@ -65,6 +73,22 @@ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ /* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC2 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ @@ -214,19 +238,24 @@ #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +/* local bus read write buffer mapping */ +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ +#define CFG_LBLAWBAR3_PRELIM 0xFA000000 +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* Vitesse 7385 */ + #define CFG_VSC7385_BASE 0xF0000000 -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ +#ifdef CONFIG_VSC7385_ENET + #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ -/* local bus read write buffer mapping */ -#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ -#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ -#define CFG_LBLAWBAR3_PRELIM 0xFA000000 -#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -263,13 +292,6 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -/* TSEC */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) -#define CONFIG_NET_MULTI - /* * General PCI * Addresses are mapped 1-1. @@ -288,26 +310,31 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ /* - * TSEC configuration + * TSEC */ #define CONFIG_TSEC_ENET /* TSEC ethernet support */ -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 +#define CFG_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0x1c -#define TSEC2_PHY_ADDR 4 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 +#define CFG_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC1" @@ -496,10 +523,13 @@ */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 +#endif + +#ifdef CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 +#endif #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index ff7101f249..af7872628e 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -299,7 +299,7 @@ #define CFG_PCI_MMIO_BASE 0x90000000 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_BASE 0x00000000 #define CFG_PCI_IO_PHYS 0xE0300000 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index bf5ef4b59a..94c4c6b040 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -66,6 +66,13 @@ #define CFG_IMMR 0xE0000000 /* + * System performance + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ + +/* * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ @@ -82,17 +89,51 @@ /* Manually set up DDR parameters */ #define CFG_DDR_SIZE 64 /* MB */ -#define CFG_DDR_CS0_CONFIG 0x80840101 -#define CFG_DDR_TIMING_0 0x00220802 -#define CFG_DDR_TIMING_1 0x3935d322 -#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | CSCONFIG_ODT_WR_ACS \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) + /* 0x80010101 */ +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x26253222 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | (31 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x1f9048c7 */ #define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_CLK_CNTL 0x02000000 -#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /* 0x02000000 */ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44480232 */ #define CFG_DDR_MODE2 0x8000c000 -#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03200064 */ #define CFG_DDR_CS0_BNDS 0x00000003 -#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ #define CFG_DDR_SDRAM_CFG2 0x00401000 #endif @@ -280,10 +321,10 @@ #define CFG_I2C_OFFSET 0x3000 /* - * Config on-board RTC + * Config on-board EEPROM */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* * General PCI @@ -376,6 +417,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM #define CONFIG_CMD_ASKENV #if defined(CONFIG_PCI) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f32c4f70cf..be2ab45584 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -346,7 +346,7 @@ #define CFG_PCI_MMIO_BASE 0x90000000 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_BASE 0x00000000 #define CFG_PCI_IO_PHYS 0xE0300000 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 48c2736fcb..6b8b74dd96 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -68,12 +68,16 @@ #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ +#define CONFIG_MISC_INIT_F +#define CONFIG_MISC_INIT_R -/* On-board devices */ +/* + * On-board devices + */ #ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ -#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ +#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ #endif #define CONFIG_PCI @@ -88,9 +92,6 @@ /* I2C */ #ifdef CONFIG_HARD_I2C -#define CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R - #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE @@ -155,7 +156,7 @@ #define CFG_MEMTEST_END 0x2000 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC2 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFEFFE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + /* * BRx, ORx, LBLAWBARx, and LBLAWARx */ @@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */ /* Vitesse 7385 */ -#ifdef CONFIG_VSC7385 - #define CFG_VSC7385_BASE 0xF8000000 +#ifdef CONFIG_VSC7385_ENET + #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ @@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 -#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ + #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 #define TSEC2_FLAGS TSEC_GIGABIT @@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_TSEC1 +#ifdef CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 #endif -#ifdef CONFIG_TSEC2 +#ifdef CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index c8dcbc628b..46451c4c98 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -194,6 +194,7 @@ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -374,7 +375,7 @@ #define CFG_PCI_MMIO_BASE 0x90000000 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_BASE 0x00000000 #define CFG_PCI_IO_PHYS 0xE0300000 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 27b037ad00..a4f6af6733 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -30,8 +30,8 @@ * System Clock Setup */ #ifdef CONFIG_CLKIN_33MHZ -#define CONFIG_83XX_CLKIN 33000000 -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_83XX_CLKIN 33333333 +#define CONFIG_SYS_CLK_FREQ 33333333 #define PCI_33M 1 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 #else @@ -89,8 +89,8 @@ #define CFG_83XX_DDR_USES_CS0 -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ /* * DDRCDR - DDR Control Driver Register @@ -104,20 +104,44 @@ */ #define CONFIG_DDR_II #define CFG_DDR_SIZE 256 /* MB */ -#define CFG_DDRCDR 0x80080001 #define CFG_DDR_CS0_BNDS 0x0000000f #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) -#define CFG_DDR_TIMING_0 0x00330903 -#define CFG_DDR_TIMING_1 0x3835a322 -#define CFG_DDR_TIMING_2 0x00104909 -#define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_CLK_CNTL 0x02000000 + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) +#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN) +#define CFG_DDR_SDRAM_CFG2 0x00001000 +#define CFG_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) #define CFG_DDR_MODE 0x47800432 #define CFG_DDR_MODE2 0x8000c000 -#define CFG_DDR_INTERVAL 0x045b0100 -#define CFG_DDR_SDRAM_CFG 0x03000000 -#define CFG_DDR_SDRAM_CFG2 0x00001000 + +#define CFG_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CFG_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ + (10 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CFG_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (0 << TIMING_CFG2_CPO_SHIFT)) + +#define CFG_DDR_TIMING_3 0x00000000 /* * Memory test @@ -184,6 +208,11 @@ * NAND flash on the local bus */ #define CFG_NAND_BASE 0x60000000 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_UPM 1 +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ @@ -230,6 +259,7 @@ /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -290,7 +320,7 @@ #define CFG_UEC1_TX_CLK QE_CLK9 #define CFG_UEC1_ETH_TYPE GIGA_ETH #define CFG_UEC1_PHY_ADDR 2 -#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -301,7 +331,7 @@ #define CFG_UEC2_TX_CLK QE_CLK4 #define CFG_UEC2_ETH_TYPE GIGA_ETH #define CFG_UEC2_PHY_ADDR 4 -#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID #endif /* @@ -340,6 +370,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -499,27 +530,44 @@ "consoledev=ttyS0\0"\ "loadaddr=a00000\0"\ "fdtaddr=900000\0"\ - "bootfile=uImage\0"\ "fdtfile=dtb\0"\ "fsfile=fs\0"\ "ubootfile=u-boot.bin\0"\ + "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ "$gatewayip:$netmask:$hostname:$netdev:off "\ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ + "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ "tftp_get_fs=tftp c00000 $fsfile\0"\ + "nand_erase_kernel=nand erase 0 400000\0"\ + "nand_erase_dtb=nand erase 400000 20000\0"\ + "nand_erase_fs=nand erase 420000 3be0000\0"\ + "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\ + "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\ + "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\ + "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ + "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ "cp.b 100000 ff800000 $filesize\0"\ + "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ + "nand_write_kernel\0"\ + "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ + "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\ + "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\ + "nand_reflash_fs\0"\ "boot_m=bootm $loadaddr - $fdtaddr\0"\ - "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ - "boot_m\0"\ + "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ - "boot_m\0"\ + "boot_m\0"\ + "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ + "boot_m\0"\ "" #define CONFIG_BOOTCOMMAND "run dhcpboot" diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5586533de5..b307bf71ef 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -338,7 +338,7 @@ #define CFG_PCI_MMIO_BASE 0x90000000 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_BASE 0x00000000 #define CFG_PCI_IO_PHYS 0xE0300000 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1964946ec8..90812e92a9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -32,6 +32,15 @@ #define CONFIG_PCI 1 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + */ +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ +#define CONFIG_VSC7385_ENET + /* * System Clock Setup */ @@ -118,6 +127,22 @@ #define CFG_IMMR 0xE0000000 /* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC2 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ @@ -251,15 +276,38 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +/* + * NAND Flash on the Local Bus + */ +#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CFG_BR1_PRELIM (CFG_NAND_BASE | \ + (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ + BR_PS_8 | /* Port Size = 8 bit */ \ + BR_MS_FCM | /* MSEL = FCM */ \ + BR_V) /* valid */ +#define CFG_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ + OR_FCM_CSCT | \ + OR_FCM_CST | \ + OR_FCM_CHT | \ + OR_FCM_SCY_1 | \ + OR_FCM_TRLX | \ + OR_FCM_EHTR) +#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +/* Vitesse 7385 */ + #define CFG_VSC7385_BASE 0xF0000000 -/* VSC7385 Gigabit Switch support */ -#define CONFIG_VSC7385_ENET +#ifdef CONFIG_VSC7385_ENET + #define CFG_BR2_PRELIM 0xf0000801 /* Base address */ #define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */ #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ +#endif + /* * Serial Port */ @@ -276,6 +324,11 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER @@ -285,6 +338,7 @@ /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -312,7 +366,7 @@ #define CFG_PCI_MMIO_BASE 0x90000000 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_BASE 0x00000000 #define CFG_PCI_IO_PHYS 0xE0300000 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ @@ -324,43 +378,43 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - /* * TSEC */ -#define CONFIG_TSEC_ENET /* TSEC ethernet support */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#ifdef CONFIG_TSEC_ENET -/* - * TSEC ethernet configuration - */ -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ + +#define CONFIG_TSEC1 + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0x1c #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 +#endif +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CFG_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 0x1c +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHYIDX 0 +#endif /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" +#endif + /* * Environment */ @@ -529,10 +583,15 @@ */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ -#define CONFIG_ETHADDR 00:04:9f:ef:04:01 -#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ -#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 +#ifdef CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:04:9f:ef:04:01 +#endif + +#ifdef CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 +#endif + +#define CONFIG_HAS_FSL_DR_USB #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 9a0e9b84af..b36c8264da 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -252,12 +252,22 @@ "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" #endif +#if defined(CONFIG_TQM5200_B) +#define ENV_FLASH_LAYOUT \ + "fdt_addr=FC100000\0" \ + "kernel_addr=FC140000\0" \ + "ramdisk_addr=FC600000\0" +#else /* !CONFIG_TQM5200_B */ +#define ENV_FLASH_LAYOUT \ + "fdt_addr=FC0A0000\0" \ + "kernel_addr=FC0C0000\0" \ + "ramdisk_addr=FC300000\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "console=ttyPSC0\0" \ - "fdt_addr=FC0A0000\0" \ - "kernel_addr=FC0C0000\0" \ - "ramdisk_addr=FC300000\0" \ + ENV_FLASH_LAYOUT \ "kernel_addr_r=400000\0" \ "fdt_addr_r=600000\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ @@ -400,8 +410,9 @@ # if defined(CONFIG_TQM5200_B) # if defined(CFG_LOWBOOT) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \ - "1536k(kernel)," \ - "3584k(small-fs)," \ + "256k(dtb)," \ + "2304k(kernel)," \ + "2560k(small-fs)," \ "2m(initrd)," \ "8m(misc)," \ "16m(big-fs)" diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 6cb6bc4f71..f2c8703991 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -5,6 +5,8 @@ #ifndef __CONFIG_EZKIT533_H__ #define __CONFIG_EZKIT533_H__ +#include <asm/blackfin-config-pre.h> + #define CONFIG_BAUDRATE 57600 #define CONFIG_STAMP 1 @@ -41,10 +43,7 @@ #define CONFIG_PANIC_HANG 1 -#define ADSP_BF531 0x31 -#define ADSP_BF532 0x32 -#define ADSP_BF533 0x33 -#define BFIN_CPU ADSP_BF533 +#define CONFIG_BFIN_CPU bf533-0.3 /* This sets the default state of the cache on U-Boot's boot */ #define CONFIG_ICACHE_ON @@ -120,7 +119,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" -#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index cce6ef79f2..76dd2fa4a2 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -5,6 +5,8 @@ #ifndef __CONFIG_STAMP_H__ #define __CONFIG_STAMP_H__ +#include <asm/blackfin-config-pre.h> + #define CONFIG_STAMP 1 #define CONFIG_RTC_BFIN 1 #define CONFIG_BF533 1 @@ -21,10 +23,7 @@ #define CONFIG_PANIC_HANG 1 -#define ADSP_BF531 0x31 -#define ADSP_BF532 0x32 -#define ADSP_BF533 0x33 -#define BFIN_CPU ADSP_BF533 +#define CONFIG_BFIN_CPU bf533-0.3 /* This sets the default state of the cache on U-Boot's boot */ #define CONFIG_ICACHE_ON @@ -329,23 +328,7 @@ #define CONFIG_BAUDRATE 57600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ -#elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ -#endif -#else -#if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ -#elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ -#endif -#endif +#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index b9a9e3cb79..0e189d4324 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -5,6 +5,8 @@ #ifndef __CONFIG_BF537_H__ #define __CONFIG_BF537_H__ +#include <asm/blackfin-config-pre.h> + #define CFG_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_BAUDRATE 57600 @@ -31,10 +33,8 @@ #define CONFIG_PANIC_HANG 1 -#define ADSP_BF534 0x34 -#define ADSP_BF536 0x36 -#define ADSP_BF537 0x37 -#define BFIN_CPU ADSP_BF537 +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_MAC /* This sets the default state of the cache on U-Boot's boot */ #define CONFIG_ICACHE_ON @@ -113,7 +113,7 @@ * Network Settings */ /* network support */ -#if (BFIN_CPU != ADSP_BF534) +#ifdef CONFIG_BFIN_MAC #define CONFIG_IPADDR 192.168.0.15 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_GATEWAYIP 192.168.0.1 @@ -186,7 +186,7 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE -#if (BFIN_CPU == ADSP_BF534) +#ifndef CONFIG_BFIN_MAC #undef CONFIG_CMD_NET #else #define CONFIG_CMD_PING @@ -219,7 +219,7 @@ #define CONFIG_LOADADDR 0x1000000 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) -#if (BFIN_CPU != ADSP_BF534) +#ifdef CONFIG_BFIN_MAC #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -243,7 +243,7 @@ "" #endif #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) -#if (BFIN_CPU != ADSP_BF534) +#ifdef CONFIG_BFIN_MAC #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -267,23 +267,7 @@ #endif #endif -#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) -#if (BFIN_CPU == ADSP_BF534) -#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */ -#elif (BFIN_CPU == ADSP_BF536) -#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */ -#endif -#else -#if (BFIN_CPU == ADSP_BF534) -#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */ -#elif (BFIN_CPU == ADSP_BF536) -#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */ -#endif -#endif +#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -302,6 +286,11 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x20000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_PROTECTION +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) @@ -311,10 +300,6 @@ #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT) /* for bf537-stamp, usrt boot mode still store env in flash */ #define CFG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 29662604f9..c29555aeae 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -5,6 +5,8 @@ #ifndef __CONFIG_EZKIT561_H__ #define __CONFIG_EZKIT561_H__ +#include <asm/blackfin-config-pre.h> + #define CONFIG_VDSP 1 #define CONFIG_BF561 1 @@ -18,6 +20,8 @@ #define CONFIG_PANIC_HANG 1 +#define CONFIG_BFIN_CPU bf561-0.3 + /* * Boot Mode Set * Blackfin can support several boot modes @@ -216,7 +220,7 @@ */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h new file mode 100644 index 0000000000..a4bcc655ee --- /dev/null +++ b/include/configs/canyonlands.h @@ -0,0 +1,567 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * canyonlands.h - configuration for Canyonlands (460EX) + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */ +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_460EX 1 /* Specific PPC460EX support */ + +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ +#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */ + +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 + +#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */ + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */ + +/* EBC stuff */ +#define CFG_NAND_ADDR 0xE0000000 +#define CFG_BCSR_BASE 0xE1000000 +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ +#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */ +#define CFG_FLASH_BASE_PHYS_H 0x4 +#define CFG_FLASH_BASE_PHYS_L 0xCC000000 +#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \ + (u64)CFG_FLASH_BASE_PHYS_L) +#define CFG_FLASH_SIZE (64 << 20) + +#define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */ +#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CFG_LOCAL_CONF_REGS 0xEF000000 + +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ + +#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in OCM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH). + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */ + /* this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NAND-FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/*------------------------------------------------------------------------------ + * DDR SDRAM + *----------------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) +/* + * NAND booting U-Boot version uses a fixed initialization, since the whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot + * code. + */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ +#define CONFIG_DDR_ECC 1 /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ +#endif +#define CFG_MBYTES_SDRAM 256 /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* RTC configuration */ +#define CONFIG_RTC_M41T62 1 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 +#define CONFIG_HAS_ETH0 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_NET_MULTI 1 + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +/*----------------------------------------------------------------------- + * USB-OHCI + *----------------------------------------------------------------------*/ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */ +#define CFG_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ +#define CFG_OHCI_USE_NPS /* force NoPowerSwitching mode */ +#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000) +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + +/*----------------------------------------------------------------------- + * Default environment + *----------------------------------------------------------------------*/ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=canyonlands\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty;" \ + "bootm 200000\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=canyonlands/uImage\0" \ + "fdt_file=canyonlands/canyonlands.dtb\0" \ + "fdt_addr=400000\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 canyonlands/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_USB + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Internal Definitions + */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* + * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +/* Memory Bank 3 (NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x10055e00 +#define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ +#else +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x10055e00 +#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ +#endif + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x00804240 +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */ + +#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */ + +/* + * PPC4xx GPIO Configuration + */ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 5a85feb853..4ecaf90abc 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -1,5 +1,5 @@ /* - *(C) Copyright 2005-2007 Netstal Maschinen AG + *(C) Copyright 2005-2008 Netstal Maschinen AG * Niklaus Giger (Niklaus.Giger@netstal.com) * * See file CREDITS for list of people who contributed to this @@ -103,13 +103,19 @@ * Flash *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* board provides its own flash_init code */ +#define CONFIG_FLASH_CFI_LEGACY 1 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_LEGACY_512Kx8 1 -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 2ed8530b6d..f5f11978da 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -349,12 +349,20 @@ * Flash *----------------------------------------------------------------------*/ +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* board provides its own flash_init code */ +#define CONFIG_FLASH_CFI_LEGACY 1 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_LEGACY_512Kx8 1 + +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c3f10c75a8..ced7ba6f05 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -36,6 +36,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_RESET 1 /* Call board_reset */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -86,6 +87,15 @@ #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +/* Additional registers for watchdog timer post test */ + +#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) +#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP4) +#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) +#define CFG_WATCHDOG_MAGIC 0x12480000 +#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 +#define CFG_DSPIC_TEST_MASK 0x00000001 + /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ @@ -156,10 +166,86 @@ CFG_POST_MEMORY | \ CFG_POST_RTC | \ CFG_POST_SPR | \ - CFG_POST_UART) + CFG_POST_UART | \ + CFG_POST_SYSMON | \ + CFG_POST_WATCHDOG | \ + CFG_POST_DSP | \ + CFG_POST_BSPEC1 | \ + CFG_POST_BSPEC2 | \ + CFG_POST_BSPEC3 | \ + CFG_POST_BSPEC4 | \ + CFG_POST_BSPEC5) + +#define CONFIG_POST_WATCHDOG {\ + "Watchdog timer test", \ + "watchdog", \ + "This test checks the watchdog timer.", \ + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ + &lwmon5_watchdog_post_test, \ + NULL, \ + NULL, \ + CFG_POST_WATCHDOG \ + } + +#define CONFIG_POST_BSPEC1 {\ + "dsPIC init test", \ + "dspic_init", \ + "This test returns result of dsPIC READY test run earlier.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_init_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC1 \ + } + +#define CONFIG_POST_BSPEC2 {\ + "dsPIC test", \ + "dspic", \ + "This test gets result of dsPIC POST and dsPIC version.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC2 \ + } + +#define CONFIG_POST_BSPEC3 {\ + "FPGA test", \ + "fpga", \ + "This test checks FPGA registers and memory.", \ + POST_RAM | POST_ALWAYS, \ + &fpga_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC3 \ + } + +#define CONFIG_POST_BSPEC4 {\ + "GDC test", \ + "gdc", \ + "This test checks GDC registers and memory.", \ + POST_RAM | POST_ALWAYS, \ + &gdc_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC4 \ + } + +#define CONFIG_POST_BSPEC5 {\ + "SYSMON1 test", \ + "sysmon1", \ + "This test checks GPIO_62_EPX pin indicating power failure.", \ + POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ + &sysmon1_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC5 \ + } #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_LOGBUFFER +#define CONFIG_ALT_LH_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP1) +#define CONFIG_ALT_LB_ADDR (CFG_OCM_BASE) #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ /*----------------------------------------------------------------------- @@ -181,6 +267,7 @@ #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #if 0 @@ -366,9 +453,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * ToDo: Watchdog is not test fully, so exclude it for now - */ #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #define CONFIG_WD_PERIOD 40000 /* in usec */ @@ -431,10 +515,14 @@ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 +#define CFG_GPIO_DSPIC_READY 51 #define CFG_GPIO_EEPROM_EXT_WP 55 +#define CFG_GPIO_HIGHSIDE 56 #define CFG_GPIO_EEPROM_INT_WP 57 +#define CFG_GPIO_BOARD_RESET 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 +#define CFG_GPIO_SYSMON_STATUS 62 #define CFG_GPIO_WATCHDOG 63 /*----------------------------------------------------------------------- diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h new file mode 100644 index 0000000000..c5b6e8f68d --- /dev/null +++ b/include/configs/mcu25.h @@ -0,0 +1,361 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * mcu25.h - configuration for MCU25 board (similar to hcu4.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_MCU25 1 /* Board is MCU25 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405GP 1 +#define CONFIG_4xx 1 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) +*----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE + +/* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 +/* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + +/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_SERIAL_MULTI 1 +/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Flash + *----------------------------------------------------------------------*/ + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* board provides its own flash_init code */ +#define CONFIG_FLASH_CFI_LEGACY 1 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_LEGACY_512Kx8 1 + +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM configuration */ +#define PROM_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the first internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 0 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME mcu25 +#define CONFIG_IPADDR 172.25.1.99 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/mcu25/uImage\0" \ + "load=tftp 100000 mcu25/u-boot.bin\0" \ + "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ + "cp.b 100000 FFFB0000 50000\0" \ + "upd=run load;run update\0" \ + "vx_rom=mcu25/mcu25_vx_rom\0" \ + "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ + "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descr */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +/* SPD EEPROM (sdram speed config) disabled */ +#define CONFIG_SPD_EEPROM 1 +#define SPD_EEPROM_ADDRESS 0x50 + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) + +#define CFG_POST_UART_TABLE {UART0_BASE} +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#undef CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CFG_EBC_CFG 0x98400000 + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/ + +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB2CR 0x7A09A000u + +#define CFG_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB3CR 0x7B09A000u + +#define CFG_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB4CR 0x7C09A000u + +#define CFG_EBC_PB5AP 0x00800200u +#define CFG_EBC_PB5CR 0x7D81A000u + +#define CFG_EBC_PB6AP 0x01040200u +#define CFG_EBC_PB6CR 0x7D91A000u + +#define CFG_GPIO0_OR 0x087FFFFF /* GPIO value */ +#define CFG_GPIO0_TCR 0x7FFF8000 /* GPIO value */ +#define CFG_GPIO0_ODR 0xFFFF0000 /* GPIO value */ +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 98facf23c5..b1e3d53158 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -105,12 +105,11 @@ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyCPM0,,${baudrate}\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1 " \ - "console=${console}\0" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\ "bootm ${kernel_addr} - ${fdt_addr}\0" \ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index b035857dce..f12765d660 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -594,7 +594,5 @@ typedef unsigned int led_id_t; #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) -#define CONFIG_OF_HAS_BD_T 1 -#define CONFIG_OF_HAS_UBOOT_ENV 1 #endif /* __CONFIG_H */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 7836f28cda..890993ff9d 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -50,13 +50,11 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); void fdt_fixup_qe_firmware(void *fdt); -#ifdef CONFIG_OF_HAS_UBOOT_ENV -int fdt_env(void *fdt); -#endif - -#ifdef CONFIG_OF_HAS_BD_T -int fdt_bd_t(void *fdt); -#endif +#ifdef CONFIG_HAS_FSL_DR_USB +void fdt_fixup_dr_usb(void *blob, bd_t *bd); +#else +static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {} +#endif /* CONFIG_HAS_FSL_DR_USB */ #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); diff --git a/include/libfdt.h b/include/libfdt.h index 3a64d0b026..beeacb2e07 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -852,6 +852,32 @@ int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); int fdt_del_mem_rsv(void *fdt, int n); /** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** * fdt_setprop - create or change a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change diff --git a/include/mpc83xx.h b/include/mpc83xx.h index df052e3d4c..4ee38aafa9 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -121,6 +121,7 @@ #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ #define SPCR_PCIPR_SHIFT (31-7) #define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_OPT_SHIFT (31-8) #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ @@ -880,7 +881,7 @@ #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 -#define TIMING_CFG0_MRS_CYC 0x00000F00 +#define TIMING_CFG0_MRS_CYC 0x0000000F #define TIMING_CFG0_MRS_CYC_SHIFT 0 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 @@ -903,6 +904,7 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ diff --git a/include/post.h b/include/post.h index c8062bbbc1..ee07d2caa2 100644 --- a/include/post.h +++ b/include/post.h @@ -42,12 +42,16 @@ #define POST_REBOOT 0x0800 /* test may cause rebooting */ #define POST_PREREL 0x1000 /* test runs before relocation */ +#define POST_CRITICAL 0x2000 /* Use failbootcmd if test failed */ + #define POST_MEM (POST_RAM | POST_ROM) #define POST_ALWAYS (POST_NORMAL | \ POST_SLOWTEST | \ POST_MANUAL | \ POST_POWERON ) +#define POST_FAIL_SAVE 0x80 + #ifndef __ASSEMBLY__ struct post_test { @@ -93,6 +97,11 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_CODEC 0x00002000 #define CFG_POST_FPU 0x00004000 #define CFG_POST_ECC 0x00008000 +#define CFG_POST_BSPEC1 0x00010000 +#define CFG_POST_BSPEC2 0x00020000 +#define CFG_POST_BSPEC3 0x00040000 +#define CFG_POST_BSPEC4 0x00080000 +#define CFG_POST_BSPEC5 0x00100000 #endif /* CONFIG_POST */ diff --git a/include/ppc405.h b/include/ppc405.h index cbfe89ee41..37b121c3dc 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -118,7 +118,17 @@ /****************************************************************************** * Universal interrupt controller ******************************************************************************/ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + #define UIC_DCR_BASE 0xc0 +#define UIC0_DCR_BASE UIC_DCR_BASE #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ @@ -141,6 +151,7 @@ #define uic0vcr uicvcr /* UIC vector configuration*/ #define UIC_DCR_BASE1 0xd0 +#define UIC1_DCR_BASE 0xd0 #define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ #define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ #define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ @@ -152,6 +163,7 @@ #define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ #define UIC_DCR_BASE2 0xe0 +#define UIC2_DCR_BASE 0xe0 #define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ #define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ #define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ @@ -237,10 +249,13 @@ #define UIC_ENET1 0x00000040 /* */ #define UIC_PCIEMSI2 0x00000020 /* */ #define UIC_EIRQ4 0x00000010 /**/ -#define UIC_UIC2NC 0x00000008 /* */ -#define UIC_UIC2C 0x00000004 /* */ -#define UIC_UIC1NC 0x00000002 /* */ -#define UIC_UIC1C 0x00000001 /* */ +#define UICB0_UIC2NCI 0x00000008 /* */ +#define UICB0_UIC2CI 0x00000004 /* */ +#define UICB0_UIC1NCI 0x00000002 /* */ +#define UICB0_UIC1CI 0x00000001 /* */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ + UICB0_UIC1CI | UICB0_UIC2NCI) #define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ #define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ diff --git a/include/ppc440.h b/include/ppc440.h index 907744b872..10517cbb65 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -380,7 +380,8 @@ #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ #endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) /*----------------------------------------------------------------------------+ | SDRAM Controller +----------------------------------------------------------------------------*/ @@ -416,7 +417,8 @@ /*-----------------------------------------------------------------------------+ | Memory Bank 0-7 configuration +-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) @@ -692,6 +694,7 @@ #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 #define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 +#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000 /*-----------------------------------------------------------------------------+ | SDRAM Write Timing Register @@ -1428,6 +1431,11 @@ #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ #define GPT0_COMP6 0x00000098 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP1 0x00000084 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_USB2D0CR 0x0320 @@ -1577,49 +1585,6 @@ #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -/* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ - /* CUST1 Customer Configuration Register1 */ #define SDR0_CUST1 0x4002 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ @@ -1666,25 +1631,34 @@ #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ +#endif /* 440EP || 440GR || 440EPX || 440GRX */ + /*----------------------------------------------------------------------------- - | Internal SRAM + | L2 Cache +----------------------------------------------------------------------------*/ -#define ISRAM0_DCR_BASE 0x380 -#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ -#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ -#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ -#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ -#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ -#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ -#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ -#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ +#if defined (CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define L2_CACHE_BASE 0x030 +#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ +#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ +#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ +#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ +#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ +#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ +#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ +#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ -#else +#endif /* CONFIG_440GX */ /*----------------------------------------------------------------------------- | Internal SRAM +----------------------------------------------------------------------------*/ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define ISRAM0_DCR_BASE 0x380 +#else #define ISRAM0_DCR_BASE 0x020 +#endif #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ @@ -1697,22 +1671,52 @@ #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -/*----------------------------------------------------------------------------- - | L2 Cache - +----------------------------------------------------------------------------*/ -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define L2_CACHE_BASE 0x030 -#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ -#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ -#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ -#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ -#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ -#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ -#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ -#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ -#endif /* CONFIG_440GX */ -#endif /* !CONFIG_440EP !CONFIG_440GR*/ +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ +#endif /*----------------------------------------------------------------------------- | On-Chip Buses @@ -1722,8 +1726,14 @@ /*----------------------------------------------------------------------------- | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CNTRL_DCR_BASE 0x160 +#else #define CNTRL_DCR_BASE 0x0b0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#endif +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ @@ -1751,6 +1761,15 @@ /*----------------------------------------------------------------------------- | Universal interrupt controller +----------------------------------------------------------------------------*/ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + #define UIC0_DCR_BASE 0xc0 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ @@ -1771,7 +1790,9 @@ #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UIC2_DCR_BASE 0xe0 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ @@ -1927,7 +1948,11 @@ /*----------------------------------------------------------------------------- | DMA +----------------------------------------------------------------------------*/ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define DMA_DCR_BASE 0x200 +#else #define DMA_DCR_BASE 0x100 +#endif #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ @@ -1991,15 +2016,16 @@ #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#if defined(CONFIG_440GX) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ -#endif /* CONFIG_440GX */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ #endif /* CONFIG_440GX */ @@ -2112,6 +2138,41 @@ #define UIC_MAL_TXEOB UIC_MTE #define UIC_MAL_RXEOB UIC_MRE +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define UIC_RSVD0 0x80000000 /* N/A - unused */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_IIC1 0x10000000 /* IIC */ +#define UIC_PIM 0x08000000 /* PCI inbound message */ +#define UIC_PCRW 0x04000000 /* PCI command register write */ +#define UIC_PPM 0x02000000 /* PCI power management */ +#define UIC_PCIVPD 0x01000000 /* PCI VPD */ +#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */ +#define UIC_EIR0 0x00400000 /* External interrupt 0 */ +#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */ +#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */ +#define UIC_D0 0x00080000 /* DMA channel 0 */ +#define UIC_D1 0x00040000 /* DMA channel 1 */ +#define UIC_D2 0x00020000 /* DMA channel 2 */ +#define UIC_D3 0x00010000 /* DMA channel 3 */ +#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */ +#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */ +#define UIC_EIR1 0x00002000 /* External interrupt 1 */ +#define UIC_TRNGDA 0x00001000 /* TRNG data available */ +#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */ +#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ +#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ +#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ +#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ +#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ +#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ +#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ +#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ +#define UIC_EIP94 0x00000004 /* Security EIP94 */ +#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ +#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ + #elif !defined(CONFIG_440SPE) #define UIC_U0 0x80000000 /* UART 0 */ #define UIC_U1 0x40000000 /* UART 1 */ @@ -2221,6 +2282,41 @@ #define UIC_ETH1 0x00000002 /* Ethernet 1 */ #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define UIC_EIR2 0x80000000 /* External interrupt 2 */ +#define UIC_U0 0x40000000 /* UART 0 */ +#define UIC_SPI 0x20000000 /* SPI */ +#define UIC_TRNGAL 0x10000000 /* TRNG alarm */ +#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_NDFC 0x02000000 /* NDFC */ +#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */ +#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ +#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */ +#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */ +#define UIC_L2C 0x00100000 /* L2 cache */ +#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ +#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ +#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ +#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ +#define UIC_CT5 0x00004000 /* GPT compare timer 5 */ +#define UIC_CT6 0x00002000 /* GPT compare timer 6 */ +#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */ +#define UIC_EIR3 0x00000800 /* External interrupt 3 */ +#define UIC_EIR4 0x00000400 /* External interrupt 4 */ +#define UIC_DMAE 0x00000200 /* DMA error */ +#define UIC_I2OE 0x00000100 /* I2O error */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ +#define UIC_EIR5 0x00000020 /* External interrupt 5 */ +#define UIC_EIR6 0x00000010 /* External interrupt 6 */ +#define UIC_U2 0x00000008 /* UART 2 */ +#define UIC_U3 0x00000004 /* UART 3 */ +#define UIC_EIR7 0x00000002 /* External interrupt 7 */ +#define UIC_EIR8 0x00000001 /* External interrupt 8 */ + #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define UIC_MS 0x80000000 /* MAL SERR */ @@ -2340,6 +2436,41 @@ #define UIC_RSVD30 0x00000002 /* Reserved */ #define UIC_RSVD31 0x00000001 /* Reserved */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define UIC_TAH0 0x80000000 /* TAHOE 0 */ +#define UIC_TAH1 0x40000000 /* TAHOE 1 */ +#define UIC_EIR9 0x20000000 /* External interrupt 9 */ +#define UIC_MS 0x10000000 /* MAL SERR */ +#define UIC_MTDE 0x08000000 /* MAL TXDE */ +#define UIC_MRDE 0x04000000 /* MAL RXDE */ +#define UIC_MTE 0x02000000 /* MAL TXEOB */ +#define UIC_MRE 0x01000000 /* MAL RXEOB */ +#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */ +#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */ +#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */ +#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */ +#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */ +#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */ +#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */ +#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */ +#define UIC_ETH0 0x00008000 /* Ethernet 0 */ +#define UIC_ETH1 0x00004000 /* Ethernet 1 */ +#define UIC_ETH2 0x00002000 /* Ethernet 2 */ +#define UIC_ETH3 0x00001000 /* Ethernet 3 */ +#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */ +#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */ +#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */ +#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */ +#define UIC_EIR10 0x00000080 /* External interrupt 10 */ +#define UIC_EIR11 0x00000040 /* External interrupt 11 */ +#define UIC_RSVD2 0x00000020 /* Reserved */ +#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */ +#define UIC_OTG 0x00000008 /* USB2.0 OTG */ +#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */ +#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */ +#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */ + #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ #define UIC_EIR5 0x80000000 /* External interrupt 5 */ @@ -2366,18 +2497,38 @@ #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ -#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ - UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) +#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ + UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) + +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ +#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ +#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */ +#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */ +#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */ +#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ + UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */ +#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ +#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ +#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */ +#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ + UICB0_UIC1CI | UICB0_UIC2NCI) + +#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) +#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ +#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI) #endif /* CONFIG_440GX */ /*---------------------------------------------------------------------------+ @@ -3018,6 +3169,201 @@ #define SDR0_MFR 0x4300 #endif /* CONFIG_440SPE */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* Pin Function Control Register 0 (SDR0_PFC0) */ +#define SDR0_PFC0 0x4100 +#define SDR0_PFC0_DBG 0x00008000 /* debug enable */ +#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */ +#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */ +#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */ +#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */ +#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */ +#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */ +#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */ +#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */ +#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */ +#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */ +#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */ +#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */ +#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */ +#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */ +#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */ + +/* Pin Function Control Register 1 (SDR0_PFC1) */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ + +/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ +#define SDR0_ETH_PLL 0x4102 +#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ +#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */ +#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */ +#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */ +#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */ +#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16) +#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */ +#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8) +#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */ +#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4) +#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */ +#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f) + +/* Ethernet Configuration Register (SDR0_ETH_CFG) */ +#define SDR0_ETH_CFG 0x4103 +#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */ +#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */ +#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */ +#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */ +#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */ +#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */ +#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */ +#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */ +#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */ +#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */ +#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */ +#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */ +#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */ +#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */ +#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */ +#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */ +#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */ +#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */ +#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */ +#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */ +#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */ +#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */ +#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */ +#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */ + +#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4 +#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00 +#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01 +#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 +#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 + +/* Miscealleneaous Function Reg. (SDR0_MFR) */ +#define SDR0_MFR 0x4300 +#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */ +#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */ +#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */ +#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */ +#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */ +#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */ +#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */ +#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */ +#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */ +#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */ +#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */ +#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */ +#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */ +#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */ +#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */ +#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */ +#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */ +#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */ +#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */ +#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */ + +/* EMACx TX Status Register (SDR0_EMACxTXST)*/ +#define SDR0_EMAC0TXST 0x4400 +#define SDR0_EMAC1TXST 0x4401 +#define SDR0_EMAC2TXST 0x4402 +#define SDR0_EMAC3TXST 0x4403 + +#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ +#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ +#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ +#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ +#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ +#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */ +#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ +#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ +#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ +#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ +#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ +#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ +#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ +#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ +#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ +#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ +#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ +#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ +#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ +#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ +#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ +#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ +#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ +#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ + +/* EMACx RX Status Register (SDR0_EMACxRXST)*/ +#define SDR0_EMAC0RXST 0x4404 +#define SDR0_EMAC1RXST 0x4405 +#define SDR0_EMAC2RXST 0x4406 +#define SDR0_EMAC3RXST 0x4407 + +#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */ +#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */ +#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */ +#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */ +#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */ +#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23) +#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */ +#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */ +#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */ +#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */ +#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/ +#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/ +#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */ +#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */ +#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */ +#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */ +#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */ +#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */ +#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */ +#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */ +#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */ +#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */ +#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */ +#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */ +#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */ +#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */ +#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ +#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */ + +/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/ +#define SDR0_EMAC0REJCNT 0x4408 +#define SDR0_EMAC1REJCNT 0x4409 +#define SDR0_EMAC2REJCNT 0x440A +#define SDR0_EMAC3REJCNT 0x440B + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DPLLRST 0x80000000 +#define SDR0_DDR0_DDRM_MASK 0x60000000 +#define SDR0_DDR0_DDRM_DDR1 0x20000000 +#define SDR0_DDR0_DDRM_DDR2 0x40000000 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) + +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#endif /* CONFIG_460EX || CONFIG_460GT */ #define SDR0_SDCS_SDD (0x80000000 >> 31) @@ -3232,6 +3578,73 @@ #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define SDR0_SRST0 0x0200 +#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */ +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ +#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ +#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ +#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ +#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ +#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ +#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ +#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */ +#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ + +#define SDR0_SRST1 0x201 +#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ +#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ +#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ +#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ +#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ +#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */ +#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */ +#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */ +#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */ +#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ +#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ +#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ +#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ +#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */ +#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ +#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ +#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ +#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ +#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ +#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ +#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ +#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ +#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ +#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ +#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ +#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ +#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ +#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ +#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ + +#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */ + #else #define SDR0_SRST_BGO 0x80000000 @@ -3270,7 +3683,15 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if !defined (CONFIG_440GX) && \ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ +#elif !defined (CONFIG_440GX) && \ !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) @@ -3624,7 +4045,8 @@ #endif /* CONFIG_440GP */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 317604ae0a..02084546b2 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -131,7 +131,7 @@ typedef struct emac_4xx_hw_st { } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST; -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_460GT) #define EMAC_NUM_DEV 4 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ @@ -155,7 +155,8 @@ typedef struct emac_4xx_hw_st { /* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) #else #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) @@ -164,9 +165,6 @@ typedef struct emac_4xx_hw_st { #define ZMII_SSR (ZMII_BASE + 4) #define ZMII_SMIISR (ZMII_BASE + 8) -#define ZMII_RMII 0x22000000 -#define ZMII_MDI0 0x80000000 - /* ZMII FER Register Bit Definitions */ #define ZMII_FER_DIS (0x0) #define ZMII_FER_MDI (0x8) @@ -205,6 +203,8 @@ typedef struct emac_4xx_hw_st { /* RGMII Register Addresses */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1500) #elif defined(CONFIG_405EX) #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00) #else @@ -223,19 +223,21 @@ typedef struct emac_4xx_hw_st { #define RGMII_FER_V(__x) ((__x - 2) * 4) +#define RGMII_FER_MDIO(__x) (1 << (19 - (__x))) + /* RGMII Speed Selection Register Bit Definitions */ #define RGMII_SSR_SP_10MBPS (0x00) #define RGMII_SSR_SP_100MBPS (0x02) #define RGMII_SSR_SP_1000MBPS (0x04) #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) #define RGMII_SSR_V(__x) ((__x) * 8) #else #define RGMII_SSR_V(__x) ((__x -2) * 8) #endif - /*---------------------------------------------------------------------------+ | TCP/IP Acceleration Hardware (TAH) 440GX Only +---------------------------------------------------------------------------*/ @@ -304,7 +306,8 @@ typedef struct emac_4xx_hw_st { /* Ethernet MAC Regsiter Addresses */ #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) #else #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) @@ -345,6 +348,7 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) diff --git a/include/rtc.h b/include/rtc.h index 15f3571d76..2995144a0d 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -52,7 +52,7 @@ struct rtc_time { int tm_isdst; }; -void rtc_get (struct rtc_time *); +int rtc_get (struct rtc_time *); void rtc_set (struct rtc_time *); void rtc_reset (void); diff --git a/include/vsc7385.h b/include/vsc7385.h new file mode 100644 index 0000000000..0432499581 --- /dev/null +++ b/include/vsc7385.h @@ -0,0 +1,13 @@ +/* + * Header file for vsc7385.c + * + * Author: Timur Tabi <timur@freescale.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed + * under the terms of the GNU General Public License version 2. This + * program is licensed "as is" without any warranty of any kind, whether + * express or implied. + */ + +int vsc7385_upload_firmware(void *firmware, unsigned int size); + diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 86a3b67c98..2a5a2fce45 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -116,6 +116,7 @@ static int display_banner(void) { sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING); printf("%s\n", version_string); + printf("CPU: ADSP " MK_STR(CONFIG_BFIN_CPU) " (Detected Rev: 0.%d)\n", bfin_revid()); return (0); } @@ -404,7 +405,7 @@ void board_init_r(gd_t * id, ulong dest_addr) misc_init_r(); #endif -#if ((BFIN_CPU == ADSP_BF537) || (BFIN_CPU == ADSP_BF536)) +#ifdef CONFIG_CMD_NET printf("Net: "); eth_initialize(bd); #endif diff --git a/lib_blackfin/memcmp.S b/lib_blackfin/memcmp.S index 9b58832943..6c834a7e85 100644 --- a/lib_blackfin/memcmp.S +++ b/lib_blackfin/memcmp.S @@ -31,6 +31,7 @@ */ .globl _memcmp; +.type _memcmp, STT_FUNC; _memcmp: I1 = P3; P0 = R0; /* P0 = s1 address */ @@ -98,3 +99,5 @@ _memcmp: R0 = 0; P3 = I1; RTS; + +.size _memcmp, .-_memcmp diff --git a/lib_blackfin/memcpy.S b/lib_blackfin/memcpy.S index 24577bebdc..e6b359a344 100644 --- a/lib_blackfin/memcpy.S +++ b/lib_blackfin/memcpy.S @@ -23,6 +23,7 @@ .align 2 .globl _memcpy_ASM; +.type _memcpy_ASM, STT_FUNC; _memcpy_ASM: CC = R2 <= 0; /* length not positive?*/ IF CC JUMP .L_P1L2147483647; /* Nothing to do */ @@ -112,3 +113,5 @@ _memcpy_ASM: B[P0--] = R1; RTS; + +.size _memcpy_ASM, .-_memcpy_ASM diff --git a/lib_blackfin/memmove.S b/lib_blackfin/memmove.S index 46f79ed18d..e385c4f6f5 100644 --- a/lib_blackfin/memmove.S +++ b/lib_blackfin/memmove.S @@ -31,6 +31,7 @@ */ .globl _memmove; +.type _memmove, STT_FUNC; _memmove: I1 = P3; P0 = R0; /* P0 = To address */ @@ -91,3 +92,5 @@ _memmove: .Lno_loop: B[P0] = R1; P3 = I1; RTS; + +.size _memmove, .-_memmove diff --git a/lib_blackfin/memset.S b/lib_blackfin/memset.S index c33c551121..26f63cdc94 100644 --- a/lib_blackfin/memset.S +++ b/lib_blackfin/memset.S @@ -31,6 +31,7 @@ */ .globl _memset; +.type _memset, STT_FUNC; _memset: P0 = R0 ; /* P0 = address */ P2 = R2 ; /* P2 = count */ @@ -91,3 +92,5 @@ _memset: B[P0++] = R1; B[P0++] = R1; JUMP .Laligned; + +.size _memset, .-_memset diff --git a/lib_ppc/board.c b/lib_ppc/board.c index fbf1c5d25a..3ab22f809e 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -433,13 +433,26 @@ void board_init_f (ulong bootflag) */ len = (ulong)&_end - CFG_MONITOR_BASE; +#ifndef CONFIG_MAX_MEM_MAPPED +#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#endif + +#ifndef CONFIG_VERY_BIG_RAM addr = CFG_SDRAM_BASE + get_effective_memsize(); +#else + /* only allow stack below 256M */ + addr = CFG_SDRAM_BASE + + (gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : get_effective_memsize(); +#endif #ifdef CONFIG_LOGBUFFER +#ifndef CONFIG_ALT_LB_ADDR /* reserve kernel log buffer */ addr -= (LOGBUFF_RESERVE); debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); #endif +#endif #ifdef CONFIG_PRAM /* @@ -1126,9 +1139,11 @@ void board_init_r (gd_t *id, ulong dest_addr) pram=0; #endif #ifdef CONFIG_LOGBUFFER +#ifndef CONFIG_ALT_LB_ADDR /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; #endif +#endif sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); setenv ("mem", (char *)memsz); } diff --git a/libfdt/fdt.c b/libfdt/fdt.c index 660e2c1baf..cfa1989d8e 100644 --- a/libfdt/fdt.c +++ b/libfdt/fdt.c @@ -188,10 +188,7 @@ const char *_fdt_find_string(const char *strtab, int tabsize, const char *s) int fdt_move(const void *fdt, void *buf, int bufsize) { - int err = fdt_check_header(fdt); - - if (err) - return err; + CHECK_HEADER(fdt); if (fdt_totalsize(fdt) > bufsize) return -FDT_ERR_NOSPACE; diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index 031a15f471..11d80d2fa2 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -59,13 +59,6 @@ #include "libfdt_internal.h" -#define CHECK_HEADER(fdt) \ - { \ - int err; \ - if ((err = fdt_check_header(fdt)) != 0) \ - return err; \ - } - static int nodename_eq(const void *fdt, int offset, const char *s, int len) { @@ -464,20 +457,10 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset, int fdt_node_offset_by_compatible(const void *fdt, int startoffset, const char *compatible) { - uint32_t tag; - int offset, nextoffset; - int err; + int offset, err; CHECK_HEADER(fdt); - if (startoffset >= 0) { - tag = fdt_next_tag(fdt, startoffset, &nextoffset); - if (tag != FDT_BEGIN_NODE) - return -FDT_ERR_BADOFFSET; - } else { - nextoffset = 0; - } - /* FIXME: The algorithm here is pretty horrible: we scan each * property of a node in fdt_node_check_compatible(), then if * that didn't find what we want, we scan over them again diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index 2fb81dd398..8609fa7d76 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -73,10 +73,8 @@ static int _blocks_misordered(const void *fdt, static int rw_check_header(void *fdt) { - int err; + CHECK_HEADER(fdt); - if ((err = fdt_check_header(fdt))) - return err; if (fdt_version(fdt) < 17) return -FDT_ERR_BADVERSION; if (_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry), @@ -256,6 +254,30 @@ static int _add_property(void *fdt, int nodeoffset, const char *name, int len, return 0; } +int fdt_set_name(void *fdt, int nodeoffset, const char *name) +{ + char *namep; + int oldlen, newlen; + int err; + + if ((err = rw_check_header(fdt))) + return err; + + namep = (char *)fdt_get_name(fdt, nodeoffset, &oldlen); + if (!namep) + return oldlen; + + newlen = strlen(name); + + err = _blob_splice_struct(fdt, namep, ALIGN(oldlen+1, FDT_TAGSIZE), + ALIGN(newlen+1, FDT_TAGSIZE)); + if (err) + return err; + + memcpy(namep, name, newlen+1); + return 0; +} + int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len) { @@ -313,7 +335,7 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, do { offset = nextoffset; tag = fdt_next_tag(fdt, offset, &nextoffset); - } while (tag == FDT_PROP); + } while ((tag == FDT_PROP) || (tag == FDT_NOP)); nh = _fdt_offset_ptr_w(fdt, offset); nodelen = sizeof(*nh) + ALIGN(namelen+1, FDT_TAGSIZE) + FDT_TAGSIZE; @@ -379,9 +401,7 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) int newsize; void *tmp; - err = fdt_check_header(fdt); - if (err) - return err; + CHECK_HEADER(fdt); mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) * sizeof(struct fdt_reserve_entry); diff --git a/libfdt/libfdt_internal.h b/libfdt/libfdt_internal.h index 1e60936beb..52e1b8d810 100644 --- a/libfdt/libfdt_internal.h +++ b/libfdt/libfdt_internal.h @@ -58,6 +58,13 @@ #define memeq(p, q, n) (memcmp((p), (q), (n)) == 0) #define streq(p, q) (strcmp((p), (q)) == 0) +#define CHECK_HEADER(fdt) \ + { \ + int err; \ + if ((err = fdt_check_header(fdt)) != 0) \ + return err; \ + } + uint32_t _fdt_next_tag(const void *fdt, int startoffset, int *nextoffset); const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); int _fdt_node_end_offset(void *fdt, int nodeoffset); diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile new file mode 100644 index 0000000000..1ec1112309 --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -0,0 +1,105 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS := start.o +SOBJS += init.o resetvec.o +SOBJS += resetvec.o +COBJS := ddr2_fixed.o +COBJS += nand_boot.o +COBJS += nand_ecc.o +COBJS += ndfc.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)ndfc.c: + @rm -f $(obj)ndfc.c + ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + +# from board directory +$(obj)init.S: + @rm -f $(obj)init.S + ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S + +# from nand_spl directory +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + +# from drivers/mtd/nand directory +$(obj)nand_ecc.c: + @rm -f $(obj)nand_ecc.c + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk new file mode 100644 index 0000000000..6dad876ae5 --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/config.mk @@ -0,0 +1,49 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 460EX Reference Platform (Canyonlands) board +# + +# +# TEXT_BASE for SPL: +# +# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, +# in the last 4kBytes of memory space in cache. +# We will copy this SPL into internal SRAM in start.S. So we set +# TEXT_BASE to starting address in internal SRAM here. +# +TEXT_BASE = 0xE3003000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +PAD_TO = 0xE3007000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c new file mode 100644 index 0000000000..48708a8eeb --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/io.h> +#include <asm/processor.h> + +static void wait_init_complete(void) +{ + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while (!(val & 0x80000000)); +} + +long int initdram(int board_type) +{ + /* + * Reset the DDR-SDRAM controller. + */ + mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, 0x00000000); + + /* + * These values are cloned from a running NOR booting + * Canyonlands with SPD-DDR2 detection and calibration + * enabled. This will only work for the same memory + * configuration as used here: + * + * Crucial CT3264AC53E.4FD - 256MB SO-DIMM + * + */ + mtsdram(SDRAM_MCOPT2, 0x00000000); + mtsdram(SDRAM_MCOPT1, 0x05122000); + mtsdram(SDRAM_MODT0, 0x01000000); + mtsdram(SDRAM_CODT, 0x00800021); + mtsdram(SDRAM_WRDTR, 0x82000823); + mtsdram(SDRAM_CLKTR, 0x40000000); + mtsdram(SDRAM_MB0CF, 0x00000201); + mtsdram(SDRAM_RTR, 0x06180000); + mtsdram(SDRAM_SDTR1, 0x80201000); + mtsdram(SDRAM_SDTR2, 0x42103243); + mtsdram(SDRAM_SDTR3, 0x0A0D0D16); + mtsdram(SDRAM_MMODE, 0x00000632); + mtsdram(SDRAM_MEMODE, 0x00000040); + mtsdram(SDRAM_INITPLR0, 0xB5380000); + mtsdram(SDRAM_INITPLR1, 0x82100400); + mtsdram(SDRAM_INITPLR2, 0x80820000); + mtsdram(SDRAM_INITPLR3, 0x80830000); + mtsdram(SDRAM_INITPLR4, 0x80810040); + mtsdram(SDRAM_INITPLR5, 0x80800532); + mtsdram(SDRAM_INITPLR6, 0x82100400); + mtsdram(SDRAM_INITPLR7, 0x8A080000); + mtsdram(SDRAM_INITPLR8, 0x8A080000); + mtsdram(SDRAM_INITPLR9, 0x8A080000); + mtsdram(SDRAM_INITPLR10, 0x8A080000); + mtsdram(SDRAM_INITPLR11, 0x80000432); + mtsdram(SDRAM_INITPLR12, 0x808103C0); + mtsdram(SDRAM_INITPLR13, 0x80810040); + mtsdram(SDRAM_INITPLR14, 0x00000000); + mtsdram(SDRAM_INITPLR15, 0x00000000); + + mtsdram(SDRAM_MCOPT2, 0x28000000); + + wait_init_complete(); + + mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ + + mtsdram(SDRAM_RDCC, 0x40000000); + mtsdram(SDRAM_RQDC, 0x80000038); + mtsdram(SDRAM_RFDC, 0x00000257); + + return CFG_MBYTES_SDRAM << 20; +} diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds new file mode 100644 index 0000000000..5bffb5b30b --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .resetvec 0xE3003FFC : + { + *(.resetvec) + } = 0xffff + + .text : + { + start.o (.text) + init.o (.text) + nand_boot.o (.text) + ddr2_fixed.o (.text) + ndfc.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + __got2_start = .; + *(.got2) + __got2_end = .; + } + + _edata = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile index 66a0959ee2..f10ed02292 100644 --- a/onenand_ipl/board/apollon/Makefile +++ b/onenand_ipl/board/apollon/Makefile @@ -9,7 +9,7 @@ AFLAGS += -DCONFIG_ONENAND_IPL CFLAGS += -DCONFIG_ONENAND_IPL OBJCLFAGS += --gap-fill=0x00 -SOBJS = start.o low_levelinit.o # _memcpy32.o +SOBJS = start.o low_levelinit.o COBJS = apollon.o onenand_read.o onenand_boot.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -19,13 +19,16 @@ LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) onenandobj := $(OBJTREE)/onenand_ipl/ -ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin +ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin all: $(obj).depend $(ALL) $(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@ +$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@ + $(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ diff --git a/onenand_ipl/onenand_boot.c b/onenand_ipl/onenand_boot.c index f30deaeca7..35668ac84f 100644 --- a/onenand_ipl/onenand_boot.c +++ b/onenand_ipl/onenand_boot.c @@ -60,7 +60,7 @@ void start_oneboot(void) buf = (uchar *) CFG_LOAD_ADDR; - if (!onenand_read_block(buf, ONENAND_START_BLOCK)) + if (!onenand_read_block0(buf)) buf += ONENAND_BLOCK_SIZE; if (buf == (uchar *)CFG_LOAD_ADDR) diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h index b9c6669a7b..9188b96625 100644 --- a/onenand_ipl/onenand_ipl.h +++ b/onenand_ipl/onenand_ipl.h @@ -23,7 +23,6 @@ #include <linux/mtd/onenand_regs.h> -#define ONENAND_START_BLOCK 0 #define ONENAND_BLOCK_SIZE 2048 #ifndef CFG_PRINTF @@ -40,5 +39,5 @@ #define ONENAND_PAGE_SIZE 2048 -extern int onenand_read_block(unsigned char *buf, ulong block); +extern int onenand_read_block0(unsigned char *buf); #endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c index f553220237..669b1ef5fa 100644 --- a/onenand_ipl/onenand_read.c +++ b/onenand_ipl/onenand_read.c @@ -33,8 +33,13 @@ #define onenand_buffer_address() ((1 << 3) << 8) #define onenand_bufferram_address(block) (0) +#ifdef __HAVE_ARCH_MEMCPY32 +extern void *memcpy32(void *dest, void *src, int size); +#endif + /* read a page with ECC */ -static inline int onenand_read_page(ulong block, ulong page, u_char *buf) +static inline int onenand_read_page(ulong block, ulong page, + u_char * buf, int pagesize) { unsigned long *base; @@ -46,15 +51,15 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) onenand_writew(onenand_block_address(block), THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + onenand_writew(onenand_bufferram_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + onenand_writew(onenand_sector_address(page), THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); onenand_writew(onenand_buffer_address(), THIS_ONENAND(ONENAND_REG_START_BUFFER)); - onenand_writew(onenand_bufferram_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); - onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); @@ -69,9 +74,9 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) #ifdef __HAVE_ARCH_MEMCPY32 /* 32 bytes boundary memory copy */ - memcpy32(buf, base, ONENAND_PAGE_SIZE); + memcpy32(buf, base, pagesize); #else - for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { + for (offset = 0; offset < (pagesize >> 2); offset++) { value = *(base + offset); *p++ = value; } @@ -87,18 +92,22 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) * onenand_read_block - Read a block data to buf * @return 0 on success */ -int onenand_read_block(unsigned char *buf, ulong block) +int onenand_read_block0(unsigned char *buf) { int page, offset = 0; + int pagesize = ONENAND_PAGE_SIZE; + + /* MLC OneNAND has 4KiB page size */ + if (onenand_readw(THIS_ONENAND(ONENAND_REG_TECHNOLOGY))) + pagesize <<= 1; /* NOTE: you must read page from page 1 of block 0 */ /* read the block page by page*/ for (page = ONENAND_START_PAGE; page < ONENAND_PAGES_PER_BLOCK; page++) { - onenand_read_page(block, page, buf + offset); - - offset += ONENAND_PAGE_SIZE; + onenand_read_page(0, page, buf + offset, pagesize); + offset += pagesize; } return 0; diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile new file mode 100644 index 0000000000..5a92d1ce73 --- /dev/null +++ b/post/board/lwmon5/Makefile @@ -0,0 +1,28 @@ +# +# (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com +# +# Developed for DENX Software Engineering GmbH +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +LIB = libpostlwmon5.a + +COBJS = sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c new file mode 100644 index 0000000000..1946f09d6b --- /dev/null +++ b/post/board/lwmon5/dsp.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_POST + +#include <post.h> + + +#if CONFIG_POST & CFG_POST_DSP +#include <asm/io.h> + +/* This test verifies DSP status bits in FPGA */ + +DECLARE_GLOBAL_DATA_PTR; + +#define DSP_STATUS_REG 0xC4000008 + +int dsp_post_test(int flags) +{ + uint read_value; + int ret; + + ret = 0; + read_value = in_be32((void *)DSP_STATUS_REG) & 0x3; + if (read_value != 0x3) { + post_log("\nDSP status read %08X\n", read_value); + ret = 1; + } + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_DSP */ +#endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c new file mode 100644 index 0000000000..fcbbc6031c --- /dev/null +++ b/post/board/lwmon5/dspic.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_POST + +/* There are two tests for dsPIC currently implemented: + * 1. dsPIC ready test. Done in board_early_init_f(). Only result verified here. + * 2. dsPIC POST result test. This test gets dsPIC POST codes and version. + */ + +#include <post.h> + +#include <i2c.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DSPIC_POST_ERROR_REG 0x800 +#define DSPIC_SYS_ERROR_REG 0x802 +#define DSPIC_VERSION_REG 0x804 + +#if CONFIG_POST & CFG_POST_BSPEC1 + +/* Verify that dsPIC ready test done early at hw init passed ok */ +int dspic_init_post_test(int flags) +{ + if (in_be32((void *)CFG_DSPIC_TEST_ADDR) & CFG_DSPIC_TEST_MASK) { + post_log("dsPIC init test failed\n"); + return 1; + } + + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_BSPEC1 */ + +#if CONFIG_POST & CFG_POST_BSPEC2 +/* Read a register from the dsPIC. */ +int dspic_read(ushort reg, ushort *data) +{ + uchar buf[sizeof(*data)]; + int rval; + + rval = i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, sizeof(reg), + buf, sizeof(*data)); + + *data = (buf[0] << 8) | buf[1]; + + return rval; +} + +/* Verify error codes regs, display version */ +int dspic_post_test(int flags) +{ + ushort data; + int ret = 0; + + post_log("\n"); + if (dspic_read(DSPIC_VERSION_REG, &data)) { + post_log("dsPIC : failed read version\n"); + ret = 1; + } else { + post_log("dsPIC version: %u.%u\n", + (data >> 8) & 0xFF, data & 0xFF); + } + + if (dspic_read(DSPIC_POST_ERROR_REG, &data)) { + post_log("dsPIC : failed read POST code\n"); + } else { + post_log("dsPIC POST code 0x%04X\n", data); + } + if (data != 0) + ret = 1; + + if (dspic_read(DSPIC_SYS_ERROR_REG, &data)) { + post_log("dsPIC : failed read system error\n"); + ret = 1; + } else if (data != 0) { + post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); + ret = 1; + } + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_BSPEC2 */ +#endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c new file mode 100644 index 0000000000..2d95b5e50a --- /dev/null +++ b/post/board/lwmon5/fpga.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#ifdef CONFIG_POST + +/* This test performs testing of FPGA SCRATCH register, + * gets FPGA version and run get_ram_size() on FPGA memory + */ + +#include <post.h> + +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define FPGA_SCRATCH_REG 0xC4000050 +#define FPGA_VERSION_REG 0xC4000040 +#define FPGA_RAM_START 0xC4200000 +#define FPGA_RAM_END 0xC4203FFF +#define FPGA_STAT 0xC400000C + +#if CONFIG_POST & CFG_POST_BSPEC3 + +static int one_scratch_test(uint value) +{ + uint read_value; + int ret = 0; + + out_be32((void *)FPGA_SCRATCH_REG, value); + /* read other location (protect against data lines capacity) */ + ret = in_be16((void *)FPGA_VERSION_REG); + /* verify test pattern */ + read_value = in_be32((void *)FPGA_SCRATCH_REG); + if (read_value != value) { + post_log("FPGA SCRATCH test failed write %08X, read %08X\n", + value, read_value); + ret = 1; + } + + return ret; +} + +/* Verify FPGA, get version & memory size */ +int fpga_post_test(int flags) +{ + uint old_value; + ushort version; + uint read_value; + int ret = 0; + + post_log("\n"); + old_value = in_be32((void *)FPGA_SCRATCH_REG); + + if (one_scratch_test(0x55555555)) + ret = 1; + if (one_scratch_test(0xAAAAAAAA)) + ret = 1; + + out_be32((void *)FPGA_SCRATCH_REG, old_value); + + version = in_be16((void *)FPGA_VERSION_REG); + post_log("FPGA : version %u.%u\n", + (version >> 8) & 0xFF, version & 0xFF); + + /* Enable write to FPGA RAM */ + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000); + + read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000); + post_log("FPGA RAM size: %d bytes\n", read_value); + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_BSPEC3 */ +#endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c new file mode 100644 index 0000000000..4af6a7a6e5 --- /dev/null +++ b/post/board/lwmon5/gdc.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#ifdef CONFIG_POST + +/* This test attempts to verify board GDC. A scratch register tested, then + * simple memory test (get_ram_size()) run over GDC memory. + */ + +#include <post.h> + +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GDC_SCRATCH_REG 0xC1FF8044 +#define GDC_VERSION_REG 0xC1FF8084 +#define GDC_RAM_START 0xC0000000 +#define GDC_RAM_END 0xC2000000 + +#if CONFIG_POST & CFG_POST_BSPEC4 + +static int gdc_test_reg_one(uint value) +{ + int ret; + uint read_value; + + /* write test pattern */ + out_be32((void *)GDC_SCRATCH_REG, value); + /* read other location (protect against data lines capacity) */ + ret = in_be32((void *)GDC_RAM_START); + /* verify test pattern */ + read_value = in_be32((void *)GDC_SCRATCH_REG); + if (read_value != value) { + post_log("GDC SCRATCH test failed write %08X, read %08X\n", + value, read_value); + } + + return (read_value != value); +} + +/* Verify GDC, get memory size */ +int gdc_post_test(int flags) +{ + uint old_value; + int ret = 0; + + post_log("\n"); + old_value = in_be32((void *)GDC_SCRATCH_REG); + + /* + * GPIOC2 register behaviour: the LIME graphics processor has a + * maximum of 5 GPIO ports that can be used in this hardware + * configuration. Thus only the bits for these 5 GPIOs can be + * activated in the GPIOC2 register. All other bits will always be + * read as zero. + */ + if (gdc_test_reg_one(0x00150015)) + ret = 1; + if (gdc_test_reg_one(0x000A000A)) + ret = 1; + + out_be32((void *)GDC_SCRATCH_REG, old_value); + + old_value = in_be32((void *)GDC_VERSION_REG); + post_log("GDC chip version %u.%u, year %04X\n", + (old_value >> 8) & 0xFF, old_value & 0xFF, + (old_value >> 16) & 0xFFFF); + + old_value = get_ram_size((void *)GDC_RAM_START, + GDC_RAM_END - GDC_RAM_START); + post_log("GDC RAM size: %d bytes\n", old_value); + + return ret; +} +#endif /* CONFIG_POST & CFG_POST_BSPEC4 */ +#endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c new file mode 100644 index 0000000000..0cf1cf2a24 --- /dev/null +++ b/post/board/lwmon5/sysmon.c @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <post.h> +#include <common.h> + +#ifdef CONFIG_POST + +/* + * SYSMON test + * + * This test performs the system hardware monitoring. + * The test passes when all the following voltages and temperatures + * are within allowed ranges: + * + * Temperature -40 .. +85 C + * +5V +4.75 .. +5.25 V + * +5V standby +4.75 .. +5.25 V + * + * LCD backlight is not enabled if temperature values are not within + * allowed ranges (-30 .. + 80). The brightness of backlite can be + * controlled by setting "brightness" enviroment variable. Default value is 50% + * + * See the list of all parameters in the sysmon_table below + */ + +#include <post.h> +#include <watchdog.h> +#include <i2c.h> + +#if defined(CONFIG_VIDEO) +#include <mb862xx.h> +#endif + +#if CONFIG_POST & CFG_POST_SYSMON + +DECLARE_GLOBAL_DATA_PTR; + +/* from dspic.c */ +extern int dspic_read(ushort reg, ushort *data); + +#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) + +typedef struct sysmon_s sysmon_t; +typedef struct sysmon_table_s sysmon_table_t; + +static void sysmon_dspic_init (sysmon_t * this); +static int sysmon_dspic_read (sysmon_t * this, uint addr); +static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr); +static void sysmon_backlight_disable (sysmon_table_t * this); + +struct sysmon_s +{ + uchar chip; + void (*init)(sysmon_t *); + int (*read)(sysmon_t *, uint); +}; + +static sysmon_t sysmon_dspic = + {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read}; + +static sysmon_t sysmon_dspic_sgn = + {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read_sgn}; + +static sysmon_t * sysmon_list[] = +{ + &sysmon_dspic, + &sysmon_dspic_sgn, + NULL +}; + +struct sysmon_table_s +{ + char * name; + char * unit_name; + sysmon_t * sysmon; + void (*exec_before)(sysmon_table_t *); + void (*exec_after)(sysmon_table_t *); + + int unit_precision; + int unit_div; + int unit_min; + int unit_max; + uint val_mask; + uint val_min; + uint val_max; + int val_valid; + uint val_min_alt; + uint val_max_alt; + int val_valid_alt; + uint addr; +}; + +static sysmon_table_t sysmon_table[] = +{ + {"Temperature", " C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0, + 0x8000-30, 0x8000+80, 0, 0x12BC}, + + {"+ 5 V", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0, + 4750, 5250, 0, 0x12CA}, + + {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0, + 4750, 5250, 0, 0x12C6}, +}; +static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); + +int sysmon_init_f (void) +{ + sysmon_t ** l; + + for (l = sysmon_list; *l; l++) + (*l)->init(*l); + + return 0; +} + +void sysmon_reloc (void) +{ + sysmon_t ** l; + sysmon_table_t * t; + + for (l = sysmon_list; *l; l++) { + RELOC(*l); + RELOC((*l)->init); + RELOC((*l)->read); + } + + for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + RELOC(t->exec_before); + RELOC(t->exec_after); + RELOC(t->sysmon); + } +} + +static char *sysmon_unit_value (sysmon_table_t *s, uint val) +{ + static char buf[32]; + char *p, sign; + int decimal, frac; + int unit_val = + s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; + + if (val == -1) + return "I/O ERROR"; + + if (unit_val < 0) { + sign = '-'; + unit_val = -unit_val; + } else + sign = '+'; + + p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); + + + frac = unit_val % s->unit_div; + + frac /= (s->unit_div / s->unit_precision); + + decimal = s->unit_precision; + + if (decimal != 1) + *p++ = '.'; + for (decimal /= 10; decimal != 0; decimal /= 10) + *p++ = '0' + (frac / decimal) % 10; + strcpy(p, s->unit_name); + + return buf; +} + +static void sysmon_dspic_init (sysmon_t * this) +{ +} + +static int sysmon_dspic_read (sysmon_t * this, uint addr) +{ + ushort data; + + return (dspic_read(addr, &data)) ? -1 : data; +} + +static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr) +{ + ushort data; + + /* To fit into the table range we should add 0x8000 */ + return (dspic_read(addr, &data)) ? -1 : + (signed short)data + 0x8000; +} + +static void sysmon_backlight_disable (sysmon_table_t * this) +{ +#if defined(CONFIG_VIDEO) + board_backlight_switch(this->val_valid_alt); +#endif +} + +int sysmon_post_test (int flags) +{ + int res = 0; + sysmon_table_t * t; + int val; + + for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + if (t->exec_before) + t->exec_before(t); + + val = t->sysmon->read(t->sysmon, t->addr); + if (val != -1) { + t->val_valid = val >= t->val_min && val <= t->val_max; + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; + } else { + t->val_valid = 0; + t->val_valid_alt = 0; + } + + if (t->exec_after) + t->exec_after(t); + + if ((!t->val_valid) || (flags & POST_MANUAL)) { + printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); + printf("allowed range"); + printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); + printf(" %-8s", sysmon_unit_value(t, t->val_max)); + printf(" %s\n", t->val_valid ? "OK" : "FAIL"); + } + + if (!t->val_valid) + res = 1; + } + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_SYSMON */ +#endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c new file mode 100644 index 0000000000..48ff687460 --- /dev/null +++ b/post/board/lwmon5/watchdog.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * This test verifies if the reason of last reset was an abnormal voltage + * condition, than it performs watchdog test, measuing time required to + * trigger watchdog reset. + */ + +#ifdef CONFIG_POST + +#include <post.h> + +#if CONFIG_POST & CFG_POST_WATCHDOG + +#include <watchdog.h> +#include <asm/gpio.h> +#include <asm/io.h> + +static uint watchdog_magic_read(void) +{ + return in_be32((void *)CFG_WATCHDOG_FLAGS_ADDR) & + CFG_WATCHDOG_MAGIC_MASK; +} + +static void watchdog_magic_write(uint value) +{ + out_be32((void *)CFG_WATCHDOG_FLAGS_ADDR, value | + (in_be32((void *)CFG_WATCHDOG_FLAGS_ADDR) & + ~CFG_WATCHDOG_MAGIC_MASK)); +} + +int sysmon1_post_test(int flags) +{ + if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) { + /* + * 3.1. GPIO62 is low + * Assuming system voltage failure. + */ + post_log("Abnormal voltage detected (GPIO62)\n"); + return 1; + } + + return 0; +} + +int lwmon5_watchdog_post_test(int flags) +{ + ulong time; + + /* On each reset scratch register 1 should be tested, + * but first test GPIO62: + */ + if (!(flags & POST_MANUAL) && sysmon1_post_test(flags)) { + /* + * 3.1. GPIO62 is low + * Assuming system voltage failure. + */ + /* 3.1.1. Set scratch register 1 to 0x0000xxxx */ + watchdog_magic_write(0); + /* 3.1.2. Mark test as failed due to voltage?! */ + return 1; + } + + if (watchdog_magic_read() != CFG_WATCHDOG_MAGIC) { + /* + * 3.2. Scratch register 1 differs from magic value 0x1248xxxx + * Assuming PowerOn + */ + int ints; + ulong base; + + /* 3.2.1. Set magic value to scratch register */ + watchdog_magic_write(CFG_WATCHDOG_MAGIC); + + ints = disable_interrupts (); + /* 3.2.2. strobe watchdog once */ + WATCHDOG_RESET(); + out_be32((void *)CFG_WATCHDOG_TIME_ADDR, 0); + /* 3.2.3. save time of strobe in scratch register 2 */ + base = post_time_ms (0); + + /* 3.2.4. Wait for 150 ms (enough for reset to happen) */ + while ((time = post_time_ms (base)) < 150) + out_be32((void *)CFG_WATCHDOG_TIME_ADDR, time); + if (ints) + enable_interrupts (); + + /* + * 3.2.5. Reset didn't happen. - Set 0x0000xxxx + * into scratch register 1 + */ + watchdog_magic_write(0); + /* 3.2.6. Mark test as failed. */ + post_log("hw watchdog time : %u ms, failed ", time); + return 2; + } + + /* + * 3.3. Scratch register matches magic value 0x1248xxxx + * Assume this is watchdog-initiated reset + */ + /* 3.3.1. So, the test succeed, save measured time to syslog. */ + time = in_be32((void *)CFG_WATCHDOG_TIME_ADDR); + post_log("hw watchdog time : %u ms, passed ", time); + /* 3.3.2. Set scratch register 1 to 0x0000xxxx */ + watchdog_magic_write(0); + + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index c86a150692..466ca926b7 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -42,8 +42,6 @@ #define CACHE_POST_SIZE 1024 -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); - int cache_post_test1 (int tlb, void *p, int size); int cache_post_test2 (int tlb, void *p, int size); int cache_post_test3 (int tlb, void *p, int size); diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index 7d4f9b88ee..e3da5e64ce 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -28,6 +28,8 @@ * * The Real Time Clock (RTC) operation is verified by this test. * The following features are verified: + * o) RTC Power Fault + * This is verified by analyzing the rtc_get() return status. * o) Time uniformity * This is verified by reading RTC in polling within * a short period of time. @@ -96,6 +98,10 @@ int rtc_post_test (int flags) unsigned int ynl = 1999; unsigned int yl = 2000; unsigned int skipped = 0; + int reliable; + + /* Time reliability */ + reliable = rtc_get (&svtm); /* Time uniformity */ if (rtc_post_skip (&diff) != 0) { @@ -176,6 +182,15 @@ int rtc_post_test (int flags) } rtc_post_restore (&svtm, skipped); + /* If come here, then RTC operates correcty, check the correctness + * of the time it reports. + */ + if (reliable < 0) { + post_log ("RTC Time is not reliable! Power fault? \n"); + + return -1; + } + return 0; } diff --git a/post/post.c b/post/post.c index 4ff75ee4b1..1df0657d8b 100644 --- a/post/post.c +++ b/post/post.c @@ -157,8 +157,10 @@ static void post_bootmode_test_off (void) static void post_get_flags (int *test_flags) { - int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST }; - char *var[] = { "post_poweron", "post_normal", "post_slowtest" }; + int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST, + POST_CRITICAL }; + char *var[] = { "post_poweron", "post_normal", "post_slowtest", + "post_critical" }; int varnum = sizeof (var) / sizeof (var[0]); char list[128]; /* long enough for POST list */ char *name; @@ -224,7 +226,9 @@ static int post_run_single (struct post_test *test, if (!(flags & POST_REBOOT)) { if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { - post_bootmode_test_on (i); + post_bootmode_test_on ( + (gd->flags & GD_FLG_POSTFAIL) ? + POST_FAIL_SAVE | i : i); } if (test_flags & POST_PREREL) @@ -236,10 +240,14 @@ static int post_run_single (struct post_test *test, if (test_flags & POST_PREREL) { if ((*test->test) (flags) == 0) post_log_mark_succ ( test->testid ); + else if (test_flags & POST_CRITICAL) + gd->flags |= GD_FLG_POSTFAIL; } else { if ((*test->test) (flags) != 0) { post_log ("FAILED\n"); show_boot_progress (-32); + if (test_flags & POST_CRITICAL) + gd->flags |= GD_FLG_POSTFAIL; } else post_log ("PASSED\n"); @@ -266,6 +274,10 @@ int post_run (char *name, int flags) unsigned int last; if (post_bootmode_get (&last) & POST_POWERTEST) { + if (last & POST_FAIL_SAVE) { + last &= ~POST_FAIL_SAVE; + gd->flags |= GD_FLG_POSTFAIL; + } if (last < post_list_size && (flags & test_flags[last] & POST_ALWAYS) && (flags & test_flags[last] & POST_MEM)) { diff --git a/post/tests.c b/post/tests.c index 698f85c98d..53d01e355e 100644 --- a/post/tests.c +++ b/post/tests.c @@ -48,6 +48,13 @@ extern int dsp_post_test (int flags); extern int codec_post_test (int flags); extern int ecc_post_test (int flags); +extern int dspic_init_post_test (int flags); +extern int dspic_post_test (int flags); +extern int gdc_post_test (int flags); +extern int fpga_post_test (int flags); +extern int lwmon5_watchdog_post_test(int flags); +extern int sysmon1_post_test(int flags); + extern int sysmon_init_f (void); extern void sysmon_reloc (void); @@ -68,6 +75,9 @@ struct post_test post_list[] = }, #endif #if CONFIG_POST & CFG_POST_WATCHDOG +#if defined(CONFIG_POST_WATCHDOG) + CONFIG_POST_WATCHDOG, +#else { "Watchdog timer test", "watchdog", @@ -79,6 +89,7 @@ struct post_test post_list[] = CFG_POST_WATCHDOG }, #endif +#endif #if CONFIG_POST & CFG_POST_I2C { "I2C test", @@ -225,7 +236,7 @@ struct post_test post_list[] = CFG_POST_DSP }, #endif -#if CONFIG_POST & CFG_POST_DSP +#if CONFIG_POST & CFG_POST_CODEC { "CODEC test", "codec", @@ -249,6 +260,21 @@ struct post_test post_list[] = CFG_POST_ECC }, #endif +#if CONFIG_POST & CFG_POST_BSPEC1 + CONFIG_POST_BSPEC1, +#endif +#if CONFIG_POST & CFG_POST_BSPEC2 + CONFIG_POST_BSPEC2, +#endif +#if CONFIG_POST & CFG_POST_BSPEC3 + CONFIG_POST_BSPEC3, +#endif +#if CONFIG_POST & CFG_POST_BSPEC4 + CONFIG_POST_BSPEC4, +#endif +#if CONFIG_POST & CFG_POST_BSPEC4 + CONFIG_POST_BSPEC5, +#endif }; unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test); diff --git a/tools/setlocalversion b/tools/setlocalversion index 9a23825218..9bbdafdb6d 100755 --- a/tools/setlocalversion +++ b/tools/setlocalversion @@ -11,12 +11,15 @@ cd "${1:-.}" || usage # Check for git and a git repo. if head=`git rev-parse --verify HEAD 2>/dev/null`; then # Do we have an untagged version? - if [ "`git name-rev --tags HEAD`" = "HEAD undefined" ]; then - printf '%s%s' -g `echo "$head" | cut -c1-8` + if git name-rev --tags HEAD | \ + grep -E '^HEAD[[:space:]]+(.*~[0-9]*|undefined)$' > /dev/null; then + git describe | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}' fi # Are there uncommitted changes? - if git diff-files | read dummy; then + git update-index --refresh --unmerged > /dev/null + if git diff-index --name-only HEAD | grep -v "^scripts/package" \ + | read dummy; then printf '%s' -dirty fi fi |
