diff options
98 files changed, 2086 insertions, 614 deletions
diff --git a/arch/arm/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c index 6144729185..ecceb98c75 100644 --- a/arch/arm/cpu/arm920t/ep93xx/led.c +++ b/arch/arm/cpu/arm920t/ep93xx/led.c @@ -13,7 +13,7 @@ static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN, 1 << STATUS_LED_RED}; -inline void switch_LED_on(uint8_t led) +static inline void switch_LED_on(uint8_t led) { register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; @@ -21,7 +21,7 @@ inline void switch_LED_on(uint8_t led) saved_state[led] = STATUS_LED_ON; } -inline void switch_LED_off(uint8_t led) +static inline void switch_LED_off(uint8_t led) { register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 1633ddc6b0..466348f940 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -38,11 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_OF_CONTROL) -/* - * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove - * the CONFIGs. At the same time, we should move this to the board files. - */ +#if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM2 @@ -57,14 +53,14 @@ static const struct ns16550_platdata am33xx_serial[] = { }; U_BOOT_DEVICES(am33xx_uarts) = { - { "serial_omap", &am33xx_serial[0] }, + { "ns16550_serial", &am33xx_serial[0] }, # ifdef CONFIG_SYS_NS16550_COM2 - { "serial_omap", &am33xx_serial[1] }, + { "ns16550_serial", &am33xx_serial[1] }, # ifdef CONFIG_SYS_NS16550_COM3 - { "serial_omap", &am33xx_serial[2] }, - { "serial_omap", &am33xx_serial[3] }, - { "serial_omap", &am33xx_serial[4] }, - { "serial_omap", &am33xx_serial[5] }, + { "ns16550_serial", &am33xx_serial[2] }, + { "ns16550_serial", &am33xx_serial[3] }, + { "ns16550_serial", &am33xx_serial[4] }, + { "ns16550_serial", &am33xx_serial[5] }, # endif # endif }; diff --git a/arch/arm/cpu/armv7m/config.mk b/arch/arm/cpu/armv7m/config.mk index 0b31e44d49..4a53006b6a 100644 --- a/arch/arm/cpu/armv7m/config.mk +++ b/arch/arm/cpu/armv7m/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index d3ab862c55..58cde9391f 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -3,7 +3,7 @@ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S index e05e984228..49f27201cf 100644 --- a/arch/arm/cpu/armv7m/start.S +++ b/arch/arm/cpu/armv7m/start.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile b/arch/arm/cpu/armv7m/stm32f1/Makefile index 4faf4359d5..e2081dbf9e 100644 --- a/arch/arm/cpu/armv7m/stm32f1/Makefile +++ b/arch/arm/cpu/armv7m/stm32f1/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # Copyright 2015 ATS Advanced Telematics Systems GmbH # Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c b/arch/arm/cpu/armv7m/stm32f1/clock.c index acad116a52..28208485d4 100644 --- a/arch/arm/cpu/armv7m/stm32f1/clock.c +++ b/arch/arm/cpu/armv7m/stm32f1/clock.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/flash.c b/arch/arm/cpu/armv7m/stm32f1/flash.c index bb88f236af..7d41f63733 100644 --- a/arch/arm/cpu/armv7m/stm32f1/flash.c +++ b/arch/arm/cpu/armv7m/stm32f1/flash.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/soc.c b/arch/arm/cpu/armv7m/stm32f1/soc.c index 8275ad7798..4438621b9a 100644 --- a/arch/arm/cpu/armv7m/stm32f1/soc.c +++ b/arch/arm/cpu/armv7m/stm32f1/soc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/timer.c b/arch/arm/cpu/armv7m/stm32f1/timer.c index c6292b5f3c..6a261986e9 100644 --- a/arch/arm/cpu/armv7m/stm32f1/timer.c +++ b/arch/arm/cpu/armv7m/stm32f1/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/cpu/armv7m/stm32f4/Makefile index e98283031c..42d01db14d 100644 --- a/arch/arm/cpu/armv7m/stm32f4/Makefile +++ b/arch/arm/cpu/armv7m/stm32f4/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index d520a13efd..3deb17aa83 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * (C) Copyright 2014 * STMicroelectronics diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index dd058bd643..a379f477df 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/cpu/armv7m/stm32f4/soc.c index 202a1269fb..b5d06dbe83 100644 --- a/arch/arm/cpu/armv7m/stm32f4/soc.c +++ b/arch/arm/cpu/armv7m/stm32f4/soc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c index 102ae6d960..1dee190766 100644 --- a/arch/arm/cpu/armv7m/stm32f4/timer.c +++ b/arch/arm/cpu/armv7m/stm32f4/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 23e7b40ff9..521aa4cff4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sr1500.dtb + dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index 21fcc440fc..b26e21bd7f 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -214,6 +214,7 @@ ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; + reg-shift = <2>; interrupts = <72>; status = "disabled"; dmas = <&edma 26>, <&edma 27>; @@ -225,6 +226,7 @@ ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; + reg-shift = <2>; interrupts = <73>; status = "disabled"; dmas = <&edma 28>, <&edma 29>; @@ -236,6 +238,7 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; + reg-shift = <2>; interrupts = <74>; status = "disabled"; dmas = <&edma 30>, <&edma 31>; @@ -247,6 +250,7 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; + reg-shift = <2>; interrupts = <44>; status = "disabled"; }; @@ -256,6 +260,7 @@ ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; + reg-shift = <2>; interrupts = <45>; status = "disabled"; }; @@ -265,6 +270,7 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; + reg-shift = <2>; interrupts = <46>; status = "disabled"; }; diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index ade28c790f..3fffe1eec3 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -152,6 +152,7 @@ uart0: serial@44e09000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x44e09000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; }; @@ -159,6 +160,7 @@ uart1: serial@48022000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x48022000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; status = "disabled"; @@ -167,6 +169,7 @@ uart2: serial@48024000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x48024000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; status = "disabled"; @@ -175,6 +178,7 @@ uart3: serial@481a6000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481a6000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; status = "disabled"; @@ -183,6 +187,7 @@ uart4: serial@481a8000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481a8000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; status = "disabled"; @@ -191,6 +196,7 @@ uart5: serial@481aa000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481aa000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; status = "disabled"; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 096f68be99..e4daa991e9 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -14,6 +14,10 @@ model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; + chosen { + stdout-path = &uart1; + }; + memory { device_type = "memory"; reg = <0x80000000 0x60000000>; /* 1536 MB */ diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 8f1e25bcec..feb3708dc6 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -399,6 +399,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; + reg-shift = <2>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; @@ -410,6 +411,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; @@ -421,6 +423,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; @@ -432,6 +435,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; @@ -443,6 +447,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; @@ -454,6 +459,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; @@ -465,6 +471,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; clock-frequency = <48000000>; @@ -474,6 +481,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; clock-frequency = <48000000>; @@ -483,6 +491,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; clock-frequency = <48000000>; @@ -492,6 +501,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; clock-frequency = <48000000>; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts new file mode 100644 index 0000000000..3729ca02cd --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "SoCFPGA Cyclone V SR1500"; + compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + /* + * This allows the ethaddr uboot environmnet variable + * contents to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + speed-mode = <0>; +}; + +&i2c1 { + status = "okay"; + speed-mode = <0>; +}; + +&mmc0 { + status = "okay"; + bus-width = <8>; + u-boot,dm-pre-reloc; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h index 6976e1f3e4..8e8712fecc 100644 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ b/arch/arm/include/asm/arch-stm32f1/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 686cb4f596..4094a75393 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h index 4ab30314c9..7dd5077d0c 100644 --- a/arch/arm/include/asm/arch-stm32f4/fmc.h +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -3,7 +3,7 @@ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index dd33b96c48..831c542db0 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index d2aa1c4522..200444dda1 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -3,7 +3,7 @@ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index ee56d7403e..a477cae010 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -290,7 +290,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) s = getenv("machid"); if (s) { - strict_strtoul(s, 16, &machid); + if (strict_strtoul(s, 16, &machid) < 0) { + debug("strict_strtoul failed!\n"); + return; + } printf("Using machid 0x%lx from environment\n", machid); } diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 89ce493861..8a36c189df 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S index abc7f88e00..cf14a34ca6 100644 --- a/arch/arm/lib/vectors_m.S +++ b/arch/arm/lib/vectors_m.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 9260ee2df7..af94dff2ac 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -125,34 +125,6 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 -#ifdef CONFIG_BCM2836 -#define BCM2836_BOARD_REV_2_B 0x4 -#else -/* - * 0x2..0xf from: - * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ - * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 - * http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796 - */ -#define BCM2835_BOARD_REV_B_I2C0_2 0x2 -#define BCM2835_BOARD_REV_B_I2C0_3 0x3 -#define BCM2835_BOARD_REV_B_I2C1_4 0x4 -#define BCM2835_BOARD_REV_B_I2C1_5 0x5 -#define BCM2835_BOARD_REV_B_I2C1_6 0x6 -#define BCM2835_BOARD_REV_A_7 0x7 -#define BCM2835_BOARD_REV_A_8 0x8 -#define BCM2835_BOARD_REV_A_9 0x9 -#define BCM2835_BOARD_REV_B_REV2_d 0xd -#define BCM2835_BOARD_REV_B_REV2_e 0xe -#define BCM2835_BOARD_REV_B_REV2_f 0xf -#define BCM2835_BOARD_REV_B_PLUS 0x10 -#define BCM2835_BOARD_REV_CM 0x11 -#define BCM2835_BOARD_REV_A_PLUS 0x12 -#define BCM2835_BOARD_REV_B_PLUS_13 0x13 -#define BCM2835_BOARD_REV_CM_14 0x14 -#define BCM2835_BOARD_REV_A_PLUS_15 0x15 -#endif - struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; union { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index e4cc468e72..0cb9f9e281 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_SR1500 + bool "SR1500 (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -43,6 +47,7 @@ config SYS_BOARD default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "sr1500" if TARGET_SOCFPGA_SR1500 config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -62,5 +67,6 @@ config SYS_CONFIG_NAME default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 endif diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index bbd31ef7b5..b110f5bb42 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -130,17 +130,6 @@ int cpu_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_DWMMC -/* - * Initializes MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ - return socfpga_dwmmc_init(gd->fdt_blob); -} -#endif - struct { const char *mode; const char *name; diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 8c8927d591..3d1d26d13d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -214,7 +214,7 @@ void board_init_uart_f(void) setup_uarts(uart_ids); } -#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL) +#if !CONFIG_IS_ENABLED(OF_CONTROL) static struct ns16550_platdata ns16550_com1_pdata = { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6451d1d916..4b80d7b742 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -74,117 +74,132 @@ struct msg_get_clock_rate { u32 end_tag; }; -/* See comments in mbox.h for data source */ -static const struct { +/* + * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 + * http://git.drogon.net/?p=wiringPi;a=blob;f=wiringPi/wiringPi.c;h=503151f61014418b9c42f4476a6086f75cd4e64b;hb=refs/heads/master#l922 + */ +struct rpi_model { const char *name; const char *fdtfile; bool has_onboard_eth; -} models[] = { - [0] = { - "Unknown model", +}; + +static const struct rpi_model rpi_model_unknown = { + "Unknown model", #ifdef CONFIG_BCM2836 - "bcm2836-rpi-other.dtb", + "bcm2836-rpi-other.dtb", #else - "bcm2835-rpi-other.dtb", + "bcm2835-rpi-other.dtb", #endif - false, - }, -#ifdef CONFIG_BCM2836 - [BCM2836_BOARD_REV_2_B] = { + false, +}; + +static const struct rpi_model rpi_models_new_scheme[] = { + [0x4] = { "2 Model B", "bcm2836-rpi-2-b.dtb", true, }, -#else - [BCM2835_BOARD_REV_B_I2C0_2] = { + [0x9] = { + "Zero", + "bcm2835-rpi-zero.dtb", + false, + }, +}; + +static const struct rpi_model rpi_models_old_scheme[] = { + [0x2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C0_3] = { + [0x3] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_4] = { + [0x4] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_5] = { + [0x5] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_6] = { + [0x6] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_A_7] = { + [0x7] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_8] = { + [0x8] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_9] = { + [0x9] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_B_REV2_d] = { + [0xd] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_e] = { + [0xe] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_f] = { + [0xf] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_PLUS] = { + [0x10] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM] = { + [0x11] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS] = { + [0x12] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, - [BCM2835_BOARD_REV_B_PLUS_13] = { + [0x13] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM_14] = { + [0x14] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS_15] = { + [0x15] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, -#endif }; -u32 rpi_board_rev = 0; +static uint32_t revision; +static uint32_t rev_scheme; +static uint32_t rev_type; +static const struct rpi_model *model; int dram_init(void) { @@ -212,7 +227,7 @@ static void set_fdtfile(void) if (getenv("fdtfile")) return; - fdtfile = models[rpi_board_rev].fdtfile; + fdtfile = model->fdtfile; setenv("fdtfile", fdtfile); } @@ -221,7 +236,7 @@ static void set_usbethaddr(void) ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1); int ret; - if (!models[rpi_board_rev].has_onboard_eth) + if (!model->has_onboard_eth) return; if (getenv("usbethaddr")) @@ -245,10 +260,16 @@ static void set_usbethaddr(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG static void set_board_info(void) { - char str_rev[11]; - sprintf(str_rev, "0x%X", rpi_board_rev); - setenv("board_rev", str_rev); - setenv("board_name", models[rpi_board_rev].name); + char s[11]; + + snprintf(s, sizeof(s), "0x%X", revision); + setenv("board_revision", s); + snprintf(s, sizeof(s), "%d", rev_scheme); + setenv("board_rev_scheme", s); + /* Can't rename this to board_rev_type since it's an ABI for scripts */ + snprintf(s, sizeof(s), "0x%X", rev_type); + setenv("board_rev", s); + setenv("board_name", model->name); } #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ @@ -290,7 +311,8 @@ static void get_board_rev(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); int ret; - const char *name; + const struct rpi_model *models; + uint32_t models_count; BCM2835_MBOX_INIT_HDR(msg); BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); @@ -313,23 +335,29 @@ static void get_board_rev(void) * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 */ - rpi_board_rev = msg->get_board_rev.body.resp.rev; - if (rpi_board_rev & 0x800000) - rpi_board_rev = (rpi_board_rev >> 4) & 0xff; - else - rpi_board_rev &= 0xff; - if (rpi_board_rev >= ARRAY_SIZE(models)) { - printf("RPI: Board rev %u outside known range\n", - rpi_board_rev); - rpi_board_rev = 0; + revision = msg->get_board_rev.body.resp.rev; + if (revision & 0x800000) { + rev_scheme = 1; + rev_type = (revision >> 4) & 0xff; + models = rpi_models_new_scheme; + models_count = ARRAY_SIZE(rpi_models_new_scheme); + } else { + rev_scheme = 0; + rev_type = revision & 0xff; + models = rpi_models_old_scheme; + models_count = ARRAY_SIZE(rpi_models_old_scheme); } - if (!models[rpi_board_rev].name) { - printf("RPI: Board rev %u unknown\n", rpi_board_rev); - rpi_board_rev = 0; + if (rev_type >= models_count) { + printf("RPI: Board rev 0x%x outside known range\n", rev_type); + model = &rpi_model_unknown; + } else if (!models[rev_type].name) { + printf("RPI: Board rev 0x%x unknown\n", rev_type); + model = &rpi_model_unknown; + } else { + model = &models[rev_type]; } - name = models[rpi_board_rev].name; - printf("RPI %s\n", name); + printf("RPI %s (0x%x)\n", model->name, revision); } int board_init(void) diff --git a/board/sr1500/MAINTAINERS b/board/sr1500/MAINTAINERS new file mode 100644 index 0000000000..ed013a8524 --- /dev/null +++ b/board/sr1500/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA SR1500 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/sr1500/ +F: include/configs/socfpga_sr1500.h +F: configs/socfpga_sr1500_defconfig diff --git a/board/sr1500/Makefile b/board/sr1500/Makefile new file mode 100644 index 0000000000..eae7ad0302 --- /dev/null +++ b/board/sr1500/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h new file mode 100644 index 0000000000..aa1e65c2ae --- /dev/null +++ b/board/sr1500/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00100000, + 0x40000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x000E0180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x000700C0, + 0x1C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x00018060, + 0x0E018000, + 0x06000000, + 0x00000038, + 0x0000E018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x001C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x000000E0, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x1C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x700C0000, + 0x0FF00000, + 0x00000000, + 0x000700C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x10018060, + 0x0E018000, + 0x06000000, + 0x00010018, + 0x0000E018, + 0x00001000, + 0x0001C030, + 0x04000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x80E380D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D5551E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D555, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D9651E, + 0x035AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010000, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00202000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3D5, + 0xF6D9651E, + 0x035AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00034AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00800000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020000, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00001000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xCB2CA3D5, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1ECB2CA3, + 0x48F6D965, + 0x00034A92, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820004, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00004000, + 0x00010000, + 0x40002080, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000008, + 0x00000020, + 0x00008000, + 0x20001040, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/sr1500/qts/pinmux_config.h b/board/sr1500/qts/pinmux_config.h new file mode 100644 index 0000000000..45e390debb --- /dev/null +++ b/board/sr1500/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 0, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 0, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 0, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 0, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 0, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 0, /* GPLMUX40 */ + 0, /* GPLMUX41 */ + 0, /* GPLMUX42 */ + 0, /* GPLMUX43 */ + 0, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 0, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 0, /* GPLMUX53 */ + 0, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 0, /* GPLMUX57 */ + 0, /* GPLMUX58 */ + 0, /* GPLMUX59 */ + 0, /* GPLMUX60 */ + 0, /* GPLMUX61 */ + 0, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h new file mode 100644 index 0000000000..359e7ad734 --- /dev/null +++ b/board/sr1500/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 12500000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h new file mode 100644 index 0000000000..edbaf8929f --- /dev/null +++ b/board/sr1500/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c new file mode 100644 index 0000000000..9f895842f7 --- /dev/null +++ b/board/sr1500/socfpga.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <asm/arch/reset_manager.h> +#include <asm/gpio.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int board_early_init_f(void) +{ + int ret; + + /* Reset the Marvell PHY 88E1510 */ + ret = gpio_request(63, "PHY reset"); + if (ret) + return ret; + + gpio_direction_output(63, 0); + mdelay(1); + gpio_set_value(63, 1); + mdelay(10); + + return 0; +} diff --git a/board/st/stm32f429-discovery/MAINTAINERS b/board/st/stm32f429-discovery/MAINTAINERS index 641f26a037..fdb62e98e8 100644 --- a/board/st/stm32f429-discovery/MAINTAINERS +++ b/board/st/stm32f429-discovery/MAINTAINERS @@ -1,5 +1,5 @@ STM32F429-DISCOVERY BOARD -M: Kamil Lulko <rev13@wp.pl> +M: Kamil Lulko <kamil.lulko@gmail.com> S: Maintained F: board/st/stm32f429-discovery/ F: include/configs/stm32f429-discovery.h diff --git a/board/st/stm32f429-discovery/Makefile b/board/st/stm32f429-discovery/Makefile index 7e764e3308..d94059d0ae 100644 --- a/board/st/stm32f429-discovery/Makefile +++ b/board/st/stm32f429-discovery/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 306e550a7c..ee22009f31 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/common/Makefile b/common/Makefile index d8dc892f72..2a1d9f8331 100644 --- a/common/Makefile +++ b/common/Makefile @@ -227,6 +227,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o +obj-$(CONFIG_SPL_OF_TRANSLATE) += fdt_support.o ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o diff --git a/common/board_f.c b/common/board_f.c index 8325dc333c..eac7c5e4c5 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -524,6 +524,7 @@ static int reserve_global_data(void) static int reserve_fdt(void) { +#ifndef CONFIG_OF_EMBED /* * If the device tree is sitting immediately above our image then we * must relocate it. If it is embedded in the data section, then it @@ -537,6 +538,7 @@ static int reserve_fdt(void) debug("Reserving %lu Bytes for FDT at: %08lx\n", gd->fdt_size, gd->start_addr_sp); } +#endif return 0; } @@ -674,12 +676,14 @@ static int setup_dram_config(void) static int reloc_fdt(void) { +#ifndef CONFIG_OF_EMBED if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_fdt) { memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); gd->fdt_blob = gd->new_fdt; } +#endif return 0; } diff --git a/common/board_r.c b/common/board_r.c index 3bf49fdfb3..5af32dd65b 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -168,6 +168,14 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE; #endif +#ifdef CONFIG_OF_EMBED + /* + * The fdt_blob needs to be moved to new relocation address + * incase of FDT blob is embedded with in image + */ + gd->fdt_blob += gd->reloc_off; +#endif + return 0; } diff --git a/common/cli_hush.c b/common/cli_hush.c index a7cac4fcb9..7f69c062a7 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -2162,7 +2162,7 @@ int set_local_var(const char *s, int flg_export) * NAME=VALUE format. So the first order of business is to * split 's' on the '=' into 'name' and 'value' */ value = strchr(name, '='); - if (value == NULL && ++value == NULL) { + if (value == NULL || *(value + 1) == 0) { free(name); return -1; } @@ -2471,11 +2471,16 @@ static int done_word(o_string *dest, struct p_context *ctx) } argc = ++child->argc; child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); - if (child->argv == NULL) return 1; + if (child->argv == NULL) { + free(str); + return 1; + } child->argv_nonnull = realloc(child->argv_nonnull, (argc+1)*sizeof(*child->argv_nonnull)); - if (child->argv_nonnull == NULL) + if (child->argv_nonnull == NULL) { + free(str); return 1; + } child->argv[argc-1]=str; child->argv_nonnull[argc-1] = dest->nonnull; child->argv[argc]=NULL; diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index dfc1ec850e..a6b7313e4a 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -747,7 +747,7 @@ static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag, dev = simple_strtoul(argv[1], NULL, 10); enable = simple_strtoul(argv[2], NULL, 10); - if (enable > 2 || enable < 0) { + if (enable > 2) { puts("Invalid RST_n_ENABLE value\n"); return CMD_RET_USAGE; } diff --git a/common/image-fdt.c b/common/image-fdt.c index 5180a03a61..5e4e5bd914 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -326,7 +326,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, if (load == image_start || load == image_data) { - fdt_blob = (char *)image_data; + fdt_addr = load; break; } diff --git a/common/miiphyutil.c b/common/miiphyutil.c index e499b58836..7e41957185 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -114,6 +114,8 @@ void miiphy_register(const char *name, if (new_dev == NULL || ldev == NULL) { printf("miiphy_register: cannot allocate memory for '%s'\n", name); + free(ldev); + mdio_free(new_dev); return; } @@ -159,7 +161,7 @@ void mdio_free(struct mii_dev *bus) int mdio_register(struct mii_dev *bus) { - if (!bus || !bus->name || !bus->read || !bus->write) + if (!bus || !bus->read || !bus->write) return -1; /* check if we have unique name */ diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index b3c2c642e4..f2c1af5d35 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -78,10 +78,11 @@ int spl_mmc_get_device_index(u32 boot_device) return -ENODEV; } -#ifdef CONFIG_DM_MMC -static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) +static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) { +#ifdef CONFIG_DM_MMC struct udevice *dev; +#endif int err, mmc_dev; mmc_dev = spl_mmc_get_device_index(boot_device); @@ -96,47 +97,23 @@ static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) return err; } +#ifdef CONFIG_DM_MMC err = uclass_get_device(UCLASS_MMC, mmc_dev, &dev); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not find mmc device. error: %d\n", err); -#endif - return err; - } - - *mmc = NULL; - *mmc = mmc_get_mmc_dev(dev); - return *mmc != NULL ? 0 : -ENODEV; -} + if (!err) + *mmcp = mmc_get_mmc_dev(dev); #else -static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) -{ - int err, mmc_dev; - - mmc_dev = spl_mmc_get_device_index(boot_device); - if (mmc_dev < 0) - return mmc_dev; - - err = mmc_initialize(gd->bd); + *mmcp = find_mmc_device(mmc_dev); + err = *mmcp ? 0 : -ENODEV; +#endif if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not initialize mmc. error: %d\n", err); + printf("spl: could not find mmc device. error: %d\n", err); #endif return err; } - /* We register only one device. So, the dev id is always 0 */ - *mmc = find_mmc_device(mmc_dev); - if (!*mmc) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: mmc device not found\n"); -#endif - return -ENODEV; - } - return 0; } -#endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) @@ -248,7 +225,7 @@ int spl_mmc_do_fs_boot(struct mmc *mmc) int spl_mmc_load_image(u32 boot_device) { - struct mmc *mmc; + struct mmc *mmc = NULL; u32 boot_mode; int err = 0; __maybe_unused int part; diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 29303441d9..8add08d76d 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -13,11 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y -<<<<<<< HEAD CONFIG_SPI_FLASH_WINBOND=y -======= CONFIG_PCI_TEGRA=y ->>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 5760018d68..c9f565a4f5 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -13,11 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y -<<<<<<< HEAD CONFIG_SPI_FLASH_WINBOND=y -======= CONFIG_PCI_TEGRA=y ->>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig index 7bff294fbb..394edbec2e 100644 --- a/configs/dra74_evm_defconfig +++ b/configs/dra74_evm_defconfig @@ -16,5 +16,6 @@ CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 9500d2cff6..efc4aeeb32 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -13,11 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y -<<<<<<< HEAD CONFIG_SPI_FLASH_WINBOND=y -======= CONFIG_PCI_TEGRA=y ->>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index b4c23d95b3..f59bc00e61 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -20,3 +20,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index ac7bd0bc3a..c0d6913425 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -20,3 +20,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index d21029f8f9..a4f75e6f01 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -18,3 +18,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 97f6c5d140..382db6561b 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -18,3 +18,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index d3b9c893e6..03f8effcba 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -22,3 +22,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index d391f46ee9..932f0e8c2d 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -21,3 +21,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig new file mode 100644 index 0000000000..2c75bda084 --- /dev/null +++ b/configs/socfpga_sr1500_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DM=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_SR1500=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_DWAPB_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_MMC=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index ee40218d1c..e34faa3cfd 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -13,11 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y -<<<<<<< HEAD CONFIG_SPI_FLASH_WINBOND=y -======= CONFIG_PCI_TEGRA=y ->>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SFLASH=y CONFIG_USB=y diff --git a/doc/README.nand b/doc/README.nand index 0ff56331d5..545d88ca68 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -94,7 +94,7 @@ Configuration Options: address of u-boot MTD partition in NAND. CONFIG_CMD_NAND - Enables NAND support and commmands. + Enables NAND support and commands. CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). diff --git a/doc/README.update b/doc/README.update index eab124ce1d..d37f2c4d4a 100644 --- a/doc/README.update +++ b/doc/README.update @@ -51,7 +51,7 @@ the mkimage tool. dtc tool with support for binary includes, e.g. in version to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT images. -This mechanism can be also triggered by the commmand "fitupd". +This mechanism can be also triggered by the command "fitupd". If an optional, non-zero address is provided as argument, the TFTP transfer is skipped and the image at this address is used. The fitupd command is enabled by CONFIG_CMD_FITUPD. diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 1ad638ea05..5efa821dad 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -818,7 +818,7 @@ static int ata_scsiop_read_capacity10(ccb *pccb) if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tPlease run SCSI command INQUIRY first!\n"); return -EPERM; } @@ -847,7 +847,7 @@ static int ata_scsiop_read_capacity16(ccb *pccb) if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tPlease run SCSI command INQUIRY first!\n"); return -EPERM; } diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 208a0ae889..e000ebff76 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -398,7 +398,7 @@ static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis debug("attribute = %08x\n\r", val32); cmd_hdr->attribute = cpu_to_le32(val32); - /* Make sure cmd desc and cmd slot valid before commmand issue */ + /* Make sure cmd desc and cmd slot valid before command issue */ sync(); /* PMP*/ diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index d7a194e3ca..75a84e111f 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 2bd0ebd96c..5b0c3a8eda 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -5,24 +5,29 @@ */ #include <common.h> -#include <malloc.h> -#include <fdtdec.h> -#include <libfdt.h> -#include <dwmmc.h> -#include <errno.h> -#include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/dwmmc.h> #include <asm/arch/system_manager.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <linux/err.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; -/* socfpga implmentation specific drver private data */ +/* socfpga implmentation specific driver private data */ struct dwmci_socfpga_priv_data { - unsigned int drvsel; - unsigned int smplsel; + struct dwmci_host host; + unsigned int drvsel; + unsigned int smplsel; }; static void socfpga_dwmci_clksel(struct dwmci_host *host) @@ -46,98 +51,77 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } -static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) +static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) { /* FIXME: probe from DT eventually too/ */ const unsigned long clk = cm_get_mmc_controller_clk_hz(); - struct dwmci_host *host; - struct dwmci_socfpga_priv_data *priv; - fdt_addr_t reg_base; - int bus_width, fifo_depth; + struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int fifo_depth; if (clk == 0) { - printf("DWMMC%d: MMC clock is zero!", idx); - return -EINVAL; - } - - /* Get the register address from the device node */ - reg_base = fdtdec_get_addr(blob, node, "reg"); - if (!reg_base) { - printf("DWMMC%d: Can't get base address\n", idx); + printf("DWMMC: MMC clock is zero!"); return -EINVAL; } - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "bus-width", 0); - if (bus_width <= 0) { - printf("DWMMC%d: Can't get bus-width\n", idx); - return -EINVAL; - } - - fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); if (fifo_depth < 0) { - printf("DWMMC%d: Can't get FIFO depth\n", idx); + printf("DWMMC: Can't get FIFO depth\n"); return -EINVAL; } - /* Allocate the host */ - host = calloc(1, sizeof(*host)); - if (!host) - return -ENOMEM; - - /* Allocate the priv */ - priv = calloc(1, sizeof(*priv)); - if (!priv) { - free(host); - return -ENOMEM; - } - - host->name = "SOCFPGA DWMMC"; - host->ioaddr = (void *)reg_base; - host->buswidth = bus_width; + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); host->clksel = socfpga_dwmci_clksel; - host->dev_index = idx; + + /* + * TODO(sjg@chromium.org): Remove the need for this hack. + * We only have one dwmmc block on gen5 SoCFPGA. + */ + host->dev_index = 0; /* Fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); - priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3); - priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0); + priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "drvsel", 3); + priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "smplsel", 0); host->priv = priv; - return add_dwmci(host, host->bus_hz, 400000); -} - -static int socfpga_dwmci_process_node(const void *blob, int nodes[], - int count) -{ - int i, node, ret; - - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = socfpga_dwmci_of_probe(blob, node, i); - if (ret) { - printf("%s: failed to decode dev %d\n", __func__, i); - return ret; - } - } return 0; } -int socfpga_dwmmc_init(const void *blob) +static int socfpga_dwmmc_probe(struct udevice *dev) { - int nodes[2]; /* Max. two controllers. */ - int ret, count; + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int ret; - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_ALTERA_SOCFPGA_DWMMC, - nodes, ARRAY_SIZE(nodes)); + ret = add_dwmci(host, host->bus_hz, 400000); + if (ret) + return ret; - ret = socfpga_dwmci_process_node(blob, nodes, count); + upriv->mmc = host->mmc; - return ret; + return 0; } + +static const struct udevice_id socfpga_dwmmc_ids[] = { + { .compatible = "altr,socfpga-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(socfpga_dwmmc_drv) = { + .name = "socfpga_dwmmc", + .id = UCLASS_MMC, + .of_match = socfpga_dwmmc_ids, + .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata, + .probe = socfpga_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data), +}; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 1565a9a060..f65b499beb 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -451,7 +451,7 @@ static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info, } /** - * NOTE: it is a must to set ND_RUN firstly, then write + * NOTE: it is a must to set ND_RUN first, then write * command buffer, otherwise, it does not work. * We enable all the interrupt at the same time, and * let pxa3xx_nand_irq to handle all logic. diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index a421e12e5d..200cf61bc9 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -66,7 +66,7 @@ static int _rproc_name_is_unique(struct udevice *dev, const char *check_name = data; /* devices not yet populated with data - so skip them */ - if (!uc_pdata->name && check_name) + if (!uc_pdata->name || !check_name) return 0; /* Return 0 to search further if we dont match */ diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 166deabcd4..3fab3f1efb 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -403,7 +403,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->base = addr; plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "reg-shift", 1); + "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock-frequency", CONFIG_SYS_NS16550_CLK); @@ -451,5 +451,6 @@ U_BOOT_DRIVER(ns16550_serial) = { .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, }; #endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 422d3aedc3..f1bd15b002 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -527,7 +527,7 @@ static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; * * Do a loopback test of the currently selected serial port. This * function is only useful in the context of the POST testing framwork. - * The serial port is firstly configured into loopback mode and then + * The serial port is first configured into loopback mode and then * characters are sent through it. * * Returns 0 on success, value otherwise. diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0ae3de5c27..85cc96ac87 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -613,7 +613,7 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) int dwc3_uboot_init(struct dwc3_device *dwc3_dev) { struct dwc3 *dwc; - struct device *dev; + struct device *dev = NULL; u8 lpm_nyet_threshold; u8 tx_de_emphasis; u8 hird_threshold; diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index ac9a856190..3dcc2f4847 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -374,7 +374,7 @@ static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode) int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev) { u32 reg; - struct device *dev; + struct device *dev = NULL; struct dwc3_omap *omap; omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2a2bffe06f..0096a2fdd9 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -73,4 +73,12 @@ config USB_EHCI_UNIPHIER ---help--- Enables support for the on-chip EHCI controller on UniPhier SoCs. +config USB_EHCI_GENERIC + bool "Support for generic EHCI USB controller" + depends on OF_CONTROL + depends on DM_USB + default n + ---help--- + Enables support for generic EHCI controller. + endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c9e8..0b4b458cca 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -32,6 +32,7 @@ else obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o +obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o @@ -54,6 +55,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c new file mode 100644 index 0000000000..1292caae4d --- /dev/null +++ b/drivers/usb/host/ehci-generic.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include "ehci.h" + +/* + * Even though here we don't explicitly use "struct ehci_ctrl" + * ehci_register() expects it to be the first thing that resides in + * device's private data. + */ +struct generic_ehci { + struct ehci_ctrl ctrl; +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); + struct ehci_hcor *hcor; + + hcor = (struct ehci_hcor *)((uintptr_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + return ehci_deregister(dev); +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "generic-ehci" }, + { } +}; + +U_BOOT_DRIVER(ehci_generic) = { + .name = "ehci_generic", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct generic_ehci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 38d5f92ad0..d494ca10bb 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -87,7 +87,7 @@ static const struct udevice_id ehci_usb_ids[] = { { } }; -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_sunxi) = { .name = "ehci_sunxi", .id = UCLASS_USB, .of_match = ehci_usb_ids, diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index c722c504ad..33961cd634 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -44,6 +44,8 @@ void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) /* reset USB3 phy - if required */ dwc3_phy_reset(dwc3_reg); + mdelay(100); + /* After PHYs are stable we can take Core out of reset state */ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); } diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 6481e07823..05f09d7600 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -27,23 +27,6 @@ __weak int __board_usb_init(int index, enum usb_init_type init) return 0; } -void usb_phy_reset(struct dwc3 *dwc3_reg) -{ - /* Assert USB3 PHY reset */ - setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Assert USB2 PHY reset */ - setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); - - mdelay(200); - - /* Clear USB3 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Clear USB2 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); -} - static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) { int ret = 0; diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index 104e7a7282..fd19f79f0f 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct omap_xhci omap; -inline int __board_usb_init(int index, enum usb_init_type init) +__weak int __board_usb_init(int index, enum usb_init_type init) { return 0; } diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c new file mode 100644 index 0000000000..a7353698d7 --- /dev/null +++ b/drivers/usb/host/xhci-zynqmp.c @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * Zynq USB HOST xHCI Controller + * + * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> + * + * This file was reused from Freescale USB xHCI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm-generic/errno.h> +#include <asm/arch-zynqmp/hardware.h> +#include <linux/compat.h> +#include <linux/usb/dwc3.h> +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Default to the ZYNQMP XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct zynqmp_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static struct zynqmp_xhci zynqmp_xhci; + +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; + +static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) +{ + int ret = 0; + + ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct zynqmp_xhci *ctx = &zynqmp_xhci; + int ret = 0; + uint32_t hclen; + + if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) + return -EINVAL; + + ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; + ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = zynqmp_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); + *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); + + debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", + *hccr, *hcor, hclen); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + /* + * Currently zynqmp socs do not support PHY shutdown from + * sw. But this support may be added in future socs. + */ + + return; +} diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index f655e69f90..1bdb96e34f 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -78,7 +78,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 860615119c..828bc601aa 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,7 @@ #define ENABLE_JFFS 1 #endif -/* Define which commmands should be available at u-boot command prompt */ +/* Define which commands should be available at u-boot command prompt */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 5545cf0f10..e9b4fe139c 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -213,7 +213,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 943ba17002..e61a0988a4 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -346,7 +346,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 3da454a35b..879ad58fc4 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #endif /* Miscellaneous commands */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h new file mode 100644 index 0000000000..bccb235a11 --- /dev/null +++ b/include/configs/socfpga_sr1500.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_SR1500_H__ +#define __CONFIG_SOCFPGA_SR1500_H__ + +#include <asm/arch/base_addr_ac5.h> + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE + +#define CONFIG_HW_WATCHDOG + +/* U-Boot Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TIME + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ + +/* Ethernet on SoC (EMAC) */ +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII +/* The PHY is autodetected, so no MII PHY address is needed here */ +#define CONFIG_PHY_MARVELL +#define PHY_ANEG_TIMEOUT 8000 + +/* Extra Environment */ +#define CONFIG_HOSTNAME sr1500 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* Environment */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +/* Enable SPI NOR flash reset, needed for SPI booting */ +#define CONFIG_SPI_N25Q256A_RESET + +/* + * Bootcounter + */ +#define CONFIG_BOOTCOUNT_LIMIT +/* last 2 lwords in OCRAM */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 +#define CONFIG_SYS_BOOTCOUNT_BE + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +/* U-Boot payload is stored at offset 0x60000 */ +#undef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000 + +/* Environment setting for SPI flash */ +#undef CONFIG_ENV_SIZE +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OFFSET 0x00040000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#endif /* __CONFIG_SOCFPGA_SR1500_H__ */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index de45e71b8e..a7206f4bea 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -158,7 +158,6 @@ #define I2C_BUS_MAX 3 /* EEPROM definitions */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 6b8b9f83e9..474bbaff05 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -107,6 +107,14 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_XHCI_ZYNQMP + #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 8bdb5c9c6d..b7d506e5e7 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,8 @@ #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} #include <configs/xilinx_zynqmp.h> diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 8e3ddedfad..187e384305 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -181,6 +181,7 @@ static inline bool has_erratum_a007792(void) switch (soc) { case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 2, 0); case SVR_T1024: case SVR_T1023: diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index dd934a0e65..6d1e36505d 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -204,7 +204,6 @@ struct dwc3 { /* offset: 0xC100 */ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode); void dwc3_core_soft_reset(struct dwc3 *dwc3_reg); int dwc3_core_init(struct dwc3 *dwc3_reg); -void usb_phy_reset(struct dwc3 *dwc3_reg); void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val); #endif #endif /* __DWC3_H_ */ diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile deleted file mode 100644 index 7f6d5a084e..0000000000 --- a/post/board/lwmon/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sysmon.o diff --git a/post/board/lwmon/sysmon.c b/post/board/lwmon/sysmon.c deleted file mode 100644 index f521b27dc2..0000000000 --- a/post/board/lwmon/sysmon.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <post.h> -#include <common.h> - -/* - * SYSMON test - * - * This test performs the system hardware monitoring. - * The test passes when all the following voltages and temperatures - * are within allowed ranges: - * - * Board temperature - * Front temperature - * +3.3V CPU logic - * +5V logic - * +12V PCMCIA - * +12V CCFL - * +5V standby - * - * CCFL is not enabled if temperature values are not within allowed ranges - * - * See the list off all parameters in the sysmon_table below - */ - -#include <post.h> -#include <watchdog.h> -#include <i2c.h> - -#if CONFIG_POST & CONFIG_SYS_POST_SYSMON - -DECLARE_GLOBAL_DATA_PTR; - -static int sysmon_temp_invalid = 0; - -/* #define DEBUG */ - -typedef struct sysmon_s sysmon_t; -typedef struct sysmon_table_s sysmon_table_t; - -static void sysmon_lm87_init (sysmon_t * this); -static void sysmon_pic_init (sysmon_t * this); -static uint sysmon_i2c_read (sysmon_t * this, uint addr); -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr); -static void sysmon_ccfl_disable (sysmon_table_t * this); -static void sysmon_ccfl_enable (sysmon_table_t * this); - -struct sysmon_s -{ - uchar chip; - void (*init)(sysmon_t *); - uint (*read)(sysmon_t *, uint); -}; - -static sysmon_t sysmon_lm87 = - {CONFIG_SYS_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read}; -static sysmon_t sysmon_lm87_sgn = - {CONFIG_SYS_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read_sgn}; -static sysmon_t sysmon_pic = - {CONFIG_SYS_I2C_PICIO_ADDR, sysmon_pic_init, sysmon_i2c_read}; - -static sysmon_t * sysmon_list[] = -{ - &sysmon_lm87, - &sysmon_lm87_sgn, - &sysmon_pic, - NULL -}; - -struct sysmon_table_s -{ - char * name; - char * unit_name; - sysmon_t * sysmon; - void (*exec_before)(sysmon_table_t *); - void (*exec_after)(sysmon_table_t *); - - int unit_precision; - int unit_div; - int unit_min; - int unit_max; - uint val_mask; - uint val_min; - uint val_max; - int val_valid; - uint val_min_alt; - uint val_max_alt; - int val_valid_alt; - uint addr; -}; - -static sysmon_table_t sysmon_table[] = -{ - {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable, - 1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x6C, 0xC6, 0, 0x27}, - - {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable, - 1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xB2, 0xF1, 0, 0x29}, - - {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22}, - - {"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23}, - - {"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21}, - - {"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable, - 100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24}, - - {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL, - 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C}, -}; -static int sysmon_table_size = ARRAY_SIZE(sysmon_table); - -static int conversion_done = 0; - - -int sysmon_init_f (void) -{ - sysmon_t ** l; - ulong reg; - - /* Power on CCFL, PCMCIA */ - reg = pic_read (0x60); - reg |= 0x09; - pic_write (0x60, reg); - - for (l = sysmon_list; *l; l++) { - (*l)->init(*l); - } - - return 0; -} - -void sysmon_reloc (void) -{ - /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ -} - -static char *sysmon_unit_value (sysmon_table_t *s, uint val) -{ - static char buf[32]; - int unit_val = - s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; - char *p, sign; - int dec, frac; - - if (val == -1) { - return "I/O ERROR"; - } - - if (unit_val < 0) { - sign = '-'; - unit_val = -unit_val; - } else { - sign = '+'; - } - - p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); - - - frac = unit_val % s->unit_div; - - frac /= (s->unit_div / s->unit_precision); - - dec = s->unit_precision; - - if (dec != 1) { - *p++ = '.'; - } - for (dec /= 10; dec != 0; dec /= 10) { - *p++ = '0' + (frac / dec) % 10; - } - strcpy(p, s->unit_name); - - return buf; -} - -static void sysmon_lm87_init (sysmon_t * this) -{ - uchar val; - - /* Detect LM87 chip */ - if (i2c_read(this->chip, 0x40, 1, &val, 1) || (val & 0x80) != 0 || - i2c_read(this->chip, 0x3E, 1, &val, 1) || val != 0x02) { - printf("Error: LM87 not found at 0x%02X\n", this->chip); - return; - } - - /* Configure pins 5,6 as AIN */ - val = 0x03; - if (i2c_write(this->chip, 0x16, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } - - /* Start monitoring */ - val = 0x01; - if (i2c_write(this->chip, 0x40, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } -} - -static void sysmon_pic_init (sysmon_t * this) -{ -} - -static uint sysmon_i2c_read (sysmon_t * this, uint addr) -{ - uchar val; - uint res = i2c_read(this->chip, addr, 1, &val, 1); - - return res == 0 ? val : -1; -} - -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr) -{ - uchar val; - return i2c_read(this->chip, addr, 1, &val, 1) == 0 ? - 128 + (signed char)val : -1; -} - -static void sysmon_ccfl_disable (sysmon_table_t * this) -{ - if (!this->val_valid_alt) { - sysmon_temp_invalid = 1; - } -} - -static void sysmon_ccfl_enable (sysmon_table_t * this) -{ - ulong reg; - - if (!sysmon_temp_invalid) { - reg = pic_read (0x60); - reg |= 0x06; - pic_write (0x60, reg); - } -} - -int sysmon_post_test (int flags) -{ - int res = 0; - sysmon_table_t * t; - uint val; - - /* - * The A/D conversion on the LM87 sensor takes 300 ms. - */ - if (! conversion_done) { - while (post_time_ms(gd->post_init_f_time) < 300) WATCHDOG_RESET (); - conversion_done = 1; - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - if (t->exec_before) { - t->exec_before(t); - } - - val = t->sysmon->read(t->sysmon, t->addr); - if (val != -1) { - t->val_valid = val >= t->val_min && val <= t->val_max; - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; - } else { - t->val_valid = 0; - t->val_valid_alt = 0; - } - - if (t->exec_after) { - t->exec_after(t); - } - - if ((!t->val_valid) || (flags & POST_MANUAL)) { - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); - printf("allowed range"); - printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); - printf(" %-8s", sysmon_unit_value(t, t->val_max)); - printf(" %s\n", t->val_valid ? "OK" : "FAIL"); - } - - if (!t->val_valid) { - res = -1; - } - } - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_SYSMON */ diff --git a/tools/mkimage.c b/tools/mkimage.c index 8af9d50e2c..ae01cb1e83 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -311,21 +311,26 @@ NXTARG: ; exit (retval); } - dfd = open(params.datafile, O_RDONLY | O_BINARY); - if (dfd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - params.cmdname, params.datafile, strerror(errno)); - exit(EXIT_FAILURE); - } + if (!params.type == IH_TYPE_MULTI || + !params.type == IH_TYPE_SCRIPT) { + dfd = open(params.datafile, O_RDONLY | O_BINARY); + if (dfd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + params.cmdname, params.datafile, + strerror(errno)); + exit(EXIT_FAILURE); + } - if (fstat(dfd, &sbuf) < 0) { - fprintf(stderr, "%s: Can't stat %s: %s\n", - params.cmdname, params.datafile, strerror(errno)); - exit(EXIT_FAILURE); - } + if (fstat(dfd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + params.cmdname, params.datafile, + strerror(errno)); + exit(EXIT_FAILURE); + } - params.file_size = sbuf.st_size + tparams->header_size; - close(dfd); + params.file_size = sbuf.st_size + tparams->header_size; + close(dfd); + } /* * In case there an header with a variable |
