diff options
38 files changed, 1826 insertions, 1654 deletions
@@ -2,6 +2,16 @@ Changes since U-Boot 1.0.0: ====================================================================== +* Patch by Scott McNutt, 02 Jan 2004: + Add support for the Nios Active Serial Memory Interface (ASMI) + on Cyclone devices + +* Patch by Andrea Marson, 16 Dec 2003: + Add support for the PPChameleon ME and HI modules + +* Patch by Yuli Barcohen, 22 Dec 2003: + Add support for Motorola DUET ADS board (MPC87x/88x) + * Patch by Robert Schwebel, 15 Dec 2003: add support for cramfs (uses JFFS2 command interface) @@ -34,20 +34,21 @@ LIST_5xxx=" \ LIST_8xx=" \ AdderII ADS860 AMX860 c2mon \ - CCM cogent_mpc8xx ESTEEM192E ETX094 \ - ELPT860 FADS823 FADS850SAR FADS860T \ - FLAGADM FPS850L GEN860T GEN860T_SC \ - GENIETV GTH hermes IAD210 \ - ICU862_100MHz IP860 IVML24 IVML24_128 \ - IVML24_256 IVMS8 IVMS8_128 IVMS8_256 \ - KUP4K LANTEC lwmon MBX \ - MBX860T MHPC MPC86xADS MVS1 \ - NETVIA NETVIA_V2 NX823 pcu_e \ - QS823 QS850 QS860T R360MPI \ - RBC823 rmu RPXClassic RPXlite \ - RRvision SM850 SPD823TS svm_sc8xx \ - SXNI855T TOP860 TQM823L TQM823L_LCD \ - TQM850L TQM855L TQM860L v37 \ + CCM cogent_mpc8xx DUET_ADS ESTEEM192E \ + ETX094 ELPT860 FADS823 FADS850SAR \ + FADS860T FLAGADM FPS850L GEN860T \ + GEN860T_SC GENIETV GTH hermes \ + IAD210 ICU862_100MHz IP860 IVML24 \ + IVML24_128 IVML24_256 IVMS8 IVMS8_128 \ + IVMS8_256 KUP4K LANTEC lwmon \ + MBX MBX860T MHPC MPC86xADS \ + MVS1 NETVIA NETVIA_V2 NX823 \ + pcu_e QS823 QS850 QS860T \ + R360MPI RBC823 rmu RPXClassic \ + RPXlite RRvision SM850 SPD823TS \ + svm_sc8xx SXNI855T TOP860 TQM823L \ + TQM823L_LCD TQM850L TQM855L TQM860L \ + v37 \ " ######################################################################### @@ -99,7 +99,7 @@ LIBS = lib_generic/libgeneric.a LIBS += board/$(BOARDDIR)/lib$(BOARD).a LIBS += cpu/$(CPU)/lib$(CPU).a LIBS += lib_$(ARCH)/lib$(ARCH).a -LIBS += fs/jffs2/libjffs2.a fs/fdos/libfdos.a fs/fat/libfat.a +LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a LIBS += net/libnet.a LIBS += disk/libdisk.a LIBS += rtc/librtc.a @@ -249,7 +249,12 @@ TOP5200_config: unconfig AdderII_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx adderII -ADS860_config: unconfig +ADS860_config \ +DUET_ADS_config \ +FADS823_config \ +FADS850SAR_config \ +MPC86xADS_config \ +FADS860T_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx fads AMX860_config : unconfig @@ -279,12 +284,6 @@ ESTEEM192E_config: unconfig ETX094_config : unconfig @./mkconfig $(@:_config=) ppc mpc8xx etx094 -FADS823_config \ -FADS850SAR_config \ -MPC86xADS_config \ -FADS860T_config: unconfig - @./mkconfig $(@:_config=) ppc mpc8xx fads - FLAGADM_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx flagadm @@ -202,7 +202,7 @@ Directory Hierarchy: - board/Marvell/db64460 Files specific to db64460 board - board/mbx8xx Files specific to MBX boards - board/mpc8260ads - Files specific to MPC8260ADS and PQ2FADS-ZU boards + Files specific to MPC826xADS and PQ2FADS-ZU/VR boards - board/mpc8540ads Files specific to MPC8540ADS boards - board/mpc8560ads @@ -370,7 +370,7 @@ The following options need to be configured: CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900, CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850, CONFIG_QS823, CONFIG_QS860T, CONFIG_DB64360, - CONFIG_DB64460 + CONFIG_DB64460, CONFIG_DUET_ADS ARM based boards: ----------------- @@ -407,7 +407,7 @@ The following options need to be configured: CONFIG_ADSTYPE Possible values are: CFG_8260ADS - original MPC8260ADS - CFG_8266ADS - MPC8266ADS (untested) + CFG_8266ADS - MPC8266ADS CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR @@ -2004,7 +2004,7 @@ configurations; the following names are supported: at91rm9200dk_config omap1510inn_config MPC8260ADS_config omap1610inn_config ZPC1900_config MPC8540ADS_config MPC8560ADS_config QS850_config QS823_config - QS860T_config + QS860T_config DUET_ADS_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for @@ -3158,6 +3158,13 @@ Please note that U-Boot is implemented in C (and to some small parts in Assembler); no C++ is used, so please do not use C++ style comments (//) in your code. +Please also stick to the following formatiing rules: +- remove any trailing white space +- use TAB characters for indentation, not spaces +- make sure NOT to use DOS '\r\n' line feeds +- do not add more than 2 empty lines to source files +- do not add trailing empty lines to source files + Submissions which do not conform to the standards may be returned with a request to reformat the changes. diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index a7682ba338..61f7031b21 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -1,6 +1,9 @@ /* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * (C) Copyright 2003 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/fads/config.mk b/board/fads/config.mk index bad02f2015..dcf83fbea7 100644 --- a/board/fads/config.mk +++ b/board/fads/config.mk @@ -1,7 +1,9 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com +# # See file CREDITS for list of people who contributed to this # project. # @@ -22,9 +24,11 @@ # # -# Motorola old MPC821/860ADS, MPC8xxFADS, and new MPC866ADS boards +# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET +# (MPC87x/88x) ADS boards # TEXT_BASE = 0xFE000000 -#TEXT_BASE = 0x02800000 -#OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads +HOST_CFLAGS += -I$(TOPDIR)/board/fads +HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads diff --git a/board/fads/fads.c b/board/fads/fads.c index aca7b287e8..3083740452 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -1,7 +1,9 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -21,15 +23,16 @@ * MA 02111-1307 USA */ -#include <common.h> #include <config.h> +#include <common.h> #include <mpc8xx.h> -#include "fads.h" - -/* ------------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF +/* ========================================================================= */ + +#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */ + #if defined(CONFIG_DRAM_50MHZ) /* 50MHz tables */ static const uint dram_60ns[] = @@ -184,105 +187,6 @@ static const uint edo_70ns[] = #endif /* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -#if defined(CONFIG_FADS) && !defined(CONFIG_MPC86xADS) -static void checkdboard(void) -{ - /* get db type from BCSR 3 */ - uint k = (*((uint *)BCSR3) >> 24) & 0x3f; - - printf(" with db "); - - switch(k) { - case 0x03 : - puts ("MPC823"); - break; - case 0x20 : - puts ("MPC801"); - break; - case 0x21 : - puts ("MPC850"); - break; - case 0x22 : - puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); - break; - case 0x23 : - puts ("MPC860SAR"); - break; - case 0x24 : - case 0x2A : - puts ("MPC860T"); - break; - case 0x3F : - puts ("MPC850SAR"); - break; - default : printf("0x%x", k); - } -} -#endif /* defined(CONFIG_FADS) && !defined(CONFIG_MPC86xADS) */ - -int checkboard (void) -{ - /* get revision from BCSR 3 */ - uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) - | (((*((uint *) BCSR3) >> 19) & 1) << 2) - | (((*((uint *) BCSR3) >> 16) & 3)); - - puts ("Board: "); - -#ifdef CONFIG_FADS -# ifdef CONFIG_MPC86xADS - puts ("MPC86xADS"); -# else - puts ("FADS"); - checkdboard (); -# endif /* !CONFIG_MPC86xADS */ - printf (" rev "); - - switch (r) { - case 0x00: - puts ("ENG\n"); - break; - case 0x01: - puts ("PILOT\n"); - break; - default: - printf ("unknown (0x%x)\n", r); - return (-1); - } -#endif /* CONFIG_FADS */ - -#ifdef CONFIG_ADS - printf ("ADS rev "); - - switch (r) { - case 0x00: - puts ("ENG - this board sucks, check the errata, not supported\n"); - return -1; - case 0x01: - puts ("PILOT - warning, read errata \n"); - break; - case 0x02: - puts ("A - warning, read errata \n"); - break; - case 0x03: - puts ("B \n"); - break; - default: - printf ("unknown revision (0x%x)\n", r); - return (-1); - } -#endif /* CONFIG_ADS */ - - return 0; -} - -/* ------------------------------------------------------------------------- */ static long int dram_size (long int *base, long int maxsize) { volatile long int *addr=base; @@ -425,9 +329,11 @@ static void _dramdisable(void) /* maybe we should turn off upma here or something */ } +#endif /* !CONFIG_DUET_ADS */ -#ifdef CONFIG_FADS -/* SDRAM SUPPORT (FADS ONLY) */ +/* ========================================================================= */ + +#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ #if defined(CONFIG_SDRAM_100MHZ) @@ -728,15 +634,18 @@ static int initsdram(uint base, uint *noMbytes) } } -/* SDRAM SUPPORT (FADS ONLY) */ #endif /* CONFIG_FADS */ +/* ========================================================================= */ + long int initdram (int board_type) { uint sdramsz = 0; /* size of sdram in Mbytes */ uint base = 0; /* base of dram in bytes */ uint m = 0; /* size of dram in Mbytes */ +#ifndef CONFIG_DUET_ADS uint k, s; +#endif #ifdef CONFIG_FADS if (!initsdram (0x00000000, &sdramsz)) { @@ -744,7 +653,7 @@ long int initdram (int board_type) printf ("(%u MB SDRAM) ", sdramsz); } #endif - +#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */ k = (*((uint *) BCSR2) >> 23) & 0x0f; switch (k & 0x3) { @@ -795,17 +704,9 @@ long int initdram (int board_type) _dramdisable (); m = 0; } - +#endif /* !CONFIG_DUET_ADS */ m += sdramsz; /* add sdram size to total */ - if (!m) { - /******************************** - *DRAM ERROR, HALT PROCESSOR - *********************************/ - while (1); - return -1; - } - return (m << 20); } @@ -819,6 +720,105 @@ int testdram (void) return (0); } +/* ========================================================================= */ + +/* + * Check Board Identity: + */ + +#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) +static void checkdboard(void) +{ + /* get db type from BCSR 3 */ + uint k = (*((uint *)BCSR3) >> 24) & 0x3f; + + puts (" with db "); + + switch(k) { + case 0x03 : + puts ("MPC823"); + break; + case 0x20 : + puts ("MPC801"); + break; + case 0x21 : + puts ("MPC850"); + break; + case 0x22 : + puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); + break; + case 0x23 : + puts ("MPC860SAR"); + break; + case 0x24 : + case 0x2A : + puts ("MPC860T"); + break; + case 0x3F : + puts ("MPC850SAR"); + break; + default : printf("0x%x", k); + } +} +#endif /* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */ + +int checkboard (void) +{ + /* get revision from BCSR 3 */ + uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) + | (((*((uint *) BCSR3) >> 19) & 1) << 2) + | (((*((uint *) BCSR3) >> 16) & 3)); + + puts ("Board: "); + +#if defined(CONFIG_MPC86xADS) + puts ("MPC86xADS"); +#elif defined(CONFIG_DUET_ADS) + puts ("DUET ADS"); + r = 0; /* I've got NR (No Revision) board */ +#elif defined(CONFIG_FADS) + puts ("FADS"); + checkdboard (); +#else + puts ("ADS"); +#endif + puts (" rev "); + + switch (r) { +#if defined(CONFIG_ADS) + case 0x00: + puts ("ENG - this board sucks, check the errata, not supported\n"); + return -1; + case 0x01: + puts ("PILOT - warning, read errata \n"); + break; + case 0x02: + puts ("A - warning, read errata \n"); + break; + case 0x03: + puts ("B \n"); + break; +#elif defined(CONFIG_DUET_ADS) + case 0x00: + puts ("NR\n"); + break; +#else /* FADS and newer */ + case 0x00: + puts ("ENG\n"); + break; + case 0x01: + puts ("PILOT\n"); + break; +#endif /* CONFIG_ADS */ + default: + printf ("unknown (0x%x)\n", r); + return -1; + } + + return 0; +} + +/* ========================================================================= */ #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) @@ -964,7 +964,7 @@ int pcmcia_init(void) #endif /* CFG_CMD_PCMCIA */ -/* ------------------------------------------------------------------------- */ +/* ========================================================================= */ #ifdef CFG_PC_IDE_RESET @@ -988,4 +988,3 @@ void ide_set_reset(int on) } #endif /* CFG_PC_IDE_RESET */ -/* ------------------------------------------------------------------------- */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 0bd8e84035..668b906d56 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -1,7 +1,14 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, + * and Dan Malek + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * This header file contains values common to all FADS family boards. + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,23 +29,435 @@ */ /**************************************************************************** - * FLASH Memory Map as used by FADS Monitor: + * Flash Memory Map as used by U-Boot: * * Start Address Length * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- - * | MON8xx code | 0xFE00_0100 Reset Vector - * +-----------------------+ 0xFE0?_???? - * | (unused) | - * +-----------------------+ 0xFE01_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0xFE01_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0xFE01_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0xFE01_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0xFE02_0000 (sector border) ----------------- - * | Autostart Header | | Applications + * | | 0xFE00_0100 Reset Vector + * + + 0xFE0?_???? + * | U-Boot code | + * | | + * +-----------------------+ 0xFE04_0000 (sector border) + * | | + * | | + * | U-Boot environment | + * | | ^ + * | | | U-Boot + * +=======================+ 0xFE08_0000 (sector border) ----------------- + * | Available | | Applications * | ... | v * *****************************************************************************/ +/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ +/* in general, we always know this for FADS+new ADS anyway */ +#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "dhcp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootm" + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * New MPC86xADS and Duet provide two Ethernet connectivity options: + * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on + * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have + * got FEC so FEC is the default. + */ +#ifndef CONFIG_ADS +#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ +#define CONFIG_FEC_ENET /* Use FEC ethernet */ +#else /* Old ADS has not got FEC option */ +#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ +#undef CONFIG_FEC_ENET /* No FEC ethernet */ +#endif /* !CONFIG_ADS */ + +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#ifdef CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY +#endif + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) +#endif /* !CONFIG_COMMANDS */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */ +#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +#elif defined(CONFIG_FADS) /* Old/new FADS */ +#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ +#else /* Old ADS */ +#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ +#endif + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#if (CFG_SDRAM_SIZE) +#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ +#else +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ +#endif /* CFG_SDRAM_SIZE */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Flash organization + */ +#define CFG_FLASH_BASE TEXT_BASE +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ +#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ +#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * I2C configuration + */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ +#define CFG_I2C_SLAVE 0x7F +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/OR0 (Flash) + * BR1/OR1 (BCSR) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + +#define BCSR_ADDR ((uint) 0xFF080000) + +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) + +/* BCSRx - Board Control and Status Registers */ +#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define PCMCIA_MEM_ADDR ((uint)0xFF020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) +#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) +#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) +#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) + +/* + * (F)ADS bitvalues by Helmut Buchsbaum + * + * See User's Manual for a proper + * description of the following structures + */ + +#define BCSR0_ERB ((uint)0x80000000) +#define BCSR0_IP ((uint)0x40000000) +#define BCSR0_BDIS ((uint)0x10000000) +#define BCSR0_BPS_MASK ((uint)0x0C000000) +#define BCSR0_ISB_MASK ((uint)0x01800000) +#define BCSR0_DBGC_MASK ((uint)0x00600000) +#define BCSR0_DBPC_MASK ((uint)0x00180000) +#define BCSR0_EBDF_MASK ((uint)0x00060000) + +#define BCSR1_FLASH_EN ((uint)0x80000000) +#define BCSR1_DRAM_EN ((uint)0x40000000) +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDEN ((uint)0x10000000) +#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) +#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) +#define BCSR1_BCSR_EN ((uint)0x02000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP_MASK ((uint)0x00300000) +#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_SDRAM_EN ((uint)0x00020000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) + +#define BCSR1_PCCVCCON BCSR1_PCCVCC0 + +#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) +#define BCSR2_DRAM_PD_SHIFT 23 +#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) +#define BCSR2_DBREVNR_MASK ((uint)0x00030000) + +#define BCSR3_DBID_MASK ((ushort)0x3800) +#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) +#define BCSR3_BREVNR0 ((ushort)0x0080) +#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) +#define BCSR3_BREVN1 ((ushort)0x0008) +#define BCSR3_BREVN2_MASK ((ushort)0x0003) + +#define BCSR4_ETHLOOP ((uint)0x80000000) +#define BCSR4_TFPLDL ((uint)0x40000000) +#define BCSR4_TPSQEL ((uint)0x20000000) +#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) +#define BCSR4_FETH_EN ((uint)0x08000000) +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#define BCSR4_FETHFDE ((uint)0x02000000) +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#define BCSR4_FETHRST ((uint)0x00200000) + +#ifdef CONFIG_MPC823 +#define BCSR4_USB_EN ((uint)0x08000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860SAR +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860SAR */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETH_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_USB_SPEED ((uint)0x04000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VCCO ((uint)0x02000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHFDE ((uint)0x02000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_ON ((uint)0x00800000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_RST ((uint)0x00200000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHRST ((uint)0x00200000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_MODEM_EN ((uint)0x00100000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC850 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC850 */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ +#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850) +#define PCMCIA_SLOT_A 1 +#endif + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +#undef CONFIG_ATAPI +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +#define CFG_ATA_IDE0_OFFSET 0x0000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0000 + +#define CONFIG_DISK_SPINUP_TIME 1000000 +#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index a581e6f945..6ebd46fa47 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -38,6 +38,11 @@ #include <cramfs/cramfs_fs.h> +extern int cramfs_check (struct part_info *info); +extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename); +extern int cramfs_ls (struct part_info *info, char *filename); +extern int cramfs_info (struct part_info *info); + static int part_num=0; #ifndef CFG_JFFS_CUSTOM_PART diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index 2ef13212ec..3504422901 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -45,24 +45,16 @@ static char *cpu_warning = "\n " \ #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ !defined(CONFIG_MPC862)) +static int check_CPU (long clock, uint pvr, uint immr) +{ + char *id_str = # if defined(CONFIG_MPC855) -# define ID_STR "PC855" -# elif defined(CONFIG_MPC852T) -# define ID_STR "PC852T" -# elif defined(CONFIG_MPC859T) -# define ID_STR "PC859T" -# elif defined(CONFIG_MPC859DSL) -# define ID_STR "PC859DSL" + "PC855"; # elif defined(CONFIG_MPC860P) -# define ID_STR "PC860P" -# elif defined(CONFIG_MPC866T) -# define ID_STR "PC866T" + "PC860P"; # else -# define ID_STR "PC86x" /* unknown 86x chip */ + NULL; # endif - -static int check_CPU (long clock, uint pvr, uint immr) -{ volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); uint k, m; char buf[32]; @@ -78,12 +70,12 @@ static int check_CPU (long clock, uint pvr, uint immr) k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); m = 0; + /* + * Some boards use sockets so different CPUs can be used. + * We have to check chip version in run time. + */ switch (k) { -#ifdef CONFIG_MPC866_et_al - /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ - case 0x08000003: pre = 'M'; suf = ""; m = 1; break; -#else - case 0x00020001: pre = 'p'; suf = ""; break; + case 0x00020001: pre = 'P'; suf = ""; break; case 0x00030001: suf = ""; break; case 0x00120003: suf = "A"; break; case 0x00130003: suf = "A3"; break; @@ -98,18 +90,38 @@ static int check_CPU (long clock, uint pvr, uint immr) case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; case 0x05010000: suf = "D3"; m = 1; break; case 0x05020000: suf = "D4"; m = 1; break; - case 0x08000003: suf = ""; m = 1; break; /* this value is not documented anywhere */ case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; -#endif + /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ + case 0x08000003: pre = 'M'; suf = ""; m = 1; + if (id_str == NULL) + id_str = +# if defined(CONFIG_MPC852T) + "PC852T"; +# elif defined(CONFIG_MPC859T) + "PC859T"; +# elif defined(CONFIG_MPC859DSL) + "PC859DSL"; +# elif defined(CONFIG_MPC866T) + "PC866T"; +# else + "PC866x"; /* Unknown chip from MPC866 family */ +# endif + break; + case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; + if (id_str == NULL) + id_str = "PC885"; /* 870/875/880/885 */ + break; default: suf = NULL; break; } + if (id_str == NULL) + id_str = "PC86x"; /* Unknown 86x chip */ if (suf) - printf ("%c" ID_STR "%sZPnn%s", pre, mid, suf); + printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); else - printf ("unknown M" ID_STR " (0x%08x)", k); + printf ("unknown M%s (0x%08x)", id_str, k); printf (" at %s MHz:", strmhz (buf, clock)); @@ -471,36 +483,46 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Get timebase clock frequency (like cpu_clk in Hz) * - * See table 15-5 pp. 15-16, and SCCR[RTSEL] pp. 15-27. + * See sections 14.2 and 14.6 of the User's Manual */ unsigned long get_tbclk (void) { DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (volatile immap_t *) CFG_IMMR; - ulong oscclk, factor; + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); + ulong oscclk, factor, pll; - if (immr->im_clkrst.car_sccr & SCCR_TBS) { + if (immap->im_clkrst.car_sccr & SCCR_TBS) { return (gd->cpu_clk / 16); } -#define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) -#ifdef CONFIG_MPC866_et_al - /* MFN - MFI + ------- - MFD + 1 - factor = ----------------- - (PDF + 1) * 2^S - */ - factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ - (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); -#else - factor = PLPRCR_val(MF)+1; -#endif + pll = immap->im_clkrst.car_plprcr; + +#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) + + /* + * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication + * factor is calculated as follows: + * + * MFN + * MFI + ------- + * MFD + 1 + * factor = ----------------- + * (PDF + 1) * 2^S + * + * For older chips, it's just MF field of PLPRCR plus one. + */ + if ((immr & 0xFFFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ + factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ + (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); + } else { + factor = PLPRCR_val(MF)+1; + } oscclk = gd->cpu_clk / factor; - if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { + if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { return (oscclk / 4); } return (oscclk / 16); diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 8f06dd1ab9..cbf21268be 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -42,6 +42,7 @@ void cpu_init_f (volatile immap_t * immr) { #ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; + ulong mfmask; #endif ulong reg; @@ -86,16 +87,23 @@ void cpu_init_f (volatile immap_t * immr) /* If CFG_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CFG_PLPRCR over car_plprcr, - * otherwise OR in CFG_PLPRCR so we do not change the currentMF + * otherwise OR in CFG_PLPRCR so we do not change the current MF * field value. + * + * For newer (starting MPC866) chips PLPRCR layout is different. */ -#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) - reg = CFG_PLPRCR; /* reset control bits */ -#else - reg = immr->im_clkrst.car_plprcr; - reg &= PLPRCR_MF_MSK; /* isolate MF field */ - reg |= CFG_PLPRCR; /* reset control bits */ -#endif + if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) + mfmask = PLPRCR_MFACT_MSK; + else + mfmask = PLPRCR_MF_MSK; + + if ((CFG_PLPRCR & mfmask) != 0) + reg = CFG_PLPRCR; /* reset control bits */ + else { + reg = immr->im_clkrst.car_plprcr; + reg &= mfmask; /* isolate MF-related fields */ + reg |= CFG_PLPRCR; /* reset control bits */ + } immr->im_clkrst.car_plprcr = reg; /* diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 6b579c94d6..811ac79719 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -217,8 +217,10 @@ static int fec_init(struct eth_device* dev, bd_t * bd) volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile fec_t *fecp = &(immr->im_cpm.cp_fec); -#if defined(CONFIG_FADS) && \ - ( defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al) ) +#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ +#if defined(CONFIG_DUET_ADS) + *(vu_char *)BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); +#else /* configure FADS for fast (FEC) ethernet, half-duplex */ /* The LXT970 needs about 50ms to recover from reset, so * wait for it by discovering the PHY before leaving eth_init(). @@ -234,7 +236,8 @@ static int fec_init(struct eth_device* dev, bd_t * bd) *bcsr4 |= BCSR4_FETHRST; udelay (10); } -#endif +#endif /* CONFIG_DUET_ADS */ +#endif /* CONFIG_FADS */ /* Whack a reset. * A delay is required between a reset of the FEC block and * initialization of other FEC registers because the reset takes @@ -350,7 +353,20 @@ static int fec_init(struct eth_device* dev, bd_t * bd) */ fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; -#if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) +#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ + immr->im_ioport.iop_papar |= 0xf830; + immr->im_ioport.iop_padir |= 0x0830; + immr->im_ioport.iop_padir &= ~0xf000; + immr->im_cpm.cp_pbpar |= 0x00001001; + immr->im_cpm.cp_pbdir &= ~0x00001001; + immr->im_ioport.iop_pcpar |= 0x000c; + immr->im_ioport.iop_pcdir &= ~0x000c; + immr->im_ioport.iop_pdpar |= 0x0080; + immr->im_ioport.iop_pddir &= ~0x0080; + immr->im_cpm.cp_pepar |= 0x00000003; + immr->im_cpm.cp_pedir |= 0x00000003; + immr->im_cpm.cp_peso &= ~0x00000003; +#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) /* Configure all of port D for MII. */ immr->im_ioport.iop_pdpar = 0x1fff; @@ -465,7 +481,7 @@ static uint phytype; #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ - +#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ /* send command to phy using mii, wait for result */ static uint @@ -541,6 +557,9 @@ mii_discover_phy(void) case PHY_ID_LSI80225B: printf("LSI L80225/B\n"); break; + case PHY_ID_DM9161: + printf("Davicom DM9161\n"); + break; default: printf("0x%08x\n", phytype); break; @@ -614,7 +633,20 @@ void mii_init (void) */ fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; -#if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) +#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ + immr->im_ioport.iop_papar |= 0xf830; + immr->im_ioport.iop_padir |= 0x0830; + immr->im_ioport.iop_padir &= ~0xf000; + immr->im_cpm.cp_pbpar |= 0x00001001; + immr->im_cpm.cp_pbdir &= ~0x00001001; + immr->im_ioport.iop_pcpar |= 0x000c; + immr->im_ioport.iop_pcdir &= ~0x000c; + immr->im_ioport.iop_pdpar |= 0x0080; + immr->im_ioport.iop_pddir &= ~0x0080; + immr->im_cpm.cp_pepar |= 0x00000003; + immr->im_cpm.cp_pedir |= 0x00000003; + immr->im_cpm.cp_peso &= ~0x00000003; +#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) /* Configure all of port D for MII. */ immr->im_ioport.iop_pdpar = 0x1fff; diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c index 558dc09c07..20e7012c37 100644 --- a/cpu/mpc8xx/interrupts.c +++ b/cpu/mpc8xx/interrupts.c @@ -274,11 +274,21 @@ void timer_interrupt_cpu (struct pt_regs *regs) /* Reset Timer Expired and Timers Interrupt Status */ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; __asm__ ("nop"); -#ifdef CONFIG_MPC866_et_al - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; -#else - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST; -#endif + /* + Clear TEXPS (and TMIST on older chips). SPLSS (on older + chips) is cleared too. + + Bitwise OR is a read-modify-write operation so ALL bits + which are cleared by writing `1' would be cleared by + operations like + + immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; + + The same can be achieved by simple writing of the PLPRCR + to itself. If a bit value should be preserved, read the + register, ZERO the bit and write, not OR, the result back. + */ + immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; } /************************************************************************/ diff --git a/cpu/nios/Makefile b/cpu/nios/Makefile index baf752f170..a9adbc593c 100644 --- a/cpu/nios/Makefile +++ b/cpu/nios/Makefile @@ -27,7 +27,7 @@ LIB = lib$(CPU).a START = start.o AOBJS = traps.o -OBJS = cpu.o interrupts.o serial.o +OBJS = cpu.o interrupts.o serial.o asmi.o all: .depend $(START) $(LIB) diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c new file mode 100644 index 0000000000..ce2863e5c6 --- /dev/null +++ b/cpu/nios/asmi.c @@ -0,0 +1,695 @@ +/* + * (C) Copyright 2003, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_NIOS_ASMI) +#include <command.h> +#include <nios-io.h> + +#if !defined(CFG_NIOS_ASMIBASE) +#error "*** CFG_NIOS_ASMIBASE not defined ***" +#endif + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "asmi - read/write Cyclone ASMI configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "asmi erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "asmi info\n"\ + " - display ASMI device information.\n"\ + "asmi protect on | off\n"\ + " - turn device protection on or off.\n"\ + "asmi read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "asmi write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "asmi verify addr offset count\n"\ + " - verify count bytes at offset from addr.\n" + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define ASMI_WRITE_ENA 0x06 /* Write enable */ +#define ASMI_WRITE_DIS 0x04 /* Write disable */ +#define ASMI_READ_STAT 0x05 /* Read status */ +#define ASMI_READ_BYTES 0x03 /* Read bytes */ +#define ASMI_READ_ID 0xab /* Read silicon id */ +#define ASMI_WRITE_STAT 0x01 /* Write status */ +#define ASMI_WRITE_BYTES 0x02 /* Write bytes */ +#define ASMI_ERASE_BULK 0xc7 /* Erase entire device */ +#define ASMI_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define ASMI_STATUS_WIP (1<<0) /* Write in progress */ +#define ASMI_STATUS_WEL (1<<1) /* Write enable latch */ + +static nios_asmi_t *asmi = (nios_asmi_t *)CFG_NIOS_ASMIBASE; + +/*********************************************************************** + * Device access + ***********************************************************************/ +static void asmi_cs (int assert) +{ + if (assert) { + asmi->control |= NIOS_ASMI_SSO; + } else { + /* Let all bits shift out */ + while ((asmi->status & NIOS_ASMI_TMT) == 0) + ; + asmi->control &= ~NIOS_ASMI_SSO; + } +} + +static void asmi_tx (unsigned char c) +{ + while ((asmi->status & NIOS_ASMI_TRDY) == 0) + ; + asmi->txdata = c; +} + +static int asmi_rx (void) +{ + while ((asmi->status & NIOS_ASMI_RRDY) == 0) + ; + return (asmi->rxdata); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char asmi_bitrev( unsigned char c ) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void asmi_rcv (unsigned char *dst, int len) +{ + while (len--) { + asmi_tx (0); + *dst++ = asmi_rx (); + } +} + +static void asmi_rrcv (unsigned char *dst, int len) +{ + while (len--) { + asmi_tx (0); + *dst++ = asmi_bitrev (asmi_rx ()); + } +} + +static void asmi_snd (unsigned char *src, int len) +{ + while (len--) { + asmi_tx (*src++); + asmi_rx (); + } +} + +static void asmi_rsnd (unsigned char *src, int len) +{ + while (len--) { + asmi_tx (asmi_bitrev (*src++)); + asmi_rx (); + } +} + +static void asmi_wr_enable (void) +{ + asmi_cs (1); + asmi_tx (ASMI_WRITE_ENA); + asmi_rx (); + asmi_cs (0); +} + +static unsigned char asmi_status_rd (void) +{ + unsigned char status; + + asmi_cs (1); + asmi_tx (ASMI_READ_STAT); + asmi_rx (); + asmi_tx (0); + status = asmi_rx (); + asmi_cs (0); + return (status); +} + +static void asmi_status_wr (unsigned char status) +{ + asmi_wr_enable (); + asmi_cs (1); + asmi_tx (ASMI_WRITE_STAT); + asmi_rx (); + asmi_tx (status); + asmi_rx (); + asmi_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ +typedef struct asmi_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}asmi_devinfo_t; + +static struct asmi_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +static asmi_devinfo_t *asmi_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct asmi_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = ASMI_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rcv (buf,1); + asmi_cs (0); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +static unsigned asmi_cfgsz (void) +{ + unsigned sz = 0; + unsigned char buf[128]; + unsigned char *p; + + /* Read in the first 128 bytes of the device */ + buf[0] = ASMI_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rrcv (buf, sizeof(buf)); + asmi_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +static int asmi_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("asmi erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = ASMI_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_wr_enable (); + asmi_cs (1); + asmi_snd (buf,4); + asmi_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (asmi_status_rd() & ASMI_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +static int asmi_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + + buf[0] = ASMI_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rrcv ((unsigned char *)addr, cnt); + asmi_cs (0); + + return (0); +} + +static +int asmi_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<<dev->sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = ASMI_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_wr_enable (); + asmi_cs (1); + asmi_snd (buf,4); + asmi_rsnd ((unsigned char *)addr, wrcnt); + asmi_cs (0); + + /* Wait for write to complete */ + while (asmi_status_rd() & ASMI_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +static +int asmi_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + asmi_read ((ulong)buf, off, rdcnt); + for (i=0; i<rdcnt; i++) { + if (*end != buf[i]) { + *err = end - start; + return(-1); + } + end++; + } + cnt -= rdcnt; + off += rdcnt; + } + return (0); +} + +static int asmi_sect_erased (int sect, unsigned *offset, + struct asmi_devinfo_t *dev) +{ + unsigned char buf[128]; + unsigned off, end; + unsigned sectsz; + int i; + + sectsz = (1 << dev->sz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + asmi_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_asmi_info (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = asmi_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & ASMI_STATUS_WIP) ? 1 : 0, + (stat & ASMI_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = asmi_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; i<dev->num_sects; i++) { + erased = asmi_sect_erased (i, &tmp, dev); + printf (" %d: %06x ", + i, i*(1<<dev->sz_sect) ); + if (erased) + printf ("erased\n"); + else + printf ("data @ 0x%06x\n", tmp); + } + + return; +} + +static +void do_asmi_erase (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: asmi erase sect [end]\n"); + return; + } + if ((asmi_status_rd() & dev->prot_mask) != 0) { + printf ( "asmi: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("asmi: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + asmi_erase (start, end); + + return; +} + +static +void do_asmi_protect (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: asmi protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = asmi_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("asmi: unknown protection: %s\n", argv[2]); + return; + } + asmi_status_wr (stat); + return; +} + +static +void do_asmi_read (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: asmi read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + asmi_read (addr, off, cnt); + + return; +} + +static +void do_asmi_write (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: asmi write addr offset count\n"); + return; + } + if ((asmi_status_rd() & dev->prot_mask) != 0) { + printf ( "asmi: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + asmi_write (addr, off, cnt); + if (asmi_verify (addr, off, cnt, &err) != 0) + printf ("asmi: write error at offset %06lx\n", err); + + return; +} + +static +void do_asmi_verify (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: asmi verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (asmi_verify (addr, off, cnt, &err) != 0) + printf ("asmi: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_asmi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (argc < 2) { + printf ("Usage:%s", LONG_HELP); + return (0); + } + + if (!dev) { + printf ("asmi: device not found.\n"); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_asmi_info ( dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_asmi_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_asmi_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_asmi_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_asmi_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_asmi_verify (dev, argc, argv); + } else { + printf ("asmi: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( asmi, 5, 0, do_asmi, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_ASMI */ diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c index 5cf1883bc5..d2bb2c09d1 100644 --- a/cpu/nios/cpu.c +++ b/cpu/nios/cpu.c @@ -37,8 +37,8 @@ int checkcpu (void) printf ("CPU: "); printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); rev_major = (val>>12) & 0x07; - rev_minor = val & 0x0f; - printf ("Rev. %d.%02d (0x%04x)", rev_major, rev_minor, + rev_minor = (val>>4) & 0x0ff; + printf ("Rev. %d.%d (0x%04x)", rev_major, rev_minor, val & 0xffff); if (rev_major == 0x08) printf (" [OpenCore (R) Plus]"); diff --git a/doc/README.dk1c20 b/doc/README.dk1c20 index b3a6b8bb0b..bf3b6995e1 100644 --- a/doc/README.dk1c20 +++ b/doc/README.dk1c20 @@ -2,7 +2,7 @@ Nios Development Kit Cyclone Editions - Last Update: October 15, 2003 + Last Update: January 2, 2004 ==================================================================== This file contains information regarding U-Boot and the Altera @@ -12,31 +12,41 @@ information see doc/README.nios. For those interested in contributing ... see HELP WANTED section in doc/README.nios. +Contents: -Files ------- + 1. Files + 2. Memory Organization + 3. Examples + 4. Programming U-Boot into FLASH with GERMS + 5. Active Serial Memory Interface (ASMI) Support + +==================================================================== + +1. Files +========= board/dk1c20/* include/configs/DK1C20.h -Memory Organization --------------------- +2. Memory Organization +======================= - -The heap is placed below the monitor (U-Boot code). - -Global data is placed below the heap. - -The stack is placed below global data (&grows down). + -The heap is placed below the monitor (U-Boot code). + -Global data is placed below the heap. + -The stack is placed below global data (&grows down). -Misc ------ +3. Examples +============ -The hello_world example works fine. +The hello_world example works fine. The default load address +is 0x0100_0000 (the start of SDRAM). -Programming U-Boot into FLASH with GERMS ------------------------------------------ -The current version of the DK-1C20 port occupies less than -60 KByte with network support disabled. So everything will fit -into a single flash sector. With network support (e.g. bootp, -tftpboot, ping, etc) the flash footprint is about 77K. +4. Programming U-Boot into FLASH with GERMS +============================================ +The current version of the DK-1C20 port with the default +configuration settings occupies about 81 KBytes of flash. +A minimal configuration occupies less than 60 KByte (asmi +and network support disabled). To program U-Boot into the DK-1C20 flash using GERMS do the following: @@ -51,10 +61,10 @@ see the following: U-Boot 1.0.0-pre (Oct 4 2003 - 07:39:24) - CPU: Nios-32 Rev. 3.08 (0x3018) + CPU: Nios-32 Rev. 3.3 (0x3038) Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14 Board: Altera Nios 1C20 Development Kit - In: serial + In: serial Out: serial Err: serial ==> @@ -63,18 +73,18 @@ see the following: 2. Quit nios-run and start your terminal application (e.g. start Hyperterminal or minicom). -3. From the U-Boot command prompt, erase a sector of flash at 0x40000: +3. From the U-Boot command prompt, erase flash 0x40000 to 0x 5ffff: - ==> erase 40000 4ffff + ==> erase 1:4-5 4. Download the u-boot code to RAM. When using Hyperterminal, do the following: - --From the u-boot command prompt start a binary download to SRAM: + a. From the u-boot command prompt start a binary download to SRAM: ==> loadb 800000 - --Download u-boot.bin using kermit. + b. Download u-boot.bin using kermit. 5. Copy the binary image from SRAM to flash: @@ -85,3 +95,59 @@ reset using the Standard-32 configuration. To start U-Boot with the Safe-32 configuration, enter the following GERMS command: + g 40000 + +5. Active Serial Memory Interface (ASMI) Support +================================================ +ASMI is fully supported in U-Boot. Please note that ASMI is supported +only on Cyclone devices. Do not expect ASMI to work with Stratix or +APEX devices. + + ************* IMPORTANT ************* + =================================================== + IN ORDER FOR THE NIOS ASMI TO OPERATE PROPERLY, THE + CYCLONE DEVICE MUST BE CONFIGURED USING JTAG OR ASMI. + +There are two techniques you can use to bootstrap the ASMI. The +first is to use the program_epcs utility that is part of Altera's SDK. +But I've found program_epcs to be slow and cumbersome at best. + +An undocumented alternative is to use the Quartus device programing +interface: + + 1. Select "Active Serial" mode. + + 2. Choose the xxx.pof file. For example, for the standard_32 + configuration use the "standard_32.pof" file. + + 3. Attach your ByteBlaster to J28. Make sure you have the + cable attached properly -- the orientation of J28 is + different than J24 (the JTAG header). On J28, pin 1 is on + the bottom row, left-most pin. + + 4. Press and hold the "Power-On Reset" switch (SW10). You will + see the green "Loading" and red "Error" LEDs (LED3 and LED4) + in the on state. + + 5. While holding down the "Power-On Reset" switch, start the + programming sequence. This only takes about 10 seconds. + + 6. After programming is complete, release the "Power-On Reset" + switch. The Cyclone device should now load its configuration + from the EPCS4 (U59). The green "User" LED (LED 1) should be + blinking if the device was successfully loaded via ASMI. + + 7. Remove the ByteBlaster cable. The cable must be removed to + allow the Nios ASMI access to the EPCS4 device. + +After you have successfully programmed a configuration into the +EPCS4, the ASMI will be used to load the Cyclone configuration +unless the "Force Safe" switch (SW9) is pressed. + +NOTE: To maximize the amount of space available for program use, +you can enable configuration compression in Quartus. With compression +enabled, the size of the standard_32 configuration data is +approximately 192 KBytes. + +To use the U-Boot ASMI commands, try typing "help asmi" at the +command prompt. The command "asmi info" will show the current +status of the ASMI. diff --git a/doc/README.nios b/doc/README.nios index 8765df7391..af21b3e427 100644 --- a/doc/README.nios +++ b/doc/README.nios @@ -1,7 +1,7 @@ U-Boot for Nios-32 - Last Update: November 30, 2003 + Last Update: January 2, 2004 ==================================================================== This file contains information regarding U-Boot and the Altera @@ -31,7 +31,7 @@ For those interested in contributing ... see HELP WANTED below. U-Boot has been successfully tested on the Nios Cyclone development board using both the 'safe' and 'standard 32' configurations with -Nios CPU revision 3.08 (CPU_ID = 0x3008). U-Boot can be used with +Nios CPU revision 3.1 (CPU_ID = 0x3018). U-Boot can be used with or without the GERMS monitor. The initial version of U-Boot for the Cyclone development kit is about 60 Kbyte and will fit in a single sector of on-board FLASH. Only the Nios 32-bit CPU is supported. @@ -55,9 +55,6 @@ sources (when altera silicon is not involved). This isn't really a problem as little, if any, of the Altera source contains features that are not already available in U-Boot. -The Nios port also does not use the long-winded peripheral -structure definitions from the Nios SDK. - 2. CONFIGURATION OPTIONS/SETTINGS ---------------------------------- @@ -103,6 +100,9 @@ CFG_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to CFG_NIOS_TMRMS -- the period of the timer in milliseconds. +CFG_NIOS_ASMIBASE -- the base address of the ASMI peripheral. + (standard-32: na_asmi_base). + 2.2 Differences in U-Boot Options/Settings ------------------------------------------- Some 'standard' U-Boot options/settings are treated differently in @@ -238,8 +238,6 @@ for those interested in contributing: -CompactFlash. Port & test CF/FAT. --ASMI support. Use ASMI for environment, etc. - -Bedbug. Develop bedbug for Nios ... or at least provide a disassemble command. diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index 1e3510461c..98ff567269 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -31,8 +31,9 @@ #include <asm/byteorder.h> #include <linux/stat.h> +#include <jffs2/jffs2.h> #include <jffs2/load_kernel.h> -#include "cramfs_fs.h" +#include <cramfs/cramfs_fs.h> /* These two macros may change in future, to provide better st_ino semantics. */ @@ -198,36 +199,6 @@ int cramfs_load (char *loadoffset, struct part_info *info, char *filename) (unsigned long) loadoffset); } -static char *mkmodestr (unsigned long mode, char *str) -{ - static const char *l = "xwr"; - int mask = 1, i; - char c; - - switch (mode & S_IFMT) { - case S_IFDIR: str[0] = 'd'; break; - case S_IFBLK: str[0] = 'b'; break; - case S_IFCHR: str[0] = 'c'; break; - case S_IFIFO: str[0] = 'f'; break; - case S_IFLNK: str[0] = 'l'; break; - case S_IFSOCK: str[0] = 's'; break; - case S_IFREG: str[0] = '-'; break; - default: str[0] = '?'; break; - } - - for (i = 0; i < 9; i++) { - c = l[i % 3]; - str[9 - i] = (mode & mask) ? c : '-'; - mask = mask << 1; - } - - if (mode & S_ISUID) str[3] = (mode & S_IXUSR) ? 's' : 'S'; - if (mode & S_ISGID) str[6] = (mode & S_IXGRP) ? 's' : 'S'; - if (mode & S_ISVTX) str[9] = (mode & S_IXOTH) ? 't' : 'T'; - str[10] = '\0'; - return str; -} - static int cramfs_list_inode (struct part_info *info, unsigned long offset) { struct cramfs_inode *inode = (struct cramfs_inode *) diff --git a/fs/cramfs/cramfs_fs.h b/fs/cramfs/cramfs_fs.h deleted file mode 100644 index 78cc9ecd3a..0000000000 --- a/fs/cramfs/cramfs_fs.h +++ /dev/null @@ -1,133 +0,0 @@ -#ifndef __CRAMFS_FS_H -#define __CRAMFS_FS_H - -/* Uncompression interfaces to the underlying zlib */ -int cramfs_uncompress_block (void *dst, void *src, int srclen); -int cramfs_uncompress_init (void); - -#define CRAMFS_MAGIC 0x28cd3d45 /* some random number */ -#define CRAMFS_SIGNATURE "Compressed ROMFS" - -/* - * Width of various bitfields in struct cramfs_inode. - * Primarily used to generate warnings in mkcramfs. - */ -#define CRAMFS_MODE_WIDTH 16 -#define CRAMFS_UID_WIDTH 16 -#define CRAMFS_SIZE_WIDTH 24 -#define CRAMFS_GID_WIDTH 8 -#define CRAMFS_NAMELEN_WIDTH 6 -#define CRAMFS_OFFSET_WIDTH 26 - -/* - * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs - * path length is 63 << 2 = 252. - */ -#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2) - -/* - * Reasonably terse representation of the inode data. - */ -struct cramfs_inode { - u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH; - /* SIZE for device files is i_rdev */ - u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH; - /* NAMELEN is the length of the file name, divided by 4 and - rounded up. (cramfs doesn't support hard links.) */ - /* OFFSET: For symlinks and non-empty regular files, this - contains the offset (divided by 4) of the file data in - compressed form (starting with an array of block pointers; - see README). For non-empty directories it is the offset - (divided by 4) of the inode of the first file in that - directory. For anything else, offset is zero. */ - u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH; -}; - -struct cramfs_info { - u32 crc; - u32 edition; - u32 blocks; - u32 files; -}; - -/* - * Superblock information at the beginning of the FS. - */ -struct cramfs_super { - u32 magic; /* 0x28cd3d45 - random number */ - u32 size; /* length in bytes */ - u32 flags; /* feature flags */ - u32 future; /* reserved for future use */ - u8 signature[16]; /* "Compressed ROMFS" */ - struct cramfs_info fsid; /* unique filesystem info */ - u8 name[16]; /* user-defined name */ - struct cramfs_inode root; /* root inode data */ -}; - -/* - * Feature flags - * - * 0x00000000 - 0x000000ff: features that work for all past kernels - * 0x00000100 - 0xffffffff: features that don't work for past kernels - */ -#define CRAMFS_FLAG_FSID_VERSION_2 0x00000001 /* fsid version #2 */ -#define CRAMFS_FLAG_SORTED_DIRS 0x00000002 /* sorted dirs */ -#define CRAMFS_FLAG_HOLES 0x00000100 /* support for holes */ -#define CRAMFS_FLAG_WRONG_SIGNATURE 0x00000200 /* reserved */ -#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400 /* shifted root fs */ - -/* - * Valid values in super.flags. Currently we refuse to mount - * if (flags & ~CRAMFS_SUPPORTED_FLAGS). Maybe that should be - * changed to test super.future instead. - */ -#define CRAMFS_SUPPORTED_FLAGS ( 0x000000ff \ - | CRAMFS_FLAG_HOLES \ - | CRAMFS_FLAG_WRONG_SIGNATURE \ - | CRAMFS_FLAG_SHIFTED_ROOT_OFFSET ) - -/* - * Since cramfs is little-endian, provide macros to swab the bitfields. - */ - -#ifndef __BYTE_ORDER -#if defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) -#define __BYTE_ORDER __LITTLE_ENDIAN -#elif defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) -#define __BYTE_ORDER __BIG_ENDIAN -#else -#error "unable to define __BYTE_ORDER" -#endif -#endif /* not __BYTE_ORDER */ - -#if __BYTE_ORDER == __LITTLE_ENDIAN -#define CRAMFS_16(x) (x) -#define CRAMFS_24(x) (x) -#define CRAMFS_32(x) (x) -#define CRAMFS_GET_NAMELEN(x) ((x)->namelen) -#define CRAMFS_GET_OFFSET(x) ((x)->offset) -#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y)) -#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y)) -#elif __BYTE_ORDER == __BIG_ENDIAN -#ifdef __KERNEL__ -#define CRAMFS_16(x) swab16(x) -#define CRAMFS_24(x) ((swab32(x)) >> 8) -#define CRAMFS_32(x) swab32(x) -#else /* not __KERNEL__ */ -#define CRAMFS_16(x) bswap_16(x) -#define CRAMFS_24(x) ((bswap_32(x)) >> 8) -#define CRAMFS_32(x) bswap_32(x) -#endif /* not __KERNEL__ */ -#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f) -#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\ - ((((u32*)(x))[2] & 0xc0000000) >> 30)) -#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \ - (0xc0 & ((u8*)(x))[8]))) -#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \ - CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \ - (((u32)(((u8*)(x))[8] & 0x3f)) << 24)) -#else -#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" -#endif - -#endif /* not __CRAMFS_FS_H */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index fb69beeaad..8a23c8345b 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -512,7 +512,7 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) return inode; } -static char *mkmodestr(unsigned long mode, char *str) +char *mkmodestr(unsigned long mode, char *str) { static const char *l = "xwr"; int mask = 1, i; diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index 53559c01e8..469edb34f1 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -435,7 +435,19 @@ typedef struct comm_proc { u_char res13[2]; ushort cp_pbodr; uint cp_pbdat; - u_char res14[0x18]; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; /* Serial Interface and Time Slot Assignment. */ diff --git a/include/bmp_logo.h b/include/bmp_logo.h index 9c924b8592..265f744d0e 100644 --- a/include/bmp_logo.h +++ b/include/bmp_logo.h @@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = { 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, - 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, + 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, }; unsigned char bmp_logo_bitmap[] = { diff --git a/include/common.h b/include/common.h index 6b92548243..32107a0942 100644 --- a/include/common.h +++ b/include/common.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,7 +29,7 @@ typedef unsigned char uchar; typedef volatile unsigned long vu_long; -typedef volatile unsigned short vu_short; +typedef volatile unsigned short vu_short; typedef volatile unsigned char vu_char; #include <config.h> @@ -41,21 +41,25 @@ typedef volatile unsigned char vu_char; #if defined(CONFIG_PCI) && defined(CONFIG_440) #include <pci.h> #endif -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) #include <asm/8xx_immap.h> -#ifdef CONFIG_MPC860 -#define CONFIG_MPC86x 1 -#endif -#ifdef CONFIG_MPC860T -#define CONFIG_MPC86x 1 -#endif #if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ defined(CONFIG_MPC859DSL) || \ defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ defined(CONFIG_MPC866P) -#define CONFIG_MPC866_et_al 1 -#define CONFIG_MPC86x 1 +# define CONFIG_MPC866_et_al 1 +#elif defined(CONFIG_MPC870) \ + || defined(CONFIG_MPC875) \ + || defined(CONFIG_MPC880) \ + || defined(CONFIG_MPC885) +# define CONFIG_DUET 1 +#endif +#if defined(CONFIG_MPC860) \ + || defined(CONFIG_MPC860T) \ + || defined(CONFIG_MPC866_et_al) \ + || defined(CONFIG_DUET) +# define CONFIG_MPC86x 1 #endif #elif defined(CONFIG_5xx) #include <asm/5xx_immap.h> diff --git a/include/commproc.h b/include/commproc.h index 8bab5225c2..11f31e9da4 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -716,13 +716,14 @@ typedef struct scc_enet { /*** FADS860T********************************************************/ -#if (defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al)) \ - && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC860TFADS/MPC8xxADS with ethernet on SCC1. +#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) +/* + * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. */ #ifdef CONFIG_SCC1_ENET + #define SCC_ENET 0 -#endif /* CONFIG_SCC1_ETHERNET */ + #define PROFF_ENET PROFF_SCC1 #define CPM_CR_ENET CPM_CR_CH_SCC1 @@ -739,14 +740,17 @@ typedef struct scc_enet { #define SICR_ENET_MASK ((uint)0x000000ff) #define SICR_ENET_CLKRT ((uint)0x0000002c) -/* This ENET stuff is for the MPC860TFADS with ethernet on FEC. +#endif /* CONFIG_SCC1_ETHERNET */ + +/* + * This ENET stuff is for the MPC860TFADS/MPC86xADS/DUET with ethernet on FEC. */ #ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ +#define FEC_ENET /* Use FEC for Ethernet */ +#endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_FADS860T */ +#endif /* CONFIG_FADS && CONFIG_MPC86x */ /*** FPS850L, FPS860L ************************************************/ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index 1b037c9b11..916272dce1 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -5,17 +5,14 @@ * Helmut Buchsbaum added bitvalues for BCSRx * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* ------------------------------------------------------------------------- */ - -#ifndef _CONFIG_ADS860_H -#define _CONFIG_ADS860_H - -/* - * High Level Configuration Options - * (easy to change) - */ +#ifndef __CONFIG_H +#define __CONFIG_H /* Board type */ #define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ @@ -38,351 +35,20 @@ #define CFG_8XX_FACT 12 /* Multiply by 12 */ #endif -#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -#define CONFIG_DRAM_50MHZ 1 - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ + | CFG_CMD_PING \ ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_DRAM_50MHZ 1 -#define CFG_LOAD_ADDR 0x00100000 +#include "fads.h" -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve one flash sector - (256 KB) for monitor */ -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* the other CS:s are determined by looking at parameters in BCSRx */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ #define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 | SCCR_DFALCD00) - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - * BR1 and OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xff010000) - -#define CFG_PRELIM_OR_AM 0xff800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ -#define BCSR0 (BCSR_ADDR + 0x00) -#define BCSR1 (BCSR_ADDR + 0x04) -#define BCSR2 (BCSR_ADDR + 0x08) -#define BCSR3 (BCSR_ADDR + 0x0c) - - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#undef CONFIG_IDE_LED /* LED for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -#define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ - -/* (F)ADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -/* We don't use the 8259. - */ -#define NR_8259_INTS 0 - -/* Machine type - */ -#define _MACH_8xx (_MACH_ads) - -#endif /* _CONFIG_ADS860_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index 2b0b176e24..0d8e4631b3 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -413,7 +413,7 @@ #endif /*------------------------------------------------------------------------ - * Ethernet -- needs work! + * Ethernet *----------------------------------------------------------------------*/ #if (CFG_NIOS_CPU_LAN_NUMS == 1) @@ -642,6 +642,15 @@ #endif /* CFG_NIOS_CPU_PIO_NUMS */ /*------------------------------------------------------------------------ + * ASMI - Active Serial Memory Interface. + * + * ASMI is for Cyclone devices only and only works when the configuration + * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS_ASMI /* Enable ASMI */ +#define CFG_NIOS_ASMIBASE 0x00920b00 /* ASMI base address */ + +/*------------------------------------------------------------------------ * COMMANDS *----------------------------------------------------------------------*/ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ diff --git a/include/configs/DUET_ADS.h b/include/configs/DUET_ADS.h new file mode 100644 index 0000000000..8a4025797d --- /dev/null +++ b/include/configs/DUET_ADS.h @@ -0,0 +1,53 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola DUET ADS board. Values common to all FADS family boards + * are in board/fads/fads.h + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CFG_8XX_FACT 5 /* Multiply by 5 */ +#define CFG_8XX_XIN 10000000 /* 10 MHz in */ + +#define CONFIG_SDRAM_50MHZ 1 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control + */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) + +#include "fads.h" + +#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + +#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 3b201a7910..4f3d3977a8 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -66,8 +66,6 @@ * High Level Configuration Options * (easy to change) */ -#include <mpc8xx_irq.h> - #define CONFIG_MPC823 1 #define CONFIG_MPC823FADS 1 #define CONFIG_FADS 1 @@ -433,14 +431,6 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - /* We don't use the 8259. */ #define NR_8259_INTS 0 @@ -468,4 +458,6 @@ #define PCMCIA_SLOT_A 1 #endif +#define CFG_DAUGHTERBOARD + #endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 3d04ef0dd9..9e292ae0eb 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -30,8 +30,6 @@ * High Level Configuration Options * (easy to change) */ -#include <mpc8xx_irq.h> - #define CONFIG_MPC850 1 #define CONFIG_MPC850SAR 1 #define CONFIG_FADS 1 @@ -393,14 +391,6 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - /* We don't use the 8259. */ #define NR_8259_INTS 0 @@ -420,4 +410,6 @@ #define PCMCIA_SLOT_A 1 #endif +#define CFG_DAUGHTERBOARD + #endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h index 114603c627..e57571bf3a 100644 --- a/include/configs/FADS860T.h +++ b/include/configs/FADS860T.h @@ -5,32 +5,15 @@ * Helmut Buchsbaum added bitvalues for BCSRx * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom - * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ - /* board type */ #define CONFIG_FADS 1 /* old/new FADS + new ADS */ @@ -51,403 +34,25 @@ # define CFG_8XX_XIN 5000000 /* 5 MHz in */ #endif -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* ATA / IDE and partition support */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 -#undef CONFIG_ATAPI -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -/* choose SCC1 ethernet (10BASET on motherboard) - * or FEC ethernet (10/100 on daughterboard) - */ -#if 0 -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* disable FEC ethernet */ -#else /* all 86x cores have FECs, if in doubt, use it */ -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CFG_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*---------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#ifdef CONFIG_FADS -# define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */ -#else /* !CONFIG_FADS */ /* old ADS */ -# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */ -#endif - -#define CFG_FLASH_BASE TEXT_BASE - -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ +#include "fads.h" -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) #ifdef USE_REAL_FLASH_VALUES /* * These values fit our FADS860T ... * The "default" behaviour with 1Mbyte initial doesn't work for us! */ +#undef CFG_OR0_PRELIM +#undef CFG_BR0_PRELIM #define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ #define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ -#else -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) -#endif - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 #endif -/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */ -#define CFG_PCMCIA_MEM_ADDR (0x50000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x54000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0x5C000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -/* we have 8 windows, we take everything up to 60000000 */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 -/*#define CFG_ATA_ALT_OFFSET 0x0100 */ +#define CFG_DAUGHTERBOARD /* FADS has processor-specfic daughterboard */ #endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 1eac6ef68f..a6e2606714 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -3,24 +3,12 @@ * the Motorola MPC8xxADS board. Copied from the FADS config. * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1 - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> fennnnnn : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram connected to CS4 - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - #ifndef __CONFIG_H #define __CONFIG_H @@ -33,7 +21,7 @@ #define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -/* new 86xADS only - pick one of these */ +/* New MPC86xADS - pick one of these */ #define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T @@ -44,374 +32,20 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#ifdef CONFIG_MPC86xADS # define CFG_8XX_FACT 5 /* Multiply by 5 */ # define CFG_8XX_XIN 10000000 /* 10 MHz in */ -#else /* ! CONFIG_MPC86xADS */ -# if 0 /* old FADS */ -# define CFG_8XX_FACT 12 /* Multiply by 12 */ -# define CFG_8XX_XIN 4000000 /* 4 MHz in */ -# else /* new FADS */ -# define CFG_8XX_FACT 10 /* Multiply by 10 */ -# define CFG_8XX_XIN 5000000 /* 5 MHz in */ -# endif -#endif /* ! CONFIG_MPC86xADS */ - -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -/* ATA / IDE and partition support */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 -#undef CONFIG_ATAPI -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -/* - * New MPC86xADS provides two Ethernet connectivity options: - * 10Mbit/s on SCC1 and 100Mbit/s on FEC. All new PQ1 chips - * has got FEC so FEC is the default. - */ -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#ifdef CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decr freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) /* new ADS */ -#define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */ -#elif defined(CONFIG_FADS) /* old/new FADS */ -#define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */ -#else /* old ADS */ -#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CFG_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 /*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state + * set the PLL, the low-power modes and the reset control */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_PCMCIA_MEM_ADDR (0x50000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x54000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0x5C000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -/* we have 8 windows, we take everything up to 60000000 */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 -/*#define CFG_ATA_ALT_OFFSET 0x0100 */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#include "fads.h" #endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 78ae6ba9c0..50e8a15b8d 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -521,7 +521,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if 1 /* test-only */ + #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ /*--------------------------------------------------------------------*/ @@ -651,16 +651,11 @@ #define PLL_PCIDIV_3 0x00000002 #define PLL_PCIDIV_4 0x00000003 -/* -!----------------------------------------------------------------------- -! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, -! assuming a 33.3MHz input clock to the 405EP. -!----------------------------------------------------------------------- -*/ -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ +#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ +#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ @@ -669,27 +664,35 @@ #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ +#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ +#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#if 0 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif +#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) +/* Model HI */ +#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55 +/* Model ME */ +#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) +#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33 +#else +/* Model BA (default) */ +#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33 #endif -#endif + +#endif /* CONFIG_NO_SERIAL_EEPROM */ #define CFG_OPB_FREQ 50000000 diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h index 7b292c0c1e..233370988b 100644 --- a/include/cramfs/cramfs_fs.h +++ b/include/cramfs/cramfs_fs.h @@ -1,14 +1,6 @@ #ifndef __CRAMFS_H #define __CRAMFS_H -#ifndef __KERNEL__ - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; - -#endif - #define CRAMFS_MAGIC 0x28cd3d45 /* some random number */ #define CRAMFS_SIGNATURE "Compressed ROMFS" @@ -16,12 +8,12 @@ typedef unsigned int u32; * Width of various bitfields in struct cramfs_inode. * Primarily used to generate warnings in mkcramfs. */ -#define CRAMFS_MODE_WIDTH 16 -#define CRAMFS_UID_WIDTH 16 -#define CRAMFS_SIZE_WIDTH 24 -#define CRAMFS_GID_WIDTH 8 -#define CRAMFS_NAMELEN_WIDTH 6 -#define CRAMFS_OFFSET_WIDTH 26 +#define CRAMFS_MODE_WIDTH 16 +#define CRAMFS_UID_WIDTH 16 +#define CRAMFS_SIZE_WIDTH 24 +#define CRAMFS_GID_WIDTH 8 +#define CRAMFS_NAMELEN_WIDTH 6 +#define CRAMFS_OFFSET_WIDTH 26 /* * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs @@ -34,8 +26,10 @@ typedef unsigned int u32; */ struct cramfs_inode { u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH; + /* SIZE for device files is i_rdev */ u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH; + /* NAMELEN is the length of the file name, divided by 4 and rounded up. (cramfs doesn't support hard links.) */ /* OFFSET: For symlinks and non-empty regular files, this @@ -90,9 +84,53 @@ struct cramfs_super { | CRAMFS_FLAG_WRONG_SIGNATURE \ | CRAMFS_FLAG_SHIFTED_ROOT_OFFSET ) +/* + * Since cramfs is little-endian, provide macros to swab the bitfields. + */ + +#ifndef __BYTE_ORDER +#if defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) +#define __BYTE_ORDER __LITTLE_ENDIAN +#elif defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) +#define __BYTE_ORDER __BIG_ENDIAN +#else +#error "unable to define __BYTE_ORDER" +#endif +#endif /* not __BYTE_ORDER */ + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define CRAMFS_16(x) (x) +#define CRAMFS_24(x) (x) +#define CRAMFS_32(x) (x) +#define CRAMFS_GET_NAMELEN(x) ((x)->namelen) +#define CRAMFS_GET_OFFSET(x) ((x)->offset) +#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y)) +#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y)) +#elif __BYTE_ORDER == __BIG_ENDIAN +#ifdef __KERNEL__ +#define CRAMFS_16(x) swab16(x) +#define CRAMFS_24(x) ((swab32(x)) >> 8) +#define CRAMFS_32(x) swab32(x) +#else /* not __KERNEL__ */ +#define CRAMFS_16(x) bswap_16(x) +#define CRAMFS_24(x) ((bswap_32(x)) >> 8) +#define CRAMFS_32(x) bswap_32(x) +#endif /* not __KERNEL__ */ +#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f) +#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\ + ((((u32*)(x))[2] & 0xc0000000) >> 30)) +#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \ + (0xc0 & ((u8*)(x))[8]))) +#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \ + CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \ + (((u32)(((u8*)(x))[8] & 0x3f)) << 24)) +#else +#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" +#endif + /* Uncompression interfaces to the underlying zlib */ -int cramfs_uncompress_block(void *dst, int dstlen, void *src, int srclen); +int cramfs_uncompress_block(void *dst, void *src, int srclen); int cramfs_uncompress_init(void); int cramfs_uncompress_exit(void); -#endif +#endif /* __CRAMFS_H */ diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h index 4bdc525ce2..dee43a6d31 100644 --- a/include/jffs2/jffs2.h +++ b/include/jffs2/jffs2.h @@ -202,4 +202,5 @@ void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen); +char *mkmodestr(unsigned long mode, char *str); #endif /* __LINUX_JFFS2_H__ */ diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 847c2b4b6b..3976125bfe 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -132,10 +132,15 @@ #define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) /*----------------------------------------------------------------------- + * Newer chips (MPC866 family and MPC87x/88x family) have different + * clock distribution system. Their IMMR lower half is >= 0x0800 + */ +#define MPC8xx_NEW_CLK 0x0800 + +/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_MF_MSK 0xFFFF001E /* Multiplication factor + PDF bits */ +/* Newer chips (MPC866/87x/88x et al) defines */ #define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ #define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ #define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ @@ -144,32 +149,39 @@ #define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ #define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ #define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ -#else + +#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ +#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ +#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ + +/* Multiplication factor + PDF bits */ +#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ + PLPRCR_MFD_MSK | \ + PLPRCR_S_MSK | \ + PLPRCR_MFI_MSK | \ + PLPRCR_PDF_MSK) + +/* Older chips (MPC860/862 et al) defines */ #define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */ #define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */ -#endif + #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ -#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#ifndef CONFIG_MPC866_et_al #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#endif -#define PLPRCR_CSRC 0x00000400 /* Clock Source */ -#ifndef CONFIG_MPC866_et_al + #define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ #define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ #define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ #define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ #define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ #define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ -#endif + +/* Common defines */ +#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ +#define PLPRCR_CSRC 0x00000400 /* Clock Source */ + #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ -#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ -#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ -#endif /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 diff --git a/include/nios-io.h b/include/nios-io.h index 11ff78d076..64da92abfe 100644 --- a/include/nios-io.h +++ b/include/nios-io.h @@ -136,4 +136,35 @@ typedef volatile struct nios_spi_t { #define NIOS_SPI_IE (1 << 8) /* exception int ena */ #define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ +/*------------------------------------------------------------------------ + * ASMI + *----------------------------------------------------------------------*/ +typedef volatile struct nios_asmi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; + unsigned slavesel; /* Slave select */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_asmi_t; + +/* status register */ +#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ +#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ +#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ +#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ +#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ +#define NIOS_ASMI_E (1 << 8) /* exception */ +#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ + +/* control register */ +#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ +#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ +#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ + #endif /* __NIOSIO_H__ */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 388b149e0b..3080be3b00 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -40,10 +40,10 @@ /* The RPX series use SLOT_B */ #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) # define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ADS) /* The ADS board use SLOT_A */ +#elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ # define CONFIG_PCMCIA_SLOT_A #elif defined(CONFIG_FADS) /* The FADS series are a mess */ -# if defined(CONFIG_MPC86x || defined(CONFIG_MPC821) +# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) # define CONFIG_PCMCIA_SLOT_A # else # define CONFIG_PCMCIA_SLOT_B |
