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-rw-r--r--arch/arm/mach-aspeed/platform_g5.S317
1 files changed, 266 insertions, 51 deletions
diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S
index c810f44b9a..16948284fc 100644
--- a/arch/arm/mach-aspeed/platform_g5.S
+++ b/arch/arm/mach-aspeed/platform_g5.S
@@ -17,56 +17,74 @@
*
* Gary Hsu, <gary_hsu@aspeedtech.com>
*
- * Version : 11
- * Release date: 2016.05.10
+ * Version : 15
+ * Release date: 2017.04.13
+ *
+ * Priority of fix item:
+ * [P1] = critical
+ * [P2] = nice to have
+ * [P3] = minor
*
* Change List :
- * V2|2014.07.25 : 1. Modify HPLL config sequence
- * V2|2014.07.30 : 1. Modify DDR3 AC parameters table
- * | 2. Turn on ZQCS mode
- * V2|2014.08.13 : 1. Add disable XDMA
- * V2|2014.09.09 : 1. Disable CKE dynamic power down
- * V2|2014.10.31 : 1. Enable VGA wide screen support (SCU40[0]=1)
- * V2|2015.03.26 : 1. Revise AC timing table
- * | 2. Add check code to bypass A0 patch
- * | 3. Add MPLL parameter of A1
- * | 4. Set X-DMA into VGA memory domain
- * V2|2015.04.24 : 1. Add disabling all DRAM requests during PHY init
- * | 2. Set MCR1C & MCR38
- * V3|2015.05.13 : 1. Modify DDR4 PHY Vref training algorithm
- * | 2. Enable CKE dynamic power down
- * V4|2015.06.15 : 1. Add MAC timing setting
- * V5|2015.07.09 : 1. Modify MHCLK divider ratio
- * | 2. Add DDR read margin report
- * V6|2015.08.13 : 1. Disable MMC password before exit
- * V6|2015.08.24 : 1. Fix SCU160 parameter value for CLKIN=25MHz condition
- * V7|2015.09.18 : 1. Clear AHB bus lock condition at power up time
- * | 2. Add reset MMC controller to solve init DRAM again during VGA ON
- * V7|2015.09.22 : 1. Add watchdog full reset for resolving reset incomplete issue at fast reset condition
- * | 2. Add DRAM stress test after train complete, and redo DRAM initial if stress fail
- * | 3. Enable JTAG master mode
- * | 4. Add DDR4 Vref trainig retry timeout
- * V8|2015.11.02 : 1. Clear software strap flag before doing watchdog full reset
- * |2015.12.10 : 1. Add USB PHY initial code
- * |2016.01.27 : 1. Modify the first reset from full chip reset to SOC reset
- * | 2. Remove HPLL/MPLL patch code for revision A0
- * | 3. Move the reset_mmc code to be after MPLL initialized
- * V9|2016.02.19 : 1. Remove definietion "CONFIG_FIRMWARE_2ND_BOOT"
- * V10|2016.04.21 : 1. Add USB PHY initial code - port B, to prevent wrong state on USB pins
- * V11|2016.05.10 : 1. Add DRAM Extended temperature range support
+ * V2 |2014.07.25 : 1.[P1] Modify HPLL config sequence
+ * V2 |2014.07.30 : 1.[P1] Modify DDR3 AC parameters table
+ * | 2.[P1] Turn on ZQCS mode
+ * V2 |2014.08.13 : 1.[P1] Add disable XDMA
+ * V2 |2014.09.09 : 1.[P1] Disable CKE dynamic power down
+ * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
+ * V2 |2015.03.26 : 1.[P1] Revise AC timing table
+ * | 2.[P1] Add check code to bypass A0 patch
+ * | 3.[P1] Add MPLL parameter of A1
+ * | 4.[P1] Set X-DMA into VGA memory domain
+ * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init
+ * | 2.[P1] Set MCR1C & MCR38
+ * V3 |2015.05.13 : 1.[P1] Modify DDR4 PHY Vref training algorithm
+ * | 2.[P2] Enable CKE dynamic power down
+ * V4 |2015.06.15 : 1.[P1] Add MAC timing setting
+ * V5 |2015.07.09 : 1.[P1] Modify MHCLK divider ratio
+ * | 2.[P2] Add DDR read margin report
+ * V6 |2015.08.13 : 1.[P3] Disable MMC password before exit
+ * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition
+ * V7 |2015.09.18 : 1.[P1] Clear AHB bus lock condition at power up time
+ * | 2.[P1] Add reset MMC controller to solve init DRAM again during VGA ON
+ * V7 |2015.09.22 : 1.[P1] Add watchdog full reset for resolving reset incomplete issue at fast reset condition
+ * | 2.[P1] Add DRAM stress test after train complete, and redo DRAM initial if stress fail
+ * | 3.[P2] Enable JTAG master mode
+ * | 4.[P2] Add DDR4 Vref trainig retry timeout
+ * V8 |2015.11.02 : 1.[P2] Clear software strap flag before doing watchdog full reset
+ * |2015.12.10 : 1.[P1] Add USB PHY initial code
+ * |2016.01.27 : 1.[P3] Modify the first reset from full chip reset to SOC reset
+ * | 2.[P3] Remove HPLL/MPLL patch code for revision A0
+ * | 3.[P2] Move the reset_mmc code to be after MPLL initialized
+ * V9 |2016.02.19 : 1.[P3] Remove definition "CONFIG_FIRMWARE_2ND_BOOT"
+ * V10|2016.04.21 : 1.[P1] Add USB PHY initial code - port B, to prevent wrong state on USB pins
+ * V11|2016.05.10 : 1.[P3] Add DRAM Extended temperature range support
+ * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled
+ * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
+ * | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
+ * | : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35 to 0.3. Add "Warning" while violated.
+ * V13|2016.08.29 : 1.[P3] Add option to route debug message output port from UART5 to UART1
+ * |2016.09.02 : 2.[P2] Add range control for cache function when ECC enabled
+ * |2016.09.06 : 3.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough
+ * V14|2016.10.25 : 1.[P2] Change Ron manual calibration to default OFF, customer can enable it to do fine-tuning of the Vix issue
+ * |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training
+ * V15|2017.04.06 : 1.[P1] Modify USB portA initial sequence, this is to prevent DMA lock condition of USB Virtual Hub device for some chips.
+ * |2017.04.13 : 2.[P2] Add initial sequence for LPC controller
+ * | : Note: Read timing report is only a reference, it is not a solid rule for stability.
*
* Optional define variable
- * 1. DRAM Speed //
- * CONFIG_DRAM_1333 //
- * CONFIG_DRAM_1600 // (default)
+ * 1. DRAM Speed //
+ * CONFIG_DRAM_1333 //
+ * CONFIG_DRAM_1600 // (default)
* 2. ECC Function enable
- * CONFIG_DRAM_ECC // define to enable ECC function
- * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size
- * 3. UART5 message output //
- * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ * CONFIG_DRAM_ECC // define to enable ECC function
+ * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size
+ * 3. UART5 message output //
+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
+ * CONFIG_DRAM_UART_TO_UART1 // route UART5 to UART port1
* 4. DRAM Type
- * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die
- * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part
+ * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die
+ * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part
* 5. Firmware 2nd boot flash
* CONFIG_FIRMWARE_2ND_BOOT (Removed)
* 6. Enable DRAM extended temperature range mode
@@ -83,8 +101,21 @@
Free registers:
r0, r1, r2, r3, r6, r7, r8, r9, r10, r11
******************************************************************************/
-#define ASTMMC_INIT_VER 0x0B @ 8bit verison number
-#define ASTMMC_INIT_DATE 0x20160510 @ Release date
+#define ASTMMC_INIT_VER 0x0F @ 8bit verison number
+#define ASTMMC_INIT_DATE 0x20170413 @ Release date
+
+/******************************************************************************
+ BMC side DDR IO driving manual mode fine-tuning, used to improve CK/CKN Vix violation.
+ Default disabled, the driver setting is hardware auto tuned.
+
+ ASTMMC_DDR4_MANUAL_RPU | ASTMMC_DDR4_MANUAL_RPD
+ -----------------------+-----------------------
+ No | x : manual mode disabled
+ Yes | No : enable Rpu manual setting
+ Yes | Yes : enable Rpu/Rpd manual setting
+ ******************************************************************************/
+//#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving
+//#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving
#define ASTMMC_REGIDX_010 0x00
#define ASTMMC_REGIDX_014 0x04
@@ -290,9 +321,18 @@ init_dram:
ldr r1, [r0]
and r1, r1, #0x01
str r1, [r0]
+ ldr r0, =0x1e78501c @ restore normal mask setting
+ ldr r1, =0x023FFFF3 @ added 2016.09.06
+ str r1, [r0]
b bypass_first_reset
start_first_reset:
+ ldr r0, =0x1e789130 @ Clear LPC interrupt
+ ldr r1, =0x00000080
+ str r1, [r0]
+ ldr r0, =0x1e789138 @ Clear LPC interrupt
+ ldr r1, =0x00010198
+ str r1, [r0]
ldr r0, =0x1e62009c @ clear software strap flag for doing again after reset
ldr r1, =0xAEEDFC20
str r1, [r0]
@@ -302,7 +342,10 @@ start_first_reset:
ldr r0, =0x1e785008
ldr r1, =0x00004755
str r1, [r0]
- ldr r0, =0x1e78500c @ enable soc reset
+ ldr r0, =0x1e78501c @ enable full mask of SOC reset
+ ldr r1, =0x03FFFFFF @ added 2016.09.06
+ str r1, [r0]
+ ldr r0, =0x1e78500c @ enable SOC reset
ldr r1, =0x00000013
str r1, [r0]
wait_first_reset:
@@ -339,12 +382,24 @@ bypass_first_reset:
orr r1, r1, #0x80
str r1, [r0]
+ /* Change LPC reset source to PERST# when eSPI mode enabled */
+ ldr r0, =0x1e6e2070
+ ldr r1, [r0]
+ ldr r0, =0x1e6e207c
+ ldr r2, =0x02000000
+ ldr r3, =0x00004000
+ tst r1, r2
+ strne r3, [r0]
+
/* Configure USB ports to the correct pin state */
ldr r0, =0x1e6e200c @ enable portA clock
ldr r2, =0x00004000
ldr r1, [r0]
orr r1, r1, r2
str r1, [r0]
+ ldr r0, =0x1e6e2090 @ set portA as host mode
+ ldr r1, =0x2000A000
+ str r1, [r0]
ldr r0, =0x1e6e2094 @ set portB as host mode
ldr r1, =0x00004000
str r1, [r0]
@@ -379,11 +434,13 @@ bypass_USB_init:
/******************************************************************************
Disable WDT2 for 2nd boot function
******************************************************************************/
+/*
#ifndef CONFIG_FIRMWARE_2ND_BOOT
ldr r0, =0x1e78502c
mov r1, #0
str r1, [r0]
#endif
+*/
/******************************************************************************
Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function
******************************************************************************/
@@ -490,6 +547,18 @@ wait_mmc_reset_done:
str r1, [r0]
/* Debug - UART console message */
+#ifdef CONFIG_DRAM_UART_TO_UART1
+ ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29
+ ldr r1, =0x10000004
+ str r1, [r0]
+
+ ldr r0, =0x1e6e2084
+ ldr r1, [r0]
+ mov r2, #0xC0 @ Enable pinmux of TXD1/RXD1
+ orr r1, r1, r2, lsl #16
+ str r1, [r0]
+#endif
+
ldr r0, =0x1e78400c
mov r1, #0x83
str r1, [r0]
@@ -926,7 +995,7 @@ ddr4_init:
str r1, [r0]
ldr r0, =0x1e6e0204
- ldr r1, =0x09002000
+ ldr r1, =0x09002800
str r1, [r0]
ldr r0, =0x1e6e020c
@@ -992,6 +1061,49 @@ ddr4_init:
/* Debug - UART console message */
/********************************************
+ Set Ron value to manual mode
+ Target to fix DDR CK Vix issue
+ Set Ron_pu = 0, Ron_pd = trained value
+ *******************************************/
+#ifdef ASTMMC_DDR4_MANUAL_RPU
+ ldr r0, =0x1e6e02c0
+ ldr r1, =0x00001806
+ str r1, [r0]
+ ldr r0, =0x1e6e02cc
+ ldr r1, =0x00005050
+ str r1, [r0]
+ ldr r0, =0x1e6e0120
+ mov r1, #0x04
+ str r1, [r0]
+ ldr r0, =0x1e6e0060 @ Fire DDRPHY Init
+ mov r1, #0x05
+ str r1, [r0]
+ b ddr_phy_init_process
+
+ddr4_ron_phyinit_done:
+
+ ldr r0, =0x1e6e0300 @ read calibrated Ron_pd
+ ldr r3, [r0]
+ bic r3, r3, #0xFFFFFF0F
+ ldr r0, =0x1e6e0240
+ ldr r1, [r0]
+ bic r1, r1, #0xFF000000
+ mov r2, #ASTMMC_DDR4_MANUAL_RPU
+ orr r1, r1, r2, lsl #24
+#ifdef ASTMMC_DDR4_MANUAL_RPD
+ mov r2, #ASTMMC_DDR4_MANUAL_RPD
+ orr r1, r1, r2, lsl #28
+#else
+ orr r1, r1, r3, lsl #24
+#endif
+ orr r1, r1, #0x02
+ str r1, [r0]
+
+ ldr r0, =0x1e6e0060 @ Reset PHY
+ mov r1, #0x00
+ str r1, [r0]
+#endif
+ /********************************************
PHY Vref Scan
r6 : recorded vref value
r7 : max read eye pass window
@@ -1051,6 +1163,11 @@ ddr4_vref_phy_phyinit_done:
b cbr_test_start
ddr4_vref_phy_cbrtest_done:
+ ldr r0, =0x1e6e03d0 @ read eye pass window
+ ldr r1, [r0]
+ ldr r0, =0x1e720000
+ add r0, r0, r10, lsl #2
+ str r1, [r0]
cmp r9, #0x01
bne ddr4_vref_phy_test_fail
add r8, r8, #0x01
@@ -1076,6 +1193,9 @@ ddr4_vref_phy_loop_end:
ldr r0, =0x1e6e02cc
orr r1, r6, r6, lsl #8
str r1, [r0]
+ ldr r0, =0x1e720010
+ orr r1, r6, r7, lsl #8
+ str r1, [r0]
/********************************************
DDR Vref Scan
@@ -1163,6 +1283,9 @@ ddr4_vref_ddr_loop_end:
mov r1, r2, lsl #8
orr r1, r1, #0x06
str r1, [r0]
+ ldr r0, =0x1e720014
+ orr r1, r6, r7, lsl #8
+ str r1, [r0]
/* Debug - UART console message */
ldr r0, =0x1e784000
@@ -1180,6 +1303,7 @@ ddr4_vref_ddr_loop_end:
b ddr_phy_init_process
ddr4_phyinit_done:
+
/*******************************************/
/* Debug - UART console message */
ldr r0, =0x1e784000
@@ -1275,6 +1399,10 @@ ddr_phy_init_success:
beq ddr4_vref_phy_phyinit_done
cmp r1, #2
beq ddr4_vref_ddr_phyinit_done
+#ifdef ASTMMC_DDR4_MANUAL_RPU
+ cmp r1, #4
+ beq ddr4_ron_phyinit_done
+#endif
b ddr4_phyinit_done
/********************************************
@@ -1619,10 +1747,18 @@ wait_print_2:
ldr r7, =0x000001FE @ divide by 510
mov r8, #10 @ multiply by 10
+ mov r9, #0 @ record violation
+ ldr r0, =0x1e6e0004
+ ldr r1, [r0]
+ tst r1, #0x10 @ bit[4]=1 => DDR4
+ movne r10, #0x9A @ DDR4 min = 0x99 (0.30)
+ moveq r10, #0xB3 @ DDR3 min = 0xB3 (0.35)
print_DQL_eye_margin:
ldr r0, =0x1e6e03d0
ldr r2, [r0]
and r2, r2, #0xFF
+ cmp r2, r10 @ check violation
+ movlt r9, #1
ldr r0, =0x1e784000
mov r1, #0x30 @ '0'
str r1, [r0]
@@ -1675,6 +1811,8 @@ wait_print_3:
ldr r2, [r0]
mov r2, r2, lsr #8
and r2, r2, #0xFF
+ cmp r2, r10 @ check violation
+ movlt r9, #1
ldr r0, =0x1e784000
mov r1, #0x30 @ '0'
str r1, [r0]
@@ -1715,6 +1853,12 @@ print_DQ_eye_margin_last:
mov r1, #0x4B @ 'K'
str r1, [r0]
+ ldr r0, =0x1e6e0004
+ ldr r1, [r0]
+ tst r1, #0x10 @ bit[4]=1 => DDR4
+ movne r10, #0x30 @ DDR4 min = 0.30
+ moveq r10, #0x35 @ DDR4 min = 0.35
+
ldr r0, =0x1e784014
wait_print_4:
ldr r1, [r0]
@@ -1740,10 +1884,79 @@ wait_print_4:
str r1, [r0]
mov r1, #0x33 @ '3'
str r1, [r0]
- mov r1, #0x35 @ '5'
- str r1, [r0]
+ str r10, [r0]
mov r1, #0x29 @ ')'
str r1, [r0]
+
+ cmp r9, #0
+ beq print_DQ_margin_last
+ mov r1, #0x20 @ ' '
+ str r1, [r0]
+ ldr r0, =0x1e784014
+wait_print_5:
+ ldr r1, [r0]
+ tst r1, #0x40
+ beq wait_print_5
+
+ ldr r0, =0x1e784000
+ mov r1, #0x57 @ 'W'
+ str r1, [r0]
+ mov r1, #0x61 @ 'a'
+ str r1, [r0]
+ mov r1, #0x72 @ 'r'
+ str r1, [r0]
+ mov r1, #0x6E @ 'n'
+ str r1, [r0]
+ mov r1, #0x69 @ 'i'
+ str r1, [r0]
+ mov r1, #0x6E @ 'n'
+ str r1, [r0]
+ mov r1, #0x67 @ 'g'
+ str r1, [r0]
+ mov r1, #0x3A @ ':'
+ str r1, [r0]
+ mov r1, #0x20 @ ' '
+ str r1, [r0]
+ mov r1, #0x4D @ 'M'
+ str r1, [r0]
+ mov r1, #0x61 @ 'a'
+ str r1, [r0]
+ mov r1, #0x72 @ 'r'
+ str r1, [r0]
+ mov r1, #0x67 @ 'g'
+ str r1, [r0]
+ mov r1, #0x69 @ 'i'
+ str r1, [r0]
+ mov r1, #0x6E @ 'n'
+ str r1, [r0]
+ ldr r0, =0x1e784014
+wait_print_6:
+ ldr r1, [r0]
+ tst r1, #0x40
+ beq wait_print_6
+ ldr r0, =0x1e784000
+ mov r1, #0x20 @ ' '
+ str r1, [r0]
+ mov r1, #0x74 @ 't'
+ str r1, [r0]
+ mov r1, #0x6F @ 'o'
+ str r1, [r0]
+ mov r1, #0x6F @ 'o'
+ str r1, [r0]
+ mov r1, #0x20 @ ' '
+ str r1, [r0]
+ mov r1, #0x73 @ 's'
+ str r1, [r0]
+ mov r1, #0x6D @ 'm'
+ str r1, [r0]
+ mov r1, #0x61 @ 'a'
+ str r1, [r0]
+ mov r1, #0x6C @ 'l'
+ str r1, [r0]
+ mov r1, #0x6C @ 'l'
+ str r1, [r0]
+
+print_DQ_margin_last:
mov r1, #0x0D @ '\r'
str r1, [r0]
mov r1, #0x0A @ '\n'
@@ -1753,8 +1966,9 @@ wait_print_4:
platform_exit:
#ifdef CONFIG_DRAM_ECC
ldr r0, =0x1e6e0004
+ ldr r2, =0x00000880 @ add cache range control, 2016.09.02
ldr r1, [r0]
- orr r1, r1, #0x80
+ orr r1, r1, r2
str r1, [r0]
ldr r0, =0x1e6e0054
@@ -1968,6 +2182,7 @@ set_D2PLL:
ldr r0, =0x1e6e2090 @ Enable MAC interface pull low
ldr r1, [r0]
bic r1, r1, #0x0000F000
+ bic r1, r1, #0x20000000 @ Set USB portA as Device mode
str r1, [r0]
/* Test - DRAM initial time */
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