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| author | Anatolij Gustschin <agust@denx.de> | 2008-02-25 20:04:20 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-03-02 21:33:51 +0100 |
| commit | 60ec654c5eb80d0fe0c38a3bd42140215bc06484 (patch) | |
| tree | 18f63eca24ff9eec1635e029919af4e9916faafd /post/cpu | |
| parent | c313b2c6c555e7d89ec59bd51c59ab164ad0105d (diff) | |
| download | talos-obmc-uboot-60ec654c5eb80d0fe0c38a3bd42140215bc06484.tar.gz talos-obmc-uboot-60ec654c5eb80d0fe0c38a3bd42140215bc06484.zip | |
POST: Disable cache while SPR POST
Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'post/cpu')
| -rw-r--r-- | post/cpu/ppc4xx/spr.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index c12e378f54..37c95598f5 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -43,6 +43,12 @@ #include <asm/processor.h> +#ifdef CONFIG_4xx_DCACHE +#include <asm/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; +#endif + static struct { int number; char * name; @@ -164,6 +170,10 @@ int spr_post_test (int flags) }; unsigned long (*get_spr) (void) = (void *) code; +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif for (i = 0; i < spr_test_list_size; i++) { int num = spr_test_list[i].number; @@ -180,6 +190,10 @@ int spr_post_test (int flags) ret = -1; } } +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return ret; } |
