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authorScott Wood <scottwood@freescale.com>2012-08-08 15:03:33 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-22 16:07:43 -0500
commit7b8f6685fb840fbaff0baf7d2297b4a2c7ddbf65 (patch)
treefde0ee437ee015c8227318a96ad94d3992fca180 /nand_spl
parent7de8a7169e0e87c960d06c60570bc062416e681f (diff)
downloadtalos-obmc-uboot-7b8f6685fb840fbaff0baf7d2297b4a2c7ddbf65.tar.gz
talos-obmc-uboot-7b8f6685fb840fbaff0baf7d2297b4a2c7ddbf65.zip
nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()
This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used before the final write to LSOR that initiates the transaction, to ensure all the other set up has been completed. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl')
-rw-r--r--nand_spl/nand_boot_fsl_elbc.c47
1 files changed, 25 insertions, 22 deletions
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 502605b1d5..e9d649743e 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -66,39 +66,42 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
if (large) {
fmr |= FMR_ECCM;
- out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
- (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
- out_be32(&regs->fir,
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_CW1 << FIR_OP3_SHIFT) |
- (FIR_OP_RBW << FIR_OP4_SHIFT));
+ __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT),
+ &regs->fcr);
+ __raw_writel(
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_CW1 << FIR_OP3_SHIFT) |
+ (FIR_OP_RBW << FIR_OP4_SHIFT),
+ &regs->fir);
} else {
- out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
- out_be32(&regs->fir,
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_RBW << FIR_OP3_SHIFT));
+ __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
+ __raw_writel(
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_RBW << FIR_OP3_SHIFT),
+ &regs->fir);
}
- out_be32(&regs->fbcr, 0);
- clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
+ __raw_writel(0, &regs->fbcr);
while (pos < uboot_size) {
int i = 0;
- out_be32(&regs->fbar, offs >> block_shift);
+ __raw_writel(offs >> block_shift, &regs->fbar);
do {
int j;
unsigned int page_offs = (offs & (block_size - 1)) << 1;
- out_be32(&regs->ltesr, ~0);
- out_be32(&regs->lteatr, 0);
- out_be32(&regs->fpar, page_offs);
- out_be32(&regs->fmr, fmr);
- out_be32(&regs->lsor, 0);
+ __raw_writel(~0, &regs->ltesr);
+ __raw_writel(0, &regs->lteatr);
+ __raw_writel(page_offs, &regs->fpar);
+ __raw_writel(fmr, &regs->fmr);
+ sync();
+ __raw_writel(0, &regs->lsor);
nand_wait();
page_offs %= WINDOW_SIZE;
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