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| author | Simon Glass <sjg@chromium.org> | 2016-05-08 16:55:22 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-07-05 13:23:04 -0700 |
| commit | 703aaf76c2c06109fc36266767b2d1dcfce6f3ba (patch) | |
| tree | 4c488c32b46ac5a82e36d7f2768d2895c9a7164a /include | |
| parent | 8d37483e7cfff9e36a928379d7ab6c4fc11bd4c1 (diff) | |
| download | talos-obmc-uboot-703aaf76c2c06109fc36266767b2d1dcfce6f3ba.tar.gz talos-obmc-uboot-703aaf76c2c06109fc36266767b2d1dcfce6f3ba.zip | |
fdt: Drop some unused compatible strings
We have driver-model drivers for some of these now, so drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fdtdec.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/fdtdec.h b/include/fdtdec.h index 54e3d8139f..05d70c4b9b 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -119,10 +119,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ - COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ - COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ - COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */ COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ @@ -146,7 +143,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ - COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ |
