diff options
| author | Stefan Roese <sr@denx.de> | 2009-09-28 17:33:45 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:53:37 +0200 |
| commit | fb95169e39f2d03270bed552d27bbb02627a443e (patch) | |
| tree | c94e691e322097c7cdc43943cd3bb05b3e7c760e /include/ppc405.h | |
| parent | d24bd2517a2b847f773453eab0ee5b1c8ebc74ba (diff) | |
| download | talos-obmc-uboot-fb95169e39f2d03270bed552d27bbb02627a443e.tar.gz talos-obmc-uboot-fb95169e39f2d03270bed552d27bbb02627a443e.zip | |
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Diffstat (limited to 'include/ppc405.h')
| -rw-r--r-- | include/ppc405.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index 8a4ba3faf6..5e56897819 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -768,10 +768,6 @@ #define SDR0_SDCS_SDD (0x80000000 >> 31) -/* SDR0_SDSTP0 Serial Device Strap Register0 */ -#define SDR0_SDSTP0 0x0020 -#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07)) - /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ |
