diff options
| author | Wang Huan <b18965@freescale.com> | 2014-09-05 13:52:39 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 10:30:33 -0700 |
| commit | c82e9de400ee36038c76be67c5a6fb39c165ac1c (patch) | |
| tree | 7da71ffa7005b4a59dd53aeb27e7df17be952c51 /include/fsl_esdhc.h | |
| parent | 52d00a812a29974e660f64a8839ddb550dca5290 (diff) | |
| download | talos-obmc-uboot-c82e9de400ee36038c76be67c5a6fb39c165ac1c.tar.gz talos-obmc-uboot-c82e9de400ee36038c76be67c5a6fb39c165ac1c.zip | |
esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 9814964937..c1b6648591 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -162,7 +162,19 @@ struct fsl_esdhc_cfg { }; /* Select the correct accessors depending on endianess */ -#if __BYTE_ORDER == __LITTLE_ENDIAN +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN #define esdhc_read32 in_le32 #define esdhc_write32 out_le32 #define esdhc_clrsetbits32 clrsetbits_le32 |
