summaryrefslogtreecommitdiffstats
path: root/include/fsl_esdhc.h
diff options
context:
space:
mode:
authorDirk Behme <dirk.behme@de.bosch.com>2012-03-26 03:13:05 +0000
committerAndy Fleming <afleming@freescale.com>2012-05-08 18:02:22 -0500
commit7a5b80297bc6cef0c10e5f57ac0450678dc7bc5e (patch)
tree8fba80e7160033710083598973ef35be98ef0765 /include/fsl_esdhc.h
parentffdea5dab902b522f8744234184ffa11a4e275c2 (diff)
downloadtalos-obmc-uboot-7a5b80297bc6cef0c10e5f57ac0450678dc7bc5e.tar.gz
talos-obmc-uboot-7a5b80297bc6cef0c10e5f57ac0450678dc7bc5e.zip
mmc: fsl_esdhc: Poll until card is not busy anymore
This patch imports parts of two patches from the Freescale U-Boot with the following commit messages: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=e436525a70fe47623d346bc7d9f08f12ff8ad787 The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=a77c6fec8596891be96b2cdbc742c9824844b92a Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. This patch imports the polling part of both patches. The auto-clock gating code don't apply for i.MX6 as implemented in these two patches. SYSCTL_RSTA was defined twice. Remove one definition. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Andy Fleming <afleming@freescale.com> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'include/fsl_esdhc.h')
-rw-r--r--include/fsl_esdhc.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 8418bf7f47..0e265584bd 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -34,12 +34,13 @@
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
-#define SYSCTL_RSTA 0x01000000
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTD 0x04000000
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
@@ -85,6 +86,7 @@
#define IRQSTATEN_CC (0x00000001)
#define PRSSTAT 0x0002e024
+#define PRSSTAT_DAT0 (0x01000000)
#define PRSSTAT_CLSL (0x00800000)
#define PRSSTAT_WPSPL (0x00080000)
#define PRSSTAT_CDPL (0x00040000)
OpenPOWER on IntegriCloud