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| author | Simon Glass <sjg@chromium.org> | 2015-06-23 15:39:13 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-07-21 17:39:29 -0600 |
| commit | f9917454d55caf3dafa41b27d8d8274716433a4c (patch) | |
| tree | 81f7c0e4cb2a9c3e04eab94ef17da21f2de1192f /include/dm/uclass-id.h | |
| parent | 92a655c326b22de58dcd5371ca1a62fdc57f8e04 (diff) | |
| download | talos-obmc-uboot-f9917454d55caf3dafa41b27d8d8274716433a4c.tar.gz talos-obmc-uboot-f9917454d55caf3dafa41b27d8d8274716433a4c.zip | |
dm: Add a system reset uclass
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/dm/uclass-id.h')
| -rw-r--r-- | include/dm/uclass-id.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 93a38575bd..b993fc0a06 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -44,6 +44,7 @@ enum uclass_id { UCLASS_PCI_GENERIC, /* Generic PCI bus device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_REGULATOR, /* Regulator device */ + UCLASS_RESET, /* Reset device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SPI, /* SPI bus */ |
