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authorThierry Reding <treding@nvidia.com>2014-12-09 22:25:23 -0700
committerTom Warren <twarren@nvidia.com>2014-12-18 13:21:41 -0700
commitd1e5b4065ee14a6dbabd9318a8f73194c6536d6e (patch)
tree1384c72c6af679be2a35dc0d60797f23468c7351 /include/configs
parent1dfdd9ba4e699562a3b282f4fb5efe4c80e6e8c7 (diff)
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ARM: tegra: Enable non-cached memory
Some boards, most notably those with a PCIe ethernet NIC, require this to avoid cache coherency problems. Since the option adds very little code and overhead enable it across all Tegra generations. Other drivers may also start supporting this functionality at some point, so enabling it now will automatically reap the benefits later on. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/tegra-common.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 06853285a2..8f1e370915 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -47,7 +47,9 @@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
/*
* NS16550 Configuration
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