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| author | Stephen Warren <swarren@nvidia.com> | 2015-08-07 16:12:45 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-13 13:06:04 -0700 |
| commit | bbc1b99e8b8a1b87c2d0d959a1fcd1990abe82dd (patch) | |
| tree | 4b298ee4094e9dd8686c3b5532566cf673baef00 /include/configs | |
| parent | a5fc3d0b35a7e83a05dc41c1b966710d28118a29 (diff) | |
| download | talos-obmc-uboot-bbc1b99e8b8a1b87c2d0d959a1fcd1990abe82dd.tar.gz talos-obmc-uboot-bbc1b99e8b8a1b87c2d0d959a1fcd1990abe82dd.zip | |
ARM: tegra: represent RAM in 1 or 2 banks
Represent all available RAM in either one or two banks. The first bank
describes any RAM below 4GB. The second bank describes any RAM above 4GB.
This split is driven by the following requirements:
- The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
property for memory below and above the 4GB boundary. The layout of that
DT property is directly driven by the entries in the U-Boot bank array.
- On systems with RAM beyond a physical address of 4GB, the potential
existence of a carve-out at the end of RAM below 4GB can only be
represented using multiple banks, since usable RAM is not contiguous.
While making this change, add a lot more comments re: how and why RAM is
represented in banks, and implement a few more "semantic" functions that
define (and perhaps later detect at run-time) the size of any carve-out.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/tegra-common.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 145f63587f..6fe5f2ce65 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -111,7 +111,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
