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author | Tom Rini <trini@konsulko.com> | 2015-08-23 20:44:25 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-23 20:44:25 -0400 |
commit | c851a2458fbc12495f4f786d4eabb612850a5143 (patch) | |
tree | fa0b97f9ff8f744db11a1d296283ce7ce335a536 /include/configs | |
parent | 14e7a30f2e8963fc5b91ba68e53bb2de708aee65 (diff) | |
parent | 29aa439759ed2e5dfa45cd8d6d5a1d51604e3820 (diff) | |
download | talos-obmc-uboot-c851a2458fbc12495f4f786d4eabb612850a5143.tar.gz talos-obmc-uboot-c851a2458fbc12495f4f786d4eabb612850a5143.zip |
Merge git://git.denx.de/u-boot-socfpga
Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs')
-rw-r--r-- | include/configs/socfpga_arria5.h | 2 | ||||
-rw-r--r-- | include/configs/socfpga_cyclone5.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h index e1cd9cc8aa..3193684798 100644 --- a/include/configs/socfpga_arria5.h +++ b/include/configs/socfpga_arria5.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -30,7 +31,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 9b317413e7..9e733e5c48 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -30,7 +31,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |