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| author | York Sun <yorksun@freescale.com> | 2014-08-13 10:21:05 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 08:36:18 -0700 |
| commit | d9c68b1444acb383684636eb856fd7e4cec04129 (patch) | |
| tree | 10f046be69384766c2418bde0b6f215412ded707 /include/configs/ls2085a_common.h | |
| parent | 1d71efbb0345ff3a8ac45e62bef36813abe1703e (diff) | |
| download | talos-obmc-uboot-d9c68b1444acb383684636eb856fd7e4cec04129.tar.gz talos-obmc-uboot-d9c68b1444acb383684636eb856fd7e4cec04129.zip | |
ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/ls2085a_common.h')
| -rw-r--r-- | include/configs/ls2085a_common.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 6355e4a6b0..5ac7623f76 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -54,6 +54,18 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 + +#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL +/* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ +#define CONFIG_SYS_DP_DDR_BASE_PHY 0 +#define CONFIG_DP_DDR_CTRL 2 +#define CONFIG_DP_DDR_NUM_CTRLS 1 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 12000000 /* 12MHz */ @@ -236,7 +248,7 @@ #define CONFIG_SYS_CLK_FREQ 133333333 -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 3 #define CONFIG_SYS_HZ 1000 |
