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authorYork Sun <yorksun@freescale.com>2015-04-29 10:35:35 -0700
committerYork Sun <yorksun@freescale.com>2015-05-20 10:34:09 -0700
commita88cc3bd90b05420a84ee360efa1133652dcac5c (patch)
tree6f72a887ed50be221033043db0f186a1d6cca0bd /include/configs/ls1021atwr.h
parentd9be24c92dbb43b6bb694612fa09d9a4ed0ba1fc (diff)
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arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
Diffstat (limited to 'include/configs/ls1021atwr.h')
-rw-r--r--include/configs/ls1021atwr.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 9cad60c0eb..8ea428e898 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -35,6 +35,29 @@
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
+#define DDR_SDRAM_CFG 0x470c0008
+#define DDR_CS0_BNDS 0x008000bf
+#define DDR_CS0_CONFIG 0x80014302
+#define DDR_TIMING_CFG_0 0x50550004
+#define DDR_TIMING_CFG_1 0xbcb38c56
+#define DDR_TIMING_CFG_2 0x0040d120
+#define DDR_TIMING_CFG_3 0x010e1000
+#define DDR_TIMING_CFG_4 0x00000001
+#define DDR_TIMING_CFG_5 0x03401400
+#define DDR_SDRAM_CFG_2 0x00401010
+#define DDR_SDRAM_MODE 0x00061c60
+#define DDR_SDRAM_MODE_2 0x00180000
+#define DDR_SDRAM_INTERVAL 0x18600618
+#define DDR_DDR_WRLVL_CNTL 0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2 0x05060607
+#define DDR_DDR_WRLVL_CNTL_3 0x05050505
+#define DDR_DDR_CDR1 0x80040000
+#define DDR_DDR_CDR2 0x00000001
+#define DDR_SDRAM_CLK_CNTL 0x02000000
+#define DDR_DDR_ZQ_CNTL 0x89080600
+#define DDR_CS0_CONFIG_2 0
+#define DDR_SDRAM_CFG_MEM_EN 0x80000000
+
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif
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