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| author | york <yorksun@freescale.com> | 2010-07-02 22:25:58 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-26 13:16:10 -0500 |
| commit | 394c46caf965f47717a952a09a51b73c2cb473b3 (patch) | |
| tree | 29adb2ef20cb63cf655f872362e1f598277e2637 /include/configs/P2020DS.h | |
| parent | 5fb8a8a7315689cfbc81ec596cce160ee2ec6562 (diff) | |
| download | talos-obmc-uboot-394c46caf965f47717a952a09a51b73c2cb473b3.tar.gz talos-obmc-uboot-394c46caf965f47717a952a09a51b73c2cb473b3.zip | |
powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfig
Enabled SPD
Enabled DDR2
Enabled hwconfig
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/P2020DS.h')
| -rw-r--r-- | include/configs/P2020DS.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a1ecf0524e..7f6f5e70b2 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -92,7 +92,11 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_MK_DDR2 +#define CONFIG_FSL_DDR2 +#else #define CONFIG_FSL_DDR3 1 +#endif #undef CONFIG_FSL_DDR_INTERACTIVE /* ECC will be enabled based on perf_mode environment variable */ @@ -109,6 +113,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ @@ -228,6 +233,7 @@ #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #ifdef CONFIG_FSL_NGPIXIS |
